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[RISCV] Collapse fast unaligned access into a single feature [nfc-ish] (#73971)
When we'd originally added unaligned-scalar-mem and unaligned-vector-mem, they were separated into two parts under the theory that some processor might implement one, but not the other. At the moment, we don't have evidence of such a processor. The C/C++ level interface, and the clang driver command lines have settled on a single unaligned flag which indicates both scalar and vector support unaligned. Given that, let's remove the test matrix complexity for a set of configurations which don't appear useful. Given these are internal feature names, I don't think we need to provide any forward compatibility. Anyone disagree? Note: The immediate trigger for this patch was finding another case where the unaligned-vector-mem wasn't being properly serialized to IR from clang which resulted in problems reproducing assembly from clang's -emit-llvm feature. Instead of fixing this, I decided getting rid of the complexity was the better approach.
1 parent ca2d79f commit e817966

20 files changed

+51
-68
lines changed

‎clang/lib/Basic/Targets/RISCV.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -376,7 +376,7 @@ bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
376376
if (ISAInfo->hasExtension("zfh") || ISAInfo->hasExtension("zhinx"))
377377
HasLegalHalfType = true;
378378

379-
FastUnalignedAccess = llvm::is_contained(Features, "+unaligned-scalar-mem");
379+
FastUnalignedAccess = llvm::is_contained(Features, "+fast-unaligned-access");
380380

381381
return true;
382382
}

‎clang/lib/Driver/ToolChains/Arch/RISCV.cpp

Lines changed: 5 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,7 @@ static void getRISCFeaturesFromMcpu(const Driver &D, const Arg *A,
6565
}
6666

6767
if (llvm::RISCV::hasFastUnalignedAccess(Mcpu))
68-
Features.push_back("+unaligned-scalar-mem");
68+
Features.push_back("+fast-unaligned-access");
6969
}
7070

7171
void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
@@ -171,18 +171,12 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
171171
Features.push_back("-save-restore");
172172

173173
// -mno-unaligned-access is default, unless -munaligned-access is specified.
174-
bool HasV = llvm::is_contained(Features, "+zve32x");
175174
if (const Arg *A = Args.getLastArg(options::OPT_munaligned_access,
176175
options::OPT_mno_unaligned_access)) {
177-
if (A->getOption().matches(options::OPT_munaligned_access)) {
178-
Features.push_back("+unaligned-scalar-mem");
179-
if (HasV)
180-
Features.push_back("+unaligned-vector-mem");
181-
} else {
182-
Features.push_back("-unaligned-scalar-mem");
183-
if (HasV)
184-
Features.push_back("-unaligned-vector-mem");
185-
}
176+
if (A->getOption().matches(options::OPT_munaligned_access))
177+
Features.push_back("+fast-unaligned-access");
178+
else
179+
Features.push_back("-fast-unaligned-access");
186180
}
187181

188182
// Now add any that the user explicitly requested on the command line,

‎clang/test/Driver/riscv-features.c

Lines changed: 7 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -27,19 +27,13 @@
2727
// DEFAULT: "-target-feature" "-save-restore"
2828
// DEFAULT-NOT: "-target-feature" "+save-restore"
2929

30-
// RUN: %clang --target=riscv32-unknown-elf -### %s -munaligned-access 2>&1 | FileCheck %s -check-prefix=UNALIGNED-SCALAR-MEM
31-
// RUN: %clang --target=riscv32-unknown-elf -### %s -mno-unaligned-access 2>&1 | FileCheck %s -check-prefix=NO-UNALIGNED-SCALAR-MEM
32-
// RUN: %clang --target=riscv32-unknown-elf -### %s -mno-strict-align 2>&1 | FileCheck %s -check-prefix=UNALIGNED-SCALAR-MEM
33-
// RUN: %clang --target=riscv32-unknown-elf -### %s -mstrict-align 2>&1 | FileCheck %s -check-prefix=NO-UNALIGNED-SCALAR-MEM
34-
// RUN: %clang --target=riscv32-unknown-elf -### %s -march=rv32gv -munaligned-access 2>&1 | FileCheck %s -check-prefix=UNALIGNED-VECTOR-MEM
35-
// RUN: %clang --target=riscv32-unknown-elf -### %s -march=rv32gv -mno-unaligned-access 2>&1 | FileCheck %s -check-prefix=NO-UNALIGNED-VECTOR-MEM
36-
// RUN: %clang --target=riscv32-unknown-elf -### %s -march=rv32gv -mno-strict-align 2>&1 | FileCheck %s -check-prefix=UNALIGNED-VECTOR-MEM
37-
// RUN: %clang --target=riscv32-unknown-elf -### %s -march=rv32gv -mstrict-align 2>&1 | FileCheck %s -check-prefix=NO-UNALIGNED-VECTOR-MEM
38-
39-
// UNALIGNED-SCALAR-MEM: "-target-feature" "+unaligned-scalar-mem"
40-
// NO-UNALIGNED-SCALAR-MEM: "-target-feature" "-unaligned-scalar-mem"
41-
// UNALIGNED-VECTOR-MEM: "-target-feature" "+unaligned-vector-mem"
42-
// NO-UNALIGNED-VECTOR-MEM: "-target-feature" "-unaligned-vector-mem"
30+
// RUN: %clang --target=riscv32-unknown-elf -### %s -munaligned-access 2>&1 | FileCheck %s -check-prefix=FAST-UNALIGNED-ACCESS
31+
// RUN: %clang --target=riscv32-unknown-elf -### %s -mno-unaligned-access 2>&1 | FileCheck %s -check-prefix=NO-FAST-UNALIGNED-ACCESS
32+
// RUN: %clang --target=riscv32-unknown-elf -### %s -mno-strict-align 2>&1 | FileCheck %s -check-prefix=FAST-UNALIGNED-ACCESS
33+
// RUN: %clang --target=riscv32-unknown-elf -### %s -mstrict-align 2>&1 | FileCheck %s -check-prefix=NO-FAST-UNALIGNED-ACCESS
34+
35+
// FAST-UNALIGNED-ACCESS: "-target-feature" "+fast-unaligned-access"
36+
// NO-FAST-UNALIGNED-ACCESS: "-target-feature" "-fast-unaligned-access"
4337

4438
// RUN: %clang --target=riscv32-linux -### %s -fsyntax-only 2>&1 \
4539
// RUN: | FileCheck %s -check-prefix=DEFAULT-LINUX

‎llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -309,8 +309,8 @@ bool RISCVExpandPseudo::expandRV32ZdinxStore(MachineBasicBlock &MBB,
309309
.addReg(MBBI->getOperand(1).getReg())
310310
.add(MBBI->getOperand(2));
311311
if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
312-
// FIXME: Zdinx RV32 can not work on unaligned scalar memory.
313-
assert(!STI->enableUnalignedScalarMem());
312+
// FIXME: Zdinx RV32 can not work on unaligned memory.
313+
assert(!STI->hasFastUnalignedAccess());
314314

315315
assert(MBBI->getOperand(2).getOffset() % 8 == 0);
316316
MBBI->getOperand(2).setOffset(MBBI->getOperand(2).getOffset() + 4);

‎llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 4 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -946,15 +946,10 @@ def FeatureTrailingSeqCstFence : SubtargetFeature<"seq-cst-trailing-fence",
946946
"true",
947947
"Enable trailing fence for seq-cst store.">;
948948

949-
def FeatureUnalignedScalarMem
950-
: SubtargetFeature<"unaligned-scalar-mem", "EnableUnalignedScalarMem",
951-
"true", "Has reasonably performant unaligned scalar "
952-
"loads and stores">;
953-
954-
def FeatureUnalignedVectorMem
955-
: SubtargetFeature<"unaligned-vector-mem", "EnableUnalignedVectorMem",
956-
"true", "Has reasonably performant unaligned vector "
957-
"loads and stores">;
949+
def FeatureFastUnalignedAccess
950+
: SubtargetFeature<"fast-unaligned-access", "HasFastUnalignedAccess",
951+
"true", "Has reasonably performant unaligned "
952+
"loads and stores (both scalar and vector)">;
958953

959954
def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
960955
"UsePostRAScheduler", "true", "Schedule again after register allocation">;

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1874,7 +1874,7 @@ bool RISCVTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
18741874
// replace. If we don't support unaligned scalar mem, prefer the constant
18751875
// pool.
18761876
// TODO: Can the caller pass down the alignment?
1877-
if (!Subtarget.enableUnalignedScalarMem())
1877+
if (!Subtarget.hasFastUnalignedAccess())
18781878
return true;
18791879

18801880
// Prefer to keep the load if it would require many instructions.
@@ -14689,7 +14689,7 @@ static bool matchIndexAsWiderOp(EVT VT, SDValue Index, SDValue Mask,
1468914689
if (WiderElementSize > ST.getELen()/8)
1469014690
return false;
1469114691

14692-
if (!ST.enableUnalignedVectorMem() && BaseAlign < WiderElementSize)
14692+
if (!ST.hasFastUnalignedAccess() && BaseAlign < WiderElementSize)
1469314693
return false;
1469414694

1469514695
for (unsigned i = 0; i < Index->getNumOperands(); i++) {
@@ -19288,8 +19288,8 @@ bool RISCVTargetLowering::allowsMisalignedMemoryAccesses(
1928819288
unsigned *Fast) const {
1928919289
if (!VT.isVector()) {
1929019290
if (Fast)
19291-
*Fast = Subtarget.enableUnalignedScalarMem();
19292-
return Subtarget.enableUnalignedScalarMem();
19291+
*Fast = Subtarget.hasFastUnalignedAccess();
19292+
return Subtarget.hasFastUnalignedAccess();
1929319293
}
1929419294

1929519295
// All vector implementations must support element alignment
@@ -19305,8 +19305,8 @@ bool RISCVTargetLowering::allowsMisalignedMemoryAccesses(
1930519305
// misaligned accesses. TODO: Work through the codegen implications of
1930619306
// allowing such accesses to be formed, and considered fast.
1930719307
if (Fast)
19308-
*Fast = Subtarget.enableUnalignedVectorMem();
19309-
return Subtarget.enableUnalignedVectorMem();
19308+
*Fast = Subtarget.hasFastUnalignedAccess();
19309+
return Subtarget.hasFastUnalignedAccess();
1931019310
}
1931119311

1931219312

@@ -19341,7 +19341,7 @@ EVT RISCVTargetLowering::getOptimalMemOpType(const MemOp &Op,
1934119341

1934219342
// Do we have sufficient alignment for our preferred VT? If not, revert
1934319343
// to largest size allowed by our alignment criteria.
19344-
if (PreferredVT != MVT::i8 && !Subtarget.enableUnalignedVectorMem()) {
19344+
if (PreferredVT != MVT::i8 && !Subtarget.hasFastUnalignedAccess()) {
1934519345
Align RequiredAlign(PreferredVT.getStoreSize());
1934619346
if (Op.isFixedDstAlign())
1934719347
RequiredAlign = std::min(RequiredAlign, Op.getDstAlign());
@@ -19533,7 +19533,7 @@ bool RISCVTargetLowering::isLegalStridedLoadStore(EVT DataType,
1953319533
if (!isLegalElementTypeForRVV(ScalarType))
1953419534
return false;
1953519535

19536-
if (!Subtarget.enableUnalignedVectorMem() &&
19536+
if (!Subtarget.hasFastUnalignedAccess() &&
1953719537
Alignment < ScalarType.getStoreSize())
1953819538
return false;
1953919539

‎llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -199,7 +199,7 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
199199
return false;
200200

201201
EVT ElemType = DataTypeVT.getScalarType();
202-
if (!ST->enableUnalignedVectorMem() && Alignment < ElemType.getStoreSize())
202+
if (!ST->hasFastUnalignedAccess() && Alignment < ElemType.getStoreSize())
203203
return false;
204204

205205
return TLI->isLegalElementTypeForRVV(ElemType);
@@ -224,7 +224,7 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
224224
return false;
225225

226226
EVT ElemType = DataTypeVT.getScalarType();
227-
if (!ST->enableUnalignedVectorMem() && Alignment < ElemType.getStoreSize())
227+
if (!ST->hasFastUnalignedAccess() && Alignment < ElemType.getStoreSize())
228228
return false;
229229

230230
return TLI->isLegalElementTypeForRVV(ElemType);

‎llvm/test/CodeGen/RISCV/memcpy-inline.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,9 +3,9 @@
33
; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32
44
; RUN: llc < %s -mtriple=riscv64 \
55
; RUN: | FileCheck %s --check-prefixes=RV64-BOTH,RV64
6-
; RUN: llc < %s -mtriple=riscv32 -mattr=+unaligned-scalar-mem \
6+
; RUN: llc < %s -mtriple=riscv32 -mattr=+fast-unaligned-access \
77
; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32-FAST
8-
; RUN: llc < %s -mtriple=riscv64 -mattr=+unaligned-scalar-mem \
8+
; RUN: llc < %s -mtriple=riscv64 -mattr=+fast-unaligned-access \
99
; RUN: | FileCheck %s --check-prefixes=RV64-BOTH,RV64-FAST
1010

1111
; ----------------------------------------------------------------------

‎llvm/test/CodeGen/RISCV/memcpy.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,9 +3,9 @@
33
; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32
44
; RUN: llc < %s -mtriple=riscv64 \
55
; RUN: | FileCheck %s --check-prefixes=RV64-BOTH,RV64
6-
; RUN: llc < %s -mtriple=riscv32 -mattr=+unaligned-scalar-mem \
6+
; RUN: llc < %s -mtriple=riscv32 -mattr=+fast-unaligned-access \
77
; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32-FAST
8-
; RUN: llc < %s -mtriple=riscv64 -mattr=+unaligned-scalar-mem \
8+
; RUN: llc < %s -mtriple=riscv64 -mattr=+fast-unaligned-access \
99
; RUN: | FileCheck %s --check-prefixes=RV64-BOTH,RV64-FAST
1010
%struct.x = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 }
1111

‎llvm/test/CodeGen/RISCV/memset-inline.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,9 +3,9 @@
33
; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32
44
; RUN: llc < %s -mtriple=riscv64 -mattr=+m \
55
; RUN: | FileCheck %s --check-prefixes=RV64-BOTH,RV64
6-
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+unaligned-scalar-mem \
6+
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+fast-unaligned-access \
77
; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32-FAST
8-
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+unaligned-scalar-mem \
8+
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+fast-unaligned-access \
99
; RUN: | FileCheck %s --check-prefixes=RV64-BOTH,RV64-FAST
1010
%struct.x = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 }
1111

‎llvm/test/CodeGen/RISCV/pr56110.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc < %s -mtriple=riscv32 | FileCheck %s
3-
; RUN: llc < %s -mtriple=riscv32 -mattr=+unaligned-scalar-mem | FileCheck %s
3+
; RUN: llc < %s -mtriple=riscv32 -mattr=+fast-unaligned-access | FileCheck %s
44

55
define void @foo_set(ptr nocapture noundef %a, i32 noundef %v) {
66
; CHECK-LABEL: foo_set:

‎llvm/test/CodeGen/RISCV/riscv-func-target-feature.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ entry:
3636
}
3737

3838
; CHECK-NOT: .option push
39-
define void @test5() "target-features"="+unaligned-scalar-mem" {
39+
define void @test5() "target-features"="+fast-unaligned-access" {
4040
; CHECK-LABEL: test5
4141
; CHECK-NOT: .option pop
4242
entry:

‎llvm/test/CodeGen/RISCV/rvv/concat-vectors-constant-stride.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+v,+unaligned-vector-mem -target-abi=ilp32 \
2+
; RUN: llc -mtriple=riscv32 -mattr=+v,+fast-unaligned-access -target-abi=ilp32 \
33
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
4-
; RUN: llc -mtriple=riscv64 -mattr=+v,+unaligned-vector-mem -target-abi=lp64 \
4+
; RUN: llc -mtriple=riscv64 -mattr=+v,+fast-unaligned-access -target-abi=lp64 \
55
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
66

77
define void @constant_forward_stride(ptr %s, ptr %d) {

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
22
; RUN: llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,CHECK-NO-MISALIGN,RV32
33
; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,CHECK-NO-MISALIGN,RV64
4-
; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh,+unaligned-vector-mem -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV64,RV64-MISALIGN
4+
; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh,+fast-unaligned-access -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV64,RV64-MISALIGN
55

66
; RUN: llc -mtriple=riscv64 -mattr=+f,+zfh,+zve64f,+zvl128b,+zvfh -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,CHECK-NO-MISALIGN,ZVE64F
77

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,9 +3,9 @@
33
; RUN: | FileCheck %s --check-prefixes=SLOW,RV32-SLOW
44
; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s \
55
; RUN: | FileCheck %s --check-prefixes=SLOW,RV64-SLOW
6-
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+unaligned-vector-mem -verify-machineinstrs < %s \
6+
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+fast-unaligned-access -verify-machineinstrs < %s \
77
; RUN: | FileCheck %s --check-prefixes=FAST,RV32-FAST
8-
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+unaligned-vector-mem -verify-machineinstrs < %s \
8+
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+fast-unaligned-access -verify-machineinstrs < %s \
99
; RUN: | FileCheck %s --check-prefixes=FAST,RV64-FAST
1010

1111
define <4 x i32> @load_v4i32_align1(ptr %ptr) {

‎llvm/test/CodeGen/RISCV/rvv/memcpy-inline.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,9 +3,9 @@
33
; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32
44
; RUN: llc < %s -mtriple=riscv64 -mattr=+v \
55
; RUN: | FileCheck %s --check-prefixes=RV64-BOTH,RV64
6-
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+unaligned-scalar-mem,+unaligned-vector-mem \
6+
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+fast-unaligned-access \
77
; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32-FAST
8-
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+unaligned-scalar-mem,+unaligned-vector-mem \
8+
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+fast-unaligned-access \
99
; RUN: | FileCheck %s --check-prefixes=RV64-BOTH,RV64-FAST
1010

1111
; ----------------------------------------------------------------------

‎llvm/test/CodeGen/RISCV/rvv/memset-inline.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,9 +3,9 @@
33
; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32
44
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v \
55
; RUN: | FileCheck %s --check-prefixes=RV64-BOTH,RV64
6-
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v,+unaligned-scalar-mem,,+unaligned-vector-mem \
6+
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v,+fast-unaligned-access \
77
; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32-FAST
8-
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+unaligned-scalar-mem,+unaligned-vector-mem \
8+
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+fast-unaligned-access \
99
; RUN: | FileCheck %s --check-prefixes=RV64-BOTH,RV64-FAST
1010
%struct.x = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 }
1111

‎llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,9 +3,9 @@
33
; RUN: -verify-machineinstrs | FileCheck %s
44
; RUN: llc -mtriple riscv64 -mattr=+d,+zfh,+zvfh,+v < %s \
55
; RUN: -verify-machineinstrs | FileCheck %s
6-
; RUN: llc -mtriple riscv32 -mattr=+d,+zfh,+zvfh,+v,+unaligned-vector-mem < %s \
6+
; RUN: llc -mtriple riscv32 -mattr=+d,+zfh,+zvfh,+v,+fast-unaligned-access < %s \
77
; RUN: -verify-machineinstrs | FileCheck --check-prefix=FAST %s
8-
; RUN: llc -mtriple riscv64 -mattr=+d,+zfh,+zvfh,+v,+unaligned-vector-mem < %s \
8+
; RUN: llc -mtriple riscv64 -mattr=+d,+zfh,+zvfh,+v,+fast-unaligned-access < %s \
99
; RUN: -verify-machineinstrs | FileCheck --check-prefix=FAST %s
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1111

‎llvm/test/CodeGen/RISCV/unaligned-load-store.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,9 +3,9 @@
33
; RUN: | FileCheck -check-prefixes=ALL,SLOW,RV32I %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
55
; RUN: | FileCheck -check-prefixes=ALL,SLOW,RV64I %s
6-
; RUN: llc -mtriple=riscv32 -mattr=+unaligned-scalar-mem -verify-machineinstrs < %s \
6+
; RUN: llc -mtriple=riscv32 -mattr=+fast-unaligned-access -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=ALL,FAST,RV32I-FAST %s
8-
; RUN: llc -mtriple=riscv64 -mattr=+unaligned-scalar-mem -verify-machineinstrs < %s \
8+
; RUN: llc -mtriple=riscv64 -mattr=+fast-unaligned-access -verify-machineinstrs < %s \
99
; RUN: | FileCheck -check-prefixes=ALL,FAST,RV64I-FAST %s
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1111
; A collection of cases showing codegen for unaligned loads and stores

‎llvm/utils/TableGen/RISCVTargetDefEmitter.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -62,7 +62,7 @@ static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) {
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const bool FastUnalignedAccess =
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any_of(Rec->getValueAsListOfDefs("Features"), [&](auto &Feature) {
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return Feature->getValueAsString("Name") == "unaligned-scalar-mem";
65+
return Feature->getValueAsString("Name") == "fast-unaligned-access";
6666
});
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OS << "PROC(" << Rec->getName() << ", "

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