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[RISCV] Bump rvv-related extensions from 0.10 to 1.0
Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D112987
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‎clang/test/Driver/riscv-arch.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -412,20 +412,20 @@
412412
// RV32-EXPERIMENTAL-V-BADVERS: error: invalid arch name 'rv32iv0p1'
413413
// RV32-EXPERIMENTAL-V-BADVERS: unsupported version number 0.1 for experimental extension 'v'
414414

415-
// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p10 -menable-experimental-extensions -### %s -c 2>&1 | \
415+
// RUN: %clang -target riscv32-unknown-elf -march=rv32iv1p0 -menable-experimental-extensions -### %s -c 2>&1 | \
416416
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-V-GOODVERS %s
417417
// RV32-EXPERIMENTAL-V-GOODVERS: "-target-feature" "+experimental-v"
418418

419-
// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p10_zvl32b0p10 -### %s -c 2>&1 | \
419+
// RUN: %clang -target riscv32-unknown-elf -march=rv32iv1p0_zvl32b1p0 -### %s -c 2>&1 | \
420420
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVL-NOFLAG %s
421-
// RV32-EXPERIMENTAL-ZVL-NOFLAG: error: invalid arch name 'rv32iv0p10_zvl32b0p10'
421+
// RV32-EXPERIMENTAL-ZVL-NOFLAG: error: invalid arch name 'rv32iv1p0_zvl32b1p0'
422422
// RV32-EXPERIMENTAL-ZVL-NOFLAG: requires '-menable-experimental-extensions'
423423

424-
// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p10_zvl32b0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
424+
// RUN: %clang -target riscv32-unknown-elf -march=rv32iv1p0_zvl32b0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
425425
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVL-BADVERS %s
426-
// RV32-EXPERIMENTAL-ZVL-BADVERS: error: invalid arch name 'rv32iv0p10_zvl32b0p1'
426+
// RV32-EXPERIMENTAL-ZVL-BADVERS: error: invalid arch name 'rv32iv1p0_zvl32b0p1'
427427
// RV32-EXPERIMENTAL-ZVL-BADVERS: unsupported version number 0.1 for experimental extension
428428

429-
// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p10_zvl32b0p10 -menable-experimental-extensions -### %s -c 2>&1 | \
429+
// RUN: %clang -target riscv32-unknown-elf -march=rv32iv1p0_zvl32b1p0 -menable-experimental-extensions -### %s -c 2>&1 | \
430430
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVL-GOODVERS %s
431431
// RV32-EXPERIMENTAL-ZVL-GOODVERS: "-target-feature" "+experimental-zvl32b"

‎clang/test/Preprocessor/riscv-target-features.c

Lines changed: 32 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -212,12 +212,12 @@
212212
// CHECK-ZBT-EXT: __riscv_zbt 93000{{$}}
213213

214214
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
215-
// RUN: -march=rv32iv0p10 -x c -E -dM %s \
215+
// RUN: -march=rv32iv1p0 -x c -E -dM %s \
216216
// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
217217
// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
218-
// RUN: -march=rv64iv0p10 -x c -E -dM %s \
218+
// RUN: -march=rv64iv1p0 -x c -E -dM %s \
219219
// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
220-
// CHECK-V-EXT: __riscv_v 10000{{$}}
220+
// CHECK-V-EXT: __riscv_v 1000000{{$}}
221221
// CHECK-V-EXT: __riscv_vector 1
222222

223223
// RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -237,107 +237,107 @@
237237
// CHECK-ZFH-EXT: __riscv_zfh 1000000{{$}}
238238

239239
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
240-
// RUN: -march=rv64iv0p10 -x c -E -dM %s -o - \
240+
// RUN: -march=rv64iv1p0 -x c -E -dM %s -o - \
241241
// RUN: | FileCheck --check-prefix=CHECK-V-MINVLEN %s
242242
// CHECK-V-MINVLEN: __riscv_v_elen 64
243243
// CHECK-V-MINVLEN: __riscv_v_elen_fp 64
244244
// CHECK-V-MINVLEN: __riscv_v_min_vlen 128
245245

246246
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
247-
// RUN: -march=rv64iv0p10_zvl256b0p10 -x c -E -dM %s -o - \
247+
// RUN: -march=rv64iv1p0_zvl256b1p0 -x c -E -dM %s -o - \
248248
// RUN: | FileCheck --check-prefix=CHECK-ZVL256b %s
249249
// CHECK-ZVL256b: __riscv_v_min_vlen 256
250250

251251
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
252-
// RUN: -march=rv64iv0p10_zvl512b0p10 -x c -E -dM %s -o - \
252+
// RUN: -march=rv64iv1p0_zvl512b1p0 -x c -E -dM %s -o - \
253253
// RUN: | FileCheck --check-prefix=CHECK-ZVL512b %s
254254
// CHECK-ZVL512b: __riscv_v_min_vlen 512
255255

256256
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
257-
// RUN: -march=rv64iv0p10_zvl1024b0p10 -x c -E -dM %s -o - \
257+
// RUN: -march=rv64iv1p0_zvl1024b1p0 -x c -E -dM %s -o - \
258258
// RUN: | FileCheck --check-prefix=CHECK-ZVL1024b %s
259259
// CHECK-ZVL1024b: __riscv_v_min_vlen 1024
260260

261261
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
262-
// RUN: -march=rv64iv0p10_zvl2048b0p10 -x c -E -dM %s -o - \
262+
// RUN: -march=rv64iv1p0_zvl2048b1p0 -x c -E -dM %s -o - \
263263
// RUN: | FileCheck --check-prefix=CHECK-ZVL2048b %s
264264
// CHECK-ZVL2048b: __riscv_v_min_vlen 2048
265265

266266
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
267-
// RUN: -march=rv64iv0p10_zvl4096b0p10 -x c -E -dM %s -o - \
267+
// RUN: -march=rv64iv1p0_zvl4096b1p0 -x c -E -dM %s -o - \
268268
// RUN: | FileCheck --check-prefix=CHECK-ZVL4096b %s
269269
// CHECK-ZVL4096b: __riscv_v_min_vlen 4096
270270

271271
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
272-
// RUN: -march=rv64iv0p10_zvl8192b0p10 -x c -E -dM %s -o - \
272+
// RUN: -march=rv64iv1p0_zvl8192b1p0 -x c -E -dM %s -o - \
273273
// RUN: | FileCheck --check-prefix=CHECK-ZVL8192b %s
274274
// CHECK-ZVL8192b: __riscv_v_min_vlen 8192
275275

276276
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
277-
// RUN: -march=rv64iv0p10_zvl16384b0p10 -x c -E -dM %s -o - \
277+
// RUN: -march=rv64iv1p0_zvl16384b1p0 -x c -E -dM %s -o - \
278278
// RUN: | FileCheck --check-prefix=CHECK-ZVL16384b %s
279279
// CHECK-ZVL16384b: __riscv_v_min_vlen 16384
280280

281281
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
282-
// RUN: -march=rv64iv0p10_zvl32768b0p10 -x c -E -dM %s -o - \
282+
// RUN: -march=rv64iv1p0_zvl32768b1p0 -x c -E -dM %s -o - \
283283
// RUN: | FileCheck --check-prefix=CHECK-ZVL32768b %s
284284
// CHECK-ZVL32768b: __riscv_v_min_vlen 32768
285285

286286
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
287-
// RUN: -march=rv64iv0p10_zvl65536b0p10 -x c -E -dM %s -o - \
287+
// RUN: -march=rv64iv1p0_zvl65536b1p0 -x c -E -dM %s -o - \
288288
// RUN: | FileCheck --check-prefix=CHECK-ZVL65536b %s
289289
// CHECK-ZVL65536b: __riscv_v_min_vlen 65536
290290

291291
// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
292-
// RUN: -march=rv64ifdzve64d0p10 -x c -E -dM %s -o - \
292+
// RUN: -march=rv64ifdzve64d1p0 -x c -E -dM %s -o - \
293293
// RUN: | FileCheck --check-prefix=CHECK-ZVE64D-EXT %s
294294
// CHECK-ZVE64D-EXT: __riscv_v_elen 64
295295
// CHECK-ZVE64D-EXT: __riscv_v_elen_fp 64
296296
// CHECK-ZVE64D-EXT: __riscv_v_min_vlen 64
297297
// CHECK-ZVE64D-EXT: __riscv_vector 1
298-
// CHECK-ZVE64D-EXT: __riscv_zve32f 10000{{$}}
299-
// CHECK-ZVE64D-EXT: __riscv_zve32x 10000{{$}}
300-
// CHECK-ZVE64D-EXT: __riscv_zve64d 10000{{$}}
301-
// CHECK-ZVE64D-EXT: __riscv_zve64f 10000{{$}}
302-
// CHECK-ZVE64D-EXT: __riscv_zve64x 10000{{$}}
298+
// CHECK-ZVE64D-EXT: __riscv_zve32f 1000000{{$}}
299+
// CHECK-ZVE64D-EXT: __riscv_zve32x 1000000{{$}}
300+
// CHECK-ZVE64D-EXT: __riscv_zve64d 1000000{{$}}
301+
// CHECK-ZVE64D-EXT: __riscv_zve64f 1000000{{$}}
302+
// CHECK-ZVE64D-EXT: __riscv_zve64x 1000000{{$}}
303303

304304
// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
305-
// RUN: -march=rv64ifzve64f0p10 -x c -E -dM %s -o - \
305+
// RUN: -march=rv64ifzve64f1p0 -x c -E -dM %s -o - \
306306
// RUN: | FileCheck --check-prefix=CHECK-ZVE64F-EXT %s
307307
// CHECK-ZVE64F-EXT: __riscv_v_elen 64
308308
// CHECK-ZVE64F-EXT: __riscv_v_elen_fp 32
309309
// CHECK-ZVE64F-EXT: __riscv_v_min_vlen 64
310310
// CHECK-ZVE64F-EXT: __riscv_vector 1
311-
// CHECK-ZVE64F-EXT: __riscv_zve32f 10000{{$}}
312-
// CHECK-ZVE64F-EXT: __riscv_zve32x 10000{{$}}
313-
// CHECK-ZVE64F-EXT: __riscv_zve64f 10000{{$}}
314-
// CHECK-ZVE64F-EXT: __riscv_zve64x 10000{{$}}
311+
// CHECK-ZVE64F-EXT: __riscv_zve32f 1000000{{$}}
312+
// CHECK-ZVE64F-EXT: __riscv_zve32x 1000000{{$}}
313+
// CHECK-ZVE64F-EXT: __riscv_zve64f 1000000{{$}}
314+
// CHECK-ZVE64F-EXT: __riscv_zve64x 1000000{{$}}
315315

316316
// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
317-
// RUN: -march=rv64izve64x0p10 -x c -E -dM %s -o - \
317+
// RUN: -march=rv64izve64x1p0 -x c -E -dM %s -o - \
318318
// RUN: | FileCheck --check-prefix=CHECK-ZVE64X-EXT %s
319319
// CHECK-ZVE64X-EXT: __riscv_v_elen 64
320320
// CHECK-ZVE64X-EXT: __riscv_v_elen_fp 0
321321
// CHECK-ZVE64X-EXT: __riscv_v_min_vlen 64
322322
// CHECK-ZVE64X-EXT: __riscv_vector 1
323-
// CHECK-ZVE64X-EXT: __riscv_zve32x 10000{{$}}
324-
// CHECK-ZVE64X-EXT: __riscv_zve64x 10000{{$}}
323+
// CHECK-ZVE64X-EXT: __riscv_zve32x 1000000{{$}}
324+
// CHECK-ZVE64X-EXT: __riscv_zve64x 1000000{{$}}
325325

326326
// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
327-
// RUN: -march=rv64ifzve32f0p10 -x c -E -dM %s -o - \
327+
// RUN: -march=rv64ifzve32f1p0 -x c -E -dM %s -o - \
328328
// RUN: | FileCheck --check-prefix=CHECK-ZVE32F-EXT %s
329329
// CHECK-ZVE32F-EXT: __riscv_v_elen 32
330330
// CHECK-ZVE32F-EXT: __riscv_v_elen_fp 32
331331
// CHECK-ZVE32F-EXT: __riscv_v_min_vlen 32
332332
// CHECK-ZVE32F-EXT: __riscv_vector 1
333-
// CHECK-ZVE32F-EXT: __riscv_zve32f 10000{{$}}
334-
// CHECK-ZVE32F-EXT: __riscv_zve32x 10000{{$}}
333+
// CHECK-ZVE32F-EXT: __riscv_zve32f 1000000{{$}}
334+
// CHECK-ZVE32F-EXT: __riscv_zve32x 1000000{{$}}
335335

336336
// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
337-
// RUN: -march=rv64izve32x0p10 -x c -E -dM %s -o - \
337+
// RUN: -march=rv64izve32x1p0 -x c -E -dM %s -o - \
338338
// RUN: | FileCheck --check-prefix=CHECK-ZVE32X-EXT %s
339339
// CHECK-ZVE32X-EXT: __riscv_v_elen 32
340340
// CHECK-ZVE32X-EXT: __riscv_v_elen_fp 0
341341
// CHECK-ZVE32X-EXT: __riscv_v_min_vlen 32
342342
// CHECK-ZVE32X-EXT: __riscv_vector 1
343-
// CHECK-ZVE32X-EXT: __riscv_zve32x 10000{{$}}
343+
// CHECK-ZVE32X-EXT: __riscv_zve32x 1000000{{$}}

‎llvm/lib/Support/RISCVISAInfo.cpp

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -60,31 +60,31 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
6060
};
6161

6262
static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
63-
{"v", RISCVExtensionVersion{0, 10}},
63+
{"v", RISCVExtensionVersion{1, 0}},
6464
{"zbe", RISCVExtensionVersion{0, 93}},
6565
{"zbf", RISCVExtensionVersion{0, 93}},
6666
{"zbm", RISCVExtensionVersion{0, 93}},
6767
{"zbp", RISCVExtensionVersion{0, 93}},
6868
{"zbr", RISCVExtensionVersion{0, 93}},
6969
{"zbt", RISCVExtensionVersion{0, 93}},
7070

71-
{"zvl32b", RISCVExtensionVersion{0, 10}},
72-
{"zvl64b", RISCVExtensionVersion{0, 10}},
73-
{"zvl128b", RISCVExtensionVersion{0, 10}},
74-
{"zvl256b", RISCVExtensionVersion{0, 10}},
75-
{"zvl512b", RISCVExtensionVersion{0, 10}},
76-
{"zvl1024b", RISCVExtensionVersion{0, 10}},
77-
{"zvl2048b", RISCVExtensionVersion{0, 10}},
78-
{"zvl4096b", RISCVExtensionVersion{0, 10}},
79-
{"zvl8192b", RISCVExtensionVersion{0, 10}},
80-
{"zvl16384b", RISCVExtensionVersion{0, 10}},
81-
{"zvl32768b", RISCVExtensionVersion{0, 10}},
82-
{"zvl65536b", RISCVExtensionVersion{0, 10}},
83-
{"zve32x", RISCVExtensionVersion{0, 10}},
84-
{"zve32f", RISCVExtensionVersion{0, 10}},
85-
{"zve64x", RISCVExtensionVersion{0, 10}},
86-
{"zve64f", RISCVExtensionVersion{0, 10}},
87-
{"zve64d", RISCVExtensionVersion{0, 10}},
71+
{"zvl32b", RISCVExtensionVersion{1, 0}},
72+
{"zvl64b", RISCVExtensionVersion{1, 0}},
73+
{"zvl128b", RISCVExtensionVersion{1, 0}},
74+
{"zvl256b", RISCVExtensionVersion{1, 0}},
75+
{"zvl512b", RISCVExtensionVersion{1, 0}},
76+
{"zvl1024b", RISCVExtensionVersion{1, 0}},
77+
{"zvl2048b", RISCVExtensionVersion{1, 0}},
78+
{"zvl4096b", RISCVExtensionVersion{1, 0}},
79+
{"zvl8192b", RISCVExtensionVersion{1, 0}},
80+
{"zvl16384b", RISCVExtensionVersion{1, 0}},
81+
{"zvl32768b", RISCVExtensionVersion{1, 0}},
82+
{"zvl65536b", RISCVExtensionVersion{1, 0}},
83+
{"zve32x", RISCVExtensionVersion{1, 0}},
84+
{"zve32f", RISCVExtensionVersion{1, 0}},
85+
{"zve64x", RISCVExtensionVersion{1, 0}},
86+
{"zve64f", RISCVExtensionVersion{1, 0}},
87+
{"zve64d", RISCVExtensionVersion{1, 0}},
8888
};
8989

9090
static bool stripExperimentalPrefix(StringRef &Ext) {

‎llvm/test/CodeGen/RISCV/attributes.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -59,8 +59,8 @@
5959
; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"
6060
; RV32ZBS: .attribute 5, "rv32i2p0_zbs1p0"
6161
; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
62-
; RV32V: .attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
63-
; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
62+
; RV32V: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
63+
; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zfh1p0_zfhmin1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
6464
; RV32ZBKB: .attribute 5, "rv32i2p0_zbkb1p0"
6565

6666
; RV64M: .attribute 5, "rv64i2p0_m2p0"
@@ -80,8 +80,8 @@
8080
; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93"
8181
; RV64ZBS: .attribute 5, "rv64i2p0_zbs1p0"
8282
; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93"
83-
; RV64V: .attribute 5, "rv64i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
84-
; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_d2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
83+
; RV64V: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
84+
; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zfh1p0_zfhmin1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
8585
; RV64ZBKB: .attribute 5, "rv64i2p0_zbkb1p0"
8686

8787
define i32 @addi(i32 %a) {

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