@@ -332,6 +332,8 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
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setOperationAction (ISD::FNEARBYINT, {MVT::f16 , MVT::f32 , MVT::f64 }, Custom);
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+ setOperationAction (ISD::FROUNDEVEN, {MVT::f16 , MVT::f32 , MVT::f64 }, Custom);
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+
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setOperationAction (ISD::FREM, {MVT::f16 , MVT::f32 , MVT::f64 }, Custom);
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if (Subtarget->has16BitInsts ())
@@ -1252,6 +1254,8 @@ SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
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case ISD::FTRUNC: return LowerFTRUNC (Op, DAG);
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case ISD::FRINT: return LowerFRINT (Op, DAG);
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case ISD::FNEARBYINT: return LowerFNEARBYINT (Op, DAG);
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+ case ISD::FROUNDEVEN:
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+ return LowerFROUNDEVEN (Op, DAG);
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case ISD::FROUND: return LowerFROUND (Op, DAG);
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case ISD::FFLOOR: return LowerFFLOOR (Op, DAG);
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case ISD::FLOG:
@@ -2244,6 +2248,13 @@ SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) con
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return DAG.getNode (ISD::FRINT, SDLoc (Op), Op.getValueType (), Op.getOperand (0 ));
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}
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+ SDValue AMDGPUTargetLowering::LowerFROUNDEVEN (SDValue Op,
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+ SelectionDAG &DAG) const {
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+ auto VT = Op.getValueType ();
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+ auto Arg = Op.getOperand (0u );
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+ return DAG.getNode (ISD::FRINT, SDLoc (Op), VT, Arg);
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+ }
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+
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// XXX - May require not supporting f32 denormals?
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// Don't handle v2f16. The extra instructions to scalarize and repack around the
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