[RISCV] Pin a test to scalar lowering to preserve test intent [nfc]

In an upcoming change to enable fixed length vector lowering via vector registers, the codepath exercised would change.  Pin this to the old lowering.

Author: preames

llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll

@@ -1,8 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
-; RUN:     | FileCheck %s --check-prefix=RV32
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
-; RUN:     | FileCheck %s --check-prefix=RV64
+; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \
+; RUN:     -riscv-v-vector-bits-min=0 < %s | FileCheck %s --check-prefix=RV32
+; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
+; RUN:     -riscv-v-vector-bits-min=0 < %s | FileCheck %s --check-prefix=RV64
 
 ; This test would lead one of the DAGCombiner's visitVSELECT optimizations to
 ; call getSetCCResultType, from which we'd return an invalid MVT (<3 x i1>)