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[RISCV] Add support for new unprivileged extensions defined in profiles spec (#77458)
This adds minimal support for 7 new unprivileged extensions that were defined as a part of the RISC-V Profiles specification here: https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#7-new-isa-extensions * Ziccif: Main memory supports instruction fetch with atomicity requirement * Ziccrse: Main memory supports forward progress on LR/SC sequences * Ziccamoa: Main memory supports all atomics in A * Zicclsm: Main memory supports misaligned loads/stores * Za64rs: Reservation set size of 64 bytes * Za128rs: Reservation set size of 128 bytes * Zic64b: Cache block size isf 64 bytes As stated in the specification, these extensions don't add any new features but describe existing features. So this patch only adds parsing and subtarget features.
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‎clang/test/Preprocessor/riscv-target-features.c

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@@ -52,6 +52,8 @@
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// CHECK-NOT: __riscv_xtheadsync {{.*$}}
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// CHECK-NOT: __riscv_xtheadvdot {{.*$}}
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// CHECK-NOT: __riscv_xventanacondops {{.*$}}
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// CHECK-NOT: __riscv_za128rs {{.*$}}
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// CHECK-NOT: __riscv_za64rs {{.*$}}
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// CHECK-NOT: __riscv_zawrs {{.*$}}
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// CHECK-NOT: __riscv_zba {{.*$}}
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// CHECK-NOT: __riscv_zbb {{.*$}}
@@ -73,9 +75,14 @@
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// CHECK-NOT: __riscv_zfinx {{.*$}}
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// CHECK-NOT: __riscv_zhinx {{.*$}}
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// CHECK-NOT: __riscv_zhinxmin {{.*$}}
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// CHECK-NOT: __riscv_zic64b {{.*$}}
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// CHECK-NOT: __riscv_zicbom {{.*$}}
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// CHECK-NOT: __riscv_zicbop {{.*$}}
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// CHECK-NOT: __riscv_zicboz {{.*$}}
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// CHECK-NOT: __riscv_ziccamoa {{.*$}}
83+
// CHECK-NOT: __riscv_ziccif {{.*$}}
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// CHECK-NOT: __riscv_zicclsm {{.*$}}
85+
// CHECK-NOT: __riscv_ziccrse {{.*$}}
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// CHECK-NOT: __riscv_zicntr {{.*$}}
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// CHECK-NOT: __riscv_zicsr {{.*$}}
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// CHECK-NOT: __riscv_zifencei {{.*$}}
@@ -473,6 +480,22 @@
473480
// RUN: -o - | FileCheck --check-prefix=CHECK-XVENTANACONDOPS-EXT %s
474481
// CHECK-XVENTANACONDOPS-EXT: __riscv_xventanacondops 1000000{{$}}
475482

483+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
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// RUN: -march=rv32iza128rs -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZA128RS-EXT %s
486+
// RUN: %clang --target=riscv64-unknown-linux-gnu \
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// RUN: -march=rv64iza128rs -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZA128RS-EXT %s
489+
// CHECK-ZA128RS-EXT: __riscv_za128rs 1000000{{$}}
490+
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// RUN: %clang --target=riscv32-unknown-linux-gnu \
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// RUN: -march=rv32iza64rs -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZA64RS-EXT %s
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// RUN: %clang --target=riscv64-unknown-linux-gnu \
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// RUN: -march=rv64iza64rs -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZA64RS-EXT %s
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// CHECK-ZA64RS-EXT: __riscv_za64rs 1000000{{$}}
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476499
// RUN: %clang --target=riscv32-unknown-linux-gnu \
477500
// RUN: -march=rv32izawrs -x c -E -dM %s \
478501
// RUN: -o - | FileCheck --check-prefix=CHECK-ZAWRS-EXT %s
@@ -667,6 +690,14 @@
667690
// RUN: -o - | FileCheck --check-prefix=CHECK-ZHINXMIN-EXT %s
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// CHECK-ZHINXMIN-EXT: __riscv_zhinxmin 1000000{{$}}
669692

693+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
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// RUN: -march=rv32izic64b -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZIC64B-EXT %s
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// RUN: %clang --target=riscv64-unknown-linux-gnu \
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// RUN: -march=rv64izic64b -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZIC64B-EXT %s
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// CHECK-ZIC64B-EXT: __riscv_zic64b 1000000{{$}}
700+
670701
// RUN: %clang --target=riscv32-unknown-linux-gnu \
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// RUN: -march=rv32izicbom -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZICBOM-EXT %s
@@ -691,6 +722,38 @@
691722
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICBOZ-EXT %s
692723
// CHECK-ZICBOZ-EXT: __riscv_zicboz 1000000{{$}}
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725+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
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// RUN: -march=rv32iziccamoa -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZICCAMOA-EXT %s
728+
// RUN: %clang --target=riscv64-unknown-linux-gnu \
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// RUN: -march=rv64iziccamoa -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZICCAMOA-EXT %s
731+
// CHECK-ZICCAMOA-EXT: __riscv_ziccamoa 1000000{{$}}
732+
733+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
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// RUN: -march=rv32iziccif -x c -E -dM %s \
735+
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICCIF-EXT %s
736+
// RUN: %clang --target=riscv64-unknown-linux-gnu \
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// RUN: -march=rv64iziccif -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZICCIF-EXT %s
739+
// CHECK-ZICCIF-EXT: __riscv_ziccif 1000000{{$}}
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741+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
742+
// RUN: -march=rv32izicclsm -x c -E -dM %s \
743+
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICCLSM-EXT %s
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// RUN: %clang --target=riscv64-unknown-linux-gnu \
745+
// RUN: -march=rv64izicclsm -x c -E -dM %s \
746+
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICCLSM-EXT %s
747+
// CHECK-ZICCLSM-EXT: __riscv_zicclsm 1000000{{$}}
748+
749+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
750+
// RUN: -march=rv32iziccrse -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZICCRSE-EXT %s
752+
// RUN: %clang --target=riscv64-unknown-linux-gnu \
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// RUN: -march=rv64iziccrse -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZICCRSE-EXT %s
755+
// CHECK-ZICCRSE-EXT: __riscv_ziccrse 1000000{{$}}
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// RUN: %clang --target=riscv32-unknown-linux-gnu \
695758
// RUN: -march=rv32izicntr -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZICNTR-EXT %s

‎llvm/docs/RISCVUsage.rst

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@@ -97,6 +97,8 @@ on support follow.
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``Svnapot`` Assembly Support
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``Svpbmt`` Supported
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``V`` Supported
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``Za128rs`` Supported (`See note <#riscv-profiles-extensions-note>`__)
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``Za64rs`` Supported (`See note <#riscv-profiles-extensions-note>`__)
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``Zawrs`` Assembly Support
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``Zba`` Supported
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``Zbb`` Supported
@@ -118,9 +120,14 @@ on support follow.
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``Zfinx`` Supported
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``Zhinx`` Supported
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``Zhinxmin`` Supported
123+
``Zic64b`` Supported (`See note <#riscv-profiles-extensions-note>`__)
121124
``Zicbom`` Assembly Support
122125
``Zicbop`` Supported
123126
``Zicboz`` Assembly Support
127+
``Ziccamoa`` Supported (`See note <#riscv-profiles-extensions-note>`__)
128+
``Ziccif`` Supported (`See note <#riscv-profiles-extensions-note>`__)
129+
``Zicclsm`` Supported (`See note <#riscv-profiles-extensions-note>`__)
130+
``Ziccrse`` Supported (`See note <#riscv-profiles-extensions-note>`__)
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``Zicntr`` (`See Note <#riscv-i2p1-note>`__)
125132
``Zicsr`` (`See Note <#riscv-i2p1-note>`__)
126133
``Zifencei`` (`See Note <#riscv-i2p1-note>`__)
@@ -205,6 +212,11 @@ Supported
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``zicntr``, ``zicsr``, ``zifencei``, ``zihpm``
206213
Between versions 2.0 and 2.1 of the base I specification, a backwards incompatible change was made to remove selected instructions and CSRs from the base ISA. These instructions were grouped into a set of new extensions, but were no longer required by the base ISA. This change is partially described in "Preface to Document Version 20190608-Base-Ratified" from the specification document (the ``zicntr`` and ``zihpm`` bits are not mentioned). LLVM currently implements version 2.1 of the base specification. To maintain compatibility, instructions from these extensions are accepted without being in the ``-march`` string. LLVM also allows the explicit specification of the extensions in an ``-march`` string.
207214

215+
.. _riscv-profiles-extensions-note:
216+
217+
``Za128rs``, ``Za64rs``, ``Zic64b``, ``Ziccamoa``, ``Ziccif``, ``Zicclsm``, ``Ziccrse``
218+
These extensions are defined as part of the `RISC-V Profiles specification <https://github.com/riscv/riscv-profiles/releases/tag/v1.0>`_. They do not introduce any new features themselves, but instead describe existing hardware features.
219+
208220
Experimental Extensions
209221
=======================
210222

‎llvm/docs/ReleaseNotes.rst

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@@ -157,6 +157,9 @@ Changes to the RISC-V Backend
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* ``-mcpu=sifive-p450`` was added.
158158
* CodeGen of RV32E/RV64E was supported experimentally.
159159
* CodeGen of ilp32e/lp64e was supported experimentally.
160+
* Support was added for the Ziccif, Ziccrse, Ziccamoa, Zicclsm, Za64rs, Za128rs
161+
and Zic64b extensions which were introduced as a part of the RISC-V Profiles
162+
specification.
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161164
Changes to the WebAssembly Backend
162165
----------------------------------

‎llvm/lib/Support/RISCVISAInfo.cpp

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@@ -88,6 +88,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
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{"xtheadvdot", {1, 0}},
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{"xventanacondops", {1, 0}},
9090

91+
{"za128rs", {1, 0}},
92+
{"za64rs", {1, 0}},
9193
{"zawrs", {1, 0}},
9294

9395
{"zba", {1, 0}},
@@ -116,9 +118,14 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
116118
{"zhinx", {1, 0}},
117119
{"zhinxmin", {1, 0}},
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121+
{"zic64b", {1, 0}},
119122
{"zicbom", {1, 0}},
120123
{"zicbop", {1, 0}},
121124
{"zicboz", {1, 0}},
125+
{"ziccamoa", {1, 0}},
126+
{"ziccif", {1, 0}},
127+
{"zicclsm", {1, 0}},
128+
{"ziccrse", {1, 0}},
122129
{"zicntr", {2, 0}},
123130
{"zicsr", {2, 0}},
124131
{"zifencei", {2, 0}},

‎llvm/lib/Target/RISCV/RISCVFeatures.td

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@@ -93,6 +93,22 @@ def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
9393
AssemblerPredicate<(all_of FeatureStdExtZifencei),
9494
"'Zifencei' (fence.i)">;
9595

96+
def FeatureStdExtZiccamoa
97+
: SubtargetFeature<"ziccamoa", "HasStdExtZiccamoa", "true",
98+
"'Ziccamoa' (Main Memory Supports All Atomics in A)">;
99+
100+
def FeatureStdExtZiccif
101+
: SubtargetFeature<"ziccif", "HasStdExtZiccif", "true",
102+
"'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)">;
103+
104+
def FeatureStdExtZicclsm
105+
: SubtargetFeature<"zicclsm", "HasStdExtZicclsm", "true",
106+
"'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)">;
107+
108+
def FeatureStdExtZiccrse
109+
: SubtargetFeature<"ziccrse", "HasStdExtZiccrse", "true",
110+
"'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)">;
111+
96112
def FeatureStdExtZicntr
97113
: SubtargetFeature<"zicntr", "HasStdExtZicntr", "true",
98114
"'Zicntr' (Base Counters and Timers)",
@@ -517,6 +533,10 @@ def HasStdExtZfhOrZvfh
517533
"'Zfh' (Half-Precision Floating-Point) or "
518534
"'Zvfh' (Vector Half-Precision Floating-Point)">;
519535

536+
def FeatureStdExtZic64b
537+
: SubtargetFeature<"zic64b", "HasStdExtZic64b", "true",
538+
"'Zic64b' (Cache Block Size Is 64 Bytes)">;
539+
520540
def FeatureStdExtZicbom
521541
: SubtargetFeature<"zicbom", "HasStdExtZicbom", "true",
522542
"'Zicbom' (Cache-Block Management Instructions)">;
@@ -561,6 +581,12 @@ def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZtso()">,
561581
"'Ztso' (Memory Model - Total Store Order)">;
562582
def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
563583

584+
def FeatureStdExtZa64rs : SubtargetFeature<"za64rs", "HasStdExtZa64rs", "true",
585+
"'Za64rs' (Reservation Set Size of at Most 64 Bytes)">;
586+
587+
def FeatureStdExtZa128rs : SubtargetFeature<"za128rs", "HasStdExtZa128rs", "true",
588+
"'Za128rs' (Reservation Set Size of at Most 128 Bytes)">;
589+
564590
def FeatureStdExtZawrs : SubtargetFeature<"zawrs", "HasStdExtZawrs", "true",
565591
"'Zawrs' (Wait on Reservation Set)">;
566592
def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,

‎llvm/test/CodeGen/RISCV/attributes.ll

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Original file line numberDiff line numberDiff line change
@@ -130,6 +130,7 @@
130130
; RUN: llc -mtriple=riscv64 -mattr=+zkn,+zkr,+zkt %s -o - | FileCheck --check-prefixes=CHECK,RV64COMBINEINTOZK %s
131131
; RUN: llc -mtriple=riscv64 -mattr=+zbkb,+zbkc,+zbkx,+zkne,+zknd,+zknh %s -o - | FileCheck --check-prefixes=CHECK,RV64COMBINEINTOZKN %s
132132
; RUN: llc -mtriple=riscv64 -mattr=+zbkb,+zbkc,+zbkx,+zksed,+zksh %s -o - | FileCheck --check-prefixes=CHECK,RV64COMBINEINTOZKS %s
133+
; RUN: llc -mtriple=riscv64 -mattr=+zic64b %s -o - | FileCheck --check-prefixes=CHECK,RV64ZIC64B %s
133134
; RUN: llc -mtriple=riscv64 -mattr=+zicbom %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICBOM %s
134135
; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICBOZ %s
135136
; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICBOP %s
@@ -149,13 +150,19 @@
149150
; RUN: llc -mtriple=riscv64 -mattr=+xtheadmempair %s -o - | FileCheck --check-prefix=RV64XTHEADMEMPAIR %s
150151
; RUN: llc -mtriple=riscv64 -mattr=+xtheadsync %s -o - | FileCheck --check-prefix=RV64XTHEADSYNC %s
151152
; RUN: llc -mtriple=riscv64 -mattr=+xtheadvdot %s -o - | FileCheck --check-prefixes=CHECK,RV64XTHEADVDOT %s
153+
; RUN: llc -mtriple=riscv64 -mattr=+za64rs %s -o - | FileCheck --check-prefixes=CHECK,RV64ZA64RS %s
154+
; RUN: llc -mtriple=riscv64 -mattr=+za128rs %s -o - | FileCheck --check-prefixes=CHECK,RV64ZA128RS %s
152155
; RUN: llc -mtriple=riscv64 -mattr=+zawrs %s -o - | FileCheck --check-prefixes=CHECK,RV64ZAWRS %s
153156
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefixes=CHECK,RV64ZTSO %s
154157
; RUN: llc -mtriple=riscv64 -mattr=+zca %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCA %s
155158
; RUN: llc -mtriple=riscv64 -mattr=+zcb %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCB %s
156159
; RUN: llc -mtriple=riscv64 -mattr=+zcd %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCD %s
157160
; RUN: llc -mtriple=riscv64 -mattr=+zcmp %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCMP %s
158161
; RUN: llc -mtriple=riscv64 -mattr=+zcmt %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCMT %s
162+
; RUN: llc -mtriple=riscv64 -mattr=+ziccamoa %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICCAMOA %s
163+
; RUN: llc -mtriple=riscv64 -mattr=+ziccif %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICCIF %s
164+
; RUN: llc -mtriple=riscv64 -mattr=+zicclsm %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICCLSM %s
165+
; RUN: llc -mtriple=riscv64 -mattr=+ziccrse %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICCRSE %s
159166
; RUN: llc -mtriple=riscv64 -mattr=+zicsr %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICSR %s
160167
; RUN: llc -mtriple=riscv64 -mattr=+zifencei %s -o - | FileCheck --check-prefixes=CHECK,RV64ZIFENCEI %s
161168
; RUN: llc -mtriple=riscv64 -mattr=+zicntr %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICNTR %s
@@ -319,8 +326,11 @@
319326
; RV64COMBINEINTOZK: .attribute 5, "rv64i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
320327
; RV64COMBINEINTOZKN: .attribute 5, "rv64i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
321328
; RV64COMBINEINTOZKS: .attribute 5, "rv64i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
329+
; RV64ZIC64B: .attribute 5, "rv64i2p1_zic64b1p0"
322330
; RV64ZICBOM: .attribute 5, "rv64i2p1_zicbom1p0"
323331
; RV64ZICBOZ: .attribute 5, "rv64i2p1_zicboz1p0"
332+
; RV64ZA64RS: .attribute 5, "rv64i2p1_za64rs1p0"
333+
; RV64ZA128RS: .attribute 5, "rv64i2p1_za128rs1p0"
324334
; RV64ZAWRS: .attribute 5, "rv64i2p1_zawrs1p0"
325335
; RV64ZICBOP: .attribute 5, "rv64i2p1_zicbop1p0"
326336
; RV64SVNAPOT: .attribute 5, "rv64i2p1_svnapot1p0"
@@ -345,6 +355,10 @@
345355
; RV64ZCD: .attribute 5, "rv64i2p1_f2p2_d2p2_zicsr2p0_zca1p0_zcd1p0"
346356
; RV64ZCMP: .attribute 5, "rv64i2p1_zca1p0_zcmp1p0"
347357
; RV64ZCMT: .attribute 5, "rv64i2p1_zicsr2p0_zca1p0_zcmt1p0"
358+
; RV64ZICCAMOA: .attribute 5, "rv64i2p1_ziccamoa1p0"
359+
; RV64ZICCIF: .attribute 5, "rv64i2p1_ziccif1p0"
360+
; RV64ZICCLSM: .attribute 5, "rv64i2p1_zicclsm1p0"
361+
; RV64ZICCRSE: .attribute 5, "rv64i2p1_ziccrse1p0"
348362
; RV64ZICSR: .attribute 5, "rv64i2p1_zicsr2p0"
349363
; RV64ZIFENCEI: .attribute 5, "rv64i2p1_zifencei2p0"
350364
; RV64ZICNTR: .attribute 5, "rv64i2p1_zicntr2p0_zicsr2p0"

‎llvm/test/MC/RISCV/attribute-arch.s

Lines changed: 22 additions & 1 deletion
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@@ -91,6 +91,9 @@
9191
.attribute arch, "rv32ifdzve64d"
9292
# CHECK: attribute 5, "rv32i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
9393

94+
.attribute arch, "rv32izic64b"
95+
# CHECK: attribute 5, "rv32i2p1_zic64b1p0"
96+
9497
.attribute arch, "rv32izicbom"
9598
# CHECK: attribute 5, "rv32i2p1_zicbom1p0"
9699

@@ -100,6 +103,18 @@
100103
.attribute arch, "rv32izicbop"
101104
# CHECK: attribute 5, "rv32i2p1_zicbop1p0"
102105

106+
.attribute arch, "rv32iziccamoa"
107+
# CHECK: attribute 5, "rv32i2p1_ziccamoa1p0"
108+
109+
.attribute arch, "rv32iziccif"
110+
# CHECK: attribute 5, "rv32i2p1_ziccif1p0"
111+
112+
.attribute arch, "rv32izicclsm"
113+
# CHECK: attribute 5, "rv32i2p1_zicclsm1p0"
114+
115+
.attribute arch, "rv32iziccrse"
116+
# CHECK: attribute 5, "rv32i2p1_ziccrse1p0"
117+
103118
## Experimental extensions require version string to be explicitly specified
104119

105120
.attribute arch, "rv32izba1p0"
@@ -125,7 +140,7 @@
125140

126141
.attribute arch, "rv32i_zve64x_zvkn1p0"
127142
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvkned1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
128-
143+
129144
.attribute arch, "rv32i_zve64x_zvknc1p0"
130145
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
131146

@@ -249,6 +264,12 @@
249264
.attribute arch, "rv64i_xsfvcp"
250265
# CHECK: attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfvcp1p0"
251266

267+
.attribute arch, "rv32iza128rs1p0"
268+
# CHECK: attribute 5, "rv32i2p1_za128rs1p0"
269+
270+
.attribute arch, "rv32iza64rs1p0"
271+
# CHECK: attribute 5, "rv32i2p1_za64rs1p0"
272+
252273
.attribute arch, "rv32izawrs1p0"
253274
# CHECK: attribute 5, "rv32i2p1_zawrs1p0"
254275

‎llvm/unittests/Support/RISCVISAInfoTest.cpp

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -675,16 +675,23 @@ R"(All available -march extensions for RISC-V
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c 2.0
676676
v 1.0
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h 1.0
678+
zic64b 1.0
678679
zicbom 1.0
679680
zicbop 1.0
680681
zicboz 1.0
682+
ziccamoa 1.0
683+
ziccif 1.0
684+
zicclsm 1.0
685+
ziccrse 1.0
681686
zicntr 2.0
682687
zicsr 2.0
683688
zifencei 2.0
684689
zihintntl 1.0
685690
zihintpause 2.0
686691
zihpm 2.0
687692
zmmul 1.0
693+
za128rs 1.0
694+
za64rs 1.0
688695
zawrs 1.0
689696
zfa 1.0
690697
zfh 1.0

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