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[AMDGPU] Enable serializing of argument info.
Summary: - Support serialization of all arguments in machine function info. This enables fabricating MIR tests depending on argument info. Reviewers: arsenm, rampitec Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64096 llvm-svn: 364995
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lines changed

6 files changed

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‎llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

Lines changed: 79 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1059,5 +1059,84 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
10591059
return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
10601060
}
10611061

1062+
auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1063+
const TargetRegisterClass &RC,
1064+
ArgDescriptor &Arg) {
1065+
// Skip parsing if it's not present.
1066+
if (!A)
1067+
return false;
1068+
1069+
if (A->IsRegister) {
1070+
unsigned Reg;
1071+
if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value,
1072+
Error)) {
1073+
SourceRange = A->RegisterName.SourceRange;
1074+
return true;
1075+
}
1076+
if (!RC.contains(Reg))
1077+
return diagnoseRegisterClass(A->RegisterName);
1078+
Arg = ArgDescriptor::createRegister(Reg);
1079+
} else
1080+
Arg = ArgDescriptor::createStack(A->StackOffset);
1081+
// Check and apply the optional mask.
1082+
if (A->Mask)
1083+
Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1084+
1085+
return false;
1086+
};
1087+
1088+
if (YamlMFI.ArgInfo &&
1089+
(parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1090+
AMDGPU::SReg_128RegClass,
1091+
MFI->ArgInfo.PrivateSegmentBuffer) ||
1092+
parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1093+
AMDGPU::SReg_64RegClass,
1094+
MFI->ArgInfo.DispatchPtr) ||
1095+
parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1096+
MFI->ArgInfo.QueuePtr) ||
1097+
parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1098+
AMDGPU::SReg_64RegClass,
1099+
MFI->ArgInfo.KernargSegmentPtr) ||
1100+
parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1101+
AMDGPU::SReg_64RegClass,
1102+
MFI->ArgInfo.DispatchID) ||
1103+
parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1104+
AMDGPU::SReg_64RegClass,
1105+
MFI->ArgInfo.FlatScratchInit) ||
1106+
parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1107+
AMDGPU::SGPR_32RegClass,
1108+
MFI->ArgInfo.PrivateSegmentSize) ||
1109+
parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1110+
AMDGPU::SGPR_32RegClass,
1111+
MFI->ArgInfo.WorkGroupIDX) ||
1112+
parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1113+
AMDGPU::SGPR_32RegClass,
1114+
MFI->ArgInfo.WorkGroupIDY) ||
1115+
parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1116+
AMDGPU::SGPR_32RegClass,
1117+
MFI->ArgInfo.WorkGroupIDZ) ||
1118+
parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1119+
AMDGPU::SGPR_32RegClass,
1120+
MFI->ArgInfo.WorkGroupInfo) ||
1121+
parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1122+
AMDGPU::SGPR_32RegClass,
1123+
MFI->ArgInfo.PrivateSegmentWaveByteOffset) ||
1124+
parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1125+
AMDGPU::SReg_64RegClass,
1126+
MFI->ArgInfo.ImplicitArgPtr) ||
1127+
parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1128+
AMDGPU::SReg_64RegClass,
1129+
MFI->ArgInfo.ImplicitBufferPtr) ||
1130+
parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1131+
AMDGPU::VGPR_32RegClass,
1132+
MFI->ArgInfo.WorkItemIDX) ||
1133+
parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1134+
AMDGPU::VGPR_32RegClass,
1135+
MFI->ArgInfo.WorkItemIDY) ||
1136+
parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1137+
AMDGPU::VGPR_32RegClass,
1138+
MFI->ArgInfo.WorkItemIDZ)))
1139+
return true;
1140+
10621141
return false;
10631142
}

‎llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

Lines changed: 53 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -324,6 +324,57 @@ static yaml::StringValue regToString(unsigned Reg,
324324
return Dest;
325325
}
326326

327+
static Optional<yaml::SIArgumentInfo>
328+
convertArgumentInfo(const AMDGPUFunctionArgInfo &ArgInfo,
329+
const TargetRegisterInfo &TRI) {
330+
yaml::SIArgumentInfo AI;
331+
332+
auto convertArg = [&](Optional<yaml::SIArgument> &A,
333+
const ArgDescriptor &Arg) {
334+
if (!Arg)
335+
return false;
336+
337+
// Create a register or stack argument.
338+
yaml::SIArgument SA = yaml::SIArgument::createArgument(Arg.isRegister());
339+
if (Arg.isRegister()) {
340+
raw_string_ostream OS(SA.RegisterName.Value);
341+
OS << printReg(Arg.getRegister(), &TRI);
342+
} else
343+
SA.StackOffset = Arg.getStackOffset();
344+
// Check and update the optional mask.
345+
if (Arg.isMasked())
346+
SA.Mask = Arg.getMask();
347+
348+
A = SA;
349+
return true;
350+
};
351+
352+
bool Any = false;
353+
Any |= convertArg(AI.PrivateSegmentBuffer, ArgInfo.PrivateSegmentBuffer);
354+
Any |= convertArg(AI.DispatchPtr, ArgInfo.DispatchPtr);
355+
Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr);
356+
Any |= convertArg(AI.KernargSegmentPtr, ArgInfo.KernargSegmentPtr);
357+
Any |= convertArg(AI.DispatchID, ArgInfo.DispatchID);
358+
Any |= convertArg(AI.FlatScratchInit, ArgInfo.FlatScratchInit);
359+
Any |= convertArg(AI.PrivateSegmentSize, ArgInfo.PrivateSegmentSize);
360+
Any |= convertArg(AI.WorkGroupIDX, ArgInfo.WorkGroupIDX);
361+
Any |= convertArg(AI.WorkGroupIDY, ArgInfo.WorkGroupIDY);
362+
Any |= convertArg(AI.WorkGroupIDZ, ArgInfo.WorkGroupIDZ);
363+
Any |= convertArg(AI.WorkGroupInfo, ArgInfo.WorkGroupInfo);
364+
Any |= convertArg(AI.PrivateSegmentWaveByteOffset,
365+
ArgInfo.PrivateSegmentWaveByteOffset);
366+
Any |= convertArg(AI.ImplicitArgPtr, ArgInfo.ImplicitArgPtr);
367+
Any |= convertArg(AI.ImplicitBufferPtr, ArgInfo.ImplicitBufferPtr);
368+
Any |= convertArg(AI.WorkItemIDX, ArgInfo.WorkItemIDX);
369+
Any |= convertArg(AI.WorkItemIDY, ArgInfo.WorkItemIDY);
370+
Any |= convertArg(AI.WorkItemIDZ, ArgInfo.WorkItemIDZ);
371+
372+
if (Any)
373+
return AI;
374+
375+
return None;
376+
}
377+
327378
yaml::SIMachineFunctionInfo::SIMachineFunctionInfo(
328379
const llvm::SIMachineFunctionInfo& MFI,
329380
const TargetRegisterInfo &TRI)
@@ -337,7 +388,8 @@ yaml::SIMachineFunctionInfo::SIMachineFunctionInfo(
337388
ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
338389
ScratchWaveOffsetReg(regToString(MFI.getScratchWaveOffsetReg(), TRI)),
339390
FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
340-
StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)) {}
391+
StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
392+
ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)) {}
341393

342394
void yaml::SIMachineFunctionInfo::mappingImpl(yaml::IO &YamlIO) {
343395
MappingTraits<SIMachineFunctionInfo>::mapping(YamlIO, *this);

‎llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h

Lines changed: 121 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,7 @@
2121
#include "llvm/ADT/ArrayRef.h"
2222
#include "llvm/ADT/DenseMap.h"
2323
#include "llvm/ADT/Optional.h"
24+
#include "llvm/ADT/STLExtras.h"
2425
#include "llvm/ADT/SmallVector.h"
2526
#include "llvm/ADT/SparseBitVector.h"
2627
#include "llvm/CodeGen/MIRYamlMapping.h"
@@ -114,6 +115,123 @@ class AMDGPUGWSResourcePseudoSourceValue final : public AMDGPUPseudoSourceValue
114115

115116
namespace yaml {
116117

118+
struct SIArgument {
119+
bool IsRegister;
120+
union {
121+
StringValue RegisterName;
122+
unsigned StackOffset;
123+
};
124+
Optional<unsigned> Mask;
125+
126+
// Default constructor, which creates a stack argument.
127+
SIArgument() : IsRegister(false), StackOffset(0) {}
128+
SIArgument(const SIArgument &Other) {
129+
IsRegister = Other.IsRegister;
130+
if (IsRegister) {
131+
::new ((void *)std::addressof(RegisterName))
132+
StringValue(Other.RegisterName);
133+
} else
134+
StackOffset = Other.StackOffset;
135+
Mask = Other.Mask;
136+
}
137+
SIArgument &operator=(const SIArgument &Other) {
138+
IsRegister = Other.IsRegister;
139+
if (IsRegister) {
140+
::new ((void *)std::addressof(RegisterName))
141+
StringValue(Other.RegisterName);
142+
} else
143+
StackOffset = Other.StackOffset;
144+
Mask = Other.Mask;
145+
return *this;
146+
}
147+
~SIArgument() {
148+
if (IsRegister)
149+
RegisterName.~StringValue();
150+
}
151+
152+
// Helper to create a register or stack argument.
153+
static inline SIArgument createArgument(bool IsReg) {
154+
if (IsReg)
155+
return SIArgument(IsReg);
156+
return SIArgument();
157+
}
158+
159+
private:
160+
// Construct a register argument.
161+
SIArgument(bool) : IsRegister(true), RegisterName() {}
162+
};
163+
164+
template <> struct MappingTraits<SIArgument> {
165+
static void mapping(IO &YamlIO, SIArgument &A) {
166+
if (YamlIO.outputting()) {
167+
if (A.IsRegister)
168+
YamlIO.mapRequired("reg", A.RegisterName);
169+
else
170+
YamlIO.mapRequired("offset", A.StackOffset);
171+
} else {
172+
auto Keys = YamlIO.keys();
173+
if (is_contained(Keys, "reg")) {
174+
A = SIArgument::createArgument(true);
175+
YamlIO.mapRequired("reg", A.RegisterName);
176+
} else if (is_contained(Keys, "offset"))
177+
YamlIO.mapRequired("offset", A.StackOffset);
178+
else
179+
YamlIO.setError("missing required key 'reg' or 'offset'");
180+
}
181+
YamlIO.mapOptional("mask", A.Mask);
182+
}
183+
static const bool flow = true;
184+
};
185+
186+
struct SIArgumentInfo {
187+
Optional<SIArgument> PrivateSegmentBuffer;
188+
Optional<SIArgument> DispatchPtr;
189+
Optional<SIArgument> QueuePtr;
190+
Optional<SIArgument> KernargSegmentPtr;
191+
Optional<SIArgument> DispatchID;
192+
Optional<SIArgument> FlatScratchInit;
193+
Optional<SIArgument> PrivateSegmentSize;
194+
195+
Optional<SIArgument> WorkGroupIDX;
196+
Optional<SIArgument> WorkGroupIDY;
197+
Optional<SIArgument> WorkGroupIDZ;
198+
Optional<SIArgument> WorkGroupInfo;
199+
Optional<SIArgument> PrivateSegmentWaveByteOffset;
200+
201+
Optional<SIArgument> ImplicitArgPtr;
202+
Optional<SIArgument> ImplicitBufferPtr;
203+
204+
Optional<SIArgument> WorkItemIDX;
205+
Optional<SIArgument> WorkItemIDY;
206+
Optional<SIArgument> WorkItemIDZ;
207+
};
208+
209+
template <> struct MappingTraits<SIArgumentInfo> {
210+
static void mapping(IO &YamlIO, SIArgumentInfo &AI) {
211+
YamlIO.mapOptional("privateSegmentBuffer", AI.PrivateSegmentBuffer);
212+
YamlIO.mapOptional("dispatchPtr", AI.DispatchPtr);
213+
YamlIO.mapOptional("queuePtr", AI.QueuePtr);
214+
YamlIO.mapOptional("kernargSegmentPtr", AI.KernargSegmentPtr);
215+
YamlIO.mapOptional("dispatchID", AI.DispatchID);
216+
YamlIO.mapOptional("flatScratchInit", AI.FlatScratchInit);
217+
YamlIO.mapOptional("privateSegmentSize", AI.PrivateSegmentSize);
218+
219+
YamlIO.mapOptional("workGroupIDX", AI.WorkGroupIDX);
220+
YamlIO.mapOptional("workGroupIDY", AI.WorkGroupIDY);
221+
YamlIO.mapOptional("workGroupIDZ", AI.WorkGroupIDZ);
222+
YamlIO.mapOptional("workGroupInfo", AI.WorkGroupInfo);
223+
YamlIO.mapOptional("privateSegmentWaveByteOffset",
224+
AI.PrivateSegmentWaveByteOffset);
225+
226+
YamlIO.mapOptional("implicitArgPtr", AI.ImplicitArgPtr);
227+
YamlIO.mapOptional("implicitBufferPtr", AI.ImplicitBufferPtr);
228+
229+
YamlIO.mapOptional("workItemIDX", AI.WorkItemIDX);
230+
YamlIO.mapOptional("workItemIDY", AI.WorkItemIDY);
231+
YamlIO.mapOptional("workItemIDZ", AI.WorkItemIDZ);
232+
}
233+
};
234+
117235
struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo {
118236
uint64_t ExplicitKernArgSize = 0;
119237
unsigned MaxKernArgAlign = 0;
@@ -128,6 +246,8 @@ struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo {
128246
StringValue FrameOffsetReg = "$fp_reg";
129247
StringValue StackPtrOffsetReg = "$sp_reg";
130248

249+
Optional<SIArgumentInfo> ArgInfo;
250+
131251
SIMachineFunctionInfo() = default;
132252
SIMachineFunctionInfo(const llvm::SIMachineFunctionInfo &,
133253
const TargetRegisterInfo &TRI);
@@ -154,6 +274,7 @@ template <> struct MappingTraits<SIMachineFunctionInfo> {
154274
StringValue("$fp_reg"));
155275
YamlIO.mapOptional("stackPtrOffsetReg", MFI.StackPtrOffsetReg,
156276
StringValue("$sp_reg"));
277+
YamlIO.mapOptional("argumentInfo", MFI.ArgInfo);
157278
}
158279
};
159280

‎llvm/test/CodeGen/AMDGPU/hazard-hidden-bundle.mir

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
# RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-WavefrontSize32,+WavefrontSize64 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,NOXNACK,GFX10 %s
44

55
# GCN-LABEL: name: break_smem_clause_simple_load_smrd8_ptr_hidden_bundle
6+
# GCN: bb.0:
67
# GCN: }
78
# XNACK-NEXT: S_NOP
89
# NOXNACK-NOT: S_NOP

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