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[RISCV] Add explicit types to some XTHead isel patterns to reduce RISCVGenDAGISel.inc size.
HWMode expansion of GPR can create patterns with i32 types with Subtarget->is64Bit() or i64 types with !Subtarget->is64Bit(). These patterns will never match. They just waste space in the table. By adding explicit i32 or i64 to patterns that only apply to RV32 or RV64 we can filter these patterns.
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llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -770,7 +770,7 @@ def : Pat<(vt (LoadOp (AddrRegRegScale GPR:$rs1, GPR:$rs2, uimm2:$uimm2))),
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}
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multiclass LdZextIdxPat<PatFrag LoadOp, RVInst Inst, ValueType vt = i64> {
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def : Pat<(vt (LoadOp (AddrRegZextRegScale GPR:$rs1, GPR:$rs2, uimm2:$uimm2))),
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def : Pat<(vt (LoadOp (AddrRegZextRegScale (i64 GPR:$rs1), GPR:$rs2, uimm2:$uimm2))),
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(Inst GPR:$rs1, GPR:$rs2, uimm2:$uimm2)>;
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}
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@@ -784,7 +784,7 @@ def : Pat<(StoreOp (vt StTy:$rd),
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multiclass StZextIdxPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy,
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ValueType vt = i64> {
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def : Pat<(StoreOp (vt StTy:$rd),
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(AddrRegZextRegScale GPR:$rs1, GPR:$rs2, uimm2:$uimm2)),
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(AddrRegZextRegScale (i64 GPR:$rs1), GPR:$rs2, uimm2:$uimm2)),
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(Inst StTy:$rd, GPR:$rs1, GPR:$rs2, uimm2:$uimm2)>;
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}
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@@ -869,13 +869,13 @@ defm : StoreUpdatePat<pre_truncsti16, TH_SHIB>;
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}
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let Predicates = [HasVendorXTHeadMemIdx, IsRV32] in {
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defm : StoreUpdatePat<post_store, TH_SWIA>;
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defm : StoreUpdatePat<pre_store, TH_SWIB>;
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defm : StoreUpdatePat<post_store, TH_SWIA, i32>;
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defm : StoreUpdatePat<pre_store, TH_SWIB, i32>;
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}
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let Predicates = [HasVendorXTHeadMemIdx, IsRV64] in {
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defm : StoreUpdatePat<post_truncsti32, TH_SWIA>;
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defm : StoreUpdatePat<pre_truncsti32, TH_SWIB>;
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defm : StoreUpdatePat<post_store, TH_SDIA>;
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defm : StoreUpdatePat<pre_store, TH_SDIB>;
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defm : StoreUpdatePat<post_truncsti32, TH_SWIA, i64>;
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defm : StoreUpdatePat<pre_truncsti32, TH_SWIB, i64>;
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defm : StoreUpdatePat<post_store, TH_SDIA, i64>;
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defm : StoreUpdatePat<pre_store, TH_SDIB, i64>;
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}

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