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[M68k] Override CanLowerReturn to fix assertion with large return
If it couldn't fit the return value in two registers, this caused an error during codegen. It seems this method is implemented in other backends but not here, and allows it to pass return values in memory when it isn't able to do so in registers. Seems to fix compilation of Rust code with certain return types: rust-lang/rust#89498 Differential Revision: https://reviews.llvm.org/D148856
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llvm/lib/Target/M68k/M68kISelLowering.cpp

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@@ -1058,6 +1058,14 @@ SDValue M68kTargetLowering::LowerFormalArguments(
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// Return Value Calling Convention Implementation
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//===----------------------------------------------------------------------===//
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bool M68kTargetLowering::CanLowerReturn(
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CallingConv::ID CCID, MachineFunction &MF, bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
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SmallVector<CCValAssign, 16> RVLocs;
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CCState CCInfo(CCID, IsVarArg, MF, RVLocs, Context);
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return CCInfo.CheckReturn(Outs, RetCC_M68k);
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}
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SDValue
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M68kTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CCID,
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bool IsVarArg,

llvm/lib/Target/M68k/M68kISelLowering.h

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@@ -257,6 +257,11 @@ class M68kTargetLowering : public TargetLowering {
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SDValue LowerCall(CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const override;
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bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
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bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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LLVMContext &Context) const override;
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/// Lower the result values of a call into the
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/// appropriate copies out of appropriate physical registers.
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SDValue LowerReturn(SDValue Chain, CallingConv::ID CCID, bool IsVarArg,
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=m68k-linux -verify-machineinstrs | FileCheck %s
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define { i32, i32, i32, i32 } @test() {
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; CHECK-LABEL: test:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: ; %bb.0: ; %start
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; CHECK-NEXT: move.l (4,%sp), %a0
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; CHECK-NEXT: move.l #23, (12,%a0)
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; CHECK-NEXT: move.l #19, (8,%a0)
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; CHECK-NEXT: move.l #17, (4,%a0)
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; CHECK-NEXT: move.l #13, (%a0)
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; CHECK-NEXT: move.l %a0, %d0
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; CHECK-NEXT: move.l (%sp), %a1
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; CHECK-NEXT: adda.l #4, %sp
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; CHECK-NEXT: move.l %a1, (%sp)
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; CHECK-NEXT: rts
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start:
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ret { i32, i32, i32, i32 } { i32 13, i32 17, i32 19, i32 23 }
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}

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