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[ARM] Add target feature to force 32-bit atomics
This adds a +atomic-32 target feature, which instructs LLVM to assume that lock-free 32-bit atomics are available for this target, even if they usually wouldn't be. If only atomic loads/stores are used, then this won't emit libcalls. If atomic CAS is used, then the user is responsible for providing any necessary __sync implementations (e.g. by masking interrupts for single-core privileged use cases). See https://reviews.llvm.org/D120026#3674333 for context on this change. The tl;dr is that the thumbv6m target in Rust has historically made atomic load/store only available, which is incompatible with the change from D120026, which switched these to use libatomic. Differential Revision: https://reviews.llvm.org/D130480 (cherry picked from commit b1b1086)
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‎llvm/lib/Target/ARM/ARM.td

+9
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@@ -556,6 +556,15 @@ def FeatureAAPCSFrameChainLeaf : SubtargetFeature<"aapcs-frame-chain-leaf",
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"for leaf functions",
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[FeatureAAPCSFrameChain]>;
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// Assume that lock-free 32-bit atomics are available, even if the target
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// and operating system combination would not usually provide them. The user
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// is responsible for providing any necessary __sync implementations. Code
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// built with this feature is not ABI-compatible with code built without this
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// feature, if atomic variables are exposed across the ABI boundary.
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def FeatureAtomics32 : SubtargetFeature<
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"atomics-32", "HasForced32BitAtomics", "true",
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"Assume that lock-free 32-bit atomics are available">;
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//===----------------------------------------------------------------------===//
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// ARM architecture class
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//

‎llvm/lib/Target/ARM/ARMISelLowering.cpp

+2-1
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@@ -1370,7 +1370,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
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// instructions. (ARMv6 doesn't have dmb, but it has an equivalent
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// encoding; see ARMISD::MEMBARRIER_MCR.)
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setMaxAtomicSizeInBitsSupported(64);
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} else if (Subtarget->isMClass() && Subtarget->hasV8MBaselineOps()) {
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} else if ((Subtarget->isMClass() && Subtarget->hasV8MBaselineOps()) ||
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Subtarget->hasForced32BitAtomics()) {
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// Cortex-M (besides Cortex-M0) have 32-bit atomics.
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setMaxAtomicSizeInBitsSupported(32);
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} else {

‎llvm/test/CodeGen/ARM/thumbv6m-atomic32.ll

+203
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@@ -0,0 +1,203 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv6m-none-eabi < %s | FileCheck %s --check-prefixes=CHECK,NO-ATOMIC32
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; RUN: llc -mtriple=thumbv6m-none-eabi -mattr=+atomics-32 < %s | FileCheck %s --check-prefixes=CHECK,ATOMIC32
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define i32 @load32(ptr %p) {
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; NO-ATOMIC32-LABEL: load32:
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; NO-ATOMIC32: @ %bb.0:
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; NO-ATOMIC32-NEXT: .save {r7, lr}
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; NO-ATOMIC32-NEXT: push {r7, lr}
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; NO-ATOMIC32-NEXT: movs r1, #5
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; NO-ATOMIC32-NEXT: bl __atomic_load_4
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; NO-ATOMIC32-NEXT: pop {r7, pc}
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;
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; ATOMIC32-LABEL: load32:
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; ATOMIC32: @ %bb.0:
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; ATOMIC32-NEXT: ldr r0, [r0]
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; ATOMIC32-NEXT: dmb sy
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; ATOMIC32-NEXT: bx lr
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%v = load atomic i32, ptr %p seq_cst, align 4
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ret i32 %v
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}
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define void @store32(ptr %p) {
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; NO-ATOMIC32-LABEL: store32:
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; NO-ATOMIC32: @ %bb.0:
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; NO-ATOMIC32-NEXT: .save {r7, lr}
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; NO-ATOMIC32-NEXT: push {r7, lr}
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; NO-ATOMIC32-NEXT: movs r1, #0
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; NO-ATOMIC32-NEXT: movs r2, #5
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; NO-ATOMIC32-NEXT: bl __atomic_store_4
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; NO-ATOMIC32-NEXT: pop {r7, pc}
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;
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; ATOMIC32-LABEL: store32:
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; ATOMIC32: @ %bb.0:
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; ATOMIC32-NEXT: dmb sy
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; ATOMIC32-NEXT: movs r1, #0
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; ATOMIC32-NEXT: str r1, [r0]
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; ATOMIC32-NEXT: dmb sy
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; ATOMIC32-NEXT: bx lr
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store atomic i32 0, ptr %p seq_cst, align 4
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ret void
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}
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define i32 @rmw32(ptr %p) {
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; NO-ATOMIC32-LABEL: rmw32:
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; NO-ATOMIC32: @ %bb.0:
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; NO-ATOMIC32-NEXT: .save {r7, lr}
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; NO-ATOMIC32-NEXT: push {r7, lr}
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; NO-ATOMIC32-NEXT: movs r1, #1
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; NO-ATOMIC32-NEXT: movs r2, #5
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; NO-ATOMIC32-NEXT: bl __atomic_fetch_add_4
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; NO-ATOMIC32-NEXT: pop {r7, pc}
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;
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; ATOMIC32-LABEL: rmw32:
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; ATOMIC32: @ %bb.0:
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; ATOMIC32-NEXT: .save {r7, lr}
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; ATOMIC32-NEXT: push {r7, lr}
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; ATOMIC32-NEXT: dmb sy
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; ATOMIC32-NEXT: movs r1, #1
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; ATOMIC32-NEXT: bl __sync_fetch_and_add_4
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; ATOMIC32-NEXT: dmb sy
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; ATOMIC32-NEXT: pop {r7, pc}
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%v = atomicrmw add ptr %p, i32 1 seq_cst, align 4
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ret i32 %v
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}
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define i32 @cmpxchg32(ptr %p) {
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; NO-ATOMIC32-LABEL: cmpxchg32:
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; NO-ATOMIC32: @ %bb.0:
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; NO-ATOMIC32-NEXT: .save {r7, lr}
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; NO-ATOMIC32-NEXT: push {r7, lr}
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; NO-ATOMIC32-NEXT: .pad #8
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; NO-ATOMIC32-NEXT: sub sp, #8
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; NO-ATOMIC32-NEXT: movs r1, #0
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; NO-ATOMIC32-NEXT: str r1, [sp, #4]
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; NO-ATOMIC32-NEXT: movs r3, #5
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; NO-ATOMIC32-NEXT: str r3, [sp]
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; NO-ATOMIC32-NEXT: add r1, sp, #4
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; NO-ATOMIC32-NEXT: movs r2, #1
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; NO-ATOMIC32-NEXT: bl __atomic_compare_exchange_4
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; NO-ATOMIC32-NEXT: ldr r0, [sp, #4]
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; NO-ATOMIC32-NEXT: add sp, #8
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; NO-ATOMIC32-NEXT: pop {r7, pc}
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;
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; ATOMIC32-LABEL: cmpxchg32:
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; ATOMIC32: @ %bb.0:
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; ATOMIC32-NEXT: .save {r7, lr}
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; ATOMIC32-NEXT: push {r7, lr}
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; ATOMIC32-NEXT: dmb sy
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; ATOMIC32-NEXT: movs r1, #0
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; ATOMIC32-NEXT: movs r2, #1
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; ATOMIC32-NEXT: bl __sync_val_compare_and_swap_4
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; ATOMIC32-NEXT: dmb sy
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; ATOMIC32-NEXT: pop {r7, pc}
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%res = cmpxchg ptr %p, i32 0, i32 1 seq_cst seq_cst
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%res.0 = extractvalue { i32, i1 } %res, 0
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ret i32 %res.0
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}
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define i64 @load64(ptr %p) {
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; CHECK-LABEL: load64:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: .pad #8
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; CHECK-NEXT: sub sp, #8
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; CHECK-NEXT: mov r1, r0
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; CHECK-NEXT: movs r0, #8
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; CHECK-NEXT: mov r2, sp
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; CHECK-NEXT: movs r3, #5
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; CHECK-NEXT: bl __atomic_load
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; CHECK-NEXT: ldr r1, [sp, #4]
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; CHECK-NEXT: ldr r0, [sp]
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; CHECK-NEXT: add sp, #8
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; CHECK-NEXT: pop {r7, pc}
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%v = load atomic i64, ptr %p seq_cst, align 4
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ret i64 %v
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}
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define void @store64(ptr %p) {
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; CHECK-LABEL: store64:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: .pad #8
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; CHECK-NEXT: sub sp, #8
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; CHECK-NEXT: mov r1, r0
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; CHECK-NEXT: movs r0, #0
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; CHECK-NEXT: str r0, [sp, #4]
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; CHECK-NEXT: str r0, [sp]
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; CHECK-NEXT: movs r0, #8
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; CHECK-NEXT: mov r2, sp
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; CHECK-NEXT: movs r3, #5
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; CHECK-NEXT: bl __atomic_store
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; CHECK-NEXT: add sp, #8
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; CHECK-NEXT: pop {r7, pc}
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store atomic i64 0, ptr %p seq_cst, align 4
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ret void
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}
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define i64 @rmw64(ptr %p) {
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; CHECK-LABEL: rmw64:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r4, lr}
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; CHECK-NEXT: push {r4, lr}
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; CHECK-NEXT: .pad #24
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; CHECK-NEXT: sub sp, #24
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; CHECK-NEXT: mov r4, r0
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; CHECK-NEXT: ldr r0, [r0]
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; CHECK-NEXT: ldr r1, [r4, #4]
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; CHECK-NEXT: .LBB6_1: @ %atomicrmw.start
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: str r0, [sp, #16]
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; CHECK-NEXT: str r1, [sp, #20]
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; CHECK-NEXT: movs r2, #0
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; CHECK-NEXT: adds r0, r0, #1
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; CHECK-NEXT: adcs r2, r1
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; CHECK-NEXT: str r2, [sp, #12]
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; CHECK-NEXT: str r0, [sp, #8]
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; CHECK-NEXT: movs r0, #5
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; CHECK-NEXT: str r0, [sp]
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; CHECK-NEXT: str r0, [sp, #4]
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; CHECK-NEXT: movs r0, #8
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; CHECK-NEXT: add r2, sp, #16
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; CHECK-NEXT: add r3, sp, #8
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; CHECK-NEXT: mov r1, r4
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; CHECK-NEXT: bl __atomic_compare_exchange
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; CHECK-NEXT: mov r2, r0
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; CHECK-NEXT: ldr r1, [sp, #20]
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; CHECK-NEXT: ldr r0, [sp, #16]
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: beq .LBB6_1
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; CHECK-NEXT: @ %bb.2: @ %atomicrmw.end
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; CHECK-NEXT: add sp, #24
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; CHECK-NEXT: pop {r4, pc}
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%v = atomicrmw add ptr %p, i64 1 seq_cst, align 4
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ret i64 %v
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}
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define i64 @cmpxchg64(ptr %p) {
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; CHECK-LABEL: cmpxchg64:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: .pad #16
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; CHECK-NEXT: sub sp, #16
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; CHECK-NEXT: movs r3, #0
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; CHECK-NEXT: str r3, [sp, #12]
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; CHECK-NEXT: str r3, [sp, #8]
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; CHECK-NEXT: movs r1, #5
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; CHECK-NEXT: str r1, [sp]
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; CHECK-NEXT: str r1, [sp, #4]
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; CHECK-NEXT: add r1, sp, #8
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; CHECK-NEXT: movs r2, #1
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; CHECK-NEXT: bl __atomic_compare_exchange_8
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; CHECK-NEXT: ldr r1, [sp, #12]
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; CHECK-NEXT: ldr r0, [sp, #8]
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; CHECK-NEXT: add sp, #16
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; CHECK-NEXT: pop {r7, pc}
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%res = cmpxchg ptr %p, i64 0, i64 1 seq_cst seq_cst
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%res.0 = extractvalue { i64, i1 } %res, 0
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ret i64 %res.0
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}

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