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[SelectionDAG] define binops as a superset of commutative binops
The test diffs show improved vector narrowing for integer min/max opcodes because those were all absent from the list. I'm not sure if we can expose functional diffs for all of the moved/added opcodes though. It seems like we are missing an AVX512 opportunity to use 256-bit ops in place of 512-bit ops on some tests/targets, but I think that can be a follow-up. Preliminary steps to make sure the callers are not misusing these queries: rL361268 rL361547 Differential Revision: https://reviews.llvm.org/D62191 llvm-svn: 361701
1 parent c9de92e commit 3f0905e

13 files changed

+658
-465
lines changed

‎llvm/include/llvm/CodeGen/TargetLowering.h

Lines changed: 26 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -2173,39 +2173,6 @@ class TargetLoweringBase {
21732173
return false;
21742174
}
21752175

2176-
/// Return true if the node is a math/logic binary operator.
2177-
virtual bool isBinOp(unsigned Opcode) const {
2178-
switch (Opcode) {
2179-
case ISD::ADD:
2180-
case ISD::SUB:
2181-
case ISD::MUL:
2182-
case ISD::AND:
2183-
case ISD::OR:
2184-
case ISD::XOR:
2185-
case ISD::SHL:
2186-
case ISD::SRL:
2187-
case ISD::SRA:
2188-
case ISD::SDIV:
2189-
case ISD::UDIV:
2190-
case ISD::SREM:
2191-
case ISD::UREM:
2192-
case ISD::FADD:
2193-
case ISD::FSUB:
2194-
case ISD::FMUL:
2195-
case ISD::FDIV:
2196-
case ISD::FREM:
2197-
case ISD::FMINNUM:
2198-
case ISD::FMAXNUM:
2199-
case ISD::FMINNUM_IEEE:
2200-
case ISD::FMAXNUM_IEEE:
2201-
case ISD::FMAXIMUM:
2202-
case ISD::FMINIMUM:
2203-
return true;
2204-
default:
2205-
return false;
2206-
}
2207-
}
2208-
22092176
/// Returns true if the opcode is a commutative binary operation.
22102177
virtual bool isCommutativeBinOp(unsigned Opcode) const {
22112178
// FIXME: This should get its info from the td file.
@@ -2233,13 +2200,39 @@ class TargetLoweringBase {
22332200
case ISD::UADDSAT:
22342201
case ISD::FMINNUM:
22352202
case ISD::FMAXNUM:
2203+
case ISD::FMINNUM_IEEE:
2204+
case ISD::FMAXNUM_IEEE:
22362205
case ISD::FMINIMUM:
22372206
case ISD::FMAXIMUM:
22382207
return true;
22392208
default: return false;
22402209
}
22412210
}
22422211

2212+
/// Return true if the node is a math/logic binary operator.
2213+
virtual bool isBinOp(unsigned Opcode) const {
2214+
// A commutative binop must be a binop.
2215+
if (isCommutativeBinOp(Opcode))
2216+
return true;
2217+
// These are non-commutative binops.
2218+
switch (Opcode) {
2219+
case ISD::SUB:
2220+
case ISD::SHL:
2221+
case ISD::SRL:
2222+
case ISD::SRA:
2223+
case ISD::SDIV:
2224+
case ISD::UDIV:
2225+
case ISD::SREM:
2226+
case ISD::UREM:
2227+
case ISD::FSUB:
2228+
case ISD::FDIV:
2229+
case ISD::FREM:
2230+
return true;
2231+
default:
2232+
return false;
2233+
}
2234+
}
2235+
22432236
/// Return true if it's free to truncate a value of type FromTy to type
22442237
/// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
22452238
/// by referencing its sub-register AX.

‎llvm/test/CodeGen/X86/horizontal-reduce-smax.ll

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -557,9 +557,9 @@ define i64 @test_reduce_v4i64(<4 x i64> %a0) {
557557
; X64-AVX512-LABEL: test_reduce_v4i64:
558558
; X64-AVX512: ## %bb.0:
559559
; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
560-
; X64-AVX512-NEXT: vpmaxsq %ymm1, %ymm0, %ymm0
560+
; X64-AVX512-NEXT: vpmaxsq %xmm1, %xmm0, %xmm0
561561
; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
562-
; X64-AVX512-NEXT: vpmaxsq %ymm1, %ymm0, %ymm0
562+
; X64-AVX512-NEXT: vpmaxsq %xmm1, %xmm0, %xmm0
563563
; X64-AVX512-NEXT: vmovq %xmm0, %rax
564564
; X64-AVX512-NEXT: vzeroupper
565565
; X64-AVX512-NEXT: retq
@@ -621,11 +621,11 @@ define i32 @test_reduce_v8i32(<8 x i32> %a0) {
621621
; X86-AVX2-LABEL: test_reduce_v8i32:
622622
; X86-AVX2: ## %bb.0:
623623
; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
624-
; X86-AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
624+
; X86-AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
625625
; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
626-
; X86-AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
626+
; X86-AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
627627
; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
628-
; X86-AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
628+
; X86-AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
629629
; X86-AVX2-NEXT: vmovd %xmm0, %eax
630630
; X86-AVX2-NEXT: vzeroupper
631631
; X86-AVX2-NEXT: retl
@@ -677,23 +677,23 @@ define i32 @test_reduce_v8i32(<8 x i32> %a0) {
677677
; X64-AVX2-LABEL: test_reduce_v8i32:
678678
; X64-AVX2: ## %bb.0:
679679
; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
680-
; X64-AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
680+
; X64-AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
681681
; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
682-
; X64-AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
682+
; X64-AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
683683
; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
684-
; X64-AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
684+
; X64-AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
685685
; X64-AVX2-NEXT: vmovd %xmm0, %eax
686686
; X64-AVX2-NEXT: vzeroupper
687687
; X64-AVX2-NEXT: retq
688688
;
689689
; X64-AVX512-LABEL: test_reduce_v8i32:
690690
; X64-AVX512: ## %bb.0:
691691
; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
692-
; X64-AVX512-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
692+
; X64-AVX512-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
693693
; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
694-
; X64-AVX512-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
694+
; X64-AVX512-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
695695
; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
696-
; X64-AVX512-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
696+
; X64-AVX512-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
697697
; X64-AVX512-NEXT: vmovd %xmm0, %eax
698698
; X64-AVX512-NEXT: vzeroupper
699699
; X64-AVX512-NEXT: retq
@@ -1276,9 +1276,9 @@ define i64 @test_reduce_v8i64(<8 x i64> %a0) {
12761276
; X64-AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
12771277
; X64-AVX512-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
12781278
; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
1279-
; X64-AVX512-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
1279+
; X64-AVX512-NEXT: vpmaxsq %xmm1, %xmm0, %xmm0
12801280
; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
1281-
; X64-AVX512-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
1281+
; X64-AVX512-NEXT: vpmaxsq %xmm1, %xmm0, %xmm0
12821282
; X64-AVX512-NEXT: vmovq %xmm0, %rax
12831283
; X64-AVX512-NEXT: vzeroupper
12841284
; X64-AVX512-NEXT: retq
@@ -1359,11 +1359,11 @@ define i32 @test_reduce_v16i32(<16 x i32> %a0) {
13591359
; X86-AVX2: ## %bb.0:
13601360
; X86-AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
13611361
; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
1362-
; X86-AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
1362+
; X86-AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
13631363
; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
1364-
; X86-AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
1364+
; X86-AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
13651365
; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
1366-
; X86-AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
1366+
; X86-AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
13671367
; X86-AVX2-NEXT: vmovd %xmm0, %eax
13681368
; X86-AVX2-NEXT: vzeroupper
13691369
; X86-AVX2-NEXT: retl
@@ -1431,11 +1431,11 @@ define i32 @test_reduce_v16i32(<16 x i32> %a0) {
14311431
; X64-AVX2: ## %bb.0:
14321432
; X64-AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
14331433
; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
1434-
; X64-AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
1434+
; X64-AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
14351435
; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
1436-
; X64-AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
1436+
; X64-AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
14371437
; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
1438-
; X64-AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
1438+
; X64-AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
14391439
; X64-AVX2-NEXT: vmovd %xmm0, %eax
14401440
; X64-AVX2-NEXT: vzeroupper
14411441
; X64-AVX2-NEXT: retq
@@ -1445,11 +1445,11 @@ define i32 @test_reduce_v16i32(<16 x i32> %a0) {
14451445
; X64-AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
14461446
; X64-AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0
14471447
; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
1448-
; X64-AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0
1448+
; X64-AVX512-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
14491449
; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
1450-
; X64-AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0
1450+
; X64-AVX512-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
14511451
; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
1452-
; X64-AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0
1452+
; X64-AVX512-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
14531453
; X64-AVX512-NEXT: vmovd %xmm0, %eax
14541454
; X64-AVX512-NEXT: vzeroupper
14551455
; X64-AVX512-NEXT: retq

‎llvm/test/CodeGen/X86/horizontal-reduce-smin.ll

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -561,9 +561,9 @@ define i64 @test_reduce_v4i64(<4 x i64> %a0) {
561561
; X64-AVX512-LABEL: test_reduce_v4i64:
562562
; X64-AVX512: ## %bb.0:
563563
; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
564-
; X64-AVX512-NEXT: vpminsq %ymm1, %ymm0, %ymm0
564+
; X64-AVX512-NEXT: vpminsq %xmm1, %xmm0, %xmm0
565565
; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
566-
; X64-AVX512-NEXT: vpminsq %ymm1, %ymm0, %ymm0
566+
; X64-AVX512-NEXT: vpminsq %xmm1, %xmm0, %xmm0
567567
; X64-AVX512-NEXT: vmovq %xmm0, %rax
568568
; X64-AVX512-NEXT: vzeroupper
569569
; X64-AVX512-NEXT: retq
@@ -625,11 +625,11 @@ define i32 @test_reduce_v8i32(<8 x i32> %a0) {
625625
; X86-AVX2-LABEL: test_reduce_v8i32:
626626
; X86-AVX2: ## %bb.0:
627627
; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
628-
; X86-AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0
628+
; X86-AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
629629
; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
630-
; X86-AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0
630+
; X86-AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
631631
; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
632-
; X86-AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0
632+
; X86-AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
633633
; X86-AVX2-NEXT: vmovd %xmm0, %eax
634634
; X86-AVX2-NEXT: vzeroupper
635635
; X86-AVX2-NEXT: retl
@@ -681,23 +681,23 @@ define i32 @test_reduce_v8i32(<8 x i32> %a0) {
681681
; X64-AVX2-LABEL: test_reduce_v8i32:
682682
; X64-AVX2: ## %bb.0:
683683
; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
684-
; X64-AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0
684+
; X64-AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
685685
; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
686-
; X64-AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0
686+
; X64-AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
687687
; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
688-
; X64-AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0
688+
; X64-AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
689689
; X64-AVX2-NEXT: vmovd %xmm0, %eax
690690
; X64-AVX2-NEXT: vzeroupper
691691
; X64-AVX2-NEXT: retq
692692
;
693693
; X64-AVX512-LABEL: test_reduce_v8i32:
694694
; X64-AVX512: ## %bb.0:
695695
; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
696-
; X64-AVX512-NEXT: vpminsd %ymm1, %ymm0, %ymm0
696+
; X64-AVX512-NEXT: vpminsd %xmm1, %xmm0, %xmm0
697697
; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
698-
; X64-AVX512-NEXT: vpminsd %ymm1, %ymm0, %ymm0
698+
; X64-AVX512-NEXT: vpminsd %xmm1, %xmm0, %xmm0
699699
; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
700-
; X64-AVX512-NEXT: vpminsd %ymm1, %ymm0, %ymm0
700+
; X64-AVX512-NEXT: vpminsd %xmm1, %xmm0, %xmm0
701701
; X64-AVX512-NEXT: vmovd %xmm0, %eax
702702
; X64-AVX512-NEXT: vzeroupper
703703
; X64-AVX512-NEXT: retq
@@ -1280,9 +1280,9 @@ define i64 @test_reduce_v8i64(<8 x i64> %a0) {
12801280
; X64-AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
12811281
; X64-AVX512-NEXT: vpminsq %zmm1, %zmm0, %zmm0
12821282
; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
1283-
; X64-AVX512-NEXT: vpminsq %zmm1, %zmm0, %zmm0
1283+
; X64-AVX512-NEXT: vpminsq %xmm1, %xmm0, %xmm0
12841284
; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
1285-
; X64-AVX512-NEXT: vpminsq %zmm1, %zmm0, %zmm0
1285+
; X64-AVX512-NEXT: vpminsq %xmm1, %xmm0, %xmm0
12861286
; X64-AVX512-NEXT: vmovq %xmm0, %rax
12871287
; X64-AVX512-NEXT: vzeroupper
12881288
; X64-AVX512-NEXT: retq
@@ -1363,11 +1363,11 @@ define i32 @test_reduce_v16i32(<16 x i32> %a0) {
13631363
; X86-AVX2: ## %bb.0:
13641364
; X86-AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0
13651365
; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
1366-
; X86-AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0
1366+
; X86-AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
13671367
; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
1368-
; X86-AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0
1368+
; X86-AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
13691369
; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
1370-
; X86-AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0
1370+
; X86-AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
13711371
; X86-AVX2-NEXT: vmovd %xmm0, %eax
13721372
; X86-AVX2-NEXT: vzeroupper
13731373
; X86-AVX2-NEXT: retl
@@ -1435,11 +1435,11 @@ define i32 @test_reduce_v16i32(<16 x i32> %a0) {
14351435
; X64-AVX2: ## %bb.0:
14361436
; X64-AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0
14371437
; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
1438-
; X64-AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0
1438+
; X64-AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
14391439
; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
1440-
; X64-AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0
1440+
; X64-AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
14411441
; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
1442-
; X64-AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0
1442+
; X64-AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
14431443
; X64-AVX2-NEXT: vmovd %xmm0, %eax
14441444
; X64-AVX2-NEXT: vzeroupper
14451445
; X64-AVX2-NEXT: retq
@@ -1449,11 +1449,11 @@ define i32 @test_reduce_v16i32(<16 x i32> %a0) {
14491449
; X64-AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
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; X64-AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0
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; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
1452-
; X64-AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0
1452+
; X64-AVX512-NEXT: vpminsd %xmm1, %xmm0, %xmm0
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; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
1454-
; X64-AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0
1454+
; X64-AVX512-NEXT: vpminsd %xmm1, %xmm0, %xmm0
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; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
1456-
; X64-AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0
1456+
; X64-AVX512-NEXT: vpminsd %xmm1, %xmm0, %xmm0
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; X64-AVX512-NEXT: vmovd %xmm0, %eax
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; X64-AVX512-NEXT: vzeroupper
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; X64-AVX512-NEXT: retq

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