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[RISCV] Enable f16 vget/vset/vcreate/vlmul_ext/vlmul_trunc/vundefined intrinsics with Zvfhmin. (#109889)
These intrinsics don't produce any instructions so don't require Zvfh. This makes Zvfhmin consistent with Zvfbfmin. See also riscv-non-isa/rvv-intrinsic-doc#351
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+44
-20
lines changed

11 files changed

+44
-20
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‎clang/include/clang/Basic/riscv_vector.td

+34-10
Original file line numberDiff line numberDiff line change
@@ -361,7 +361,11 @@ multiclass RVVNonTupleVCreateBuiltin<int dst_lmul, list<int> src_lmul_list> {
361361
defvar src_s = FixedVString<src_lmul, num, "v">.S;
362362
def vcreate # src_v # dst_v : RVVBuiltin<src_v # dst_v,
363363
dst_v # src_s,
364-
"csilxfd">;
364+
"csilfd">;
365+
let RequiredFeatures = ["Zvfhmin"] in
366+
def vcreate_h # src_v # dst_v : RVVBuiltin<src_v # dst_v,
367+
dst_v # src_s,
368+
"x", dst_v>;
365369
let RequiredFeatures = ["Zvfbfmin"] in
366370
def vcreate_bf16 # src_v # dst_v : RVVBuiltin<src_v # dst_v,
367371
dst_v # src_s,
@@ -2474,15 +2478,19 @@ let HasMasked = false, HasVL = false, IRName = "" in {
24742478
ManualCodegen = [{
24752479
return llvm::PoisonValue::get(ResultType);
24762480
}] in {
2477-
def vundefined : RVVBuiltin<"v", "v", "csilxfd">;
2481+
def vundefined : RVVBuiltin<"v", "v", "csilfd">;
2482+
let RequiredFeatures = ["Zvfhmin"] in
2483+
def vundefined_h : RVVBuiltin<"v", "v", "x">;
24782484
let RequiredFeatures = ["Zvfbfmin"] in
24792485
def vundefined_bf16 : RVVBuiltin<"v", "v", "y">;
24802486
def vundefined_u : RVVBuiltin<"Uv", "Uv", "csil">;
24812487

24822488
foreach nf = NFList in {
24832489
let NF = nf in {
24842490
defvar T = "(Tuple:" # nf # ")";
2485-
def : RVVBuiltin<T # "v", T # "v", "csilxfd">;
2491+
def : RVVBuiltin<T # "v", T # "v", "csilfd">;
2492+
let RequiredFeatures = ["Zvfhmin"] in
2493+
def : RVVBuiltin<T # "v", T # "v", "x">;
24862494
let RequiredFeatures = ["Zvfbfmin"] in
24872495
def : RVVBuiltin<T # "v", T # "v", "y">;
24882496
def : RVVBuiltin<T # "Uv", T # "Uv", "csil">;
@@ -2502,7 +2510,10 @@ let HasMasked = false, HasVL = false, IRName = "" in {
25022510
foreach dst_lmul = ["(SFixedLog2LMUL:-3)", "(SFixedLog2LMUL:-2)", "(SFixedLog2LMUL:-1)",
25032511
"(SFixedLog2LMUL:0)", "(SFixedLog2LMUL:1)", "(SFixedLog2LMUL:2)"] in {
25042512
def vlmul_trunc # dst_lmul : RVVBuiltin<"v" # dst_lmul # "v",
2505-
dst_lmul # "vv", "csilxfd", dst_lmul # "v">;
2513+
dst_lmul # "vv", "csilfd", dst_lmul # "v">;
2514+
let RequiredFeatures = ["Zvfhmin"] in
2515+
def vlmul_trunc_h # dst_lmul : RVVBuiltin<"v" # dst_lmul # "v",
2516+
dst_lmul # "vv", "x", dst_lmul # "v">;
25062517
let RequiredFeatures = ["Zvfbfmin"] in
25072518
def vlmul_trunc_bf16 # dst_lmul : RVVBuiltin<"v" # dst_lmul # "v",
25082519
dst_lmul # "vv", "y", dst_lmul # "v">;
@@ -2523,7 +2534,10 @@ let HasMasked = false, HasVL = false, IRName = "" in {
25232534
foreach dst_lmul = ["(LFixedLog2LMUL:-2)", "(LFixedLog2LMUL:-1)", "(LFixedLog2LMUL:-0)",
25242535
"(LFixedLog2LMUL:1)", "(LFixedLog2LMUL:2)", "(LFixedLog2LMUL:3)"] in {
25252536
def vlmul_ext # dst_lmul : RVVBuiltin<"v" # dst_lmul # "v",
2526-
dst_lmul # "vv", "csilxfd", dst_lmul # "v">;
2537+
dst_lmul # "vv", "csilfd", dst_lmul # "v">;
2538+
let RequiredFeatures = ["Zvfhmin"] in
2539+
def vlmul_ext_h # dst_lmul : RVVBuiltin<"v" # dst_lmul # "v",
2540+
dst_lmul # "vv", "x", dst_lmul # "v">;
25272541
let RequiredFeatures = ["Zvfbfmin"] in
25282542
def vlmul_ext_bf16 # dst_lmul : RVVBuiltin<"v" # dst_lmul # "v",
25292543
dst_lmul # "vv", "y", dst_lmul # "v">;
@@ -2555,14 +2569,18 @@ let HasMasked = false, HasVL = false, IRName = "" in {
25552569
}
25562570
}] in {
25572571
foreach dst_lmul = ["(SFixedLog2LMUL:0)", "(SFixedLog2LMUL:1)", "(SFixedLog2LMUL:2)"] in {
2558-
def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "vvKz", "csilxfd", dst_lmul # "v">;
2572+
def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "vvKz", "csilfd", dst_lmul # "v">;
2573+
let RequiredFeatures = ["Zvfhmin"] in
2574+
def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "vvKz", "x", dst_lmul # "v">;
25592575
let RequiredFeatures = ["Zvfbfmin"] in
25602576
def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "vvKz", "y", dst_lmul # "v">;
25612577
def : RVVBuiltin<"Uv" # dst_lmul # "Uv", dst_lmul # "UvUvKz", "csil", dst_lmul # "Uv">;
25622578
}
25632579
foreach nf = NFList in {
25642580
defvar T = "(Tuple:" # nf # ")";
2565-
def : RVVBuiltin<T # "vv", "v" # T # "vKz", "csilxfd", "v">;
2581+
def : RVVBuiltin<T # "vv", "v" # T # "vKz", "csilfd", "v">;
2582+
let RequiredFeatures = ["Zvfhmin"] in
2583+
def : RVVBuiltin<T # "vv", "v" # T # "vKz", "x", "v">;
25662584
let RequiredFeatures = ["Zvfbfmin"] in
25672585
def : RVVBuiltin<T # "vv", "v" # T # "vKz", "y", "v">;
25682586
def : RVVBuiltin<T # "UvUv", "Uv" # T # "UvKz", "csil", "Uv">;
@@ -2592,14 +2610,18 @@ let HasMasked = false, HasVL = false, IRName = "" in {
25922610
}
25932611
}] in {
25942612
foreach dst_lmul = ["(LFixedLog2LMUL:1)", "(LFixedLog2LMUL:2)", "(LFixedLog2LMUL:3)"] in {
2595-
def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "v" # dst_lmul # "vKzv", "csilxfd">;
2613+
def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "v" # dst_lmul # "vKzv", "csilfd">;
2614+
let RequiredFeatures = ["Zvfhmin"] in
2615+
def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "v" # dst_lmul # "vKzv", "x">;
25962616
let RequiredFeatures = ["Zvfbfmin"] in
25972617
def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "v" # dst_lmul # "vKzv", "y">;
25982618
def : RVVBuiltin<"Uv" # dst_lmul # "Uv", dst_lmul # "Uv" # dst_lmul #"UvKzUv", "csil">;
25992619
}
26002620
foreach nf = NFList in {
26012621
defvar T = "(Tuple:" # nf # ")";
2602-
def : RVVBuiltin<"v" # T # "v", T # "v" # T # "vKzv", "csilxfd">;
2622+
def : RVVBuiltin<"v" # T # "v", T # "v" # T # "vKzv", "csilfd">;
2623+
let RequiredFeatures = ["Zvfhmin"] in
2624+
def : RVVBuiltin<"v" # T # "v", T # "v" # T # "vKzv", "x">;
26032625
let RequiredFeatures = ["Zvfbfmin"] in
26042626
def : RVVBuiltin<"v" # T # "v", T # "v" # T # "vKzv", "y">;
26052627
def : RVVBuiltin<"Uv" # T # "Uv", T # "Uv" # T # "UvKzUv", "csil">;
@@ -2646,7 +2668,9 @@ let HasMasked = false, HasVL = false, IRName = "" in {
26462668
defvar T = "(Tuple:" # nf # ")";
26472669
defvar V = VString<nf, /*signed=*/true>.S;
26482670
defvar UV = VString<nf, /*signed=*/false>.S;
2649-
def : RVVBuiltin<T # "v", T # "v" # V, "csilxfd">;
2671+
def : RVVBuiltin<T # "v", T # "v" # V, "csilfd">;
2672+
let RequiredFeatures = ["Zvfhmin"] in
2673+
def : RVVBuiltin<T # "v", T # "v" # V, "x">;
26502674
let RequiredFeatures = ["Zvfbfmin"] in
26512675
def : RVVBuiltin<T # "v", T # "v" # V, "y">;
26522676
def : RVVBuiltin<T # "Uv", T # "Uv" # UV, "csil">;

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfhmin -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfhmin -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfhmin -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfhmin -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfhmin -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfhmin -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfhmin -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfhmin -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfhmin -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfhmin -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

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