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[RISCV] Change how mtune aliases are implemented.
The previous implementation translated from names like sifive-7-series to sifive-7-rv32 or sifive-7-rv64. This also required sifive-7-rv32 and sifive-7-rv64 to be valid CPU names. As those are not real CPUs it doesn't make sense to accept them in -mcpu. This patch does away with the translation and adds sifive-7-series directly to RISCV.td. Removing sifive-7-rv32 and sifive-7-rv64. sifive-7-series is only allowed in -mtune. I've also added "rocket" to RISCV.td but have not removed rocket-rv32 or rocket-rv64. To prevent -mcpu=sifive-7-series or -mcpu=rocket being used with llc, I've added a Feature32Bit to all rv32 CPUs. And made it an error to have an rv32 triple without Feature32Bit. sifive-7-series and rocket do not have Feature32Bit or Feature64Bit set so the user would need to provide -mattr=+32bit or -mattr=+64bit along with the -mcpu to avoid the error. SiFive no longer names their newer products with 3, 5, or 7 series. Instead we have p200 series, x200 series, p500 series, and p600 series. Following the previous behavior would require a sifive-p500-rv32 and sifive-p500-rv64 in order to support -mtune=sifive-p500-series. There is currently no p500 product, but it could start getting confusing if there was in the future. I'm open to hearing alternatives for how to achieve my main goal of removing sifive-7-rv32/rv64 as a CPU name. Reviewed By: reames Differential Revision: https://reviews.llvm.org/D131708
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‎clang/docs/ReleaseNotes.rst

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -191,6 +191,12 @@ CUDA Support in Clang
191191

192192
- ...
193193

194+
RISC-V Support in Clang
195+
-----------------------
196+
197+
- ``sifive-7-rv32`` and ``sifive-7-rv64`` are no longer supported for `-mcpu`.
198+
Use `sifive-e76`, `sifive-s76`, or `sifive-u74` instead.
199+
194200
X86 Support in Clang
195201
--------------------
196202

‎clang/lib/Driver/ToolChains/Clang.cpp

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2190,10 +2190,8 @@ void Clang::AddRISCVTargetArgs(const ArgList &Args,
21902190
SetRISCVSmallDataLimit(getToolChain(), Args, CmdArgs);
21912191

21922192
if (const Arg *A = Args.getLastArg(options::OPT_mtune_EQ)) {
2193-
StringRef Name =
2194-
llvm::RISCV::resolveTuneCPUAlias(A->getValue(), Triple.isArch64Bit());
21952193
CmdArgs.push_back("-tune-cpu");
2196-
CmdArgs.push_back(Name.data());
2194+
CmdArgs.push_back(A->getValue());
21972195
}
21982196
}
21992197

‎clang/test/Driver/riscv-cpus.c

Lines changed: 4 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -7,43 +7,24 @@
77
// MCPU-ROCKET64: "-nostdsysteminc" "-target-cpu" "rocket-rv64"
88
// MCPU-ROCKET64: "-target-feature" "+64bit"
99

10-
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=sifive-7-rv32 | FileCheck -check-prefix=MCPU-SIFIVE7-32 %s
11-
// MCPU-SIFIVE7-32: "-nostdsysteminc" "-target-cpu" "sifive-7-rv32"
12-
13-
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-7-rv64 | FileCheck -check-prefix=MCPU-SIFIVE7-64 %s
14-
// MCPU-SIFIVE7-64: "-nostdsysteminc" "-target-cpu" "sifive-7-rv64"
15-
// MCPU-SIFIVE7-64: "-target-feature" "+64bit"
16-
1710
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=rocket-rv32 | FileCheck -check-prefix=MTUNE-ROCKET32 %s
1811
// MTUNE-ROCKET32: "-tune-cpu" "rocket-rv32"
1912

2013
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=rocket-rv64 | FileCheck -check-prefix=MTUNE-ROCKET64 %s
2114
// MTUNE-ROCKET64: "-tune-cpu" "rocket-rv64"
2215

23-
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=sifive-7-rv32 | FileCheck -check-prefix=MTUNE-SIFIVE7-32 %s
24-
// MTUNE-SIFIVE7-32: "-tune-cpu" "sifive-7-rv32"
25-
26-
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=sifive-7-rv64 | FileCheck -check-prefix=MTUNE-SIFIVE7-64 %s
27-
// MTUNE-SIFIVE7-64: "-tune-cpu" "sifive-7-rv64"
28-
2916
// Check mtune alias CPU has resolved to the right CPU according XLEN.
3017
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=generic | FileCheck -check-prefix=MTUNE-GENERIC-32 %s
31-
// MTUNE-GENERIC-32: "-tune-cpu" "generic-rv32"
18+
// MTUNE-GENERIC-32: "-tune-cpu" "generic"
3219

3320
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=generic | FileCheck -check-prefix=MTUNE-GENERIC-64 %s
34-
// MTUNE-GENERIC-64: "-tune-cpu" "generic-rv64"
21+
// MTUNE-GENERIC-64: "-tune-cpu" "generic"
3522

3623
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=rocket | FileCheck -check-prefix=MTUNE-ROCKET-32 %s
37-
// MTUNE-ROCKET-32: "-tune-cpu" "rocket-rv32"
24+
// MTUNE-ROCKET-32: "-tune-cpu" "rocket"
3825

3926
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=rocket | FileCheck -check-prefix=MTUNE-ROCKET-64 %s
40-
// MTUNE-ROCKET-64: "-tune-cpu" "rocket-rv64"
41-
42-
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=sifive-7-series | FileCheck -check-prefix=MTUNE-SIFIVE7-SERIES-32 %s
43-
// MTUNE-SIFIVE7-SERIES-32: "-tune-cpu" "sifive-7-rv32"
44-
45-
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=sifive-7-series | FileCheck -check-prefix=MTUNE-SIFIVE7-SERIES-64 %s
46-
// MTUNE-SIFIVE7-SERIES-64: "-tune-cpu" "sifive-7-rv64"
27+
// MTUNE-ROCKET-64: "-tune-cpu" "rocket"
4728

4829
// mcpu with default march
4930
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-e20 | FileCheck -check-prefix=MCPU-SIFIVE-E20 %s

‎clang/test/Misc/target-invalid-cpu-note.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -81,16 +81,16 @@
8181

8282
// RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32
8383
// RISCV32: error: unknown target CPU 'not-a-cpu'
84-
// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-7-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76{{$}}
84+
// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76{{$}}
8585

8686
// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
8787
// RISCV64: error: unknown target CPU 'not-a-cpu'
88-
// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-7-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74{{$}}
88+
// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74{{$}}
8989

9090
// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
9191
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
92-
// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-7-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, generic, rocket, sifive-7-series{{$}}
92+
// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, generic, rocket, sifive-7-series{{$}}
9393

9494
// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
9595
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
96-
// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-7-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, generic, rocket, sifive-7-series{{$}}
96+
// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, generic, rocket, sifive-7-series{{$}}

‎llvm/include/llvm/Support/RISCVTargetParser.def

Lines changed: 10 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,3 @@
1-
#ifndef TUNE_ALIAS
2-
#define TUNE_ALIAS(NAME, RV32, RV64)
3-
#endif
4-
5-
TUNE_ALIAS("generic", "generic-rv32", "generic-rv64")
6-
TUNE_ALIAS("rocket", "rocket-rv32", "rocket-rv64")
7-
TUNE_ALIAS("sifive-7-series", "sifive-7-rv32", "sifive-7-rv64")
8-
9-
#undef TUNE_ALIAS
10-
111
#ifndef PROC
122
#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH)
133
#endif
@@ -17,8 +7,6 @@ PROC(GENERIC_RV32, {"generic-rv32"}, FK_NONE, {""})
177
PROC(GENERIC_RV64, {"generic-rv64"}, FK_64BIT, {""})
188
PROC(ROCKET_RV32, {"rocket-rv32"}, FK_NONE, {""})
199
PROC(ROCKET_RV64, {"rocket-rv64"}, FK_64BIT, {""})
20-
PROC(SIFIVE_732, {"sifive-7-rv32"}, FK_NONE, {""})
21-
PROC(SIFIVE_764, {"sifive-7-rv64"}, FK_64BIT, {""})
2210
PROC(SIFIVE_E20, {"sifive-e20"}, FK_NONE, {"rv32imc"})
2311
PROC(SIFIVE_E21, {"sifive-e21"}, FK_NONE, {"rv32imac"})
2412
PROC(SIFIVE_E24, {"sifive-e24"}, FK_NONE, {"rv32imafc"})
@@ -33,3 +21,13 @@ PROC(SIFIVE_U54, {"sifive-u54"}, FK_64BIT, {"rv64gc"})
3321
PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"})
3422

3523
#undef PROC
24+
25+
#ifndef TUNE_PROC
26+
#define TUNE_PROC(ENUM, NAME)
27+
#endif
28+
29+
TUNE_PROC(GENERIC, "generic")
30+
TUNE_PROC(ROCKET, "rocket")
31+
TUNE_PROC(SIFIVE_7, "sifive-7-series")
32+
33+
#undef TUNE_PROC

‎llvm/include/llvm/Support/TargetParser.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -159,6 +159,7 @@ namespace RISCV {
159159

160160
enum CPUKind : unsigned {
161161
#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) CK_##ENUM,
162+
#define TUNE_PROC(ENUM, NAME) CK_##ENUM,
162163
#include "RISCVTargetParser.def"
163164
};
164165

@@ -176,7 +177,6 @@ StringRef getMArchFromMcpu(StringRef CPU);
176177
void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
177178
void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
178179
bool getCPUFeaturesExceptStdExt(CPUKind Kind, std::vector<StringRef> &Features);
179-
StringRef resolveTuneCPUAlias(StringRef TuneCPU, bool IsRV64);
180180

181181
} // namespace RISCV
182182

‎llvm/lib/Support/TargetParser.cpp

Lines changed: 4 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -278,6 +278,8 @@ bool checkCPUKind(CPUKind Kind, bool IsRV64) {
278278
bool checkTuneCPUKind(CPUKind Kind, bool IsRV64) {
279279
if (Kind == CK_INVALID)
280280
return false;
281+
#define TUNE_PROC(ENUM, NAME) if (Kind == CK_##ENUM) return true;
282+
#include "llvm/Support/RISCVTargetParser.def"
281283
return RISCVCPUInfo[static_cast<unsigned>(Kind)].is64Bit() == IsRV64;
282284
}
283285

@@ -288,18 +290,10 @@ CPUKind parseCPUKind(StringRef CPU) {
288290
.Default(CK_INVALID);
289291
}
290292

291-
StringRef resolveTuneCPUAlias(StringRef TuneCPU, bool IsRV64) {
292-
return llvm::StringSwitch<StringRef>(TuneCPU)
293-
#define TUNE_ALIAS(NAME, RV32, RV64) .Case(NAME, IsRV64 ? StringRef(RV64) : StringRef(RV32))
294-
#include "llvm/Support/RISCVTargetParser.def"
295-
.Default(TuneCPU);
296-
}
297-
298293
CPUKind parseTuneCPUKind(StringRef TuneCPU, bool IsRV64) {
299-
TuneCPU = resolveTuneCPUAlias(TuneCPU, IsRV64);
300-
301294
return llvm::StringSwitch<CPUKind>(TuneCPU)
302295
#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) .Case(NAME, CK_##ENUM)
296+
#define TUNE_PROC(ENUM, NAME) .Case(NAME, CK_##ENUM)
303297
#include "llvm/Support/RISCVTargetParser.def"
304298
.Default(CK_INVALID);
305299
}
@@ -321,7 +315,7 @@ void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) {
321315
if (C.Kind != CK_INVALID && IsRV64 == C.is64Bit())
322316
Values.emplace_back(C.Name);
323317
}
324-
#define TUNE_ALIAS(NAME, RV32, RV64) Values.emplace_back(StringRef(NAME));
318+
#define TUNE_PROC(ENUM, NAME) Values.emplace_back(StringRef(NAME));
325319
#include "llvm/Support/RISCVTargetParser.def"
326320
}
327321

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -97,10 +97,13 @@ namespace RISCVFeatures {
9797
void validate(const Triple &TT, const FeatureBitset &FeatureBits) {
9898
if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit])
9999
report_fatal_error("RV64 target requires an RV64 CPU");
100-
if (!TT.isArch64Bit() && FeatureBits[RISCV::Feature64Bit])
100+
if (!TT.isArch64Bit() && !FeatureBits[RISCV::Feature32Bit])
101101
report_fatal_error("RV32 target requires an RV32 CPU");
102102
if (TT.isArch64Bit() && FeatureBits[RISCV::FeatureRV32E])
103103
report_fatal_error("RV32E can't be enabled for an RV64 target");
104+
if (FeatureBits[RISCV::Feature32Bit] &&
105+
FeatureBits[RISCV::Feature64Bit])
106+
report_fatal_error("RV32 and RV64 can't be combined");
104107
}
105108

106109
llvm::Expected<std::unique_ptr<RISCVISAInfo>>

‎llvm/lib/Target/RISCV/RISCV.td

Lines changed: 20 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -447,6 +447,10 @@ def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
447447
AssemblerPredicate<(all_of FeatureStdExtZicbop),
448448
"'Zicbop' (Cache-Block Prefetch Instructions)">;
449449

450+
// Feature32Bit exists to mark CPUs that support RV32 to distinquish them from
451+
// tuning CPU names.
452+
def Feature32Bit
453+
: SubtargetFeature<"32bit", "HasRV32", "true", "Implements RV32">;
450454
def Feature64Bit
451455
: SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
452456
def IsRV64 : Predicate<"Subtarget->is64Bit()">,
@@ -527,42 +531,47 @@ include "RISCVSchedSiFive7.td"
527531
// RISC-V processors supported.
528532
//===----------------------------------------------------------------------===//
529533

530-
def : ProcessorModel<"generic-rv32", NoSchedModel, []>;
534+
def : ProcessorModel<"generic-rv32", NoSchedModel, [Feature32Bit]>;
531535
def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
532536
// Support generic for compatibility with other targets. The triple will be used
533537
// to change to the appropriate rv32/rv64 version.
534538
def : ProcessorModel<"generic", NoSchedModel, []>;
535539

536-
def : ProcessorModel<"rocket-rv32", RocketModel, []>;
540+
def : ProcessorModel<"rocket-rv32", RocketModel, [Feature32Bit]>;
537541
def : ProcessorModel<"rocket-rv64", RocketModel, [Feature64Bit]>;
542+
def : ProcessorModel<"rocket", RocketModel, []>;
538543

539-
def : ProcessorModel<"sifive-7-rv32", SiFive7Model, [],
540-
[TuneSiFive7]>;
541-
def : ProcessorModel<"sifive-7-rv64", SiFive7Model, [Feature64Bit],
544+
def : ProcessorModel<"sifive-7-series", SiFive7Model, [],
542545
[TuneSiFive7]>;
543546

544-
def : ProcessorModel<"sifive-e20", RocketModel, [FeatureStdExtM,
547+
def : ProcessorModel<"sifive-e20", RocketModel, [Feature32Bit,
548+
FeatureStdExtM,
545549
FeatureStdExtC]>;
546550

547-
def : ProcessorModel<"sifive-e21", RocketModel, [FeatureStdExtM,
551+
def : ProcessorModel<"sifive-e21", RocketModel, [Feature32Bit,
552+
FeatureStdExtM,
548553
FeatureStdExtA,
549554
FeatureStdExtC]>;
550555

551-
def : ProcessorModel<"sifive-e24", RocketModel, [FeatureStdExtM,
556+
def : ProcessorModel<"sifive-e24", RocketModel, [Feature32Bit,
557+
FeatureStdExtM,
552558
FeatureStdExtA,
553559
FeatureStdExtF,
554560
FeatureStdExtC]>;
555561

556-
def : ProcessorModel<"sifive-e31", RocketModel, [FeatureStdExtM,
562+
def : ProcessorModel<"sifive-e31", RocketModel, [Feature32Bit,
563+
FeatureStdExtM,
557564
FeatureStdExtA,
558565
FeatureStdExtC]>;
559566

560-
def : ProcessorModel<"sifive-e34", RocketModel, [FeatureStdExtM,
567+
def : ProcessorModel<"sifive-e34", RocketModel, [Feature32Bit,
568+
FeatureStdExtM,
561569
FeatureStdExtA,
562570
FeatureStdExtF,
563571
FeatureStdExtC]>;
564572

565-
def : ProcessorModel<"sifive-e76", SiFive7Model, [FeatureStdExtM,
573+
def : ProcessorModel<"sifive-e76", SiFive7Model, [Feature32Bit,
574+
FeatureStdExtM,
566575
FeatureStdExtA,
567576
FeatureStdExtF,
568577
FeatureStdExtC],

‎llvm/lib/Target/RISCV/RISCVSubtarget.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -91,6 +91,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
9191
bool HasStdExtZicboz = false;
9292
bool HasStdExtZicbop = false;
9393
bool HasStdExtZmmul = false;
94+
bool HasRV32 = false;
9495
bool HasRV64 = false;
9596
bool IsRV32E = false;
9697
bool EnableLinkerRelax = false;

‎llvm/test/Transforms/LoopUnroll/RISCV/unroll.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2-
; RUN: opt %s -S -mtriple=riscv64 -loop-unroll -mcpu=sifive-7-rv64 | FileCheck %s
2+
; RUN: opt %s -S -mtriple=riscv64 -loop-unroll -mcpu=sifive-s76 | FileCheck %s
33

44
define dso_local void @saxpy(float %a, float* %x, float* %y) {
55
; CHECK-LABEL: @saxpy(

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