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ZCBingbenshi001
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[RISCV][NFC] Add helper function isVectorConfigInstr to reduce Repeated code.
Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D119924
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llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

+10-12
Original file line numberDiff line numberDiff line change
@@ -447,6 +447,12 @@ char RISCVInsertVSETVLI::ID = 0;
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INITIALIZE_PASS(RISCVInsertVSETVLI, DEBUG_TYPE, RISCV_INSERT_VSETVLI_NAME,
448448
false, false)
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450+
static bool isVectorConfigInstr(const MachineInstr &MI) {
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return MI.getOpcode() == RISCV::PseudoVSETVLI ||
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MI.getOpcode() == RISCV::PseudoVSETVLIX0 ||
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MI.getOpcode() == RISCV::PseudoVSETIVLI;
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}
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450456
static MachineInstr *elideCopies(MachineInstr *MI,
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const MachineRegisterInfo *MRI) {
452458
while (true) {
@@ -655,9 +661,7 @@ bool RISCVInsertVSETVLI::needVSETVLI(const VSETVLIInfo &Require,
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Require.getAVLReg().isVirtual() && !CurInfo.hasSEWLMULRatioOnly() &&
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CurInfo.hasCompatibleVTYPE(Require, /*Strict*/ false)) {
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if (MachineInstr *DefMI = MRI->getVRegDef(Require.getAVLReg())) {
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if (DefMI->getOpcode() == RISCV::PseudoVSETVLI ||
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DefMI->getOpcode() == RISCV::PseudoVSETVLIX0 ||
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DefMI->getOpcode() == RISCV::PseudoVSETIVLI) {
664+
if (isVectorConfigInstr(*DefMI)) {
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VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
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if (DefInfo.hasSameAVL(CurInfo) && DefInfo.hasSameVTYPE(CurInfo))
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return false;
@@ -870,9 +874,7 @@ bool RISCVInsertVSETVLI::computeVLVTYPEChanges(const MachineBasicBlock &MBB) {
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BlockData &BBInfo = BlockInfo[MBB.getNumber()];
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for (const MachineInstr &MI : MBB) {
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// If this is an explicit VSETVLI or VSETIVLI, update our state.
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if (MI.getOpcode() == RISCV::PseudoVSETVLI ||
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MI.getOpcode() == RISCV::PseudoVSETVLIX0 ||
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MI.getOpcode() == RISCV::PseudoVSETIVLI) {
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if (isVectorConfigInstr(MI)) {
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HadVectorOp = true;
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BBInfo.Change = getInfoForVSETVLI(MI);
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continue;
@@ -983,9 +985,7 @@ bool RISCVInsertVSETVLI::needVSETVLIPHI(const VSETVLIInfo &Require,
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// We need the PHI input to the be the output of a VSET(I)VLI.
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MachineInstr *DefMI = MRI->getVRegDef(InReg);
986-
if (!DefMI || (DefMI->getOpcode() != RISCV::PseudoVSETVLI &&
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DefMI->getOpcode() != RISCV::PseudoVSETVLIX0 &&
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DefMI->getOpcode() != RISCV::PseudoVSETIVLI))
988+
if (!DefMI || !isVectorConfigInstr(*DefMI))
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return true;
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// We found a VSET(I)VLI make sure it matches the output of the
@@ -1008,9 +1008,7 @@ void RISCVInsertVSETVLI::emitVSETVLIs(MachineBasicBlock &MBB) {
10081008

10091009
for (MachineInstr &MI : MBB) {
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// If this is an explicit VSETVLI or VSETIVLI, update our state.
1011-
if (MI.getOpcode() == RISCV::PseudoVSETVLI ||
1012-
MI.getOpcode() == RISCV::PseudoVSETVLIX0 ||
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MI.getOpcode() == RISCV::PseudoVSETIVLI) {
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if (isVectorConfigInstr(MI)) {
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// Conservatively, mark the VL and VTYPE as live.
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assert(MI.getOperand(3).getReg() == RISCV::VL &&
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MI.getOperand(4).getReg() == RISCV::VTYPE &&

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