@@ -447,6 +447,12 @@ char RISCVInsertVSETVLI::ID = 0;
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INITIALIZE_PASS (RISCVInsertVSETVLI, DEBUG_TYPE, RISCV_INSERT_VSETVLI_NAME,
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false , false )
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+ static bool isVectorConfigInstr(const MachineInstr &MI) {
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+ return MI.getOpcode () == RISCV::PseudoVSETVLI ||
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+ MI.getOpcode () == RISCV::PseudoVSETVLIX0 ||
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+ MI.getOpcode () == RISCV::PseudoVSETIVLI;
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+ }
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+
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static MachineInstr *elideCopies (MachineInstr *MI,
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const MachineRegisterInfo *MRI) {
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while (true ) {
@@ -655,9 +661,7 @@ bool RISCVInsertVSETVLI::needVSETVLI(const VSETVLIInfo &Require,
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Require.getAVLReg ().isVirtual () && !CurInfo.hasSEWLMULRatioOnly () &&
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CurInfo.hasCompatibleVTYPE (Require, /* Strict*/ false )) {
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if (MachineInstr *DefMI = MRI->getVRegDef (Require.getAVLReg ())) {
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- if (DefMI->getOpcode () == RISCV::PseudoVSETVLI ||
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- DefMI->getOpcode () == RISCV::PseudoVSETVLIX0 ||
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- DefMI->getOpcode () == RISCV::PseudoVSETIVLI) {
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+ if (isVectorConfigInstr (*DefMI)) {
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VSETVLIInfo DefInfo = getInfoForVSETVLI (*DefMI);
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if (DefInfo.hasSameAVL (CurInfo) && DefInfo.hasSameVTYPE (CurInfo))
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return false ;
@@ -870,9 +874,7 @@ bool RISCVInsertVSETVLI::computeVLVTYPEChanges(const MachineBasicBlock &MBB) {
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BlockData &BBInfo = BlockInfo[MBB.getNumber ()];
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for (const MachineInstr &MI : MBB) {
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// If this is an explicit VSETVLI or VSETIVLI, update our state.
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- if (MI.getOpcode () == RISCV::PseudoVSETVLI ||
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- MI.getOpcode () == RISCV::PseudoVSETVLIX0 ||
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- MI.getOpcode () == RISCV::PseudoVSETIVLI) {
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+ if (isVectorConfigInstr (MI)) {
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HadVectorOp = true ;
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BBInfo.Change = getInfoForVSETVLI (MI);
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continue ;
@@ -983,9 +985,7 @@ bool RISCVInsertVSETVLI::needVSETVLIPHI(const VSETVLIInfo &Require,
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// We need the PHI input to the be the output of a VSET(I)VLI.
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MachineInstr *DefMI = MRI->getVRegDef (InReg);
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- if (!DefMI || (DefMI->getOpcode () != RISCV::PseudoVSETVLI &&
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- DefMI->getOpcode () != RISCV::PseudoVSETVLIX0 &&
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- DefMI->getOpcode () != RISCV::PseudoVSETIVLI))
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+ if (!DefMI || !isVectorConfigInstr (*DefMI))
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return true ;
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// We found a VSET(I)VLI make sure it matches the output of the
@@ -1008,9 +1008,7 @@ void RISCVInsertVSETVLI::emitVSETVLIs(MachineBasicBlock &MBB) {
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for (MachineInstr &MI : MBB) {
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// If this is an explicit VSETVLI or VSETIVLI, update our state.
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- if (MI.getOpcode () == RISCV::PseudoVSETVLI ||
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- MI.getOpcode () == RISCV::PseudoVSETVLIX0 ||
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- MI.getOpcode () == RISCV::PseudoVSETIVLI) {
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+ if (isVectorConfigInstr (MI)) {
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// Conservatively, mark the VL and VTYPE as live.
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assert (MI.getOperand (3 ).getReg () == RISCV::VL &&
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MI.getOperand (4 ).getReg () == RISCV::VTYPE &&
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