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[X86] Autogenerate cfguard-x86-64-vectorcall.ll. NFC
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llvm/test/CodeGen/X86/cfguard-x86-64-vectorcall.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-pc-windows-msvc | FileCheck %s -check-prefix=X64
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; Control Flow Guard is currently only available on Windows
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; Test that Control Flow Guard checks are correctly added for x86_64 vector calls.
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define void @func_cf_vector_x64(ptr %0, ptr %1) #0 {
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; X64-LABEL: func_cf_vector_x64:
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; X64: # %bb.0: # %entry
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; X64-NEXT: subq $72, %rsp
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; X64-NEXT: .seh_stackalloc 72
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; X64-NEXT: .seh_endprologue
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; X64-NEXT: movq %rcx, %rax
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; X64-NEXT: movups (%rdx), %xmm0
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; X64-NEXT: movups 16(%rdx), %xmm1
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; X64-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
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; X64-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
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; X64-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; X64-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
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; X64-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
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; X64-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
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; X64-NEXT: callq *__guard_dispatch_icall_fptr(%rip)
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; X64-NEXT: nop
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; X64-NEXT: addq $72, %rsp
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; X64-NEXT: retq
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; X64-NEXT: .seh_endproc
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entry:
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%2 = alloca %struct.HVA, align 8
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call void @llvm.memcpy.p0.p0.i64(ptr align 8 %2, ptr align 8 %1, i64 32, i1 false)
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%3 = load %struct.HVA, ptr %2, align 8
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call x86_vectorcallcc void %0(%struct.HVA inreg %3)
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ret void
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; X64-LABEL: func_cf_vector_x64
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; X64: movq %rcx, %rax
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; X64: movups (%rdx), %xmm0
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; X64: movups 16(%rdx), %xmm1
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; X64: movaps %xmm0, 32(%rsp)
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; X64: movaps %xmm1, 48(%rsp)
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; X64: movsd 32(%rsp), %xmm0 # xmm0 = mem[0],zero
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; X64: movsd 40(%rsp), %xmm1 # xmm1 = mem[0],zero
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; X64: movsd 48(%rsp), %xmm2 # xmm2 = mem[0],zero
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; X64: movsd 56(%rsp), %xmm3 # xmm3 = mem[0],zero
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; X64: callq *__guard_dispatch_icall_fptr(%rip)
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; X64-NOT: callq
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}
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attributes #0 = { "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" }
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