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1 parent 80a4718 commit 0afbefaCopy full SHA for 0afbefa
llvm/utils/TableGen/AsmWriterEmitter.cpp
@@ -967,12 +967,11 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
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IAP.addOperand(ROName, MIOpNum, PrintMethodIdx);
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// There might be an additional predicate on the MCOperand
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- unsigned Entry = MCOpPredicateMap[Rec];
+ unsigned &Entry = MCOpPredicateMap[Rec];
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if (!Entry) {
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if (!Rec->isValueUnset("MCOperandPredicate")) {
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MCOpPredicates.push_back(Rec);
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Entry = MCOpPredicates.size();
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- MCOpPredicateMap[Rec] = Entry;
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} else
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break; // No conditions on this operand at all
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}
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