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john-brawn-armjohn-brawn-arm
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[ARM] Split up lsl-zero test into two tests
On Windows stderr and stdout happen to get interleaved in a way that causes the test to fail, so split it up into a test that checks for errors and a test that doesn't. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297273 91177308-0d34-0410-b5e6-96231b3b80d8
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‎test/MC/ARM/lsl-zero-errors.s

Lines changed: 103 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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// RUN: not llvm-mc -triple=thumbv7 -show-encoding < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-NONARM --check-prefix=CHECK-THUMBV7 %s
2+
// RUN: not llvm-mc -triple=thumbv8 -show-encoding < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-NONARM --check-prefix=CHECK-THUMBV8 %s
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// RUN: llvm-mc -triple=armv7 -show-encoding < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-ARM %s
4+
5+
// lsl #0 is actually mov, so here we check that it behaves the same as
6+
// mov with regards to the permitted registers
7+
8+
// Using PC is invalid in thumb
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lsl pc, r0, #0
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lsl r0, pc, #0
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lsl pc, pc, #0
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lsls pc, r0, #0
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lsls r0, pc, #0
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lsls pc, pc, #0
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16+
// CHECK-NONARM: error: instruction requires: arm-mode
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// CHECK-NONARM-NEXT: lsl pc, r0, #0
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// CHECK-NONARM: error: instruction requires: arm-mode
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// CHECK-NONARM-NEXT: lsl r0, pc, #0
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// CHECK-NONARM: error: instruction requires: arm-mode
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// CHECK-NONARM-NEXT: lsl pc, pc, #0
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// CHECK-NONARM: error: instruction requires: arm-mode
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// CHECK-NONARM-NEXT: lsls pc, r0, #0
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// CHECK-NONARM: error: instruction requires: arm-mode
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// CHECK-NONARM-NEXT: lsls r0, pc, #0
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// CHECK-NONARM: error: instruction requires: arm-mode
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// CHECK-NONARM-NEXT: lsls pc, pc, #0
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// CHECK-ARM: mov pc, r0 @ encoding: [0x00,0xf0,0xa0,0xe1]
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// CHECK-ARM: mov r0, pc @ encoding: [0x0f,0x00,0xa0,0xe1]
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// CHECK-ARM: mov pc, pc @ encoding: [0x0f,0xf0,0xa0,0xe1]
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// CHECK-ARM: movs pc, r0 @ encoding: [0x00,0xf0,0xb0,0xe1]
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// CHECK-ARM: movs r0, pc @ encoding: [0x0f,0x00,0xb0,0xe1]
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// CHECK-ARM: movs pc, pc @ encoding: [0x0f,0xf0,0xb0,0xe1]
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mov pc, r0, lsl #0
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mov r0, pc, lsl #0
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mov pc, pc, lsl #0
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movs pc, r0, lsl #0
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movs r0, pc, lsl #0
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movs pc, pc, lsl #0
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// FIXME: Really the error we should be giving is "requires: arm-mode"
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// CHECK-NONARM: error: invalid operand for instruction
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// CHECK-NONARM-NEXT: mov pc, r0, lsl #0
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// CHECK-NONARM: error: invalid operand for instruction
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// CHECK-NONARM-NEXT: mov r0, pc, lsl #0
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// CHECK-NONARM: error: invalid operand for instruction
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// CHECK-NONARM-NEXT: mov pc, pc, lsl #0
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// CHECK-NONARM: error: invalid operand for instruction
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// CHECK-NONARM-NEXT: movs pc, r0, lsl #0
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// CHECK-NONARM: error: invalid operand for instruction
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// CHECK-NONARM-NEXT: movs r0, pc, lsl #0
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// CHECK-NONARM: error: invalid operand for instruction
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// CHECK-NONARM-NEXT: movs pc, pc, lsl #0
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// CHECK-ARM: mov pc, r0 @ encoding: [0x00,0xf0,0xa0,0xe1]
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// CHECK-ARM: mov r0, pc @ encoding: [0x0f,0x00,0xa0,0xe1]
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// CHECK-ARM: mov pc, pc @ encoding: [0x0f,0xf0,0xa0,0xe1]
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// CHECK-ARM: movs pc, r0 @ encoding: [0x00,0xf0,0xb0,0xe1]
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// CHECK-ARM: movs r0, pc @ encoding: [0x0f,0x00,0xb0,0xe1]
62+
// CHECK-ARM: movs pc, pc @ encoding: [0x0f,0xf0,0xb0,0xe1]
63+
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// Using SP is invalid before ARMv8 in thumb unless non-flags-setting
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// and one of the source and destination is not SP
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lsl sp, sp, #0
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lsls sp, sp, #0
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lsls r0, sp, #0
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lsls sp, r0, #0
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// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later
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// CHECK-THUMBV7-NEXT: lsl sp, sp, #0
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// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later
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// CHECK-THUMBV7-NEXT: lsls sp, sp, #0
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// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later
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// CHECK-THUMBV7-NEXT: lsls r0, sp, #0
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// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later
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// CHECK-THUMBV7-NEXT: lsls sp, r0, #0
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// CHECK-ARM: mov sp, sp @ encoding: [0x0d,0xd0,0xa0,0xe1]
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// CHECK-ARM: movs sp, sp @ encoding: [0x0d,0xd0,0xb0,0xe1]
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// CHECK-ARM: movs r0, sp @ encoding: [0x0d,0x00,0xb0,0xe1]
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// CHECK-ARM: movs sp, r0 @ encoding: [0x00,0xd0,0xb0,0xe1]
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mov sp, sp, lsl #0
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movs sp, sp, lsl #0
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movs r0, sp, lsl #0
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movs sp, r0, lsl #0
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// FIXME: We should consistently have the "requires ARMv8" error here
91+
// CHECK-THUMBV7: error: invalid operand for instruction
92+
// CHECK-THUMBV7-NEXT: mov sp, sp, lsl #0
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// CHECK-THUMBV7: error: invalid operand for instruction
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// CHECK-THUMBV7-NEXT: movs sp, sp, lsl #0
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// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later
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// CHECK-THUMBV7-NEXT: movs r0, sp, lsl #0
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// CHECK-THUMBV7: error: invalid operand for instruction
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// CHECK-THUMBV7-NEXT: movs sp, r0, lsl #0
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// CHECK-ARM: mov sp, sp @ encoding: [0x0d,0xd0,0xa0,0xe1]
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// CHECK-ARM: movs sp, sp @ encoding: [0x0d,0xd0,0xb0,0xe1]
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// CHECK-ARM: movs r0, sp @ encoding: [0x0d,0x00,0xb0,0xe1]
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// CHECK-ARM: movs sp, r0 @ encoding: [0x00,0xd0,0xb0,0xe1]

‎test/MC/ARM/lsl-zero.s

Lines changed: 2 additions & 99 deletions
Original file line numberDiff line numberDiff line change
@@ -1,108 +1,11 @@
1-
// RUN: not llvm-mc -triple=thumbv7 -show-encoding < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-NONARM --check-prefix=CHECK-THUMBV7 %s
2-
// RUN: not llvm-mc -triple=thumbv8 -show-encoding < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-NONARM --check-prefix=CHECK-THUMBV8 %s
1+
// RUN: llvm-mc -triple=thumbv7 -show-encoding < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-NONARM --check-prefix=CHECK-THUMBV7 %s
2+
// RUN: llvm-mc -triple=thumbv8 -show-encoding < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-NONARM --check-prefix=CHECK-THUMBV8 %s
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// RUN: llvm-mc -triple=armv7 -show-encoding < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-ARM %s
44

55
// lsl #0 is actually mov, so here we check that it behaves the same as
66
// mov with regards to the permitted registers and how it behaves in an
77
// IT block.
88

9-
// Using PC is invalid in thumb
10-
lsl pc, r0, #0
11-
lsl r0, pc, #0
12-
lsl pc, pc, #0
13-
lsls pc, r0, #0
14-
lsls r0, pc, #0
15-
lsls pc, pc, #0
16-
17-
// CHECK-NONARM: error: instruction requires: arm-mode
18-
// CHECK-NONARM-NEXT: lsl pc, r0, #0
19-
// CHECK-NONARM: error: instruction requires: arm-mode
20-
// CHECK-NONARM-NEXT: lsl r0, pc, #0
21-
// CHECK-NONARM: error: instruction requires: arm-mode
22-
// CHECK-NONARM-NEXT: lsl pc, pc, #0
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// CHECK-NONARM: error: instruction requires: arm-mode
24-
// CHECK-NONARM-NEXT: lsls pc, r0, #0
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// CHECK-NONARM: error: instruction requires: arm-mode
26-
// CHECK-NONARM-NEXT: lsls r0, pc, #0
27-
// CHECK-NONARM: error: instruction requires: arm-mode
28-
// CHECK-NONARM-NEXT: lsls pc, pc, #0
29-
30-
// CHECK-ARM: mov pc, r0 @ encoding: [0x00,0xf0,0xa0,0xe1]
31-
// CHECK-ARM: mov r0, pc @ encoding: [0x0f,0x00,0xa0,0xe1]
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// CHECK-ARM: mov pc, pc @ encoding: [0x0f,0xf0,0xa0,0xe1]
33-
// CHECK-ARM: movs pc, r0 @ encoding: [0x00,0xf0,0xb0,0xe1]
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// CHECK-ARM: movs r0, pc @ encoding: [0x0f,0x00,0xb0,0xe1]
35-
// CHECK-ARM: movs pc, pc @ encoding: [0x0f,0xf0,0xb0,0xe1]
36-
37-
mov pc, r0, lsl #0
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mov r0, pc, lsl #0
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mov pc, pc, lsl #0
40-
movs pc, r0, lsl #0
41-
movs r0, pc, lsl #0
42-
movs pc, pc, lsl #0
43-
44-
// FIXME: Really the error we should be giving is "requires: arm-mode"
45-
// CHECK-NONARM: error: invalid operand for instruction
46-
// CHECK-NONARM-NEXT: mov pc, r0, lsl #0
47-
// CHECK-NONARM: error: invalid operand for instruction
48-
// CHECK-NONARM-NEXT: mov r0, pc, lsl #0
49-
// CHECK-NONARM: error: invalid operand for instruction
50-
// CHECK-NONARM-NEXT: mov pc, pc, lsl #0
51-
// CHECK-NONARM: error: invalid operand for instruction
52-
// CHECK-NONARM-NEXT: movs pc, r0, lsl #0
53-
// CHECK-NONARM: error: invalid operand for instruction
54-
// CHECK-NONARM-NEXT: movs r0, pc, lsl #0
55-
// CHECK-NONARM: error: invalid operand for instruction
56-
// CHECK-NONARM-NEXT: movs pc, pc, lsl #0
57-
58-
// CHECK-ARM: mov pc, r0 @ encoding: [0x00,0xf0,0xa0,0xe1]
59-
// CHECK-ARM: mov r0, pc @ encoding: [0x0f,0x00,0xa0,0xe1]
60-
// CHECK-ARM: mov pc, pc @ encoding: [0x0f,0xf0,0xa0,0xe1]
61-
// CHECK-ARM: movs pc, r0 @ encoding: [0x00,0xf0,0xb0,0xe1]
62-
// CHECK-ARM: movs r0, pc @ encoding: [0x0f,0x00,0xb0,0xe1]
63-
// CHECK-ARM: movs pc, pc @ encoding: [0x0f,0xf0,0xb0,0xe1]
64-
65-
// Using SP is invalid before ARMv8 in thumb unless non-flags-setting
66-
// and one of the source and destination is not SP
67-
lsl sp, sp, #0
68-
lsls sp, sp, #0
69-
lsls r0, sp, #0
70-
lsls sp, r0, #0
71-
72-
// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later
73-
// CHECK-THUMBV7-NEXT: lsl sp, sp, #0
74-
// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later
75-
// CHECK-THUMBV7-NEXT: lsls sp, sp, #0
76-
// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later
77-
// CHECK-THUMBV7-NEXT: lsls r0, sp, #0
78-
// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later
79-
// CHECK-THUMBV7-NEXT: lsls sp, r0, #0
80-
81-
// CHECK-ARM: mov sp, sp @ encoding: [0x0d,0xd0,0xa0,0xe1]
82-
// CHECK-ARM: movs sp, sp @ encoding: [0x0d,0xd0,0xb0,0xe1]
83-
// CHECK-ARM: movs r0, sp @ encoding: [0x0d,0x00,0xb0,0xe1]
84-
// CHECK-ARM: movs sp, r0 @ encoding: [0x00,0xd0,0xb0,0xe1]
85-
86-
mov sp, sp, lsl #0
87-
movs sp, sp, lsl #0
88-
movs r0, sp, lsl #0
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movs sp, r0, lsl #0
90-
91-
// FIXME: We should consistently have the "requires ARMv8" error here
92-
// CHECK-THUMBV7: error: invalid operand for instruction
93-
// CHECK-THUMBV7-NEXT: mov sp, sp, lsl #0
94-
// CHECK-THUMBV7: error: invalid operand for instruction
95-
// CHECK-THUMBV7-NEXT: movs sp, sp, lsl #0
96-
// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later
97-
// CHECK-THUMBV7-NEXT: movs r0, sp, lsl #0
98-
// CHECK-THUMBV7: error: invalid operand for instruction
99-
// CHECK-THUMBV7-NEXT: movs sp, r0, lsl #0
100-
101-
// CHECK-ARM: mov sp, sp @ encoding: [0x0d,0xd0,0xa0,0xe1]
102-
// CHECK-ARM: movs sp, sp @ encoding: [0x0d,0xd0,0xb0,0xe1]
103-
// CHECK-ARM: movs r0, sp @ encoding: [0x0d,0x00,0xb0,0xe1]
104-
// CHECK-ARM: movs sp, r0 @ encoding: [0x00,0xd0,0xb0,0xe1]
105-
1069
// Non-flags-setting with only one of source and destination SP should
10710
// be OK
10811
lsl sp, r0, #0

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