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[mips] Add initial release notes for MIPS32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_38@260095 91177308-0d34-0410-b5e6-96231b3b80d8
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docs/ReleaseNotes.rst

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@@ -107,8 +107,63 @@ Changes to the ARM Backend
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Changes to the MIPS Target
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--------------------------
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During this release ...
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During this release the MIPS target has:
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* Significantly extended support for the Integrated Assembler. See below for
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more information
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* Added support for the ``P5600`` processor.
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* Added support for the ``interrupt`` attribute for MIPS32R2 and later. This
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attribute will generate a function which can be used as a interrupt handler
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on bare metal MIPS targets using the static relocation model.
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* Added support for the ``ERETNC`` instruction found in MIPS32R5 and later.
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* Added support for OpenCL. See http://portablecl.org/.
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* Address spaces 1 to 255 are now reserved for software use and conversions
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between them are no-op casts.
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* Removed the ``mips16`` value for the -mcpu option since it is an :abbr:`ASE
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(Application Specific Extension)` and not a processor. If you were using this,
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please specify another CPU and use ``-mips16`` to enable MIPS16.
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* Removed ``copy_u.w`` from 32-bit MSA and ``copy_u.d`` from 64-bit MSA since
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they have been removed from the MSA specification due to forward compatibility
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issues. For example, 32-bit MSA code containing ``copy_u.w`` would behave
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differently on a 64-bit processor supporting MSA. The corresponding intrinsics
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are still available and may expand to ``copy_s.[wd]`` where this is
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appropriate for forward compatibility purposes.
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* Relaxed the ``-mnan`` option to allow ``-mnan=2008`` on MIPS32R2/MIPS64R2 for
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compatibility with GCC.
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* Made MIPS64R6 the default CPU for 64-bit Android triples.
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The MIPS target has also fixed various bugs including the following notable
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fixes:
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* Fixed reversed operands on ``mthi``/``mtlo`` in the DSP :abbr:`ASE
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(Application Specific Extension)`.
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* The code generator no longer uses ``jal`` for calls to absolute immediate
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addresses.
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* Disabled fast instruction selection on MIPS32R6 and MIPS64R6 since this is not
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yet supported.
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* Corrected addend for ``R_MIPS_HI16`` and ``R_MIPS_PCHI16`` in MCJIT
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* The code generator no longer crashes when handling subregisters of an 64-bit
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FPU register with undefined value.
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* The code generator no longer attempts to use ``$zero`` for operands that do
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not permit ``$zero``.
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* Corrected the opcode used for ``ll``/``sc`` when using MIPS32R6/MIPS64R6 and
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the Integrated Assembler.
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* Added support for atomic load and atomic store.
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* Corrected debug info when dynamically re-aligning the stack.
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Integrated Assembler
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^^^^^^^^^^^^^^^^^^^^
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We have made a large number of improvements to the integrated assembler for
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MIPS. In this release, the integrated assembler isn't quite production-ready
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since there are a few known issues related to bare-metal support, checking
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immediates on instructions, and the N32/N64 ABI's. However, the current support
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should be sufficient for many users of the O32 ABI, particularly those targeting
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MIPS32 on Linux or bare-metal MIPS32.
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If you would like to try the integrated assembler, please use
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``-fintegrated-as``.
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Changes to the PowerPC Target
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-----------------------------

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