@@ -107,8 +107,63 @@ Changes to the ARM Backend
107
107
Changes to the MIPS Target
108
108
--------------------------
109
109
110
- During this release ...
111
-
110
+ During this release the MIPS target has:
111
+
112
+ * Significantly extended support for the Integrated Assembler. See below for
113
+ more information
114
+ * Added support for the ``P5600 `` processor.
115
+ * Added support for the ``interrupt `` attribute for MIPS32R2 and later. This
116
+ attribute will generate a function which can be used as a interrupt handler
117
+ on bare metal MIPS targets using the static relocation model.
118
+ * Added support for the ``ERETNC `` instruction found in MIPS32R5 and later.
119
+ * Added support for OpenCL. See http://portablecl.org/.
120
+
121
+ * Address spaces 1 to 255 are now reserved for software use and conversions
122
+ between them are no-op casts.
123
+
124
+ * Removed the ``mips16 `` value for the -mcpu option since it is an :abbr: `ASE
125
+ ( Application Specific Extension ) ` and not a processor. If you were using this,
126
+ please specify another CPU and use ``-mips16 `` to enable MIPS16.
127
+ * Removed ``copy_u.w `` from 32-bit MSA and ``copy_u.d `` from 64-bit MSA since
128
+ they have been removed from the MSA specification due to forward compatibility
129
+ issues. For example, 32-bit MSA code containing ``copy_u.w `` would behave
130
+ differently on a 64-bit processor supporting MSA. The corresponding intrinsics
131
+ are still available and may expand to ``copy_s.[wd] `` where this is
132
+ appropriate for forward compatibility purposes.
133
+ * Relaxed the ``-mnan `` option to allow ``-mnan=2008 `` on MIPS32R2/MIPS64R2 for
134
+ compatibility with GCC.
135
+ * Made MIPS64R6 the default CPU for 64-bit Android triples.
136
+
137
+ The MIPS target has also fixed various bugs including the following notable
138
+ fixes:
139
+
140
+ * Fixed reversed operands on ``mthi ``/``mtlo `` in the DSP :abbr: `ASE
141
+ ( Application Specific Extension ) `.
142
+ * The code generator no longer uses ``jal `` for calls to absolute immediate
143
+ addresses.
144
+ * Disabled fast instruction selection on MIPS32R6 and MIPS64R6 since this is not
145
+ yet supported.
146
+ * Corrected addend for ``R_MIPS_HI16 `` and ``R_MIPS_PCHI16 `` in MCJIT
147
+ * The code generator no longer crashes when handling subregisters of an 64-bit
148
+ FPU register with undefined value.
149
+ * The code generator no longer attempts to use ``$zero `` for operands that do
150
+ not permit ``$zero ``.
151
+ * Corrected the opcode used for ``ll ``/``sc `` when using MIPS32R6/MIPS64R6 and
152
+ the Integrated Assembler.
153
+ * Added support for atomic load and atomic store.
154
+ * Corrected debug info when dynamically re-aligning the stack.
155
+
156
+ Integrated Assembler
157
+ ^^^^^^^^^^^^^^^^^^^^
158
+ We have made a large number of improvements to the integrated assembler for
159
+ MIPS. In this release, the integrated assembler isn't quite production-ready
160
+ since there are a few known issues related to bare-metal support, checking
161
+ immediates on instructions, and the N32/N64 ABI's. However, the current support
162
+ should be sufficient for many users of the O32 ABI, particularly those targeting
163
+ MIPS32 on Linux or bare-metal MIPS32.
164
+
165
+ If you would like to try the integrated assembler, please use
166
+ ``-fintegrated-as ``.
112
167
113
168
Changes to the PowerPC Target
114
169
-----------------------------
0 commit comments