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| 1 | +#include "lut.h" |
| 2 | + |
| 3 | +namespace fasm { |
| 4 | + |
| 5 | +Lut::Lut(size_t num_inputs) : num_inputs_(num_inputs), table_(1 << num_inputs, vtr::LogicValue::DONT_CARE) {} |
| 6 | + |
| 7 | +void Lut::SetOutput(const std::vector<vtr::LogicValue> &inputs, vtr::LogicValue value) { |
| 8 | + VTR_ASSERT(inputs.size() == num_inputs_); |
| 9 | + std::vector<size_t> dont_care_inputs; |
| 10 | + dont_care_inputs.reserve(num_inputs_); |
| 11 | + |
| 12 | + for(size_t address = 0; address < table_.size(); ++address) { |
| 13 | + bool match = true; |
| 14 | + for(size_t input = 0; input < inputs.size(); ++input) { |
| 15 | + if(inputs[input] == vtr::LogicValue::TRUE && (address & (1 << input)) == 0) { |
| 16 | + match = false; |
| 17 | + break; |
| 18 | + } else if(inputs[input] == vtr::LogicValue::FALSE && (address & (1 << input)) != 0) { |
| 19 | + match = false; |
| 20 | + break; |
| 21 | + } |
| 22 | + } |
| 23 | + |
| 24 | + if(match) { |
| 25 | + VTR_ASSERT(table_[address] == vtr::LogicValue::DONT_CARE || table_[address] == value); |
| 26 | + table_[address] = value; |
| 27 | + } |
| 28 | + } |
| 29 | +} |
| 30 | + |
| 31 | +void Lut::CreateWire(size_t input_pin) { |
| 32 | + std::vector<vtr::LogicValue> inputs(num_inputs_, vtr::LogicValue::DONT_CARE); |
| 33 | + inputs[input_pin] = vtr::LogicValue::FALSE; |
| 34 | + SetOutput(inputs, vtr::LogicValue::FALSE); |
| 35 | + inputs[input_pin] = vtr::LogicValue::TRUE; |
| 36 | + SetOutput(inputs, vtr::LogicValue::TRUE); |
| 37 | +} |
| 38 | + |
| 39 | +void Lut::SetConstant(vtr::LogicValue value) { |
| 40 | + std::vector<vtr::LogicValue> inputs(num_inputs_, vtr::LogicValue::DONT_CARE); |
| 41 | + SetOutput(inputs, value); |
| 42 | +} |
| 43 | + |
| 44 | +const LogicVec & Lut::table() { |
| 45 | + // Make sure the entire table is defined. |
| 46 | + for(size_t address = 0; address < table_.size(); ++address) { |
| 47 | + if(table_[address] == vtr::LogicValue::DONT_CARE) { |
| 48 | + table_[address] = vtr::LogicValue::FALSE; |
| 49 | + } |
| 50 | + } |
| 51 | + |
| 52 | + return table_; |
| 53 | +} |
| 54 | + |
| 55 | +LutOutputDefinition::LutOutputDefinition(std::string definition) { |
| 56 | + // Parse LUT.INIT[63:0] into |
| 57 | + // fasm_feature = LUT.INIT |
| 58 | + // start_bit = 0 |
| 59 | + // end_bit = 63 |
| 60 | + // num_inputs = log2(end_bit-start_bit+1) |
| 61 | + |
| 62 | + size_t slice_start = definition.find_first_of('['); |
| 63 | + size_t slice = std::string::npos; |
| 64 | + size_t slice_end = std::string::npos; |
| 65 | + |
| 66 | + if(slice_start != std::string::npos) { |
| 67 | + slice = definition.find_first_of(':', slice_start); |
| 68 | + } |
| 69 | + if(slice != std::string::npos) { |
| 70 | + slice_end = definition.find_first_of(']'); |
| 71 | + } |
| 72 | + |
| 73 | + if(slice_start == std::string::npos || |
| 74 | + slice == std::string::npos || |
| 75 | + slice_end == std::string::npos || |
| 76 | + slice_start+1 > slice-1 || |
| 77 | + slice+1 > slice_end-1) { |
| 78 | + vpr_throw( |
| 79 | + VPR_ERROR_OTHER, __FILE__, __LINE__, |
| 80 | + "Could not parse LUT definition %s", |
| 81 | + definition.c_str()); |
| 82 | + } |
| 83 | + |
| 84 | + fasm_feature = definition.substr(0, slice_start); |
| 85 | + std::string end_bit_str = definition.substr(slice_start+1, (slice-1)-(slice_start+1)+1); |
| 86 | + std::string start_bit_str = definition.substr(slice+1, (slice_end-1)-(slice+1)+1); |
| 87 | + |
| 88 | + end_bit = vtr::atoi(end_bit_str); |
| 89 | + start_bit = vtr::atoi(start_bit_str); |
| 90 | + |
| 91 | + int width = end_bit - start_bit + 1; |
| 92 | + |
| 93 | + // If an exact power of two, only 1 bit will be set in width. |
| 94 | + if(width < 0 || __builtin_popcount(width) != 1) { |
| 95 | + vpr_throw( |
| 96 | + VPR_ERROR_OTHER, __FILE__, __LINE__, |
| 97 | + "Invalid LUT start_bit %d and end_bit %d, not a power of 2 width.", |
| 98 | + start_bit, end_bit); |
| 99 | + } |
| 100 | + |
| 101 | + // For exact power's of 2, ctz (count trailing zeros) is log2(width). |
| 102 | + num_inputs = __builtin_ctz(width); |
| 103 | +} |
| 104 | + |
| 105 | +std::string LutOutputDefinition::CreateWire(int input) const { |
| 106 | + Lut lut(num_inputs); |
| 107 | + lut.CreateWire(input); |
| 108 | + |
| 109 | + return CreateInit(lut.table()); |
| 110 | +} |
| 111 | + |
| 112 | +std::string LutOutputDefinition::CreateConstant(vtr::LogicValue value) const { |
| 113 | + Lut lut(num_inputs); |
| 114 | + lut.SetConstant(value); |
| 115 | + return CreateInit(lut.table()); |
| 116 | +} |
| 117 | + |
| 118 | +std::string LutOutputDefinition::CreateInit(const LogicVec & table) const { |
| 119 | + if(table.size() != (1u << num_inputs)) { |
| 120 | + vpr_throw( |
| 121 | + VPR_ERROR_OTHER, __FILE__, __LINE__, |
| 122 | + "LUT with %d inputs requires a INIT LogicVec of size %d, got %d", |
| 123 | + num_inputs, (1 << num_inputs), table.size()); |
| 124 | + } |
| 125 | + std::stringstream ss; |
| 126 | + ss << fasm_feature << "[" << end_bit << ":" << start_bit << "]=" << table; |
| 127 | + |
| 128 | + return ss.str(); |
| 129 | +} |
| 130 | + |
| 131 | +} // namespace fasm |
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