Implement initial explicit ports.

litghost · litghost · commit 4c9eb58543c6 · 2019-12-13T11:08:44.000-08:00
This implements part one of verilog-to-routing#1063 Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h
@@ -523,6 +523,12 @@ enum class e_sb_type {
 
 };
 
+enum class e_capacity_type {
+    DUPLICATE, // Capacity duplicates ports.
+    EXPLICIT   // Capacity increases the number of logical tiles, but does not
+               // modify the physical ports.
+};
+
 constexpr int NO_SWITCH = -1;
 constexpr int DEFAULT_SWITCH = -2;
 
@@ -577,6 +583,7 @@ struct t_physical_tile_type {
     int num_clock_pins = 0;
 
     int capacity = 0;
+    e_capacity_type capacity_type = e_capacity_type::DUPLICATE;
 
     int width = 0;
     int height = 0;
@@ -625,18 +632,20 @@ struct t_physical_tile_type {
  *  vtr::bimap container.
  */
 struct t_logical_pin {
+    int z_index = -1;
     int pin = -1;
 
-    t_logical_pin(int value) {
+    t_logical_pin(int z_index_value, int value) {
+        z_index = z_index_value;
         pin = value;
     }
 
     bool operator==(const t_logical_pin o) const {
-        return pin == o.pin;
+        return z_index == o.z_index && pin == o.pin;
     }
 
     bool operator<(const t_logical_pin o) const {
-        return pin < o.pin;
+        return std::make_pair(z_index, pin) < std::make_pair(o.z_index, o.pin);
     }
 };
 
diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp
diff --git a/vpr/src/base/ShowSetup.cpp b/vpr/src/base/ShowSetup.cpp
@@ -79,7 +79,7 @@ void printClusteredNetlistStats() {
         num_blocks_type[logical_block->index]++;
         if (is_io_type(physical_tile)) {
             for (j = 0; j < logical_block->pb_type->num_pins; j++) {
-                int physical_pin = get_physical_pin(physical_tile, logical_block, j);
+                int physical_pin = get_physical_pin(physical_tile, /*z_index=*/0, logical_block, j);
                 auto pin_class = physical_tile->pin_class[physical_pin];
                 auto class_inf = physical_tile->class_inf[pin_class];
 
diff --git a/vpr/src/base/check_netlist.cpp b/vpr/src/base/check_netlist.cpp
@@ -95,7 +95,7 @@ static int check_connections_to_global_clb_pins(ClusterNetId net_id, int verbosi
         auto physical_type = pick_best_physical_type(logical_type);
 
         int log_index = cluster_ctx.clb_nlist.pin_logical_index(pin_id);
-        int pin_index = get_physical_pin(physical_type, logical_type, log_index);
+        int pin_index = get_physical_pin(physical_type, /*z_index=*/0, logical_type, log_index);
 
         if (physical_type->is_ignored_pin[pin_index] != net_is_ignored
             && !is_io_type(physical_type)) {
diff --git a/vpr/src/base/read_netlist.cpp b/vpr/src/base/read_netlist.cpp
@@ -951,7 +951,7 @@ static void load_external_nets_and_cb(ClusteredNetlist& clb_nlist) {
         block_type = clb_nlist.block_type(blk_id);
         auto tile_type = pick_best_physical_type(block_type);
         for (j = 0; j < block_type->pb_type->num_pins; j++) {
-            int physical_pin = get_physical_pin(tile_type, block_type, j);
+            int physical_pin = get_physical_pin(tile_type, /*z_index=*/0, block_type, j);
 
             //Iterate through each pin of the block, and see if there is a net allocated/used for it
             clb_net_id = clb_nlist.block_net(blk_id, j);
@@ -1001,7 +1001,7 @@ static void load_external_nets_and_cb(ClusteredNetlist& clb_nlist) {
             block_type = clb_nlist.block_type(clb_nlist.pin_block(pin_id));
             auto tile_type = pick_best_physical_type(block_type);
             int logical_pin = clb_nlist.pin_logical_index(pin_id);
-            int physical_pin = get_physical_pin(tile_type, block_type, logical_pin);
+            int physical_pin = get_physical_pin(tile_type, /*z_index=*/0, block_type, logical_pin);
 
             if (tile_type->is_ignored_pin[physical_pin] != is_ignored_net) {
                 VTR_LOG_WARN(
diff --git a/vpr/src/draw/draw.cpp b/vpr/src/draw/draw.cpp
@@ -2661,7 +2661,7 @@ void draw_highlight_blocks_color(t_logical_block_type_ptr type, ClusterBlockId b
             continue;
 
         auto physical_tile = physical_tile_type(blk_id);
-        int physical_pin = get_physical_pin(physical_tile, type, k);
+        int physical_pin = get_physical_pin(physical_tile, /*z_index=*/0, type, k);
 
         iclass = physical_tile->pin_class[physical_pin];
 
diff --git a/vpr/src/pack/output_clustering.cpp b/vpr/src/pack/output_clustering.cpp
@@ -66,7 +66,7 @@ static void print_stats() {
         auto logical_block = cluster_ctx.clb_nlist.block_type(blk_id);
         auto physical_tile = pick_best_physical_type(logical_block);
         for (ipin = 0; ipin < logical_block->pb_type->num_pins; ipin++) {
-            int physical_pin = get_physical_pin(physical_tile, logical_block, ipin);
+            int physical_pin = get_physical_pin(physical_tile, /*z_index=*/0, logical_block, ipin);
             auto pin_class = physical_tile->pin_class[physical_pin];
             auto pin_class_inf = physical_tile->class_inf[pin_class];
 
diff --git a/vpr/src/place/place_macro.cpp b/vpr/src/place/place_macro.cpp
@@ -82,7 +82,7 @@ static void find_all_the_macro(int* num_of_macro, std::vector<ClusterBlockId>& p
 
         num_blk_pins = cluster_ctx.clb_nlist.block_type(blk_id)->pb_type->num_pins;
         for (to_iblk_pin = 0; to_iblk_pin < num_blk_pins; to_iblk_pin++) {
-            int to_physical_pin = get_physical_pin(physical_tile, logical_block, to_iblk_pin);
+            int to_physical_pin = get_physical_pin(physical_tile, /*z_index=*/0, logical_block, to_iblk_pin);
 
             to_net_id = cluster_ctx.clb_nlist.block_net(blk_id, to_iblk_pin);
             to_idirect = f_idirect_from_blk_pin[physical_tile->index][to_physical_pin];
@@ -102,7 +102,7 @@ static void find_all_the_macro(int* num_of_macro, std::vector<ClusterBlockId>& p
                     || (is_constant_clb_net(to_net_id)
                         && !net_is_driven_by_direct(to_net_id)))) {
                 for (from_iblk_pin = 0; from_iblk_pin < num_blk_pins; from_iblk_pin++) {
-                    int from_physical_pin = get_physical_pin(physical_tile, logical_block, from_iblk_pin);
+                    int from_physical_pin = get_physical_pin(physical_tile, /*z_index=*/0, logical_block, from_iblk_pin);
 
                     from_net_id = cluster_ctx.clb_nlist.block_net(blk_id, from_iblk_pin);
                     from_idirect = f_idirect_from_blk_pin[physical_tile->index][from_physical_pin];
diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp
@@ -319,7 +319,7 @@ std::vector<AtomPinId> find_clb_pin_connected_atom_pins(ClusterBlockId clb, int
     auto logical_block = clb_nlist.block_type(clb);
     auto physical_tile = pick_best_physical_type(logical_block);
 
-    int physical_pin = get_physical_pin(physical_tile, logical_block, logical_pin);
+    int physical_pin = get_physical_pin(physical_tile, /*z_index=*/0, logical_block, logical_pin);
 
     if (is_opin(physical_pin, physical_tile)) {
         //output
@@ -2068,14 +2068,11 @@ void place_sync_external_block_connections(ClusterBlockId iblk) {
     auto logical_block = clb_nlist.block_type(iblk);
 
     VTR_ASSERT(physical_tile->num_pins % physical_tile->capacity == 0);
-    int max_num_block_pins = physical_tile->num_pins / physical_tile->capacity;
-    /* Logical location and physical location is offset by z * max_num_block_pins */
-
     for (auto pin : clb_nlist.block_pins(iblk)) {
         int logical_pin_index = clb_nlist.pin_logical_index(pin);
-        int physical_pin_index = get_physical_pin(physical_tile, logical_block, logical_pin_index);
-
-        int new_physical_pin_index = physical_pin_index + place_ctx.block_locs[iblk].loc.z * max_num_block_pins;
+        int new_physical_pin_index = get_physical_pin(
+            physical_tile, place_ctx.block_locs[iblk].loc.z,
+            logical_block, logical_pin_index);
 
         auto result = place_ctx.physical_pins.find(pin);
         if (result != place_ctx.physical_pins.end()) {
@@ -2123,32 +2120,34 @@ t_logical_block_type_ptr pick_best_logical_type(t_physical_tile_type_ptr physica
     return physical_tile->equivalent_sites[0];
 }
 
-int get_logical_pin(t_physical_tile_type_ptr physical_tile,
-                    t_logical_block_type_ptr logical_block,
-                    int pin) {
-    t_physical_pin physical_pin(pin);
-
-    auto direct_map = physical_tile->tile_block_pin_directs_map.at(logical_block->index);
-    auto result = direct_map.find(physical_pin);
+int get_physical_pin(const ClusterBlockId blk,
+                     t_logical_block_type_ptr logical_block,
+                     int pin) {
+    auto& place_ctx = g_vpr_ctx.placement();
+    auto& device_ctx = g_vpr_ctx.device();
 
-    if (result == direct_map.inverse_end()) {
-        VTR_LOG_WARN(
-            "Couldn't find the corresponding logical pin of the physical pin %d."
-            "Physical Tile: %s, Logical Block: %s.\n",
-            pin, physical_tile->name, logical_block->name);
-        return OPEN;
-    }
+    auto block_loc = place_ctx.block_locs[blk];
+    auto loc = block_loc.loc;
 
-    return result->second.pin;
+    return get_physical_pin(
+        device_ctx.grid[loc.x][loc.y].type,
+        loc.z,
+        logical_block,
+        pin);
 }
 
 int get_physical_pin(t_physical_tile_type_ptr physical_tile,
+                     int z_index,
                      t_logical_block_type_ptr logical_block,
                      int pin) {
-    t_logical_pin logical_pin(pin);
-
-    auto direct_map = physical_tile->tile_block_pin_directs_map.at(logical_block->index);
-    auto result = direct_map.find(logical_pin);
+    const auto& direct_map = physical_tile->tile_block_pin_directs_map.at(logical_block->index);
+    auto result = direct_map.begin();
+    if (physical_tile->capacity_type == e_capacity_type::DUPLICATE) {
+        result = direct_map.find(t_logical_pin(/*z_index=*/0, pin));
+    } else {
+        VTR_ASSERT(physical_tile->capacity_type == e_capacity_type::EXPLICIT);
+        result = direct_map.find(t_logical_pin(z_index, pin));
+    }
 
     if (result == direct_map.end()) {
         VTR_LOG_WARN(
@@ -2158,7 +2157,15 @@ int get_physical_pin(t_physical_tile_type_ptr physical_tile,
         return OPEN;
     }
 
-    return result->second.pin;
+    int physical_pin_index = result->second.pin;
+    if (physical_tile->capacity_type == e_capacity_type::DUPLICATE) {
+        int max_num_block_pins = physical_tile->num_pins / physical_tile->capacity;
+        /* Logical location and physical location is offset by z * max_num_block_pins */
+        return physical_pin_index + z_index * max_num_block_pins;
+    } else {
+        VTR_ASSERT(physical_tile->capacity_type == e_capacity_type::EXPLICIT);
+        return physical_pin_index;
+    }
 }
 
 int net_pin_to_tile_pin_index(const ClusterNetId net_id, int net_pin_index) {
diff --git a/vpr/src/util/vpr_utils.h b/vpr/src/util/vpr_utils.h
@@ -159,10 +159,11 @@ bool is_tile_compatible(t_physical_tile_type_ptr physical_tile, t_logical_block_
 t_physical_tile_type_ptr pick_best_physical_type(t_logical_block_type_ptr logical_block);
 t_logical_block_type_ptr pick_best_logical_type(t_physical_tile_type_ptr physical_tile);
 
-int get_logical_pin(t_physical_tile_type_ptr physical_tile,
-                    t_logical_block_type_ptr logical_block,
-                    int pin);
 int get_physical_pin(t_physical_tile_type_ptr physical_tile,
+                     int z_index,
+                     t_logical_block_type_ptr logical_block,
+                     int pin);
+int get_physical_pin(const ClusterBlockId blk,
                      t_logical_block_type_ptr logical_block,
                      int pin);
 
