Remove work-around for pcrel issue

laanwj · laanwj · commit 2f441ce82293 · 2019-07-09T14:52:07.000Z
With rust-lang/rust#62281, rust compiles in mcmodel=medium mode by default and this work-around is no longer needed.
diff --git a/memory-k210.x b/memory-k210.x
@@ -2,10 +2,8 @@ _max_hart_id = 1;
 
 MEMORY
 {
-    /* Workaround for the pcrel issue, as described here:
-       https://github.com/rust-embedded/riscv-rt/issues/25#issuecomment-491518168 */
-    SRAM : ORIGIN = 0xffffffff80000000, LENGTH = 6M
-    AI_SRAM : ORIGIN = 0xffffffff80600000, LENGTH = 2M
+    SRAM : ORIGIN = 0x80000000, LENGTH = 6M
+    AI_SRAM : ORIGIN = 0x80600000, LENGTH = 2M
     SRAM_NOCACHE : ORIGIN = 0x40000000, LENGTH = 6M
     AI_SRAM_NOCACHE : ORIGIN = 0x40600000, LENGTH = 2M
 }

Original file line number	Diff line number	Diff line change
`@@ -2,10 +2,8 @@ _max_hart_id = 1;`
`2`	`2`
`3`	`3`	`MEMORY`
`4`	`4`	`{`
`5`		`- /* Workaround for the pcrel issue, as described here:`
`6`		`- https://github.com/rust-embedded/riscv-rt/issues/25#issuecomment-491518168 */`
`7`		`- SRAM : ORIGIN = 0xffffffff80000000, LENGTH = 6M`
`8`		`- AI_SRAM : ORIGIN = 0xffffffff80600000, LENGTH = 2M`
	`5`	`+ SRAM : ORIGIN = 0x80000000, LENGTH = 6M`
	`6`	`+ AI_SRAM : ORIGIN = 0x80600000, LENGTH = 2M`
`9`	`7`	`SRAM_NOCACHE : ORIGIN = 0x40000000, LENGTH = 6M`
`10`	`8`	`AI_SRAM_NOCACHE : ORIGIN = 0x40600000, LENGTH = 2M`
`11`	`9`	`}`