Add FXSAVE/FXRSTOR, update Intel SDE, fix xsave tests (rust-lang#205)

* [x86] add run-time detection for fxsr
* [x86] add i386 fxsr intrinsics: FXSAVE,FXRSTOR
* [x86_64] add x86_64 fxsr intrinsics: FXSAVE64/FXRSTOR64
* [x86-runtime]: document xsave detection further
* [x86] disable xsaves and xsaves64 tests

Author: gnzlbg

ci/docker/x86_64-unknown-linux-gnu-emulated/Dockerfile

@@ -5,9 +5,9 @@ RUN apt-get update && apt-get install -y --no-install-recommends \
   file \
   make \
   ca-certificates \
-  curl \
+  wget \
   bzip2
 
-RUN curl https://s3-us-west-1.amazonaws.com/rust-lang-ci2/rust-ci-mirror/sde-external-8.9.0-2017-08-06-lin.tar.bz2 | \
-  tar xjf -
-ENV CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER="/sde-external-8.9.0-2017-08-06-lin/sde64 --"
+RUN wget https://github.com/gnzlbg/intel_sde/raw/master/sde-external-8.12.0-2017-10-23-lin.tar.bz2
+RUN tar -xjf sde-external-8.12.0-2017-10-23-lin.tar.bz2
+ENV CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER="/sde-external-8.12.0-2017-10-23-lin/sde64 --"

coresimd/src/runtime/x86.rs

@@ -132,6 +132,10 @@ macro_rules! __unstable_detect_feature {
         $crate::vendor::__unstable_detect_feature(
             $crate::vendor::__Feature::popcnt{})
     };
+    ("fxsr") => {
+        $crate::vendor::__unstable_detect_feature(
+            $crate::vendor::__Feature::fxsr{})
+    };
     ("xsave") => {
         $crate::vendor::__unstable_detect_feature(
             $crate::vendor::__Feature::xsave{})
@@ -212,6 +216,8 @@ pub enum __Feature {
     tbm,
     /// POPCNT (Population Count)
     popcnt,
+    /// FXSR (Floating-point context fast save and restor)
+    fxsr,
     /// XSAVE (Save Processor Extended States)
     xsave,
     /// XSAVEOPT (Save Processor Extended States Optimized)
@@ -325,24 +331,27 @@ pub fn detect_features() -> usize {
         enable(proc_info_ecx, 19, __Feature::sse4_1);
         enable(proc_info_ecx, 20, __Feature::sse4_2);
         enable(proc_info_ecx, 23, __Feature::popcnt);
+        enable(proc_info_edx, 24, __Feature::fxsr);
         enable(proc_info_edx, 25, __Feature::sse);
         enable(proc_info_edx, 26, __Feature::sse2);
 
         enable(extended_features_ebx, 3, __Feature::bmi);
         enable(extended_features_ebx, 8, __Feature::bmi2);
 
         // `XSAVE` and `AVX` support:
-        if bit::test(proc_info_ecx as usize, 26) {
+        let cpu_xsave = bit::test(proc_info_ecx as usize, 26);
+        if cpu_xsave {
             // 0. Here the CPU supports `XSAVE`.
 
             // 1. Detect `OSXSAVE`, that is, whether the OS is AVX enabled and
             // supports saving the state of the AVX/AVX2 vector registers on
             // context-switches, see:
             //
-            // - https://software.intel.
-            // com/en-us/blogs/2011/04/14/is-avx-enabled
-            // - https://hg.mozilla.
-            // org/mozilla-central/file/64bab5cbb9b6/mozglue/build/SSE.cpp#l190
+            // - [intel: is avx enabled?][is_avx_enabled],
+            // - [mozilla: sse.cpp][mozilla_sse_cpp].
+            //
+            // [is_avx_enabled]: https://software.intel.com/en-us/blogs/2011/04/14/is-avx-enabled
+            // [mozilla_sse_cpp]: https://hg.mozilla.org/mozilla-central/file/64bab5cbb9b6/mozglue/build/SSE.cpp#l190
             let cpu_osxsave = bit::test(proc_info_ecx as usize, 27);
 
             // 2. The OS must have signaled the CPU that it supports saving and
@@ -354,11 +363,34 @@ pub fn detect_features() -> usize {
             let os_avx_support = xcr0 & 6 == 6;
             let os_avx512_support = xcr0 & 224 == 224;
 
+            // Only if the OS and the CPU support saving/restoring the AVX
+            // registers we enable `xsave` support:
             if cpu_osxsave && os_avx_support {
-                // Only if the OS and the CPU support saving/restoring the AVX
-                // registers we enable `xsave` support:
+                // See "13.3 ENABLING THE XSAVE FEATURE SET AND XSAVE-ENABLED
+                // FEATURES" in the "Intel® 64 and IA-32 Architectures Software
+                // Developer’s Manual, Volume 1: Basic Architecture":
+                //
+                // "Software enables the XSAVE feature set by setting
+                // CR4.OSXSAVE[bit 18] to 1 (e.g., with the MOV to CR4
+                // instruction). If this bit is 0, execution of any of XGETBV,
+                // XRSTOR, XRSTORS, XSAVE, XSAVEC, XSAVEOPT, XSAVES, and XSETBV
+                // causes an invalid-opcode exception (#UD)"
+                //
                 enable(proc_info_ecx, 26, __Feature::xsave);
 
+                // For `xsaveopt`, `xsavec`, and `xsaves` we need to query:
+                // Processor Extended State Enumeration Sub-leaf (EAX = 0DH,
+                // ECX = 1):
+                if max_basic_leaf >= 0xd {
+                    let CpuidResult {
+                        eax: proc_extended_state1_eax,
+                        ..
+                    } = unsafe { __cpuid_count(0xd_u32, 1) };
+                    enable(proc_extended_state1_eax, 0, __Feature::xsaveopt);
+                    enable(proc_extended_state1_eax, 1, __Feature::xsavec);
+                    enable(proc_extended_state1_eax, 3, __Feature::xsaves);
+                }
+
                 // And AVX/AVX2:
                 enable(proc_info_ecx, 28, __Feature::avx);
                 enable(extended_features_ebx, 5, __Feature::avx2);
@@ -382,18 +414,6 @@ pub fn detect_features() -> usize {
                     );
                 }
             }
-
-            // Processor Extended State Enumeration Sub-leaf
-            // (EAX = 0DH, ECX = 1)
-            if max_basic_leaf >= 0xd {
-                let CpuidResult {
-                    eax: proc_extended_state1_eax,
-                    ..
-                } = unsafe { __cpuid_count(0xd_u32, 1) };
-                enable(proc_extended_state1_eax, 0, __Feature::xsaveopt);
-                enable(proc_extended_state1_eax, 1, __Feature::xsavec);
-                enable(proc_extended_state1_eax, 3, __Feature::xsaves);
-            }
         }
 
         // This detects ABM on AMD CPUs and LZCNT on Intel CPUs.
@@ -448,10 +468,11 @@ mod tests {
         println!("tbm: {:?}", cfg_feature_enabled!("tbm"));
         println!("popcnt: {:?}", cfg_feature_enabled!("popcnt"));
         println!("lzcnt: {:?}", cfg_feature_enabled!("lzcnt"));
-        println!("xsave {:?}", cfg_feature_enabled!("xsave"));
-        println!("xsaveopt {:?}", cfg_feature_enabled!("xsaveopt"));
-        println!("xsaves {:?}", cfg_feature_enabled!("xsaves"));
-        println!("xsavec {:?}", cfg_feature_enabled!("xsavec"));
+        println!("fxsr: {:?}", cfg_feature_enabled!("fxsr"));
+        println!("xsave: {:?}", cfg_feature_enabled!("xsave"));
+        println!("xsaveopt: {:?}", cfg_feature_enabled!("xsaveopt"));
+        println!("xsaves: {:?}", cfg_feature_enabled!("xsaves"));
+        println!("xsavec: {:?}", cfg_feature_enabled!("xsavec"));
     }
 
     #[test]

coresimd/src/x86/i386/fxsr.rs

@@ -0,0 +1,106 @@
+//! FXSR floating-point context fast save and restor.
+
+#[cfg(test)]
+use stdsimd_test::assert_instr;
+
+#[allow(improper_ctypes)]
+extern "C" {
+    #[link_name = "llvm.x86.fxsave"]
+    fn fxsave(p: *mut u8) -> ();
+    #[link_name = "llvm.x86.fxrstor"]
+    fn fxrstor(p: *const u8) -> ();
+}
+
+/// Saves the `x87` FPU, `MMX` technology, `XMM`, and `MXCSR` registers to the
+/// 512-byte-long 16-byte-aligned memory region `mem_addr`.
+///
+/// A misaligned destination operand raises a general-protection (#GP) or an
+/// alignment check exception (#AC).
+///
+/// See [`FXSAVE`][fxsave] and [`FXRSTOR`][fxrstor].
+///
+/// [fxsave]: http://www.felixcloutier.com/x86/FXSAVE.html
+/// [fxrstor]: http://www.felixcloutier.com/x86/FXRSTOR.html
+#[inline(always)]
+#[target_feature = "+fxsr"]
+#[cfg_attr(test, assert_instr(fxsave))]
+pub unsafe fn _fxsave(mem_addr: *mut u8) {
+    fxsave(mem_addr)
+}
+
+/// Restores the `XMM`, `MMX`, `MXCSR`, and `x87` FPU registers from the
+/// 512-byte-long 16-byte-aligned memory region `mem_addr`.
+///
+/// The contents of this memory region should have been written to by a
+/// previous
+/// `_fxsave` or `_fxsave64` intrinsic.
+///
+/// A misaligned destination operand raises a general-protection (#GP) or an
+/// alignment check exception (#AC).
+///
+/// See [`FXSAVE`][fxsave] and [`FXRSTOR`][fxrstor].
+///
+/// [fxsave]: http://www.felixcloutier.com/x86/FXSAVE.html
+/// [fxrstor]: http://www.felixcloutier.com/x86/FXRSTOR.html
+#[inline(always)]
+#[target_feature = "+fxsr"]
+#[cfg_attr(test, assert_instr(fxrstor))]
+pub unsafe fn _fxrstor(mem_addr: *const u8) {
+    fxrstor(mem_addr)
+}
+
+#[cfg(test)]
+mod tests {
+    use x86::i386::fxsr;
+    use stdsimd_test::simd_test;
+    use std::fmt;
+
+    #[repr(align(16))]
+    struct FxsaveArea {
+        data: [u8; 512], // 512 bytes
+    }
+
+    impl FxsaveArea {
+        fn new() -> FxsaveArea {
+            FxsaveArea { data: [0; 512] }
+        }
+        fn ptr(&mut self) -> *mut u8 {
+            &mut self.data[0] as *mut _ as *mut u8
+        }
+    }
+
+    impl PartialEq<FxsaveArea> for FxsaveArea {
+        fn eq(&self, other: &FxsaveArea) -> bool {
+            for i in 0..self.data.len() {
+                if self.data[i] != other.data[i] {
+                    return false;
+                }
+            }
+            true
+        }
+    }
+
+    impl fmt::Debug for FxsaveArea {
+        fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+            write!(f, "[")?;
+            for i in 0..self.data.len() {
+                write!(f, "{}", self.data[i])?;
+                if i != self.data.len() - 1 {
+                    write!(f, ", ")?;
+                }
+            }
+            write!(f, "]")
+        }
+    }
+
+    #[simd_test = "fxsr"]
+    unsafe fn fxsave() {
+        let mut a = FxsaveArea::new();
+        let mut b = FxsaveArea::new();
+
+        fxsr::_fxsave(a.ptr());
+        fxsr::_fxrstor(a.ptr());
+        fxsr::_fxsave(b.ptr());
+        assert_eq!(a, b);
+    }
+}

coresimd/src/x86/i386/mod.rs

@@ -2,3 +2,6 @@
 
 mod eflags;
 pub use self::eflags::*;
+
+mod fxsr;
+pub use self::fxsr::*;