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uros
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PR target/66473
* config/i386/i386.c (ix86_expand_vector_set): Use gen_int_mode to prepare mask operand for AVX512 modes. testsuite/ChangeLog: PR target/66473 * gcc.target/i386/pr66473.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@224340 138bc75d-0d04-0410-961f-82ee72b054a4
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gcc/ChangeLog

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,9 @@
1+
2015-06-10 Uros Bizjak <[email protected]>
2+
3+
PR target/66473
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* config/i386/i386.c (ix86_expand_vector_set): Use gen_int_mode
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to prepare mask operand for AVX512 modes.
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2015-06-10 Michael Meissner <[email protected]>
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39
PR target/66474

gcc/config/i386/i386.c

Lines changed: 34 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -44720,6 +44720,8 @@ ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
4472044720
{ gen_vec_set_lo_v4df, gen_vec_set_hi_v4df }
4472144721
};
4472244722
int i, j, n;
44723+
machine_mode mmode = VOIDmode;
44724+
rtx (*gen_blendm) (rtx, rtx, rtx, rtx);
4472344725

4472444726
switch (mode)
4472544727
{
@@ -44936,75 +44938,64 @@ ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
4493644938
case V8DFmode:
4493744939
if (TARGET_AVX512F)
4493844940
{
44939-
tmp = gen_reg_rtx (mode);
44940-
emit_insn (gen_rtx_SET (tmp, gen_rtx_VEC_DUPLICATE (mode, val)));
44941-
emit_insn (gen_avx512f_blendmv8df (target, tmp, target,
44942-
force_reg (QImode, GEN_INT (1 << elt))));
44943-
return;
44941+
mmode = QImode;
44942+
gen_blendm = gen_avx512f_blendmv8df;
4494444943
}
44945-
else
44946-
break;
44944+
break;
44945+
4494744946
case V8DImode:
4494844947
if (TARGET_AVX512F)
4494944948
{
44950-
tmp = gen_reg_rtx (mode);
44951-
emit_insn (gen_rtx_SET (tmp, gen_rtx_VEC_DUPLICATE (mode, val)));
44952-
emit_insn (gen_avx512f_blendmv8di (target, tmp, target,
44953-
force_reg (QImode, GEN_INT (1 << elt))));
44954-
return;
44949+
mmode = QImode;
44950+
gen_blendm = gen_avx512f_blendmv8di;
4495544951
}
44956-
else
44957-
break;
44952+
break;
44953+
4495844954
case V16SFmode:
4495944955
if (TARGET_AVX512F)
4496044956
{
44961-
tmp = gen_reg_rtx (mode);
44962-
emit_insn (gen_rtx_SET (tmp, gen_rtx_VEC_DUPLICATE (mode, val)));
44963-
emit_insn (gen_avx512f_blendmv16sf (target, tmp, target,
44964-
force_reg (HImode, GEN_INT (1 << elt))));
44965-
return;
44957+
mmode = HImode;
44958+
gen_blendm = gen_avx512f_blendmv16sf;
4496644959
}
44967-
else
44968-
break;
44960+
break;
44961+
4496944962
case V16SImode:
4497044963
if (TARGET_AVX512F)
4497144964
{
44972-
tmp = gen_reg_rtx (mode);
44973-
emit_insn (gen_rtx_SET (tmp, gen_rtx_VEC_DUPLICATE (mode, val)));
44974-
emit_insn (gen_avx512f_blendmv16si (target, tmp, target,
44975-
force_reg (HImode, GEN_INT (1 << elt))));
44976-
return;
44965+
mmode = HImode;
44966+
gen_blendm = gen_avx512f_blendmv16si;
4497744967
}
44978-
else
44979-
break;
44968+
break;
44969+
4498044970
case V32HImode:
4498144971
if (TARGET_AVX512F && TARGET_AVX512BW)
4498244972
{
44983-
tmp = gen_reg_rtx (mode);
44984-
emit_insn (gen_rtx_SET (tmp, gen_rtx_VEC_DUPLICATE (mode, val)));
44985-
emit_insn (gen_avx512bw_blendmv32hi (target, tmp, target,
44986-
force_reg (SImode, GEN_INT (1 << elt))));
44987-
return;
44973+
mmode = SImode;
44974+
gen_blendm = gen_avx512bw_blendmv32hi;
4498844975
}
44989-
else
44990-
break;
44976+
break;
44977+
4499144978
case V64QImode:
4499244979
if (TARGET_AVX512F && TARGET_AVX512BW)
4499344980
{
44994-
tmp = gen_reg_rtx (mode);
44995-
emit_insn (gen_rtx_SET (tmp, gen_rtx_VEC_DUPLICATE (mode, val)));
44996-
emit_insn (gen_avx512bw_blendmv64qi (target, tmp, target,
44997-
force_reg (DImode, GEN_INT (1 << elt))));
44998-
return;
44981+
mmode = DImode;
44982+
gen_blendm = gen_avx512bw_blendmv64qi;
4499944983
}
45000-
else
45001-
break;
44984+
break;
4500244985

4500344986
default:
4500444987
break;
4500544988
}
4500644989

45007-
if (use_vec_merge)
44990+
if (mmode != VOIDmode)
44991+
{
44992+
tmp = gen_reg_rtx (mode);
44993+
emit_insn (gen_rtx_SET (tmp, gen_rtx_VEC_DUPLICATE (mode, val)));
44994+
emit_insn (gen_blendm (target, tmp, target,
44995+
force_reg (mmode,
44996+
gen_int_mode (1 << elt, mmode))));
44997+
}
44998+
else if (use_vec_merge)
4500844999
{
4500945000
tmp = gen_rtx_VEC_DUPLICATE (mode, val);
4501045001
tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));

gcc/testsuite/ChangeLog

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,8 @@
1+
2015-06-10 Uros Bizjak <[email protected]>
2+
3+
PR target/66473
4+
* gcc.target/i386/pr66473.c: New test.
5+
16
2015-06-10 Jakub Jelinek <[email protected]>
27

38
PR target/66470
Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,17 @@
1+
/* { dg-do compile } */
2+
/* { dg-options "-O2 -mavx512f" } */
3+
4+
typedef double __m512d __attribute__ ((__vector_size__ (64)));
5+
6+
extern __m512d _ZGVeN8v_func (__m512d);
7+
8+
double
9+
func_vlen8 (double x)
10+
{
11+
__m512d mx, mr;
12+
13+
mx[0] = mx[1] = mx[2] = mx[3] = mx[4] = mx[5] = mx[6] = mx[7] = x;
14+
mr = _ZGVeN8v_func (mx);
15+
16+
return (double) mr[0];
17+
}

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