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WIP: xtensa: add -mforce-l32
Signed-off-by: Max Filippov <[email protected]>
1 parent ed248ce commit 6b0c9f9

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4 files changed

+98
-23
lines changed

4 files changed

+98
-23
lines changed

‎gcc/config/xtensa/constraints.md

+15
Original file line numberDiff line numberDiff line change
@@ -137,3 +137,18 @@
137137
(and (match_code "reg")
138138
(match_test "reload_in_progress
139139
&& REGNO (op) >= FIRST_PSEUDO_REGISTER"))))
140+
141+
(define_constraint "Y"
142+
"Memory that is not in a literal pool."
143+
(ior (and (and (match_code "mem")
144+
(match_test "! constantpool_mem_p (op)"))
145+
(match_test "!TARGET_FORCE_L32"))
146+
(and (match_code "reg")
147+
(match_test "reload_in_progress
148+
&& REGNO (op) >= FIRST_PSEUDO_REGISTER"))))
149+
150+
(define_constraint "Z"
151+
"Memory that is not in a literal pool."
152+
(and (and (match_code "mem")
153+
(match_test "! constantpool_mem_p (op)"))
154+
(match_test "TARGET_FORCE_L32")))

‎gcc/config/xtensa/xtensa.c

+52-1
Original file line numberDiff line numberDiff line change
@@ -1824,7 +1824,8 @@ xtensa_legitimate_address_p (machine_mode mode, rtx addr, bool strict)
18241824
return true;
18251825

18261826
/* Check for "register + offset" addressing. */
1827-
if (GET_CODE (addr) == PLUS)
1827+
if (GET_CODE (addr) == PLUS &&
1828+
(!TARGET_FORCE_L32 || (mode != HImode && mode != QImode)))
18281829
{
18291830
rtx xplus0 = XEXP (addr, 0);
18301831
rtx xplus1 = XEXP (addr, 1);
@@ -2308,6 +2309,8 @@ printx (FILE *file, signed int val)
23082309
fprintf (file, "0x%x", val);
23092310
}
23102311

2312+
static void
2313+
output_address_base (FILE *file, rtx addr);
23112314

23122315
void
23132316
print_operand (FILE *file, rtx x, int letter)
@@ -2317,6 +2320,13 @@ print_operand (FILE *file, rtx x, int letter)
23172320

23182321
switch (letter)
23192322
{
2323+
case 'B':
2324+
if (GET_CODE (x) == MEM)
2325+
output_address_base (file, XEXP (x, 0));
2326+
else
2327+
output_operand_lossage ("invalid %%B value");
2328+
break;
2329+
23202330
case 'D':
23212331
if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
23222332
fprintf (file, "%s", reg_names[xt_true_regnum (x) + 1]);
@@ -2450,6 +2460,47 @@ print_operand (FILE *file, rtx x, int letter)
24502460
}
24512461
}
24522462

2463+
static void
2464+
output_address_base (FILE *file, rtx addr)
2465+
{
2466+
switch (GET_CODE (addr))
2467+
{
2468+
default:
2469+
fatal_insn ("invalid address", addr);
2470+
break;
2471+
2472+
case REG:
2473+
fprintf (file, "%s", reg_names [REGNO (addr)]);
2474+
break;
2475+
2476+
case PLUS:
2477+
{
2478+
rtx reg = (rtx)0;
2479+
rtx offset = (rtx)0;
2480+
rtx arg0 = XEXP (addr, 0);
2481+
rtx arg1 = XEXP (addr, 1);
2482+
2483+
if (GET_CODE (arg0) == REG)
2484+
{
2485+
reg = arg0;
2486+
offset = arg1;
2487+
}
2488+
else if (GET_CODE (arg1) == REG)
2489+
{
2490+
reg = arg1;
2491+
offset = arg0;
2492+
}
2493+
else
2494+
fatal_insn ("no register in address", addr);
2495+
2496+
if (CONSTANT_P (offset))
2497+
fprintf (file, "%s", reg_names [REGNO (reg)]);
2498+
else
2499+
fatal_insn ("address offset not a constant", addr);
2500+
}
2501+
break;
2502+
}
2503+
}
24532504

24542505
/* A C compound statement to output to stdio stream STREAM the
24552506
assembler syntax for an instruction operand that is a memory

‎gcc/config/xtensa/xtensa.md

+27-22
Original file line numberDiff line numberDiff line change
@@ -532,26 +532,28 @@
532532
;; Zero-extend instructions.
533533

534534
(define_insn "zero_extendhisi2"
535-
[(set (match_operand:SI 0 "register_operand" "=a,a")
536-
(zero_extend:SI (match_operand:HI 1 "nonimmed_operand" "r,U")))]
535+
[(set (match_operand:SI 0 "register_operand" "=a,a,a")
536+
(zero_extend:SI (match_operand:HI 1 "nonimmed_operand" "r,Y,Z")))]
537537
""
538538
"@
539539
extui\t%0, %1, 0, 16
540-
l16ui\t%0, %1"
541-
[(set_attr "type" "arith,load")
540+
l16ui\t%0, %1
541+
ssa8l\t%B1 ; srli\t%0, %B1, 2 ; slli\t%0, %0, 2 ; l32i\t%0, %0, 0 ; srl\t%0, %0 ; extui\t%0, %0, 0, 16"
542+
[(set_attr "type" "arith,load,load")
542543
(set_attr "mode" "SI")
543-
(set_attr "length" "3,3")])
544+
(set_attr "length" "3,3,18")])
544545

545546
(define_insn "zero_extendqisi2"
546-
[(set (match_operand:SI 0 "register_operand" "=a,a")
547-
(zero_extend:SI (match_operand:QI 1 "nonimmed_operand" "r,U")))]
547+
[(set (match_operand:SI 0 "register_operand" "=a,a,a")
548+
(zero_extend:SI (match_operand:QI 1 "nonimmed_operand" "r,Y,Z")))]
548549
""
549550
"@
550551
extui\t%0, %1, 0, 8
551-
l8ui\t%0, %1"
552-
[(set_attr "type" "arith,load")
552+
l8ui\t%0, %1
553+
ssa8l\t%B1 ; srli\t%0, %B1, 2 ; slli\t%0, %0, 2 ; l32i\t%0, %0, 0 ; srl\t%0, %0 ; extui\t%0, %0, 0, 8"
554+
[(set_attr "type" "arith,load,load")
553555
(set_attr "mode" "SI")
554-
(set_attr "length" "3,3")])
556+
(set_attr "length" "3,3,18")])
555557

556558

557559
;; Sign-extend instructions.
@@ -569,15 +571,16 @@
569571
})
570572

571573
(define_insn "extendhisi2_internal"
572-
[(set (match_operand:SI 0 "register_operand" "=B,a")
573-
(sign_extend:SI (match_operand:HI 1 "sext_operand" "r,U")))]
574+
[(set (match_operand:SI 0 "register_operand" "=B,a,a")
575+
(sign_extend:SI (match_operand:HI 1 "sext_operand" "r,r,Y")))]
574576
""
575577
"@
576578
sext\t%0, %1, 15
579+
slli\t%0, %1, 16 ; srai\t%0, %0, 16
577580
l16si\t%0, %1"
578-
[(set_attr "type" "arith,load")
581+
[(set_attr "type" "arith,arith,load")
579582
(set_attr "mode" "SI")
580-
(set_attr "length" "3,3")])
583+
(set_attr "length" "3,6,3")])
581584

582585
(define_expand "extendqisi2"
583586
[(set (match_operand:SI 0 "register_operand" "")
@@ -796,21 +799,22 @@
796799
})
797800

798801
(define_insn "movhi_internal"
799-
[(set (match_operand:HI 0 "nonimmed_operand" "=D,D,a,a,a,U,*a,*A")
800-
(match_operand:HI 1 "move_operand" "M,d,r,I,U,r,*A,*r"))]
802+
[(set (match_operand:HI 0 "nonimmed_operand" "=D,D,a,a,a,a,U,*a,*A")
803+
(match_operand:HI 1 "move_operand" "M,d,r,I,Y,Z,r,*A,*r"))]
801804
"xtensa_valid_move (HImode, operands)"
802805
"@
803806
movi.n\t%0, %x1
804807
mov.n\t%0, %1
805808
mov\t%0, %1
806809
movi\t%0, %x1
807810
%v1l16ui\t%0, %1
811+
ssa8l\t%B1 ; srli\t%0, %B1, 2 ; slli\t%0, %0, 2 ; %v1l32i\t%0, %0, 0 ; srl\t%0, %0 ; extui\t%0, %0, 0, 16
808812
%v0s16i\t%1, %0
809813
rsr\t%0, ACCLO
810814
wsr\t%1, ACCLO"
811-
[(set_attr "type" "move,move,move,move,load,store,rsr,wsr")
815+
[(set_attr "type" "move,move,move,move,load,load,store,rsr,wsr")
812816
(set_attr "mode" "HI")
813-
(set_attr "length" "2,2,3,3,3,3,3,3")])
817+
(set_attr "length" "2,2,3,3,3,18,3,3,3")])
814818

815819
;; 8-bit Integer moves
816820

@@ -824,21 +828,22 @@
824828
})
825829

826830
(define_insn "movqi_internal"
827-
[(set (match_operand:QI 0 "nonimmed_operand" "=D,D,a,a,a,U,*a,*A")
828-
(match_operand:QI 1 "move_operand" "M,d,r,I,U,r,*A,*r"))]
831+
[(set (match_operand:QI 0 "nonimmed_operand" "=D,D,a,a,a,a,U,*a,*A")
832+
(match_operand:QI 1 "move_operand" "M,d,r,I,Y,Z,r,*A,*r"))]
829833
"xtensa_valid_move (QImode, operands)"
830834
"@
831835
movi.n\t%0, %x1
832836
mov.n\t%0, %1
833837
mov\t%0, %1
834838
movi\t%0, %x1
835839
%v1l8ui\t%0, %1
840+
ssa8l\t%B1 ; srli\t%0, %B1, 2 ; slli\t%0, %0, 2 ; %v1l32i\t%0, %0, 0 ; srl\t%0, %0 ; extui\t%0, %0, 0, 8
836841
%v0s8i\t%1, %0
837842
rsr\t%0, ACCLO
838843
wsr\t%1, ACCLO"
839-
[(set_attr "type" "move,move,move,move,load,store,rsr,wsr")
844+
[(set_attr "type" "move,move,move,move,load,load,store,rsr,wsr")
840845
(set_attr "mode" "QI")
841-
(set_attr "length" "2,2,3,3,3,3,3,3")])
846+
(set_attr "length" "2,2,3,3,3,18,3,3,3")])
842847

843848
;; Sub-word reloads from the constant pool.
844849

‎gcc/config/xtensa/xtensa.opt

+4
Original file line numberDiff line numberDiff line change
@@ -41,3 +41,7 @@ Intersperse literal pools with code in the text section
4141
mserialize-volatile
4242
Target Report Mask(SERIALIZE_VOLATILE)
4343
-mno-serialize-volatile Do not serialize volatile memory references with MEMW instructions
44+
45+
mforce-l32
46+
Target Report Mask(FORCE_L32)
47+
Use l32i to access 1- and 2-byte quantities in memory instead of l8ui/l16ui

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