We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent cff7ad5 commit d910fbcCopy full SHA for d910fbc
llvm/docs/ReleaseNotes.md
@@ -272,6 +272,9 @@ Changes to the RISC-V Backend
272
* `cf` constraint meaning an RVC-encoding compatible FPR (`f8`-`f15`)
273
* `R` constraint meaning an even-odd GPR pair (prints as the even register,
274
but both registers in the pair are considered live).
275
+ * `cR` constraint meaning an RVC-encoding compatible even-odd GPR Pair (prints
276
+ as an even register between `x8` and `x14`, but both registers in the pair
277
+ are considered live).
278
* `N` modifer meaning print the register encoding (0-31) rather than the name.
279
* `f` and `cf` inline assembly constraints, when using F-/D-/H-in-X extensions,
280
will use the relevant GPR rather than FPR. This makes inline assembly portable
0 commit comments