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[AMDGPU] Update AMDGPUUsage.rst to document two intrinsics (llvm#123816)
The AMDGPUUsage.rst file is updated to document two intrinsics: llvm.amdgcn.mov.dpp and llvm.amdgcn.update.dpp.
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llvm/docs/AMDGPUUsage.rst

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@@ -1422,6 +1422,19 @@ The AMDGPU backend implements the following LLVM IR intrinsics.
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Returns a pair for the swapped registers. The first element of the return
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corresponds to the swapped element of the first argument.
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llvm.amdgcn.mov.dpp The llvm.amdgcn.mov.dpp.`<type>` intrinsic represents the mov.dpp operation in AMDGPU.
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This operation is being deprecated and can be replaced with llvm.amdgcn.update.dpp.
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llvm.amdgcn.update.dpp The llvm.amdgcn.update.dpp.`<type>` intrinsic represents the update.dpp operation in AMDGPU.
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It takes an old value, a source operand, a DPP control operand, a row mask, a bank mask, and a bound control.
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Various data types are supported, including, bf16, f16, f32, f64, i16, i32, i64, p0, p3, p5, v2f16, v2f32, v2i16, v2i32, v2p0, v3i32, v4i32, v8f16.
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This operation is equivalent to a sequence of v_mov_b32 operations.
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It is preferred over llvm.amdgcn.mov.dpp.`<type>` for future use.
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`llvm.amdgcn.update.dpp.<type> <old> <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl>`
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Should be equivalent to:
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- `v_mov_b32 <dest> <old>`
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- `v_mov_b32 <dest> <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl>`
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============================================== ==========================================================
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.. TODO::

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