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[NFC][TableGen] Create valid Dag in VarLenCodeEmitter (llvm#140283)
- Set the Dag ArgNames correctly when normalizing the Dag for slice. - Add unit test to exercise the "slice" hi/lo swap case.
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+18
-10
lines changed

2 files changed

+18
-10
lines changed

llvm/test/TableGen/VarLenEncoder.td

Lines changed: 14 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,8 @@ class MyVarInst<MyMemOperand memory_op> : Instruction {
3636
(operand "$dst", 4),
3737
// Testing operand referencing with a certain bit range.
3838
(slice "$dst", 3, 1),
39+
// Testing slice hi/lo swap.
40+
(slice "$dst", 1, 3),
3941
// Testing custom encoder
4042
(operand "$dst", 2, (encoder "myCustomEncoder"))
4143
);
@@ -57,9 +59,9 @@ def FOO16 : MyVarInst<MemOp16<"src">>;
5759
def FOO32 : MyVarInst<MemOp32<"src">>;
5860

5961
// The fixed bits part
60-
// CHECK: {/*NumBits*/41,
62+
// CHECK: {/*NumBits*/44,
6163
// CHECK-SAME: // FOO16
62-
// CHECK: {/*NumBits*/57,
64+
// CHECK: {/*NumBits*/60,
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// CHECK-SAME: // FOO32
6466
// CHECK: UINT64_C(46848), // FOO16
6567
// CHECK: UINT64_C(46848), // FOO32
@@ -78,9 +80,12 @@ def FOO32 : MyVarInst<MemOp32<"src">>;
7880
// 2nd dst
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// CHECK: getMachineOpValue(MI, MI.getOperand(0), /*Pos=*/36, Scratch, Fixups, STI);
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// CHECK: Inst.insertBits(Scratch.extractBits(3, 1), 36);
83+
// Slice hi/lo swap
84+
// CHECK: getMachineOpValue(MI, MI.getOperand(0), /*Pos=*/39, Scratch, Fixups, STI);
85+
// CHECK: Inst.insertBits(Scratch.extractBits(3, 1), 39);
8186
// dst w/ custom encoder
82-
// CHECK: myCustomEncoder(MI, /*OpIdx=*/0, /*Pos=*/39, Scratch, Fixups, STI);
83-
// CHECK: Inst.insertBits(Scratch.extractBits(2, 0), 39);
87+
// CHECK: myCustomEncoder(MI, /*OpIdx=*/0, /*Pos=*/42, Scratch, Fixups, STI);
88+
// CHECK: Inst.insertBits(Scratch.extractBits(2, 0), 42);
8489

8590
// CHECK-LABEL: case ::FOO32: {
8691
// CHECK: Scratch.getBitWidth() < 32
@@ -96,6 +101,9 @@ def FOO32 : MyVarInst<MemOp32<"src">>;
96101
// 2nd dst
97102
// CHECK: getMachineOpValue(MI, MI.getOperand(0), /*Pos=*/52, Scratch, Fixups, STI);
98103
// CHECK: Inst.insertBits(Scratch.extractBits(3, 1), 52);
104+
// Slice hi/lo swap
105+
// CHECK: getMachineOpValue(MI, MI.getOperand(0), /*Pos=*/55, Scratch, Fixups, STI);
106+
// CHECK: Inst.insertBits(Scratch.extractBits(3, 1), 55);
99107
// dst w/ custom encoder
100-
// CHECK: myCustomEncoder(MI, /*OpIdx=*/0, /*Pos=*/55, Scratch, Fixups, STI);
101-
// CHECK: Inst.insertBits(Scratch.extractBits(2, 0), 55);
108+
// CHECK: myCustomEncoder(MI, /*OpIdx=*/0, /*Pos=*/58, Scratch, Fixups, STI);
109+
// CHECK: Inst.insertBits(Scratch.extractBits(2, 0), 58);

llvm/utils/TableGen/Common/VarLenCodeEmitterGen.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -212,10 +212,10 @@ void VarLenInst::buildRec(const DagInit *DI) {
212212

213213
if (NeedSwap) {
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// Normalization: Hi bit should always be the second argument.
215-
const Init *const NewArgs[] = {OperandName, LoBit, HiBit};
216-
// TODO: This creates an invalid DagInit with 3 Args but 0 ArgNames.
217-
// Extend unit test to exercise this and fix it.
218-
Segments.push_back({NumBits, DagInit::get(DI->getOperator(), NewArgs, {}),
215+
SmallVector<std::pair<const Init *, const StringInit *>> NewArgs(
216+
DI->getArgAndNames());
217+
std::swap(NewArgs[1], NewArgs[2]);
218+
Segments.push_back({NumBits, DagInit::get(DI->getOperator(), NewArgs),
219219
CustomEncoder, CustomDecoder});
220220
} else {
221221
Segments.push_back({NumBits, DI, CustomEncoder, CustomDecoder});

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