cmd/compile/internal/ssa: add support for GOARCH=mips{,le}

Change-Id: I632d4aef7295778ba5018d98bcb06a68bcf07ce1
Reviewed-on: https://go-review.googlesource.com/31478
Run-TryBot: Brad Fitzpatrick <[email protected]>
TryBot-Result: Gobot Gobot <[email protected]>
Reviewed-by: Cherry Zhang <[email protected]>

Author: Vladimir Stefanovic

Diff for: src/cmd/compile/internal/ssa/config.go

@@ -36,6 +36,7 @@ type Config struct {
 	use387          bool                       // GO386=387
 	OldArch         bool                       // True for older versions of architecture, e.g. true for PPC64BE, false for PPC64LE
 	NeedsFpScratch  bool                       // No direct move between GP and FP register sets
+	BigEndian       bool                       //
 	DebugTest       bool                       // default true unless $GOSSAHASH != ""; as a debugging aid, make new code conditional on this and use GOSSAHASH to binary search for failing cases
 	sparsePhiCutoff uint64                     // Sparse phi location algorithm used above this #blocks*#variables score
 	curFunc         *Func
@@ -204,6 +205,7 @@ func NewConfig(arch string, fe Frontend, ctxt *obj.Link, optimize bool) *Config
 		c.noDuffDevice = obj.GOOS == "darwin" // darwin linker cannot handle BR26 reloc with non-zero addend
 	case "ppc64":
 		c.OldArch = true
+		c.BigEndian = true
 		fallthrough
 	case "ppc64le":
 		c.IntSize = 8
@@ -219,7 +221,10 @@ func NewConfig(arch string, fe Frontend, ctxt *obj.Link, optimize bool) *Config
 		c.noDuffDevice = true // TODO: Resolve PPC64 DuffDevice (has zero, but not copy)
 		c.NeedsFpScratch = true
 		c.hasGReg = true
-	case "mips64", "mips64le":
+	case "mips64":
+		c.BigEndian = true
+		fallthrough
+	case "mips64le":
 		c.IntSize = 8
 		c.PtrSize = 8
 		c.RegSize = 8
@@ -245,6 +250,24 @@ func NewConfig(arch string, fe Frontend, ctxt *obj.Link, optimize bool) *Config
 		c.LinkReg = linkRegS390X
 		c.hasGReg = true
 		c.noDuffDevice = true
+		c.BigEndian = true
+	case "mips":
+		c.BigEndian = true
+		fallthrough
+	case "mipsle":
+		c.IntSize = 4
+		c.PtrSize = 4
+		c.RegSize = 4
+		c.lowerBlock = rewriteBlockMIPS
+		c.lowerValue = rewriteValueMIPS
+		c.registers = registersMIPS[:]
+		c.gpRegMask = gpRegMaskMIPS
+		c.fpRegMask = fpRegMaskMIPS
+		c.specialRegMask = specialRegMaskMIPS
+		c.FPReg = framepointerRegMIPS
+		c.LinkReg = linkRegMIPS
+		c.hasGReg = true
+		c.noDuffDevice = true
 	default:
 		fe.Fatalf(0, "arch %s not implemented", arch)
 	}

Diff for: src/cmd/compile/internal/ssa/gen/MIPS.rules

@@ -9,31 +9,57 @@
 (Int64Hi (Int64Make hi _)) -> hi
 (Int64Lo (Int64Make _ lo)) -> lo
 
-// Assuming little endian (we don't support big endian 32-bit architecture yet)
-(Load <t> ptr mem) && is64BitInt(t) && t.IsSigned() ->
+
+(Load <t> ptr mem) && is64BitInt(t) && !config.BigEndian && t.IsSigned() ->
 	(Int64Make
 		(Load <config.fe.TypeInt32()> (OffPtr <config.fe.TypeInt32().PtrTo()> [4] ptr) mem)
 		(Load <config.fe.TypeUInt32()> ptr mem))
-(Load <t> ptr mem) && is64BitInt(t) && !t.IsSigned() ->
+
+(Load <t> ptr mem) && is64BitInt(t) && !config.BigEndian && !t.IsSigned() ->
 	(Int64Make
 		(Load <config.fe.TypeUInt32()> (OffPtr <config.fe.TypeUInt32().PtrTo()> [4] ptr) mem)
 		(Load <config.fe.TypeUInt32()> ptr mem))
 
-(Store [8] dst (Int64Make hi lo) mem) ->
+(Load <t> ptr mem) && is64BitInt(t) && config.BigEndian && t.IsSigned() ->
+	(Int64Make
+		(Load <config.fe.TypeInt32()> ptr mem)
+		(Load <config.fe.TypeUInt32()> (OffPtr <config.fe.TypeUInt32().PtrTo()> [4] ptr) mem))
+
+(Load <t> ptr mem) && is64BitInt(t) && config.BigEndian && !t.IsSigned() ->
+	(Int64Make
+		(Load <config.fe.TypeUInt32()> ptr mem)
+		(Load <config.fe.TypeUInt32()> (OffPtr <config.fe.TypeUInt32().PtrTo()> [4] ptr) mem))
+
+(Store [8] dst (Int64Make hi lo) mem) && !config.BigEndian ->
 	(Store [4]
 		(OffPtr <hi.Type.PtrTo()> [4] dst)
 		hi
 		(Store [4] dst lo mem))
 
-(Arg {n} [off]) && is64BitInt(v.Type) && v.Type.IsSigned() ->
+(Store [8] dst (Int64Make hi lo) mem) && config.BigEndian ->
+	(Store [4]
+		(OffPtr <lo.Type.PtrTo()> [4] dst)
+		lo
+		(Store [4] dst hi mem))
+
+(Arg {n} [off]) && is64BitInt(v.Type) && !config.BigEndian && v.Type.IsSigned() ->
   (Int64Make
     (Arg <config.fe.TypeInt32()> {n} [off+4])
     (Arg <config.fe.TypeUInt32()> {n} [off]))
-(Arg {n} [off]) && is64BitInt(v.Type) && !v.Type.IsSigned() ->
+(Arg {n} [off]) && is64BitInt(v.Type) && !config.BigEndian && !v.Type.IsSigned() ->
   (Int64Make
     (Arg <config.fe.TypeUInt32()> {n} [off+4])
     (Arg <config.fe.TypeUInt32()> {n} [off]))
 
+(Arg {n} [off]) && is64BitInt(v.Type) && config.BigEndian && v.Type.IsSigned() ->
+  (Int64Make
+    (Arg <config.fe.TypeInt32()> {n} [off])
+    (Arg <config.fe.TypeUInt32()> {n} [off+4]))
+(Arg {n} [off]) && is64BitInt(v.Type) && config.BigEndian && !v.Type.IsSigned() ->
+  (Int64Make
+    (Arg <config.fe.TypeUInt32()> {n} [off])
+    (Arg <config.fe.TypeUInt32()> {n} [off+4]))
+
 (Add64 x y) ->
 	(Int64Make
 		(Add32withcarry <config.fe.TypeInt32()>

Diff for: src/cmd/compile/internal/ssa/gen/MIPSOps.go

@@ -195,13 +195,13 @@ func genOp() {
 			}
 			if v.faultOnNilArg0 {
 				fmt.Fprintln(w, "faultOnNilArg0: true,")
-				if v.aux != "SymOff" && v.aux != "SymValAndOff" && v.aux != "Int64" && v.aux != "" {
+				if v.aux != "SymOff" && v.aux != "SymValAndOff" && v.aux != "Int64" && v.aux != "Int32" && v.aux != "" {
 					log.Fatalf("faultOnNilArg0 with aux %s not allowed", v.aux)
 				}
 			}
 			if v.faultOnNilArg1 {
 				fmt.Fprintln(w, "faultOnNilArg1: true,")
-				if v.aux != "SymOff" && v.aux != "SymValAndOff" && v.aux != "Int64" && v.aux != "" {
+				if v.aux != "SymOff" && v.aux != "SymValAndOff" && v.aux != "Int64" && v.aux != "Int32" && v.aux != "" {
 					log.Fatalf("faultOnNilArg1 with aux %s not allowed", v.aux)
 				}
 			}

Diff for: src/cmd/compile/internal/ssa/gen/dec64.rules

@@ -184,6 +184,8 @@ func nilcheckelim2(f *Func) {
 					if v.Aux != nil || off < 0 || off >= minZeroPage {
 						continue
 					}
+				case auxInt32:
+					// Mips uses this auxType for atomic add constant. It does not affect the effective address.
 				case auxInt64:
 					// ARM uses this auxType for duffcopy/duffzero/alignment info.
 					// It does not affect the effective address.