@@ -30,39 +30,43 @@ void pinMode( uint32_t ulPin, uint32_t ulMode )
30
30
return ;
31
31
}
32
32
33
+ EPortType port = g_APinDescription [ulPin ].ulPort ;
34
+ uint32_t pin = g_APinDescription [ulPin ].ulPin ;
35
+ uint32_t pinMask = (1ul << pin );
36
+
33
37
// Set pin mode according to chapter '22.6.3 I/O Pin Configuration'
34
38
switch ( ulMode )
35
39
{
36
40
case INPUT :
37
41
// Set pin to input mode
38
- PORT -> Group [g_APinDescription [ ulPin ]. ulPort ]. PINCFG [g_APinDescription [ ulPin ]. ulPin ].reg = (uint8_t )(PORT_PINCFG_INEN ) ;
39
- PORT -> Group [g_APinDescription [ ulPin ]. ulPort ]. DIRCLR .reg = ( uint32_t )( 1 << g_APinDescription [ ulPin ]. ulPin ) ;
42
+ PORT -> Group [port ]. PINCFG [pin ].reg = (uint8_t )(PORT_PINCFG_INEN ) ;
43
+ PORT -> Group [port ]. DIRCLR .reg = pinMask ;
40
44
break ;
41
45
42
46
case INPUT_PULLUP :
43
47
// Set pin to input mode with pull-up resistor enabled
44
- PORT -> Group [g_APinDescription [ ulPin ]. ulPort ]. PINCFG [g_APinDescription [ ulPin ]. ulPin ].reg = (uint8_t )(PORT_PINCFG_INEN |PORT_PINCFG_PULLEN ) ;
45
- PORT -> Group [g_APinDescription [ ulPin ]. ulPort ]. DIRCLR .reg = ( uint32_t )( 1 << g_APinDescription [ ulPin ]. ulPin ) ;
48
+ PORT -> Group [port ]. PINCFG [pin ].reg = (uint8_t )(PORT_PINCFG_INEN |PORT_PINCFG_PULLEN ) ;
49
+ PORT -> Group [port ]. DIRCLR .reg = pinMask ;
46
50
47
51
// Enable pull level (cf '22.6.3.2 Input Configuration' and '22.8.7 Data Output Value Set')
48
- PORT -> Group [g_APinDescription [ ulPin ]. ulPort ]. OUTSET .reg = ( uint32_t )( 1 << g_APinDescription [ ulPin ]. ulPin ) ;
52
+ PORT -> Group [port ]. OUTSET .reg = pinMask ;
49
53
break ;
50
54
51
55
case INPUT_PULLDOWN :
52
56
// Set pin to input mode with pull-down resistor enabled
53
- PORT -> Group [g_APinDescription [ ulPin ]. ulPort ]. PINCFG [g_APinDescription [ ulPin ]. ulPin ].reg = (uint8_t )(PORT_PINCFG_INEN |PORT_PINCFG_PULLEN ) ;
54
- PORT -> Group [g_APinDescription [ ulPin ]. ulPort ]. DIRCLR .reg = ( uint32_t )( 1 << g_APinDescription [ ulPin ]. ulPin ) ;
57
+ PORT -> Group [port ]. PINCFG [pin ].reg = (uint8_t )(PORT_PINCFG_INEN |PORT_PINCFG_PULLEN ) ;
58
+ PORT -> Group [port ]. DIRCLR .reg = pinMask ;
55
59
56
60
// Enable pull level (cf '22.6.3.2 Input Configuration' and '22.8.6 Data Output Value Clear')
57
- PORT -> Group [g_APinDescription [ ulPin ]. ulPort ]. OUTCLR .reg = ( uint32_t )( 1 << g_APinDescription [ ulPin ]. ulPin ) ;
61
+ PORT -> Group [port ]. OUTCLR .reg = pinMask ;
58
62
break ;
59
63
60
64
case OUTPUT :
61
65
// enable input, to support reading back values, with pullups disabled
62
- PORT -> Group [g_APinDescription [ ulPin ]. ulPort ]. PINCFG [g_APinDescription [ ulPin ]. ulPin ].reg = (uint8_t )(PORT_PINCFG_INEN ) ;
66
+ PORT -> Group [port ]. PINCFG [pin ].reg = (uint8_t )(PORT_PINCFG_INEN ) ;
63
67
64
68
// Set pin to output mode
65
- PORT -> Group [g_APinDescription [ ulPin ]. ulPort ]. DIRSET .reg = ( uint32_t )( 1 << g_APinDescription [ ulPin ]. ulPin ) ;
69
+ PORT -> Group [port ]. DIRSET .reg = pinMask ;
66
70
break ;
67
71
68
72
default :
0 commit comments