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system(H7): update STM32H7xx CMSIS Drivers to v1.10.4
Included in STM32CubeH7 FW v1.11.2 Signed-off-by: Frederic Pillon <[email protected]>
1 parent 9d40b01 commit 9e27327

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‎system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h

+32-6
Original file line numberDiff line numberDiff line change
@@ -211,7 +211,7 @@ typedef enum
211211
/**
212212
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
213213
*/
214-
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
214+
#define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */
215215
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
216216
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
217217
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
@@ -3864,6 +3864,10 @@ typedef struct
38643864
#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
38653865
#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */
38663866

3867+
#define ADC3_AWD2CR_AWD2CH_Pos (0U)
3868+
#define ADC3_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC3_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
3869+
#define ADC3_AWD2CR_AWD2CH ADC3_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */
3870+
38673871
/******************** Bit definition for ADC_AWD3CR register ********************/
38683872
#define ADC_AWD3CR_AWD3CH_Pos (0U)
38693873
#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */
@@ -3889,6 +3893,10 @@ typedef struct
38893893
#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
38903894
#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */
38913895

3896+
#define ADC3_AWD3CR_AWD3CH_Pos (0U)
3897+
#define ADC3_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC3_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
3898+
#define ADC3_AWD3CR_AWD3CH ADC3_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 3 channel selection */
3899+
38923900
/******************** Bit definition for ADC_DIFSEL register ********************/
38933901
#define ADC_DIFSEL_DIFSEL_Pos (0U)
38943902
#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */
@@ -11719,7 +11727,7 @@ typedef struct
1171911727
#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
1172011728
#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
1172111729
#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
11722-
#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
11730+
#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
1172311731

1172411732
#define FMC_SDCMR_CTB2_Pos (3U)
1172511733
#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
@@ -18200,6 +18208,7 @@ typedef struct
1820018208
/* Serial Peripheral Interface (SPI/I2S) */
1820118209
/* */
1820218210
/******************************************************************************/
18211+
#define SPI_SPI6I2S_SUPPORT /*!<SPI6 I2S support feature */
1820318212
/******************* Bit definition for SPI_CR1 register ********************/
1820418213
#define SPI_CR1_SPE_Pos (0U)
1820518214
#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000001 */
@@ -21903,6 +21912,9 @@ typedef struct
2190321912
#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
2190421913
#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
2190521914
#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
21915+
#define USB_OTG_GOTGCTL_CURMOD_Pos (21U)
21916+
#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
21917+
#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */
2190621918

2190721919
/******************** Bit definition forUSB_OTG_HCFG register ********************/
2190821920

@@ -21928,7 +21940,7 @@ typedef struct
2192821940

2192921941
#define USB_OTG_DCFG_DAD_Pos (4U)
2193021942
#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
21931-
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
21943+
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
2193221944
#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
2193321945
#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
2193421946
#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
@@ -21939,13 +21951,21 @@ typedef struct
2193921951

2194021952
#define USB_OTG_DCFG_PFIVL_Pos (11U)
2194121953
#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
21942-
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
21954+
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
2194321955
#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
2194421956
#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
2194521957

21958+
#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
21959+
#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
21960+
#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
21961+
21962+
#define USB_OTG_DCFG_ERRATIM_Pos (15U)
21963+
#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
21964+
#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
21965+
2194621966
#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
2194721967
#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
21948-
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
21968+
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
2194921969
#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
2195021970
#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
2195121971

@@ -22015,6 +22035,12 @@ typedef struct
2201522035
#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
2201622036
#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
2201722037
#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
22038+
#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U)
22039+
#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
22040+
#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */
22041+
#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U)
22042+
#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
22043+
#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */
2201822044

2201922045
/******************** Bit definition forUSB_OTG_HFIR register ********************/
2202022046
#define USB_OTG_HFIR_FRIVL_Pos (0U)
@@ -22132,7 +22158,7 @@ typedef struct
2213222158
#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
2213322159
#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
2213422160
#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
22135-
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
22161+
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
2213622162

2213722163
/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
2213822164
#define USB_OTG_GRSTCTL_CSRST_Pos (0U)

‎system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h725xx.h

+32-6
Original file line numberDiff line numberDiff line change
@@ -212,7 +212,7 @@ typedef enum
212212
/**
213213
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
214214
*/
215-
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
215+
#define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */
216216
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
217217
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
218218
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
@@ -3865,6 +3865,10 @@ typedef struct
38653865
#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
38663866
#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */
38673867

3868+
#define ADC3_AWD2CR_AWD2CH_Pos (0U)
3869+
#define ADC3_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC3_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
3870+
#define ADC3_AWD2CR_AWD2CH ADC3_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */
3871+
38683872
/******************** Bit definition for ADC_AWD3CR register ********************/
38693873
#define ADC_AWD3CR_AWD3CH_Pos (0U)
38703874
#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */
@@ -3890,6 +3894,10 @@ typedef struct
38903894
#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
38913895
#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */
38923896

3897+
#define ADC3_AWD3CR_AWD3CH_Pos (0U)
3898+
#define ADC3_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC3_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
3899+
#define ADC3_AWD3CR_AWD3CH ADC3_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 3 channel selection */
3900+
38933901
/******************** Bit definition for ADC_DIFSEL register ********************/
38943902
#define ADC_DIFSEL_DIFSEL_Pos (0U)
38953903
#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */
@@ -11720,7 +11728,7 @@ typedef struct
1172011728
#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
1172111729
#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
1172211730
#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
11723-
#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
11731+
#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
1172411732

1172511733
#define FMC_SDCMR_CTB2_Pos (3U)
1172611734
#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
@@ -18212,6 +18220,7 @@ typedef struct
1821218220
/* Serial Peripheral Interface (SPI/I2S) */
1821318221
/* */
1821418222
/******************************************************************************/
18223+
#define SPI_SPI6I2S_SUPPORT /*!<SPI6 I2S support feature */
1821518224
/******************* Bit definition for SPI_CR1 register ********************/
1821618225
#define SPI_CR1_SPE_Pos (0U)
1821718226
#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000001 */
@@ -21915,6 +21924,9 @@ typedef struct
2191521924
#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
2191621925
#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
2191721926
#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
21927+
#define USB_OTG_GOTGCTL_CURMOD_Pos (21U)
21928+
#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
21929+
#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */
2191821930

2191921931
/******************** Bit definition forUSB_OTG_HCFG register ********************/
2192021932

@@ -21940,7 +21952,7 @@ typedef struct
2194021952

2194121953
#define USB_OTG_DCFG_DAD_Pos (4U)
2194221954
#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
21943-
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
21955+
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
2194421956
#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
2194521957
#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
2194621958
#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
@@ -21951,13 +21963,21 @@ typedef struct
2195121963

2195221964
#define USB_OTG_DCFG_PFIVL_Pos (11U)
2195321965
#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
21954-
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
21966+
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
2195521967
#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
2195621968
#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
2195721969

21970+
#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
21971+
#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
21972+
#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
21973+
21974+
#define USB_OTG_DCFG_ERRATIM_Pos (15U)
21975+
#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
21976+
#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
21977+
2195821978
#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
2195921979
#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
21960-
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
21980+
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
2196121981
#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
2196221982
#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
2196321983

@@ -22027,6 +22047,12 @@ typedef struct
2202722047
#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
2202822048
#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
2202922049
#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
22050+
#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U)
22051+
#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
22052+
#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */
22053+
#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U)
22054+
#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
22055+
#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */
2203022056

2203122057
/******************** Bit definition forUSB_OTG_HFIR register ********************/
2203222058
#define USB_OTG_HFIR_FRIVL_Pos (0U)
@@ -22144,7 +22170,7 @@ typedef struct
2214422170
#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
2214522171
#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
2214622172
#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
22147-
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
22173+
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
2214822174

2214922175
/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
2215022176
#define USB_OTG_GRSTCTL_CSRST_Pos (0U)

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