diff --git a/Makefile b/Makefile
index 4624ad09af..871c0b7205 100755
--- a/Makefile
+++ b/Makefile
@@ -520,6 +520,7 @@ else ifdef ESP8266_512KB
 # into ram (dram+iram) and the last 16KB are reserved for the SDK. That leaves 432KB (0x6C000).
 EMBEDDED=1
 USE_NET=1
+#USE_FILESYSTEM=1
 BOARD=ESP8266_BOARD
 # We have to disable inlining to keep code size in check
 OPTIMIZEFLAGS+=-Os -fno-inline-functions -std=gnu11 -fgnu89-inline -Wl,--allow-multiple-definition
@@ -986,7 +987,8 @@ libs/network/js/network_js.c
 
  ifdef USE_ESP8266
  DEFINES += -DUSE_ESP8266
- WRAPPERSOURCES += libs/network/esp8266/jswrap_esp8266.c
+ WRAPPERSOURCES += libs/network/esp8266/jswrap_esp8266_network.c \
+   targets/esp8266/jswrap_esp8266.c
  INCLUDE += -I$(ROOT)/libs/network/esp8266
  SOURCES += \
  libs/network/esp8266/network_esp8266.c\
@@ -1493,11 +1495,12 @@ LDFLAGS += -L$(ESP8266_SDK_ROOT)/lib \
 
 # Extra source files specific to the ESP8266
 SOURCES += targets/esp8266/uart.c \
-	   targets/esp8266/user_main.c \
-	   targets/esp8266/jshardware.c \
-	   targets/esp8266/i2c_master.c \
-	   targets/esp8266/esp8266_board_utils.c \
-	   libs/network/esp8266/network_esp8266.c
+	targets/esp8266/spi.c \
+	targets/esp8266/user_main.c \
+	targets/esp8266/jshardware.c \
+	targets/esp8266/i2c_master.c \
+	targets/esp8266/esp8266_board_utils.c \
+	libs/network/esp8266/network_esp8266.c
 # if using the hw_timer:   targets/esp8266/hw_timer.c \
 
 # The tool used for building the firmware and flashing
@@ -1602,6 +1605,7 @@ proj: $(PROJ_NAME).elf $(PROJ_NAME)_0x00000.bin $(PROJ_NAME)_0x10000.bin $(PROJ_
 $(PROJ_NAME).elf: $(OBJS) $(LINKER_FILE)
 	$(Q)$(LD) $(OPTIMIZEFLAGS) -nostdlib -Wl,--no-check-sections -Wl,-static -r -o partial.o $(OBJS)
 	$(Q)$(OBJCOPY) --rename-section .text=.irom0.text --rename-section .literal=.irom0.literal partial.o
+	$(Q)$(OBJCOPY) --rename-section .force.text=.text partial.o
 	$(Q)$(LD) $(LDFLAGS) -Ttargets/esp8266/eagle.app.v6.0x10000.ld -o $@ partial.o -Wl,--start-group $(LIBS) -Wl,--end-group
 	$(Q)rm partial.o
 	$(Q)$(OBJDUMP) --headers -j .irom0.text -j .text $(PROJ_NAME).elf | tail -n +4
diff --git a/boards/.gitignore b/boards/.gitignore
new file mode 100644
index 0000000000..a348e5040c
--- /dev/null
+++ b/boards/.gitignore
@@ -0,0 +1 @@
+/__pycache__/
diff --git a/boards/ESP8266_12.py b/boards/ESP8266_12.py
index 4a3546a0ca..cb1971e07b 100644
--- a/boards/ESP8266_12.py
+++ b/boards/ESP8266_12.py
@@ -35,7 +35,7 @@
   'flash'   : 1024,
   'speed'   : 80,
   'usart'   : 1,
-  'spi'     : 0,
+  'spi'     : 1,
   'i2c'     : 1,
   'adc'     : 1,
   'dac'     : 0,
diff --git a/boards/ESP8266_BOARD.py b/boards/ESP8266_BOARD.py
index 8751469fda..ad83e3e3ba 100644
--- a/boards/ESP8266_BOARD.py
+++ b/boards/ESP8266_BOARD.py
@@ -28,7 +28,7 @@
   'flash'   : 512,
   'speed'   : 80,
   'usart'   : 1,
-  'spi'     : 0,
+  'spi'     : 1,
   'i2c'     : 1,
   'adc'     : 1,
   'dac'     : 0,
diff --git a/libs/network/esp8266/jswrap_esp8266.c b/libs/network/esp8266/jswrap_esp8266_network.c
similarity index 99%
rename from libs/network/esp8266/jswrap_esp8266.c
rename to libs/network/esp8266/jswrap_esp8266_network.c
index 7c4469b9b9..087b6d6f5f 100644
--- a/libs/network/esp8266/jswrap_esp8266.c
+++ b/libs/network/esp8266/jswrap_esp8266_network.c
@@ -34,7 +34,7 @@ of beta.  */
 #define _GCC_WRAP_STDINT_H
 typedef long long int64_t;
 
-#include "jswrap_esp8266.h"
+#include "jswrap_esp8266_network.h"
 #include "jsinteractive.h" // Pull inn the jsiConsolePrint function
 #include "network.h"
 #include "network_esp8266.h"
diff --git a/libs/network/esp8266/jswrap_esp8266.h b/libs/network/esp8266/jswrap_esp8266_network.h
similarity index 94%
rename from libs/network/esp8266/jswrap_esp8266.h
rename to libs/network/esp8266/jswrap_esp8266_network.h
index 5aea83df01..e8c3056537 100644
--- a/libs/network/esp8266/jswrap_esp8266.h
+++ b/libs/network/esp8266/jswrap_esp8266_network.h
@@ -14,8 +14,8 @@
  * ----------------------------------------------------------------------------
  */
 
-#ifndef LIBS_NETWORK_ESP8266_JSWRAP_ESP8266_H_
-#define LIBS_NETWORK_ESP8266_JSWRAP_ESP8266_H_
+#ifndef LIBS_NETWORK_ESP8266_JSWRAP_ESP8266_NETWORK_H_
+#define LIBS_NETWORK_ESP8266_JSWRAP_ESP8266_NETWORK_H_
 #include "jsvar.h"
 
 // Deprecated
@@ -67,4 +67,4 @@ void   jswrap_ESP8266_updateCPUFreq(JsVar *jsFreq);
 
 void   jswrap_ESP8266_init();
 
-#endif /* LIBS_NETWORK_ESP8266_JSWRAP_ESP8266_H_ */
+#endif /* LIBS_NETWORK_ESP8266_JSWRAP_ESP8266_NETWORK_H_ */
diff --git a/src/jsdevices.c b/src/jsdevices.c
index c0e81e8ded..338dfe1aac 100644
--- a/src/jsdevices.c
+++ b/src/jsdevices.c
@@ -71,7 +71,7 @@ volatile unsigned char ioHead=0, ioTail=0;
  * Initialize all the devices.
  */
 void jshInitDevices() { // called from jshInit
-  int i;
+  unsigned int i;
   // setup flow control
   for (i=0;i<sizeof(jshSerialDeviceStates) / sizeof(JshSerialDeviceState);i++)
     jshSerialDeviceStates[i] = SDS_NONE;
diff --git a/targets/esp8266/jshardware.c b/targets/esp8266/jshardware.c
index 18e26143ff..50b03a478a 100644
--- a/targets/esp8266/jshardware.c
+++ b/targets/esp8266/jshardware.c
@@ -24,6 +24,7 @@
 #include <espmissingincludes.h>
 #include <uart.h>
 #include <i2c_master.h>
+#include <spi.h> // Include the MetalPhreak/ESP8266_SPI_Library headers.
 
 //#define FAKE_STDLIB
 #define _GCC_WRAP_STDINT_H
@@ -53,6 +54,10 @@ typedef long long int64_t;
 // Address in RTC RAM where we save the time
 #define RTC_TIME_ADDR (256/4) // start of "user data" in RTC RAM
 
+
+static bool g_spiInitialized = false;
+static int  g_lastSPIRead = -1;
+
 /**
  * Transmit all the characters in the transmit buffer.
  *
@@ -159,6 +164,8 @@ void jshReset() {
     jshPinSetState(i, JSHPINSTATE_GPIO_IN);
   }
   */
+  g_spiInitialized = false; // Flag the hardware SPI interface as un-initialized.
+  g_lastSPIRead = -1;
   os_printf("< jshReset\n");
 } // End of jshReset
 
@@ -588,26 +595,69 @@ void jshUSARTKick(
 //===== SPI =====
 
 /**
- * Unknown
+ * Initialize the hardware SPI device.
+ * On the ESP8266, hardware SPI is implemented via a set of pins defined
+ * as follows:
  *
+ * | GPIO   | NodeMCU | Name  | Function |
+ * |--------|---------|-------|----------|
+ * | GPIO12 | D6      | HMISO | MISO     |
+ * | GPIO13 | D7      | HMOSI | MOSI     |
+ * | GPIO14 | D5      | HSCLK | CLK      |
+ * | GPIO15 | D8      | HCS   | CS       |
  *
  */
 void jshSPISetup(
-    IOEventFlags device, //!< Unknown
-    JshSPIInfo *inf      //!< Unknown
+    IOEventFlags device, //!< The identity of the SPI device being initialized.
+    JshSPIInfo *inf      //!< Flags for the SPI device.
   ) {
-  os_printf("ESP8266: jshSPISetup: device=%d, inf=0x%x\n", device, (int)inf);
+  // The device should be one of EV_SPI1, EV_SPI2 or EV_SPI3.
+  os_printf("> jshSPISetup - jshSPISetup: device=%d\n", device);
+  switch(device) {
+  case EV_SPI1:
+    os_printf(" - Device is SPI1\n");
+    // EV_SPI1 is the ESP8266 hardware SPI ...
+    spi_init(HSPI); // Initialize the hardware SPI components.
+    spi_clock(HSPI, CPU_CLK_FREQ / (inf->baudRate * 2), 2);
+    g_spiInitialized = true;
+    g_lastSPIRead = -1;
+    break;
+  case EV_SPI2:
+    os_printf(" - Device is SPI2\n");
+    break;
+  case EV_SPI3:
+    os_printf(" - Device is SPI3\n");
+    break;
+  default:
+    os_printf(" - Device is Unknown!!\n");
+    break;
+  }
+  if (inf != NULL) {
+    os_printf("baudRate=%d, baudRateSpec=%d, pinSCK=%d, pinMISO=%d, pinMOSI=%d, spiMode=%d, spiMSB=%d\n",
+        inf->baudRate, inf->baudRateSpec, inf->pinSCK, inf->pinMISO, inf->pinMOSI, inf->spiMode, inf->spiMSB);
+  }
+  os_printf("< jshSPISetup\n");
 }
 
 /** Send data through the given SPI device (if data>=0), and return the result
  * of the previous send (or -1). If data<0, no data is sent and the function
  * waits for data to be returned */
 int jshSPISend(
-    IOEventFlags device, //!< Unknown
-    int data             //!< Unknown
+    IOEventFlags device, //!< The identity of the SPI device through which data is being sent.
+    int data             //!< The data to be sent or an indication that no data is to be sent.
   ) {
-  os_printf("ESP8266: jshSPISend\n");
-  return NAN;
+  if (device != EV_SPI1) {
+    return -1;
+  }
+  //os_printf("> jshSPISend - device=%d, data=%x\n", device, data);
+  int retData = g_lastSPIRead;
+  if (data >=0) {
+    g_lastSPIRead = spi_tx8(HSPI, data);
+  } else {
+    g_lastSPIRead = -1;
+  }
+  //os_printf("< jshSPISend\n");
+  return retData;
 }
 
 
@@ -618,9 +668,15 @@ void jshSPISend16(
     IOEventFlags device, //!< Unknown
     int data             //!< Unknown
   ) {
-  os_printf("ESP8266: jshSPISend16\n");
-  jshSPISend(device, data >> 8);
-  jshSPISend(device, data & 255);
+  //os_printf("> jshSPISend16 - device=%d, data=%x\n", device, data);
+  //jshSPISend(device, data >> 8);
+  //jshSPISend(device, data & 255);
+  if (device != EV_SPI1) {
+    return;
+  }
+
+  spi_tx16(HSPI, data);
+  //os_printf("< jshSPISend16\n");
 }
 
 
@@ -631,7 +687,8 @@ void jshSPISet16(
     IOEventFlags device, //!< Unknown
     bool is16            //!< Unknown
   ) {
-  os_printf("ESP8266: jshSPISet16\n");
+  os_printf("> jshSPISet16 - device=%d, is16=%d\n", device, is16);
+  os_printf("< jshSPISet16\n");
 }
 
 
@@ -641,11 +698,15 @@ void jshSPISet16(
 void jshSPIWait(
     IOEventFlags device //!< Unknown
   ) {
-  os_printf("ESP8266: jshSPIWait\n");
+  os_printf("> jshSPIWait - device=%d\n", device);
+  while(spi_busy(HSPI)) ;
+  os_printf("< jshSPIWait\n");
 }
 
 /** Set whether to use the receive interrupt or not */
 void jshSPISetReceive(IOEventFlags device, bool isReceive) {
+  os_printf("> jshSPISetReceive - device=%d, isReceive=%d\n", device, isReceive);
+  os_printf("< jshSPISetReceive\n");
 }
 
 //===== I2C =====
@@ -948,8 +1009,17 @@ void jshUtilTimerReschedule(JsSysTime period) {
 //===== Miscellaneous =====
 
 bool jshIsDeviceInitialised(IOEventFlags device) {
-  os_printf("ESP8266: jshIsDeviceInitialised %d\n", device);
-  return true;
+  os_printf("> jshIsDeviceInitialised - %d\n", device);
+  bool retVal = true;
+  switch(device) {
+  case EV_SPI1:
+    retVal = g_spiInitialized;
+    break;
+  default:
+    break;
+  }
+  os_printf("< jshIsDeviceInitialised - %d\n", retVal);
+  return retVal;
 } // End of jshIsDeviceInitialised
 
 // the esp8266 doesn't have any temperature sensor
diff --git a/targets/esp8266/jswrap_esp8266.c b/targets/esp8266/jswrap_esp8266.c
new file mode 100644
index 0000000000..00cd099b31
--- /dev/null
+++ b/targets/esp8266/jswrap_esp8266.c
@@ -0,0 +1,160 @@
+/*
+ * This file is part of Espruino, a JavaScript interpreter for Microcontrollers
+ *
+ * Copyright (C) 2015 Gordon Williams <gw@pur3.co.uk>
+ *
+ * This Source Code Form is subject to the terms of the Mozilla Public
+ * License, v. 2.0. If a copy of the MPL was not distributed with this
+ * file, You can obtain one at http://mozilla.org/MPL/2.0/.
+ *
+ * ----------------------------------------------------------------------------
+ * This file is designed to be parsed during the build process
+ *
+ * Contains ESP8266 board specific functions.
+ * ----------------------------------------------------------------------------
+ */
+
+/* DO_NOT_INCLUDE_IN_DOCS - this is a special token for common.py,
+ so we don't put this into espruino.com/Reference until this is out
+ of beta.  */
+
+// Because the ESP8266 JS wrapper is assured to be running on an ESP8266 we
+// can assume that inclusion of ESP8266 headers will be acceptable.
+#include <c_types.h>
+#include <user_interface.h>
+#include <mem.h>
+#include <osapi.h>
+#include <ping.h>
+#include <espconn.h>
+#include <espmissingincludes.h>
+#include <uart.h>
+
+#define _GCC_WRAP_STDINT_H
+typedef long long int64_t;
+
+#include <jswrap_esp8266.h>
+#include "jsinteractive.h" // Pull inn the jsiConsolePrint function
+
+#define _BV(bit) (1 << (bit))
+
+static uint32_t _getCycleCount(void) __attribute__((always_inline));
+
+static inline uint32_t _getCycleCount(void) {
+  uint32_t ccount;
+  __asm__ __volatile__("rsr %0,ccount":"=a" (ccount));
+  return ccount;
+}
+
+/*JSON{
+ "type"     : "staticmethod",
+ "class"    : "ESP8266",
+ "name"     : "neopixelWrite",
+ "generate" : "jswrap_ESP8266_neopixelWrite",
+ "params"   : [
+   ["pin", "JsVar", "Pin for output signal."],
+   ["arrayOfData", "JsVar", "Array of LED data."]
+ ]
+}*/
+
+__attribute__((section(".force.text"))) void jswrap_ESP8266_neopixelWrite(JsVar *jsPin, JsVar *jsArrayOfData) {
+  if (jsPin == NULL) {
+    jsExceptionHere(JSET_ERROR, "No output pin supplied.");
+    return;
+  }
+  if (!jsvIsPin(jsPin)) {
+    jsExceptionHere(JSET_ERROR, "Pin value is not a pin.");
+    return;
+  }
+  Pin pin = jshGetPinFromVar(jsPin);
+  if (!jshIsPinValid(pin)) {
+    jsExceptionHere(JSET_ERROR, "Pin is not valid.");
+    return;
+  }
+  if (jsArrayOfData == NULL) {
+    jsExceptionHere(JSET_ERROR, "No data to send to LEDs.");
+    return;
+  }
+  if (!jsvIsArray(jsArrayOfData)) {
+    jsExceptionHere(JSET_ERROR, "Data must be an array.");
+    return;
+  }
+  int dataLength = jsvGetArrayLength(jsArrayOfData);
+  if (dataLength == 0) {
+    jsExceptionHere(JSET_ERROR, "Data must be a non empty array.");
+    return;
+  }
+  if (dataLength % 3 != 0) {
+    jsExceptionHere(JSET_ERROR, "Data length must multiples of RGB bytes (3).");
+    return;
+  }
+  uint8_t *pixels = (uint8 *)os_malloc(dataLength);
+  if (pixels == NULL) {
+    jsExceptionHere(JSET_ERROR, "Out of memory.");
+    return;
+  }
+  int i;
+  for (int i=0; i<dataLength; i++) {
+    JsVar *jsItem = jsvGetArrayItem(jsArrayOfData, i);
+    pixels[i] = jsvGetInteger(jsItem);
+    jsvUnLock(jsItem);
+  }
+
+  uint32_t numBytes = dataLength;
+
+  uint8_t *p, *end, pix, mask;
+  uint32_t t, time0, time1, period, c, startTime, pinMask;
+  pinMask = _BV(pin);
+  p = pixels;
+  end = p + numBytes;
+  pix = *p++;
+  mask = 0x80;
+  c=0;
+  startTime = 0;
+  time0 = 14; // 14 cycles = (measured)
+  //time0 = 28; // 28 cycles = 0.35us
+  //time0 = 32; // 0.4us
+  //time1 = 108; // 108 cycles = 1.36us
+  time1 = 56; // 56 cycles = 0.7us
+  //time1 = 64; // 64 cycles = 0.8us
+  // Cycles/usec = 80
+  // Period = cycles/usec * usecDuration
+  //period = 136; // 136 cycles = 1.71us
+  period = 100; // cycles = 1.25us
+  //period = 104; // 1.3us
+  //GPIO_REG_WRITE(GPIO_OUT_W1TS_ADDRESS, pinMask);
+  //os_delay_us(100);
+  //GPIO_REG_WRITE(GPIO_OUT_W1TC_ADDRESS, pinMask);
+  //os_delay_us(100);
+  //GPIO_REG_WRITE(GPIO_OUT_W1TS_ADDRESS, pinMask);
+  while(1) {
+    if (pix & mask)
+      t = time1;                             // Bit high duration
+    else
+      t = time0;
+    GPIO_REG_WRITE(GPIO_OUT_W1TS_ADDRESS, pinMask);       // Set high
+    startTime = _getCycleCount();                                        // Save start time
+    while (((c = _getCycleCount()) - startTime) < t)
+      ;      // Wait high duration
+    GPIO_REG_WRITE(GPIO_OUT_W1TC_ADDRESS, pinMask);       // Set low
+    if (!(mask >>= 1)) {                                  // Next bit/byte
+      if (p >= end)
+        break;
+      pix = *p++;
+      mask = 0x80;
+    }
+    while (((c = _getCycleCount()) - startTime) < period)
+      ; // Wait for bit start
+  }
+  while ((_getCycleCount() - startTime) < period)
+    ; // Wait for last bit
+  os_free(pixels);
+}
+/*
+int d = jsvGetInteger(count);
+uint32_t cnt1 = _getCycleCount();
+os_delay_us ( d);
+uint32_t cnt2 = _getCycleCount();
+os_printf("Delaying for: %d\n", d);
+os_printf("Cycle count: %lu\n", cnt2-cnt1);
+}
+*/
diff --git a/targets/esp8266/jswrap_esp8266.h b/targets/esp8266/jswrap_esp8266.h
new file mode 100644
index 0000000000..6d8d563ce3
--- /dev/null
+++ b/targets/esp8266/jswrap_esp8266.h
@@ -0,0 +1,22 @@
+/*
+ * This file is part of Espruino, a JavaScript interpreter for Microcontrollers
+ *
+ * Copyright (C) 2015 Gordon Williams <gw@pur3.co.uk>
+ *
+ * This Source Code Form is subject to the terms of the Mozilla Public
+ * License, v. 2.0. If a copy of the MPL was not distributed with this
+ * file, You can obtain one at http://mozilla.org/MPL/2.0/.
+ *
+ * ----------------------------------------------------------------------------
+ * This file is designed to be parsed during the build process
+ *
+ * Contains ESP8266 board specific function definitions.
+ * ----------------------------------------------------------------------------
+ */
+#ifndef TARGETS_ESP8266_JSWRAP_ESP8266_H_
+#define TARGETS_ESP8266_JSWRAP_ESP8266_H_
+#include "jsvar.h"
+
+void   jswrap_ESP8266_neopixelWrite(JsVar *jsPin, JsVar *jsArrayOfData);
+
+#endif /* TARGETS_ESP8266_JSWRAP_ESP8266_H_ */
diff --git a/targets/esp8266/spi.c b/targets/esp8266/spi.c
new file mode 100644
index 0000000000..63f6c4fba3
--- /dev/null
+++ b/targets/esp8266/spi.c
@@ -0,0 +1,311 @@
+/*
+ * This file is part of Espruino, a JavaScript interpreter for Microcontrollers
+ *
+ * Copyright (c) 2015 David Ogilvy (MetalPhreak)
+ *
+ * This Source Code Form is subject to the terms of the Mozilla Public
+ * License, v. 2.0. If a copy of the MPL was not distributed with this
+ * file, You can obtain one at http://mozilla.org/MPL/2.0/.
+ *
+ * ----------------------------------------------------------------------------
+ * This file is designed to be parsed during the build process
+ *
+ * Contains ESP8266 board specific functions.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * The Github project from which this source file came from can be found
+ * at:  https://github.com/MetalPhreak/ESP8266_SPI_Driver
+ */
+
+
+#include "spi.h"
+
+
+////////////////////////////////////////////////////////////////////////////////
+//
+// Function Name: spi_init
+//   Description: Wrapper to setup HSPI/SPI GPIO pins and default SPI clock
+//    Parameters: spi_no - SPI (0) or HSPI (1)
+//				 
+////////////////////////////////////////////////////////////////////////////////
+
+void spi_init(uint8 spi_no){
+	
+	if(spi_no > 1) return; //Only SPI and HSPI are valid spi modules. 
+
+	spi_init_gpio(spi_no, SPI_CLK_USE_DIV);
+	spi_clock(spi_no, SPI_CLK_PREDIV, SPI_CLK_CNTDIV);
+	spi_tx_byte_order(spi_no, SPI_BYTE_ORDER_HIGH_TO_LOW);
+	spi_rx_byte_order(spi_no, SPI_BYTE_ORDER_HIGH_TO_LOW); 
+
+	SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_CS_SETUP|SPI_CS_HOLD);
+	CLEAR_PERI_REG_MASK(SPI_USER(spi_no), SPI_FLASH_MODE);
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+//
+// Function Name: spi_init_gpio
+//   Description: Initialises the GPIO pins for use as SPI pins.
+//    Parameters: spi_no - SPI (0) or HSPI (1)
+//				  sysclk_as_spiclk - SPI_CLK_80MHZ_NODIV (1) if using 80MHz
+//									 sysclock for SPI clock. 
+//									 SPI_CLK_USE_DIV (0) if using divider to
+//									 get lower SPI clock speed.
+//				 
+////////////////////////////////////////////////////////////////////////////////
+
+void spi_init_gpio(uint8 spi_no, uint8 sysclk_as_spiclk){
+
+//	if(spi_no > 1) return; //Not required. Valid spi_no is checked with if/elif below.
+
+	uint32 clock_div_flag = 0;
+	if(sysclk_as_spiclk){
+		clock_div_flag = 0x0001;	
+	} 
+
+	if(spi_no==SPI){
+		WRITE_PERI_REG(PERIPHS_IO_MUX, 0x005|(clock_div_flag<<8)); //Set bit 8 if 80MHz sysclock required
+		PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, 1);
+		PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CMD_U, 1);
+		PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA0_U, 1);	
+		PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA1_U, 1);	
+	}else if(spi_no==HSPI){
+		WRITE_PERI_REG(PERIPHS_IO_MUX, 0x105|(clock_div_flag<<9)); //Set bit 9 if 80MHz sysclock required
+		PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDI_U, 2); //GPIO12 is HSPI MISO pin (Master Data In)
+		PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, 2); //GPIO13 is HSPI MOSI pin (Master Data Out)
+		PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTMS_U, 2); //GPIO14 is HSPI CLK pin (Clock)
+		PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, 2); //GPIO15 is HSPI CS pin (Chip Select / Slave Select)
+	}
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+//
+// Function Name: spi_clock
+//   Description: sets up the control registers for the SPI clock
+//    Parameters: spi_no - SPI (0) or HSPI (1)
+//				  prediv - predivider value (actual division value)
+//				  cntdiv - postdivider value (actual division value)
+//				  Set either divider to 0 to disable all division (80MHz sysclock)
+//				 
+////////////////////////////////////////////////////////////////////////////////
+
+void spi_clock(uint8 spi_no, uint16 prediv, uint8 cntdiv){
+	
+	if(spi_no > 1) return;
+
+	if((prediv==0)|(cntdiv==0)){
+
+		WRITE_PERI_REG(SPI_CLOCK(spi_no), SPI_CLK_EQU_SYSCLK);
+
+	} else {
+	
+		WRITE_PERI_REG(SPI_CLOCK(spi_no), 
+					(((prediv-1)&SPI_CLKDIV_PRE)<<SPI_CLKDIV_PRE_S)|
+					(((cntdiv-1)&SPI_CLKCNT_N)<<SPI_CLKCNT_N_S)|
+					(((cntdiv>>1)&SPI_CLKCNT_H)<<SPI_CLKCNT_H_S)|
+					((0&SPI_CLKCNT_L)<<SPI_CLKCNT_L_S));
+	}
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+//
+// Function Name: spi_tx_byte_order
+//   Description: Setup the byte order for shifting data out of buffer
+//    Parameters: spi_no - SPI (0) or HSPI (1)
+//				  byte_order - SPI_BYTE_ORDER_HIGH_TO_LOW (1) 
+//							   Data is sent out starting with Bit31 and down to Bit0
+//
+//							   SPI_BYTE_ORDER_LOW_TO_HIGH (0)
+//							   Data is sent out starting with the lowest BYTE, from 
+//							   MSB to LSB, followed by the second lowest BYTE, from
+//							   MSB to LSB, followed by the second highest BYTE, from
+//							   MSB to LSB, followed by the highest BYTE, from MSB to LSB
+//							   0xABCDEFGH would be sent as 0xGHEFCDAB
+//
+//				 
+////////////////////////////////////////////////////////////////////////////////
+
+void spi_tx_byte_order(uint8 spi_no, uint8 byte_order){
+
+	if(spi_no > 1) return;
+
+	if(byte_order){
+		SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_WR_BYTE_ORDER);
+	} else {
+		CLEAR_PERI_REG_MASK(SPI_USER(spi_no), SPI_WR_BYTE_ORDER);
+	}
+}
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+//
+// Function Name: spi_rx_byte_order
+//   Description: Setup the byte order for shifting data into buffer
+//    Parameters: spi_no - SPI (0) or HSPI (1)
+//				  byte_order - SPI_BYTE_ORDER_HIGH_TO_LOW (1) 
+//							   Data is read in starting with Bit31 and down to Bit0
+//
+//							   SPI_BYTE_ORDER_LOW_TO_HIGH (0)
+//							   Data is read in starting with the lowest BYTE, from 
+//							   MSB to LSB, followed by the second lowest BYTE, from
+//							   MSB to LSB, followed by the second highest BYTE, from
+//							   MSB to LSB, followed by the highest BYTE, from MSB to LSB
+//							   0xABCDEFGH would be read as 0xGHEFCDAB
+//
+//				 
+////////////////////////////////////////////////////////////////////////////////
+
+void spi_rx_byte_order(uint8 spi_no, uint8 byte_order){
+
+	if(spi_no > 1) return;
+
+	if(byte_order){
+		SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_RD_BYTE_ORDER);
+	} else {
+		CLEAR_PERI_REG_MASK(SPI_USER(spi_no), SPI_RD_BYTE_ORDER);
+	}
+}
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+//
+// Function Name: spi_transaction
+//   Description: SPI transaction function
+//    Parameters: spi_no - SPI (0) or HSPI (1)
+//				  cmd_bits - actual number of bits to transmit
+//				  cmd_data - command data
+//				  addr_bits - actual number of bits to transmit
+//				  addr_data - address data
+//				  dout_bits - actual number of bits to transmit
+//				  dout_data - output data
+//				  din_bits - actual number of bits to receive
+//				  
+//		 Returns: read data - uint32 containing read in data only if RX was set 
+//				  0 - something went wrong (or actual read data was 0)
+//				  1 - data sent ok (or actual read data is 1)
+//				  Note: all data is assumed to be stored in the lower bits of
+//				  the data variables (for anything <32 bits). 
+//
+////////////////////////////////////////////////////////////////////////////////
+
+uint32 spi_transaction(uint8 spi_no, uint8 cmd_bits, uint16 cmd_data, uint32 addr_bits, uint32 addr_data, uint32 dout_bits, uint32 dout_data,
+				uint32 din_bits, uint32 dummy_bits){
+
+	if(spi_no > 1) return 0;  //Check for a valid SPI 
+
+	//code for custom Chip Select as GPIO PIN here
+
+	while(spi_busy(spi_no)); //wait for SPI to be ready	
+
+//########## Enable SPI Functions ##########//
+	//disable MOSI, MISO, ADDR, COMMAND, DUMMY in case previously set.
+	CLEAR_PERI_REG_MASK(SPI_USER(spi_no), SPI_USR_MOSI|SPI_USR_MISO|SPI_USR_COMMAND|SPI_USR_ADDR|SPI_USR_DUMMY);
+
+	//enable functions based on number of bits. 0 bits = disabled. 
+	//This is rather inefficient but allows for a very generic function.
+	//CMD ADDR and MOSI are set below to save on an extra if statement.
+//	if(cmd_bits) {SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_USR_COMMAND);}
+//	if(addr_bits) {SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_USR_ADDR);}
+	if(din_bits) {SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_USR_MISO);}
+	if(dummy_bits) {SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_USR_DUMMY);}
+//########## END SECTION ##########//
+
+//########## Setup Bitlengths ##########//
+	WRITE_PERI_REG(SPI_USER1(spi_no), ((addr_bits-1)&SPI_USR_ADDR_BITLEN)<<SPI_USR_ADDR_BITLEN_S | //Number of bits in Address
+									  ((dout_bits-1)&SPI_USR_MOSI_BITLEN)<<SPI_USR_MOSI_BITLEN_S | //Number of bits to Send
+									  ((din_bits-1)&SPI_USR_MISO_BITLEN)<<SPI_USR_MISO_BITLEN_S |  //Number of bits to receive
+									  ((dummy_bits-1)&SPI_USR_DUMMY_CYCLELEN)<<SPI_USR_DUMMY_CYCLELEN_S); //Number of Dummy bits to insert
+//########## END SECTION ##########//
+
+//########## Setup Command Data ##########//
+	if(cmd_bits) {
+		SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_USR_COMMAND); //enable COMMAND function in SPI module
+		uint16 command = cmd_data << (16-cmd_bits); //align command data to high bits
+		command = ((command>>8)&0xff) | ((command<<8)&0xff00); //swap byte order
+		WRITE_PERI_REG(SPI_USER2(spi_no), ((((cmd_bits-1)&SPI_USR_COMMAND_BITLEN)<<SPI_USR_COMMAND_BITLEN_S) | command&SPI_USR_COMMAND_VALUE));	
+	}
+//########## END SECTION ##########//
+
+//########## Setup Address Data ##########//
+	if(addr_bits){
+		SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_USR_ADDR); //enable ADDRess function in SPI module
+		WRITE_PERI_REG(SPI_ADDR(spi_no), addr_data<<(32-addr_bits)); //align address data to high bits
+	}
+	
+
+//########## END SECTION ##########//	
+
+//########## Setup DOUT data ##########//
+	if(dout_bits) {
+		SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_USR_MOSI); //enable MOSI function in SPI module
+	//copy data to W0
+	if(READ_PERI_REG(SPI_USER(spi_no))&SPI_WR_BYTE_ORDER) {
+		WRITE_PERI_REG(SPI_W0(spi_no), dout_data<<(32-dout_bits));
+	} else {
+
+		uint8 dout_extra_bits = dout_bits%8;
+
+		if(dout_extra_bits){
+			//if your data isn't a byte multiple (8/16/24/32 bits)and you don't have SPI_WR_BYTE_ORDER set, you need this to move the non-8bit remainder to the MSBs
+			//not sure if there's even a use case for this, but it's here if you need it...
+			//for example, 0xDA4 12 bits without SPI_WR_BYTE_ORDER would usually be output as if it were 0x0DA4, 
+			//of which 0xA4, and then 0x0 would be shifted out (first 8 bits of low byte, then 4 MSB bits of high byte - ie reverse byte order). 
+			//The code below shifts it out as 0xA4 followed by 0xD as you might require. 
+			WRITE_PERI_REG(SPI_W0(spi_no), ((0xFFFFFFFF<<(dout_bits - dout_extra_bits)&dout_data)<<(8-dout_extra_bits) | (0xFFFFFFFF>>(32-(dout_bits - dout_extra_bits)))&dout_data));
+		} else {
+			WRITE_PERI_REG(SPI_W0(spi_no), dout_data);
+		}
+	}
+	}
+//########## END SECTION ##########//
+
+//########## Begin SPI Transaction ##########//
+	SET_PERI_REG_MASK(SPI_CMD(spi_no), SPI_USR);
+//########## END SECTION ##########//
+
+//########## Return DIN data ##########//
+	if(din_bits) {
+		while(spi_busy(spi_no));	//wait for SPI transaction to complete
+		
+		if(READ_PERI_REG(SPI_USER(spi_no))&SPI_RD_BYTE_ORDER) {
+			return READ_PERI_REG(SPI_W0(spi_no)) >> (32-din_bits); //Assuming data in is written to MSB. TBC
+		} else {
+			return READ_PERI_REG(SPI_W0(spi_no)); //Read in the same way as DOUT is sent. Note existing contents of SPI_W0 remain unless overwritten! 
+		}
+
+		return 0; //something went wrong
+	}
+//########## END SECTION ##########//
+
+	//Transaction completed
+	return 1; //success
+}
+
+////////////////////////////////////////////////////////////////////////////////
+
+/*///////////////////////////////////////////////////////////////////////////////
+//
+// Function Name: func
+//   Description: 
+//    Parameters: 
+//				 
+////////////////////////////////////////////////////////////////////////////////
+
+void func(params){
+
+}
+
+///////////////////////////////////////////////////////////////////////////////*/
+
+
diff --git a/targets/esp8266/spi.h b/targets/esp8266/spi.h
new file mode 100644
index 0000000000..8a32f5d1d3
--- /dev/null
+++ b/targets/esp8266/spi.h
@@ -0,0 +1,75 @@
+/*
+ * This file is part of Espruino, a JavaScript interpreter for Microcontrollers
+ *
+ * Copyright (c) 2015 David Ogilvy (MetalPhreak)
+ *
+ * This Source Code Form is subject to the terms of the Mozilla Public
+ * License, v. 2.0. If a copy of the MPL was not distributed with this
+ * file, You can obtain one at http://mozilla.org/MPL/2.0/.
+ *
+ * ----------------------------------------------------------------------------
+ * This file is designed to be parsed during the build process
+ *
+ * Contains ESP8266 board specific functions.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * The Github project from which this source file came from can be found
+ * at:  https://github.com/MetalPhreak/ESP8266_SPI_Driver
+ */
+
+#ifndef SPI_APP_H
+#define SPI_APP_H
+
+#include "spi_register.h"
+#include "ets_sys.h"
+#include "osapi.h"
+//#include "uart.h"
+#include "os_type.h"
+
+//Define SPI hardware modules
+#define SPI 0
+#define HSPI 1
+
+#define SPI_CLK_USE_DIV 0
+#define SPI_CLK_80MHZ_NODIV 1
+
+#define SPI_BYTE_ORDER_HIGH_TO_LOW 1
+#define SPI_BYTE_ORDER_LOW_TO_HIGH 0
+
+#ifndef CPU_CLK_FREQ //Should already be defined in eagle_soc.h
+#define CPU_CLK_FREQ 80*1000000
+#endif
+
+//Define some default SPI clock settings
+#define SPI_CLK_PREDIV 10
+#define SPI_CLK_CNTDIV 2
+#define SPI_CLK_FREQ CPU_CLK_FREQ/(SPI_CLK_PREDIV*SPI_CLK_CNTDIV) // 80 / 20 = 4 MHz
+
+
+
+
+
+void spi_init(uint8 spi_no);
+void spi_init_gpio(uint8 spi_no, uint8 sysclk_as_spiclk);
+void spi_clock(uint8 spi_no, uint16 prediv, uint8 cntdiv);
+void spi_tx_byte_order(uint8 spi_no, uint8 byte_order);
+void spi_rx_byte_order(uint8 spi_no, uint8 byte_order);
+uint32 spi_transaction(uint8 spi_no, uint8 cmd_bits, uint16 cmd_data, uint32 addr_bits, uint32 addr_data, uint32 dout_bits, uint32 dout_data, uint32 din_bits, uint32 dummy_bits);
+
+//Expansion Macros
+#define spi_busy(spi_no) READ_PERI_REG(SPI_CMD(spi_no))&SPI_USR
+
+#define spi_txd(spi_no, bits, data) spi_transaction(spi_no, 0, 0, 0, 0, bits, (uint32) data, 0, 0)
+#define spi_tx8(spi_no, data)       spi_transaction(spi_no, 0, 0, 0, 0, 8,    (uint32) data, 0, 0)
+#define spi_tx16(spi_no, data)      spi_transaction(spi_no, 0, 0, 0, 0, 16,   (uint32) data, 0, 0)
+#define spi_tx32(spi_no, data)      spi_transaction(spi_no, 0, 0, 0, 0, 32,   (uint32) data, 0, 0)
+
+#define spi_rxd(spi_no, bits) spi_transaction(spi_no, 0, 0, 0, 0, 0, 0, bits, 0)
+#define spi_rx8(spi_no)       spi_transaction(spi_no, 0, 0, 0, 0, 0, 0, 8,    0)
+#define spi_rx16(spi_no)      spi_transaction(spi_no, 0, 0, 0, 0, 0, 0, 16,   0)
+#define spi_rx32(spi_no)      spi_transaction(spi_no, 0, 0, 0, 0, 0, 0, 32,   0)
+
+#endif
+
diff --git a/targets/esp8266/spi_register.h b/targets/esp8266/spi_register.h
new file mode 100644
index 0000000000..e66ad1b202
--- /dev/null
+++ b/targets/esp8266/spi_register.h
@@ -0,0 +1,277 @@
+/*
+ *  Copyright (c) 2010 - 2011 Espressif System
+ *  Modified by David Ogilvy (MetalPhreak)
+ *  Based on original file included in SDK 1.0.0
+ *
+ *  Missing defines from previous SDK versions have 
+ *  been added and are noted with comments. The
+ *  names of these defines are likely to change.
+ */
+
+#ifndef SPI_REGISTER_H_INCLUDED
+#define SPI_REGISTER_H_INCLUDED
+
+#define REG_SPI_BASE(i)  (0x60000200-i*0x100)
+
+#define SPI_CMD(i)                            (REG_SPI_BASE(i)  + 0x0)
+#define SPI_FLASH_READ (BIT(31)) //From previous SDK
+#define SPI_FLASH_WREN (BIT(30)) //From previous SDK
+#define SPI_FLASH_WRDI (BIT(29)) //From previous SDK
+#define SPI_FLASH_RDID (BIT(28)) //From previous SDK
+#define SPI_FLASH_RDSR (BIT(27)) //From previous SDK
+#define SPI_FLASH_WRSR (BIT(26)) //From previous SDK
+#define SPI_FLASH_PP (BIT(25)) //From previous SDK
+#define SPI_FLASH_SE (BIT(24)) //From previous SDK
+#define SPI_FLASH_BE (BIT(23)) //From previous SDK
+#define SPI_FLASH_CE (BIT(22)) //From previous SDK
+#define SPI_FLASH_DP (BIT(21)) //From previous SDK
+#define SPI_FLASH_RES (BIT(20)) //From previous SDK
+#define SPI_FLASH_HPM (BIT(19)) //From previous SDK
+#define SPI_USR (BIT(18))
+
+#define SPI_ADDR(i)                           (REG_SPI_BASE(i)  + 0x4)
+
+#define SPI_CTRL(i)                           (REG_SPI_BASE(i)  + 0x8)
+#define SPI_WR_BIT_ORDER (BIT(26))
+#define SPI_RD_BIT_ORDER (BIT(25))
+#define SPI_QIO_MODE (BIT(24))
+#define SPI_DIO_MODE (BIT(23))
+#define SPI_TWO_BYTE_STATUS_EN (BIT(22)) //From previous SDK
+#define SPI_WP_REG (BIT(21)) //From previous SDK
+#define SPI_QOUT_MODE (BIT(20))
+#define SPI_SHARE_BUS (BIT(19)) //From previous SDK
+#define SPI_HOLD_MODE (BIT(18)) //From previous SDK
+#define SPI_ENABLE_AHB (BIT(17)) //From previous SDK
+#define SPI_SST_AAI (BIT(16)) //From previous SDK
+#define SPI_RESANDRES (BIT(15)) //From previous SDK
+#define SPI_DOUT_MODE (BIT(14))
+#define SPI_FASTRD_MODE (BIT(13))
+
+#define SPI_CTRL1(i)                          (REG_SPI_BASE (i) + 0xC) //From previous SDK. Removed _FLASH_ from name to match other registers.
+#define SPI_CS_HOLD_DELAY 0x0000000F //Espressif BBS
+#define SPI_CS_HOLD_DELAY_S 28 //Espressif BBS
+#define SPI_CS_HOLD_DELAY_RES 0x00000FFF //Espressif BBS
+#define SPI_CS_HOLD_DELAY_RES_S 16 //Espressif BBS
+#define SPI_BUS_TIMER_LIMIT 0x0000FFFF //From previous SDK
+#define SPI_BUS_TIMER_LIMIT_S 0 //From previous SDK
+
+
+#define SPI_RD_STATUS(i)                         (REG_SPI_BASE(i)  + 0x10)
+#define SPI_STATUS_EXT 0x000000FF //From previous SDK
+#define SPI_STATUS_EXT_S 24 //From previous SDK
+#define SPI_WB_MODE 0x000000FF //From previous SDK
+#define SPI_WB_MODE_S 16 //From previous SDK
+#define SPI_FLASH_STATUS_PRO_FLAG (BIT(7)) //From previous SDK
+#define SPI_FLASH_TOP_BOT_PRO_FLAG (BIT(5)) //From previous SDK
+#define SPI_FLASH_BP2 (BIT(4)) //From previous SDK
+#define SPI_FLASH_BP1 (BIT(3)) //From previous SDK
+#define SPI_FLASH_BP0 (BIT(2)) //From previous SDK
+#define SPI_FLASH_WRENABLE_FLAG (BIT(1)) //From previous SDK
+#define SPI_FLASH_BUSY_FLAG (BIT(0)) //From previous SDK
+
+#define SPI_CTRL2(i)                           (REG_SPI_BASE(i)  + 0x14)
+#define SPI_CS_DELAY_NUM 0x0000000F
+#define SPI_CS_DELAY_NUM_S 28
+#define SPI_CS_DELAY_MODE 0x00000003
+#define SPI_CS_DELAY_MODE_S 26
+#define SPI_MOSI_DELAY_NUM 0x00000007
+#define SPI_MOSI_DELAY_NUM_S 23
+#define SPI_MOSI_DELAY_MODE 0x00000003  //mode 0 : posedge; data set at positive edge of clk
+										//mode 1 : negedge + 1 cycle delay, only if freq<10MHz ; data set at negitive edge of clk
+										//mode 2 : Do not use this mode.
+#define SPI_MOSI_DELAY_MODE_S 21
+#define SPI_MISO_DELAY_NUM 0x00000007
+#define SPI_MISO_DELAY_NUM_S 18
+#define SPI_MISO_DELAY_MODE 0x00000003
+#define SPI_MISO_DELAY_MODE_S 16
+#define SPI_CK_OUT_HIGH_MODE 0x0000000F
+#define SPI_CK_OUT_HIGH_MODE_S 12
+#define SPI_CK_OUT_LOW_MODE 0x0000000F
+#define SPI_CK_OUT_LOW_MODE_S 8
+#define SPI_HOLD_TIME 0x0000000F
+#define SPI_HOLD_TIME_S 4
+#define SPI_SETUP_TIME 0x0000000F
+#define SPI_SETUP_TIME_S 0
+
+#define SPI_CLOCK(i)                          (REG_SPI_BASE(i)  + 0x18)
+#define SPI_CLK_EQU_SYSCLK (BIT(31))
+#define SPI_CLKDIV_PRE 0x00001FFF
+#define SPI_CLKDIV_PRE_S 18
+#define SPI_CLKCNT_N 0x0000003F
+#define SPI_CLKCNT_N_S 12
+#define SPI_CLKCNT_H 0x0000003F
+#define SPI_CLKCNT_H_S 6
+#define SPI_CLKCNT_L 0x0000003F
+#define SPI_CLKCNT_L_S 0
+
+#define SPI_USER(i)                           (REG_SPI_BASE(i)  + 0x1C)
+#define SPI_USR_COMMAND (BIT(31))
+#define SPI_USR_ADDR (BIT(30))
+#define SPI_USR_DUMMY (BIT(29))
+#define SPI_USR_MISO (BIT(28))
+#define SPI_USR_MOSI (BIT(27))
+#define SPI_USR_DUMMY_IDLE (BIT(26)) //From previous SDK
+#define SPI_USR_MOSI_HIGHPART (BIT(25))
+#define SPI_USR_MISO_HIGHPART (BIT(24))
+#define SPI_USR_PREP_HOLD (BIT(23)) //From previous SDK
+#define SPI_USR_CMD_HOLD (BIT(22)) //From previous SDK
+#define SPI_USR_ADDR_HOLD (BIT(21)) //From previous SDK
+#define SPI_USR_DUMMY_HOLD (BIT(20)) //From previous SDK
+#define SPI_USR_DIN_HOLD (BIT(19)) //From previous SDK
+#define SPI_USR_DOUT_HOLD (BIT(18)) //From previous SDK
+#define SPI_USR_HOLD_POL (BIT(17)) //From previous SDK
+#define SPI_SIO (BIT(16))
+#define SPI_FWRITE_QIO (BIT(15))
+#define SPI_FWRITE_DIO (BIT(14))
+#define SPI_FWRITE_QUAD (BIT(13))
+#define SPI_FWRITE_DUAL (BIT(12))
+#define SPI_WR_BYTE_ORDER (BIT(11))
+#define SPI_RD_BYTE_ORDER (BIT(10))
+#define SPI_AHB_ENDIAN_MODE 0x00000003 //From previous SDK
+#define SPI_AHB_ENDIAN_MODE_S 8 //From previous SDK
+#define SPI_CK_OUT_EDGE (BIT(7))
+#define SPI_CK_I_EDGE (BIT(6))
+#define SPI_CS_SETUP (BIT(5))
+#define SPI_CS_HOLD (BIT(4))
+#define SPI_AHB_USR_COMMAND (BIT(3)) //From previous SDK
+#define SPI_FLASH_MODE (BIT(2))
+#define SPI_AHB_USR_COMMAND_4BYTE (BIT(1)) //From previous SDK
+#define SPI_DOUTDIN (BIT(0)) //From previous SDK
+
+//AHB = http://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_Architecture ?
+
+
+#define SPI_USER1(i)                          (REG_SPI_BASE(i) + 0x20)
+#define SPI_USR_ADDR_BITLEN 0x0000003F
+#define SPI_USR_ADDR_BITLEN_S 26
+#define SPI_USR_MOSI_BITLEN 0x000001FF
+#define SPI_USR_MOSI_BITLEN_S 17
+#define SPI_USR_MISO_BITLEN 0x000001FF
+#define SPI_USR_MISO_BITLEN_S 8
+#define SPI_USR_DUMMY_CYCLELEN 0x000000FF
+#define SPI_USR_DUMMY_CYCLELEN_S 0
+
+#define SPI_USER2(i)                          (REG_SPI_BASE(i)  + 0x24)
+#define SPI_USR_COMMAND_BITLEN 0x0000000F
+#define SPI_USR_COMMAND_BITLEN_S 28
+#define SPI_USR_COMMAND_VALUE 0x0000FFFF
+#define SPI_USR_COMMAND_VALUE_S 0
+
+#define SPI_WR_STATUS(i)                          (REG_SPI_BASE(i)  + 0x28)
+ //previously defined as SPI_FLASH_USER3. No further info available.
+
+#define SPI_PIN(i)                            (REG_SPI_BASE(i)  + 0x2C)
+#define SPI_CS2_DIS (BIT(2))
+#define SPI_CS1_DIS (BIT(1))
+#define SPI_CS0_DIS (BIT(0))
+
+#define SPI_SLAVE(i)                          (REG_SPI_BASE(i)  + 0x30)
+#define SPI_SYNC_RESET (BIT(31))
+#define SPI_SLAVE_MODE (BIT(30))
+#define SPI_SLV_WR_RD_BUF_EN (BIT(29))
+#define SPI_SLV_WR_RD_STA_EN (BIT(28))
+#define SPI_SLV_CMD_DEFINE (BIT(27))
+#define SPI_TRANS_CNT 0x0000000F
+#define SPI_TRANS_CNT_S 23
+#define SPI_SLV_LAST_STATE 0x00000007 //From previous SDK
+#define SPI_SLV_LAST_STATE_S 20 //From previous SDK
+#define SPI_SLV_LAST_COMMAND 0x00000007 //From previous SDK
+#define SPI_SLV_LAST_COMMAND_S 17 //From previous SDK
+#define SPI_CS_I_MODE 0x00000003 //From previous SDK
+#define SPI_CS_I_MODE_S 10 //From previous SDK
+#define SPI_TRANS_DONE_EN (BIT(9))
+#define SPI_SLV_WR_STA_DONE_EN (BIT(8))
+#define SPI_SLV_RD_STA_DONE_EN (BIT(7))
+#define SPI_SLV_WR_BUF_DONE_EN (BIT(6))
+#define SPI_SLV_RD_BUF_DONE_EN (BIT(5))
+#define SLV_SPI_INT_EN   0x0000001f
+#define SLV_SPI_INT_EN_S 5
+#define SPI_TRANS_DONE (BIT(4))
+#define SPI_SLV_WR_STA_DONE (BIT(3))
+#define SPI_SLV_RD_STA_DONE (BIT(2))
+#define SPI_SLV_WR_BUF_DONE (BIT(1))
+#define SPI_SLV_RD_BUF_DONE (BIT(0))
+
+#define SPI_SLAVE1(i)                         (REG_SPI_BASE(i)  + 0x34)
+#define SPI_SLV_STATUS_BITLEN 0x0000001F
+#define SPI_SLV_STATUS_BITLEN_S 27
+#define SPI_SLV_STATUS_FAST_EN (BIT(26)) //From previous SDK
+#define SPI_SLV_STATUS_READBACK (BIT(25)) //From previous SDK
+#define SPI_SLV_BUF_BITLEN 0x000001FF
+#define SPI_SLV_BUF_BITLEN_S 16
+#define SPI_SLV_RD_ADDR_BITLEN 0x0000003F
+#define SPI_SLV_RD_ADDR_BITLEN_S 10
+#define SPI_SLV_WR_ADDR_BITLEN 0x0000003F
+#define SPI_SLV_WR_ADDR_BITLEN_S 4
+#define SPI_SLV_WRSTA_DUMMY_EN (BIT(3))
+#define SPI_SLV_RDSTA_DUMMY_EN (BIT(2))
+#define SPI_SLV_WRBUF_DUMMY_EN (BIT(1))
+#define SPI_SLV_RDBUF_DUMMY_EN (BIT(0))
+
+
+
+#define SPI_SLAVE2(i)  (REG_SPI_BASE(i)  + 0x38)
+#define SPI_SLV_WRBUF_DUMMY_CYCLELEN  0X000000FF
+#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_S 24
+#define SPI_SLV_RDBUF_DUMMY_CYCLELEN  0X000000FF
+#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_S 16
+#define SPI_SLV_WRSTR_DUMMY_CYCLELEN  0X000000FF
+#define SPI_SLV_WRSTR_DUMMY_CYCLELEN_S  8
+#define SPI_SLV_RDSTR_DUMMY_CYCLELEN  0x000000FF
+#define SPI_SLV_RDSTR_DUMMY_CYCLELEN_S 0
+
+#define SPI_SLAVE3(i)                         (REG_SPI_BASE(i)  + 0x3C)
+#define SPI_SLV_WRSTA_CMD_VALUE 0x000000FF
+#define SPI_SLV_WRSTA_CMD_VALUE_S 24
+#define SPI_SLV_RDSTA_CMD_VALUE 0x000000FF
+#define SPI_SLV_RDSTA_CMD_VALUE_S 16
+#define SPI_SLV_WRBUF_CMD_VALUE 0x000000FF
+#define SPI_SLV_WRBUF_CMD_VALUE_S 8
+#define SPI_SLV_RDBUF_CMD_VALUE 0x000000FF
+#define SPI_SLV_RDBUF_CMD_VALUE_S 0
+
+//Previous SDKs referred to these following registers as SPI_C0 etc.
+
+#define SPI_W0(i) 							(REG_SPI_BASE(i) +0x40)
+#define SPI_W1(i) 							(REG_SPI_BASE(i) +0x44)
+#define SPI_W2(i) 							(REG_SPI_BASE(i) +0x48)
+#define SPI_W3(i) 							(REG_SPI_BASE(i) +0x4C)
+#define SPI_W4(i) 							(REG_SPI_BASE(i) +0x50)
+#define SPI_W5(i) 							(REG_SPI_BASE(i) +0x54)
+#define SPI_W6(i) 							(REG_SPI_BASE(i) +0x58)
+#define SPI_W7(i) 							(REG_SPI_BASE(i) +0x5C)
+#define SPI_W8(i) 							(REG_SPI_BASE(i) +0x60)
+#define SPI_W9(i) 							(REG_SPI_BASE(i) +0x64)
+#define SPI_W10(i) 							(REG_SPI_BASE(i) +0x68)
+#define SPI_W11(i) 							(REG_SPI_BASE(i) +0x6C)
+#define SPI_W12(i) 							(REG_SPI_BASE(i) +0x70)
+#define SPI_W13(i) 							(REG_SPI_BASE(i) +0x74)
+#define SPI_W14(i) 							(REG_SPI_BASE(i) +0x78)
+#define SPI_W15(i) 							(REG_SPI_BASE(i) +0x7C)
+
+ // +0x80 to +0xBC could be SPI_W16 through SPI_W31?
+
+ // +0xC0 to +0xEC not currently defined.
+
+#define SPI_EXT0(i)                           (REG_SPI_BASE(i)  + 0xF0) //From previous SDK. Removed _FLASH_ from name to match other registers.
+#define SPI_T_PP_ENA (BIT(31)) //From previous SDK
+#define SPI_T_PP_SHIFT 0x0000000F //From previous SDK
+#define SPI_T_PP_SHIFT_S 16 //From previous SDK
+#define SPI_T_PP_TIME 0x00000FFF //From previous SDK
+#define SPI_T_PP_TIME_S 0 //From previous SDK
+
+#define SPI_EXT1(i)                          (REG_SPI_BASE(i)  + 0xF4) //From previous SDK. Removed _FLASH_ from name to match other registers.
+#define SPI_T_ERASE_ENA (BIT(31)) //From previous SDK
+#define SPI_T_ERASE_SHIFT 0x0000000F //From previous SDK
+#define SPI_T_ERASE_SHIFT_S 16 //From previous SDK
+#define SPI_T_ERASE_TIME 0x00000FFF //From previous SDK
+#define SPI_T_ERASE_TIME_S 0 //From previous SDK
+
+#define SPI_EXT2(i)                           (REG_SPI_BASE(i)  + 0xF8) //From previous SDK. Removed _FLASH_ from name to match other registers.
+#define SPI_ST 0x00000007 //From previous SDK
+#define SPI_ST_S 0 //From previous SDK
+
+#define SPI_EXT3(i)                           (REG_SPI_BASE(i)  + 0xFC)
+#define SPI_INT_HOLD_ENA 0x00000003
+#define SPI_INT_HOLD_ENA_S 0
+#endif // SPI_REGISTER_H_INCLUDED
diff --git a/targets/esp8266/user_main.c b/targets/esp8266/user_main.c
index 37f7d2fe64..a4874edee4 100644
--- a/targets/esp8266/user_main.c
+++ b/targets/esp8266/user_main.c
@@ -26,7 +26,7 @@ typedef long long int64_t;
 
 #include <jsdevices.h>
 #include <jsinteractive.h>
-#include <jswrap_esp8266.h>
+#include <jswrap_esp8266_network.h>
 #include <ota.h>
 #include "ESP8266_board.h"
 
@@ -259,6 +259,7 @@ void user_init() {
 
   // Initialize the UART devices
   uart_init(BIT_RATE_115200, BIT_RATE_115200);
+  //uart_init(BIT_RATE_9600, BIT_RATE_9600);
   os_delay_us(1000); // make sure there's a gap on uart output
   UART_SetPrintPort(1);
   system_set_os_print(1);