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me-no-devme-no-dev
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Update TinyUSB DWC2 DCD
1 parent bb76cb1 commit 33f0b46

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+57
-57
lines changed

2 files changed

+57
-57
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Diff for: ‎components/arduino_tinyusb/patches/dcd_dwc2.patch

+4-4
Original file line numberDiff line numberDiff line change
@@ -19,11 +19,11 @@
1919
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
2020
const uint8_t epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
2121
@@ -266,7 +277,18 @@
22-
depctl.bm.set_data0_iso_even = 1;
22+
depctl.set_data0_iso_even = 1;
2323
}
2424
if (dir == TUSB_DIR_IN) {
25-
- depctl.bm.tx_fifo_num = epnum;
26-
+ //depctl.bm.tx_fifo_num = epnum;
25+
- depctl.tx_fifo_num = epnum;
26+
+ //depctl.tx_fifo_num = epnum;
2727
+ uint8_t fifo_num = epnum;
2828
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
2929
+ // Special Case for EP5, which is used by CDC but not actually called by the driver
@@ -34,7 +34,7 @@
3434
+ fifo_num = get_free_fifo();
3535
+ }
3636
+#endif
37-
+ depctl.bm.tx_fifo_num = fifo_num;
37+
+ depctl.tx_fifo_num = fifo_num;
3838
}
3939

4040
dwc2_dep_t* dep = &dwc2->ep[dir == TUSB_DIR_IN ? 0 : 1][epnum];

Diff for: ‎components/arduino_tinyusb/src/dcd_dwc2.c

+53-53
Original file line numberDiff line numberDiff line change
@@ -41,12 +41,6 @@
4141
#include "device/dcd.h"
4242
#include "dwc2_common.h"
4343

44-
#if TU_CHECK_MCU(OPT_MCU_GD32VF103)
45-
#define DWC2_EP_COUNT(_dwc2) DWC2_EP_MAX
46-
#else
47-
#define DWC2_EP_COUNT(_dwc2) ((_dwc2)->ghwcfg2_bm.num_dev_ep + 1)
48-
#endif
49-
5044
//--------------------------------------------------------------------+
5145
// MACRO TYPEDEF CONSTANT ENUM
5246
//--------------------------------------------------------------------+
@@ -79,6 +73,16 @@ CFG_TUD_MEM_SECTION static struct {
7973
TUD_EPBUF_DEF(setup_packet, 8);
8074
} _dcd_usbbuf;
8175

76+
TU_ATTR_ALWAYS_INLINE static inline uint8_t dwc2_ep_count(const dwc2_regs_t* dwc2) {
77+
#if TU_CHECK_MCU(OPT_MCU_GD32VF103)
78+
return DWC2_EP_MAX;
79+
#else
80+
const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2};
81+
return ghwcfg2.num_dev_ep + 1;
82+
#endif
83+
}
84+
85+
8286
//--------------------------------------------------------------------
8387
// DMA
8488
//--------------------------------------------------------------------
@@ -102,7 +106,8 @@ bool dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
102106
TU_ATTR_ALWAYS_INLINE static inline bool dma_device_enabled(const dwc2_regs_t* dwc2) {
103107
(void) dwc2;
104108
// Internal DMA only
105-
return CFG_TUD_DWC2_DMA_ENABLE && dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA;
109+
const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2};
110+
return CFG_TUD_DWC2_DMA_ENABLE && ghwcfg2.arch == GHWCFG2_ARCH_INTERNAL_DMA;
106111
}
107112

108113
static void dma_setup_prepare(uint8_t rhport) {
@@ -261,20 +266,15 @@ static void edpt_activate(uint8_t rhport, const tusb_desc_endpoint_t* p_endpoint
261266
xfer->interval = p_endpoint_desc->bInterval;
262267

263268
// Endpoint control
264-
union {
265-
uint32_t value;
266-
dwc2_depctl_t bm;
267-
} depctl;
268-
depctl.value = 0;
269-
270-
depctl.bm.mps = xfer->max_size;
271-
depctl.bm.active = 1;
272-
depctl.bm.type = p_endpoint_desc->bmAttributes.xfer;
269+
dwc2_depctl_t depctl = {.value = 0};
270+
depctl.mps = xfer->max_size;
271+
depctl.active = 1;
272+
depctl.type = p_endpoint_desc->bmAttributes.xfer;
273273
if (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS) {
274-
depctl.bm.set_data0_iso_even = 1;
274+
depctl.set_data0_iso_even = 1;
275275
}
276276
if (dir == TUSB_DIR_IN) {
277-
//depctl.bm.tx_fifo_num = epnum;
277+
//depctl.tx_fifo_num = epnum;
278278
uint8_t fifo_num = epnum;
279279
#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
280280
// Special Case for EP5, which is used by CDC but not actually called by the driver
@@ -285,7 +285,7 @@ static void edpt_activate(uint8_t rhport, const tusb_desc_endpoint_t* p_endpoint
285285
fifo_num = get_free_fifo();
286286
}
287287
#endif
288-
depctl.bm.tx_fifo_num = fifo_num;
288+
depctl.tx_fifo_num = fifo_num;
289289
}
290290

291291
dwc2_dep_t* dep = &dwc2->ep[dir == TUSB_DIR_IN ? 0 : 1][epnum];
@@ -365,31 +365,22 @@ static void edpt_schedule_packets(uint8_t rhport, const uint8_t epnum, const uin
365365
}
366366

367367
// transfer size: A full OUT transfer (multiple packets, possibly) triggers XFRC.
368-
union {
369-
uint32_t value;
370-
dwc2_ep_tsize_t bm;
371-
} deptsiz;
372-
deptsiz.value = 0;
373-
deptsiz.bm.xfer_size = total_bytes;
374-
deptsiz.bm.packet_count = num_packets;
375-
368+
dwc2_ep_tsize_t deptsiz = {.value = 0};
369+
deptsiz.xfer_size = total_bytes;
370+
deptsiz.packet_count = num_packets;
376371
dep->tsiz = deptsiz.value;
377372

378373
// control
379-
union {
380-
dwc2_depctl_t bm;
381-
uint32_t value;
382-
} depctl;
383-
depctl.value = dep->ctl;
384-
385-
depctl.bm.clear_nak = 1;
386-
depctl.bm.enable = 1;
387-
if (depctl.bm.type == DEPCTL_EPTYPE_ISOCHRONOUS && xfer->interval == 1) {
388-
const uint32_t odd_now = (dwc2->dsts_bm.frame_number & 1u);
374+
dwc2_depctl_t depctl = {.value = dep->ctl};
375+
depctl.clear_nak = 1;
376+
depctl.enable = 1;
377+
if (depctl.type == DEPCTL_EPTYPE_ISOCHRONOUS && xfer->interval == 1) {
378+
const dwc2_dsts_t dsts = {.value = dwc2->dsts};
379+
const uint32_t odd_now = dsts.frame_number & 1u;
389380
if (odd_now) {
390-
depctl.bm.set_data0_iso_even = 1;
381+
depctl.set_data0_iso_even = 1;
391382
} else {
392-
depctl.bm.set_data1_iso_odd = 1;
383+
depctl.set_data1_iso_odd = 1;
393384
}
394385
}
395386

@@ -432,7 +423,8 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
432423

433424
// XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required
434425
// when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347)
435-
if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) {
426+
const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2};
427+
if (ghwcfg2.hs_phy_type == GHWCFG2_HSPHY_ULPI) {
436428
dcfg |= DCFG_XCVRDLY;
437429
}
438430
} else {
@@ -667,7 +659,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
667659
// 7.4.1 Initialization on USB Reset
668660
static void handle_bus_reset(uint8_t rhport) {
669661
dwc2_regs_t *dwc2 = DWC2_REG(rhport);
670-
const uint8_t ep_count = DWC2_EP_COUNT(dwc2);
662+
const uint8_t ep_count = dwc2_ep_count(dwc2);
671663

672664
tu_memclr(xfer_status, sizeof(xfer_status));
673665

@@ -697,7 +689,9 @@ static void handle_bus_reset(uint8_t rhport) {
697689
dfifo_device_init(rhport);
698690

699691
// 5. Reset device address
700-
dwc2->dcfg_bm.address = 0;
692+
dwc2_dcfg_t dcfg = {.value = dwc2->dcfg};
693+
dcfg.address = 0;
694+
dwc2->dcfg = dcfg.value;
701695

702696
// Fixed both control EP0 size to 64 bytes
703697
dwc2->epin[0].ctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos);
@@ -717,8 +711,9 @@ static void handle_bus_reset(uint8_t rhport) {
717711

718712
static void handle_enum_done(uint8_t rhport) {
719713
dwc2_regs_t *dwc2 = DWC2_REG(rhport);
714+
const dwc2_dsts_t dsts = {.value = dwc2->dsts};
720715
tusb_speed_t speed;
721-
switch (dwc2->dsts_bm.enum_speed) {
716+
switch (dsts.enum_speed) {
722717
case DCFG_SPEED_HIGH:
723718
speed = TUSB_SPEED_HIGH;
724719
break;
@@ -763,12 +758,12 @@ static void handle_rxflvl_irq(uint8_t rhport) {
763758
const volatile uint32_t* rx_fifo = dwc2->fifo[0];
764759

765760
// Pop control word off FIFO
766-
const dwc2_grxstsp_t grxstsp_bm = dwc2->grxstsp_bm;
767-
const uint8_t epnum = grxstsp_bm.ep_ch_num;
761+
const dwc2_grxstsp_t grxstsp = {.value = dwc2->grxstsp};
762+
const uint8_t epnum = grxstsp.ep_ch_num;
768763

769764
dwc2_dep_t* epout = &dwc2->epout[epnum];
770765

771-
switch (grxstsp_bm.packet_status) {
766+
switch (grxstsp.packet_status) {
772767
case GRXSTS_PKTSTS_GLOBAL_OUT_NAK:
773768
// Global OUT NAK: do nothing
774769
break;
@@ -790,7 +785,7 @@ static void handle_rxflvl_irq(uint8_t rhport) {
790785

791786
case GRXSTS_PKTSTS_RX_DATA: {
792787
// Out packet received
793-
const uint16_t byte_count = grxstsp_bm.byte_count;
788+
const uint16_t byte_count = grxstsp.byte_count;
794789
xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
795790

796791
if (byte_count) {
@@ -804,7 +799,8 @@ static void handle_rxflvl_irq(uint8_t rhport) {
804799

805800
// short packet, minus remaining bytes (xfer_size)
806801
if (byte_count < xfer->max_size) {
807-
xfer->total_len -= epout->tsiz_bm.xfer_size;
802+
const dwc2_ep_tsize_t tsiz = {.value = epout->tsiz};
803+
xfer->total_len -= tsiz.xfer_size;
808804
if (epnum == 0) {
809805
xfer->total_len -= _dcd_data.ep0_pending[TUSB_DIR_OUT];
810806
_dcd_data.ep0_pending[TUSB_DIR_OUT] = 0;
@@ -866,11 +862,13 @@ static void handle_epin_slave(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diep
866862
// - 64 bytes or
867863
// - Half/Empty of TX FIFO size (configured by GAHBCFG.TXFELVL)
868864
if (diepint_bm.txfifo_empty && (dwc2->diepempmsk & (1 << epnum))) {
869-
const uint16_t remain_packets = epin->tsiz_bm.packet_count;
865+
dwc2_ep_tsize_t tsiz = {.value = epin->tsiz};
866+
const uint16_t remain_packets = tsiz.packet_count;
870867

871868
// Process every single packet (only whole packets can be written to fifo)
872869
for (uint16_t i = 0; i < remain_packets; i++) {
873-
const uint16_t remain_bytes = (uint16_t) epin->tsiz_bm.xfer_size;
870+
tsiz.value = epin->tsiz;
871+
const uint16_t remain_bytes = (uint16_t) tsiz.xfer_size;
874872
const uint16_t xact_bytes = tu_min16(remain_bytes, xfer->max_size);
875873

876874
// Check if dtxfsts has enough space available
@@ -889,7 +887,8 @@ static void handle_epin_slave(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diep
889887
}
890888

891889
// Turn off TXFE if all bytes are written.
892-
if (epin->tsiz_bm.xfer_size == 0) {
890+
tsiz.value = epin->tsiz;
891+
if (tsiz.xfer_size == 0) {
893892
dwc2->diepempmsk &= ~(1 << epnum);
894893
}
895894
}
@@ -920,7 +919,8 @@ static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepi
920919
xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
921920

922921
// determine actual received bytes
923-
const uint16_t remain = epout->tsiz_bm.xfer_size;
922+
const dwc2_ep_tsize_t tsiz = {.value = epout->tsiz};
923+
const uint16_t remain = tsiz.xfer_size;
924924
xfer->total_len -= remain;
925925

926926
// this is ZLP, so prepare EP0 for next setup
@@ -956,7 +956,7 @@ static void handle_epin_dma(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diepin
956956
static void handle_ep_irq(uint8_t rhport, uint8_t dir) {
957957
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
958958
const bool is_dma = dma_device_enabled(dwc2);
959-
const uint8_t ep_count = DWC2_EP_COUNT(dwc2);
959+
const uint8_t ep_count = dwc2_ep_count(dwc2);
960960
const uint8_t daint_offset = (dir == TUSB_DIR_IN) ? DAINT_IEPINT_Pos : DAINT_OEPINT_Pos;
961961
dwc2_dep_t* ep_base = &dwc2->ep[dir == TUSB_DIR_IN ? 0 : 1][0];
962962

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