Merge branch 'feature/i2s_built_in_adc' into 'master'

feature(I2S-ADC): add ADC mode for I2S.

See merge request !1077

Author: igrr

components/driver/i2s.c

@@ -418,7 +418,7 @@ esp_err_t i2s_set_clk(i2s_port_t i2s_num, uint32_t rate, i2s_bits_per_sample_t b
     }
 
     double mclk;
-    if (p_i2s_obj[i2s_num]->mode & I2S_MODE_DAC_BUILT_IN) {
+    if (p_i2s_obj[i2s_num]->mode & (I2S_MODE_DAC_BUILT_IN | I2S_MODE_ADC_BUILT_IN)) {
         //DAC uses bclk as sample clock, not WS. WS can be something arbitrary.
         //Rate as given to this function is the intended sample rate;
         //According to the TRM, WS clk equals to the sample rate, and bclk is double the speed of WS
@@ -708,6 +708,13 @@ esp_err_t i2s_set_dac_mode(i2s_dac_mode_t dac_mode)
     return ESP_OK;
 }
 
+esp_err_t i2s_set_adc_mode(adc_unit_t adc_unit, adc1_channel_t adc_channel)
+{
+    I2S_CHECK((adc_unit < ADC_UNIT_2), "i2s ADC unit error, only support ADC1 for now", ESP_ERR_INVALID_ARG);
+    // For now, we only support SAR ADC1.
+    return adc_i2s_mode_init(adc_unit, adc_channel);
+}
+
 esp_err_t i2s_set_pin(i2s_port_t i2s_num, const i2s_pin_config_t *pin)
 {
     I2S_CHECK((i2s_num < I2S_NUM_MAX), "i2s_num error", ESP_ERR_INVALID_ARG);
@@ -823,34 +830,42 @@ esp_err_t i2s_set_sample_rates(i2s_port_t i2s_num, uint32_t rate)
     I2S_CHECK((p_i2s_obj[i2s_num]->bytes_per_sample > 0), "bits_per_sample not set", ESP_ERR_INVALID_ARG);
     return i2s_set_clk(i2s_num, rate, p_i2s_obj[i2s_num]->bits_per_sample, p_i2s_obj[i2s_num]->channel_num);
 }
+
 static esp_err_t i2s_param_config(i2s_port_t i2s_num, const i2s_config_t *i2s_config)
 {
     I2S_CHECK((i2s_num < I2S_NUM_MAX), "i2s_num error", ESP_ERR_INVALID_ARG);
     I2S_CHECK((i2s_config), "param null", ESP_ERR_INVALID_ARG);
+    I2S_CHECK(!((i2s_config->mode & I2S_MODE_ADC_BUILT_IN) && (i2s_num != I2S_NUM_0)), "I2S ADC built-in only support on I2S0", ESP_ERR_INVALID_ARG);
+    I2S_CHECK(!((i2s_config->mode & I2S_MODE_DAC_BUILT_IN) && (i2s_num != I2S_NUM_0)), "I2S DAC built-in only support on I2S0", ESP_ERR_INVALID_ARG);
+    I2S_CHECK(!((i2s_config->mode & I2S_MODE_PDM) && (i2s_num != I2S_NUM_0)), "I2S DAC PDM only support on I2S0", ESP_ERR_INVALID_ARG);
 
     if (i2s_num == I2S_NUM_1) {
         periph_module_enable(PERIPH_I2S1_MODULE);
     } else {
         periph_module_enable(PERIPH_I2S0_MODULE);
     }
 
+    if(i2s_config->mode & I2S_MODE_ADC_BUILT_IN) {
+        //in ADC built-in mode, we need to call i2s_set_adc_mode to
+        //initialize the specific ADC channel.
+        //in the current stage, we only support ADC1 and single channel mode.
+        //In default data mode, the ADC data is in 12-bit resolution mode.
+        adc_power_on();
+    }
     // configure I2S data port interface.
     i2s_reset_fifo(i2s_num);
-
     //reset i2s
     I2S[i2s_num]->conf.tx_reset = 1;
     I2S[i2s_num]->conf.tx_reset = 0;
     I2S[i2s_num]->conf.rx_reset = 1;
     I2S[i2s_num]->conf.rx_reset = 0;
 
-
     //reset dma
     I2S[i2s_num]->lc_conf.in_rst = 1;
     I2S[i2s_num]->lc_conf.in_rst = 0;
     I2S[i2s_num]->lc_conf.out_rst = 1;
     I2S[i2s_num]->lc_conf.out_rst = 0;
 
-
     //Enable and configure DMA
     I2S[i2s_num]->lc_conf.check_owner = 0;
     I2S[i2s_num]->lc_conf.out_loop_test = 0;
@@ -861,7 +876,6 @@ static esp_err_t i2s_param_config(i2s_port_t i2s_num, const i2s_config_t *i2s_co
     I2S[i2s_num]->lc_conf.indscr_burst_en = 0;
     I2S[i2s_num]->lc_conf.out_eof_mode = 1;
 
-
     I2S[i2s_num]->conf2.lcd_en = 0;
     I2S[i2s_num]->conf2.camera_en = 0;
     I2S[i2s_num]->pdm_conf.pcm2pdm_conv_en = 0;
@@ -905,9 +919,10 @@ static esp_err_t i2s_param_config(i2s_port_t i2s_num, const i2s_config_t *i2s_co
         }
     }
 
-    if (i2s_config->mode & I2S_MODE_DAC_BUILT_IN) {
+    if (i2s_config->mode & (I2S_MODE_DAC_BUILT_IN | I2S_MODE_ADC_BUILT_IN)) {
         I2S[i2s_num]->conf2.lcd_en = 1;
         I2S[i2s_num]->conf.tx_right_first = 1;
+        I2S[i2s_num]->conf2.camera_en = 0;
     }
 
     if (i2s_config->mode & I2S_MODE_PDM) {
@@ -1029,7 +1044,12 @@ esp_err_t i2s_driver_install(i2s_port_t i2s_num, const i2s_config_t *i2s_config,
             return err;
         }
         i2s_stop(i2s_num);
-        i2s_param_config(i2s_num, i2s_config);
+        err = i2s_param_config(i2s_num, i2s_config);
+        if (err != ESP_OK) {
+            i2s_driver_uninstall(i2s_num);
+            ESP_LOGE(I2S_TAG, "I2S param configure error");
+            return err;
+        }
 
         if (i2s_queue) {
             p_i2s_obj[i2s_num]->i2s_queue = xQueueCreate(queue_size, sizeof(i2s_event_t));

components/driver/include/driver/adc.h

@@ -20,24 +20,38 @@ extern "C" {
 #endif
 
 #include <stdint.h>
+#include <stdbool.h>
 #include "esp_err.h"
 #include "driver/gpio.h"
 #include "soc/adc_channel.h"
 
 typedef enum {
-    ADC_ATTEN_0db   = 0,  /*!<The input voltage of ADC will be reduced to about 1/1 */
-    ADC_ATTEN_2_5db = 1,  /*!<The input voltage of ADC will be reduced to about 1/1.34 */
-    ADC_ATTEN_6db   = 2,  /*!<The input voltage of ADC will be reduced to about 1/2 */
-    ADC_ATTEN_11db  = 3,  /*!<The input voltage of ADC will be reduced to about 1/3.6*/
+    ADC_ATTEN_DB_0   = 0,  /*!<The input voltage of ADC will be reduced to about 1/1 */
+    ADC_ATTEN_DB_2_5 = 1,  /*!<The input voltage of ADC will be reduced to about 1/1.34 */
+    ADC_ATTEN_DB_6   = 2,  /*!<The input voltage of ADC will be reduced to about 1/2 */
+    ADC_ATTEN_DB_11  = 3,  /*!<The input voltage of ADC will be reduced to about 1/3.6*/
+    ADC_ATTEN_MAX,
 } adc_atten_t;
 
 typedef enum {
-    ADC_WIDTH_9Bit  = 0, /*!< ADC capture width is 9Bit*/
-    ADC_WIDTH_10Bit = 1, /*!< ADC capture width is 10Bit*/
-    ADC_WIDTH_11Bit = 2, /*!< ADC capture width is 11Bit*/
-    ADC_WIDTH_12Bit = 3, /*!< ADC capture width is 12Bit*/
+    ADC_WIDTH_BIT_9  = 0, /*!< ADC capture width is 9Bit*/
+    ADC_WIDTH_BIT_10 = 1, /*!< ADC capture width is 10Bit*/
+    ADC_WIDTH_BIT_11 = 2, /*!< ADC capture width is 11Bit*/
+    ADC_WIDTH_BIT_12 = 3, /*!< ADC capture width is 12Bit*/
+    ADC_WIDTH_MAX,
 } adc_bits_width_t;
 
+//this definitions are only for being back-compatible
+#define ADC_ATTEN_0db   ADC_ATTEN_DB_0
+#define ADC_ATTEN_2_5db ADC_ATTEN_DB_2_5
+#define ADC_ATTEN_6db   ADC_ATTEN_DB_6
+#define ADC_ATTEN_11db  ADC_ATTEN_DB_11
+//this definitions are only for being back-compatible
+#define ADC_WIDTH_9Bit  ADC_WIDTH_BIT_9
+#define ADC_WIDTH_10Bit ADC_WIDTH_BIT_10
+#define ADC_WIDTH_11Bit ADC_WIDTH_BIT_11
+#define ADC_WIDTH_12Bit ADC_WIDTH_BIT_12
+
 typedef enum {
     ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO36 */
     ADC1_CHANNEL_1,     /*!< ADC1 channel 1 is GPIO37 */
@@ -64,11 +78,43 @@ typedef enum {
     ADC2_CHANNEL_MAX,
 } adc2_channel_t;
 
+typedef enum {
+    ADC_CHANNEL_0 = 0, /*!< ADC channel */
+    ADC_CHANNEL_1,     /*!< ADC channel */
+    ADC_CHANNEL_2,     /*!< ADC channel */
+    ADC_CHANNEL_3,     /*!< ADC channel */
+    ADC_CHANNEL_4,     /*!< ADC channel */
+    ADC_CHANNEL_5,     /*!< ADC channel */
+    ADC_CHANNEL_6,     /*!< ADC channel */
+    ADC_CHANNEL_7,     /*!< ADC channel */
+    ADC_CHANNEL_8,     /*!< ADC channel */
+    ADC_CHANNEL_9,     /*!< ADC channel */
+    ADC_CHANNEL_MAX,
+} adc_channel_t;
+
+typedef enum {
+    ADC_UNIT_1 = 1,          /*!< SAR ADC 1*/
+    ADC_UNIT_2 = 2,          /*!< SAR ADC 2, not supported yet*/
+    ADC_UNIT_BOTH = 3,       /*!< SAR ADC 1 and 2, not supported yet */
+    ADC_UNIT_ALTER = 7,      /*!< SAR ADC 1 and 2 alternative mode, not supported yet */
+    ADC_UNIT_MAX,
+} adc_unit_t;
+
+typedef enum {
+    ADC_ENCODE_12BIT,        /*!< ADC to I2S data format, [15:12]-channel [11:0]-12 bits ADC data */
+    ADC_ENCODE_11BIT,        /*!< ADC to I2S data format, [15]-1 [14:11]-channel [10:0]-11 bits ADC data */
+    ADC_ENCODE_MAX,
+} adc_i2s_encode_t;
+
+typedef enum {
+    ADC_I2S_DATA_SRC_IO_SIG = 0, /*!< I2S data from GPIO matrix signal  */
+    ADC_I2S_DATA_SRC_ADC = 1,    /*!< I2S data from ADC */
+    ADC_I2S_DATA_SRC_MAX,
+} adc_i2s_source_t;
+
 /**
- * @brief Configure ADC1 capture width.
- *
+ * @brief Configure ADC1 capture width, meanwhile enable output invert for ADC1.
  * The configuration is for all channels of ADC1
- *
  * @param width_bit Bit capture width for ADC1
  *
  * @return
@@ -77,6 +123,16 @@ typedef enum {
  */
 esp_err_t adc1_config_width(adc_bits_width_t width_bit);
 
+/**
+ * @brief Configure ADC capture width.
+ * @param adc_unit ADC unit index
+ * @param width_bit Bit capture width for ADC unit.
+ * @return
+ *     - ESP_OK success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t adc_set_data_width(adc_unit_t adc_unit, adc_bits_width_t width_bit);
+
 /**
  * @brief Configure the ADC1 channel, including setting attenuation.
  *
@@ -89,10 +145,10 @@ esp_err_t adc1_config_width(adc_bits_width_t width_bit);
  *
  * When VDD_A is 3.3V:
  *
- * - 0dB attenuaton (ADC_ATTEN_0db) gives full-scale voltage 1.1V
- * - 2.5dB attenuation (ADC_ATTEN_2_5db) gives full-scale voltage 1.5V
- * - 6dB attenuation (ADC_ATTEN_6db) gives full-scale voltage 2.2V
- * - 11dB attenuation (ADC_ATTEN_11db) gives full-scale voltage 3.9V (see note below)
+ * - 0dB attenuaton (ADC_ATTEN_DB_0) gives full-scale voltage 1.1V
+ * - 2.5dB attenuation (ADC_ATTEN_DB_2_5) gives full-scale voltage 1.5V
+ * - 6dB attenuation (ADC_ATTEN_DB_6) gives full-scale voltage 2.2V
+ * - 11dB attenuation (ADC_ATTEN_DB_11) gives full-scale voltage 3.9V (see note below)
  *
  * @note The full-scale voltage is the voltage corresponding to a maximum reading (depending on ADC1 configured
  * bit width, this value is: 4095 for 12-bits, 2047 for 11-bits, 1023 for 10-bits, 511 for 9 bits.)
@@ -134,6 +190,62 @@ int adc1_get_raw(adc1_channel_t channel);
 int adc1_get_voltage(adc1_channel_t channel) __attribute__((deprecated));
 /** @endcond */
 
+/**
+ * @brief Power on SAR ADC
+ */
+void adc_power_on();
+
+/**
+ * @brief Power off SAR ADC
+ */
+void adc_power_off();
+
+/**
+ * @brief Initialize ADC pad
+ * @param adc_unit ADC unit index
+ * @param channel ADC channel index
+ * @return
+ *     - ESP_OK success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t adc_gpio_init(adc_unit_t adc_unit, adc_channel_t channel);
+
+/**
+ * @brief Set ADC data invert
+ * @param adc_unit ADC unit index
+ * @param inv_en whether enable data invert
+ * @return
+ *     - ESP_OK success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t adc_set_data_inv(adc_unit_t adc_unit, bool inv_en);
+
+/**
+ * @brief Set ADC source clock
+ * @param clk_div ADC clock divider, ADC clock is divided from APB clock
+ * @return
+ *     - ESP_OK success
+ */
+esp_err_t adc_set_clk_div(uint8_t clk_div);
+
+/**
+ * @brief Set I2S data source
+ * @param src I2S DMA data source, I2S DMA can get data from digital signals or from ADC.
+ * @return
+ *     - ESP_OK success
+ */
+esp_err_t adc_set_i2s_data_source(adc_i2s_source_t src);
+
+/**
+ * @brief Initialize I2S ADC mode
+ * @param adc_unit ADC unit index
+ * @param channel ADC channel index
+ * @return
+ *     - ESP_OK success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t adc_i2s_mode_init(adc_unit_t adc_unit, adc_channel_t channel);
+
 /**
  * @brief Configure ADC1 to be usable by the ULP
  *

components/driver/include/driver/i2s.h

@@ -26,6 +26,7 @@
 #include "esp_attr.h"
 #include "esp_intr_alloc.h"
 #include "driver/periph_ctrl.h"
+#include "driver/adc.h"
 #include "freertos/semphr.h"
 
 #ifdef __cplusplus
@@ -118,7 +119,7 @@ typedef enum {
     I2S_MODE_TX = 4,
     I2S_MODE_RX = 8,
     I2S_MODE_DAC_BUILT_IN = 16,       /*!< Output I2S data to built-in DAC, no matter the data format is 16bit or 32 bit, the DAC module will only take the 8bits from MSB*/
-    //I2S_MODE_ADC_BUILT_IN = 32,     /*!< Currently not supported yet, will be added for the next version*/
+    I2S_MODE_ADC_BUILT_IN = 32,       /*!< Input I2S data from built-in ADC, each data can be 12-bit width at most*/
     I2S_MODE_PDM = 64,
 } i2s_mode_t;
 
@@ -405,6 +406,17 @@ esp_err_t i2s_zero_dma_buffer(i2s_port_t i2s_num);
  */
 esp_err_t i2s_set_clk(i2s_port_t i2s_num, uint32_t rate, i2s_bits_per_sample_t bits, i2s_channel_t ch);
 
+/**
+ * @brief Set built-in ADC mode for I2S DMA, this function will initialize ADC pad,
+ *        and set ADC parameters.
+ * @param adc_unit  SAR ADC unit index
+ * @param adc_channel ADC channel index
+ * @return
+ *     - ESP_OK   Success
+ *     - ESP_FAIL Parameter error
+ */
+esp_err_t i2s_set_adc_mode(adc_unit_t adc_unit, adc1_channel_t adc_channel);
+
 #ifdef __cplusplus
 }
 #endif