refactor(soc/host): Update USB OTG struct fields

This commit updates the "*_struct.h" files for the USB OTG peripheral:

- Added/removed some missing/non-existing register fields
- Added "reserved" place holders for registers that are missing due to IP
configuration.
- Added "usb_dwc_cfg.h" listing the USB OTG IP configuration for each target.
- Updated LL/HAL according to register field updates. Also tidied up the include
directives in those headers.

Author: Dazza0

components/hal/include/hal/usb_dwc_hal.h

@@ -6,21 +6,22 @@
 
 #pragma once
 
-#ifdef __cplusplus
-extern "C" {
-#endif
-
+#include "soc/soc_caps.h"
 /*
-NOTE: Thread safety is the responsibility fo the HAL user. All USB Host HAL
-      functions must be called from critical sections unless specified otherwise
+This header is shared across all targets. Resolve to an empty header for targets
+that don't support USB OTG.
 */
-
-#include <stdlib.h>
-#include <stddef.h>
-#include "soc/usb_dwc_struct.h"
+#if SOC_USB_OTG_SUPPORTED
+#include <stdint.h>
+#include <stdbool.h>
 #include "hal/usb_dwc_ll.h"
 #include "hal/usb_dwc_types.h"
 #include "hal/assert.h"
+#endif // SOC_USB_OTG_SUPPORTED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
 
 #if SOC_USB_OTG_SUPPORTED
 

components/hal/include/hal/usb_dwc_ll.h

@@ -6,16 +6,25 @@
 
 #pragma once
 
-#ifdef __cplusplus
-extern "C" {
-#endif
-
+#include "soc/soc_caps.h"
+/*
+This header is shared across all targets. Resolve to an empty header for targets
+that don't support USB OTG.
+*/
+#if SOC_USB_OTG_SUPPORTED
 #include <stdint.h>
 #include <stdbool.h>
 #include "soc/usb_dwc_struct.h"
+#include "soc/usb_dwc_cfg.h"
 #include "hal/usb_dwc_types.h"
 #include "hal/misc.h"
+#endif // SOC_USB_OTG_SUPPORTED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
 
+#if SOC_USB_OTG_SUPPORTED
 
 /* -----------------------------------------------------------------------------
 --------------------------------- DWC Constants --------------------------------
@@ -853,28 +862,48 @@ static inline uint32_t usb_dwc_ll_hctsiz_get_pid(volatile usb_dwc_host_chan_regs
 
 static inline void usb_dwc_ll_hctsiz_set_qtd_list_len(volatile usb_dwc_host_chan_regs_t *chan, int qtd_list_len)
 {
-    HAL_FORCE_MODIFY_U32_REG_FIELD(chan->hctsiz_reg, ntd, qtd_list_len - 1);    //Set the length of the descriptor list
+    usb_dwc_hctsiz_reg_t hctsiz;
+    hctsiz.val = chan->hctsiz_reg.val;
+    //Set the length of the descriptor list. NTD occupies xfersize[15:8]
+    hctsiz.xfersize &= ~(0xFF << 8);
+    hctsiz.xfersize |= ((qtd_list_len - 1) & 0xFF) << 8;
+    chan->hctsiz_reg.val = hctsiz.val;
 }
 
 static inline void usb_dwc_ll_hctsiz_init(volatile usb_dwc_host_chan_regs_t *chan)
 {
-    chan->hctsiz_reg.dopng = 0;         //Don't do ping
-    HAL_FORCE_MODIFY_U32_REG_FIELD(chan->hctsiz_reg, sched_info, 0xFF); //Schedinfo is always 0xFF for fullspeed. Not used in Bulk/Ctrl channels
+    usb_dwc_hctsiz_reg_t hctsiz;
+    hctsiz.val = chan->hctsiz_reg.val;
+    hctsiz.dopng = 0;         //Don't do ping
+    /*
+    Set SCHED_INFO which occupies xfersize[7:0]
+    It is always set to 0xFF for full speed and not used in Bulk/Ctrl channels
+    */
+    hctsiz.xfersize |= 0xFF;
+    chan->hctsiz_reg.val = hctsiz.val;
 }
 
 // ---------------------------- HCDMAi Register --------------------------------
 
 static inline void usb_dwc_ll_hcdma_set_qtd_list_addr(volatile usb_dwc_host_chan_regs_t *chan, void *dmaaddr, uint32_t qtd_idx)
 {
-    //Set HCDMAi
-    chan->hcdma_reg.val = 0;
-    chan->hcdma_reg.non_iso.dmaaddr = (((uint32_t)dmaaddr) >> 9) & 0x7FFFFF;  //MSB of 512 byte aligned address
-    chan->hcdma_reg.non_iso.ctd = qtd_idx;
+    usb_dwc_hcdma_reg_t hcdma;
+    /*
+    Set the base address portion of the field which is dmaaddr[31:9]. This is
+    the based address of the QTD list and must be 512 bytes aligned
+    */
+    hcdma.dmaaddr = ((uint32_t)dmaaddr) & 0xFFFFFE00;
+    //Set the current QTD index in the QTD list which is dmaaddr[8:3]
+    hcdma.dmaaddr |= (qtd_idx & 0x3F) << 3;
+    //dmaaddr[2:0] is reserved thus doesn't not need to be set
+
+    chan->hcdma_reg.val = hcdma.val;
 }
 
 static inline int usb_dwc_ll_hcdam_get_cur_qtd_idx(usb_dwc_host_chan_regs_t *chan)
 {
-    return chan->hcdma_reg.non_iso.ctd;
+    //The current QTD index is dmaaddr[8:3]
+    return (chan->hcdma_reg.dmaaddr >> 3) & 0x3F;
 }
 
 // ---------------------------- HCDMABi Register -------------------------------
@@ -994,6 +1023,8 @@ static inline void usb_dwc_ll_qtd_get_status(usb_dwc_ll_dma_qtd_t *qtd, int *rem
     qtd->buffer_status_val = 0;
 }
 
+#endif // SOC_USB_OTG_SUPPORTED
+
 #ifdef __cplusplus
 }
 #endif

components/hal/usb_dwc_hal.c

@@ -9,9 +9,9 @@
 #include <string.h>
 #include "sdkconfig.h"
 #include "soc/chip_revision.h"
-#include "hal/efuse_hal.h"
 #include "hal/usb_dwc_hal.h"
 #include "hal/usb_dwc_ll.h"
+#include "hal/efuse_hal.h"
 #include "hal/assert.h"
 
 // ------------------------------------------------ Macros and Types ---------------------------------------------------

components/soc/esp32s2/include/soc/usb_dwc_cfg.h

@@ -0,0 +1,89 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+Configuration Set ID: 1
+*/
+
+/* 3.1 Basic Config Parameters */
+#define OTG_MODE                0
+#define OTG_ARCHITECTURE        2
+#define OTG_SINGLE_POINT        1
+#define OTG_ENABLE_LPM          0
+#define OTG_EN_DED_TX_FIFO      1
+#define OTG_EN_DESC_DMA         1
+#define OTG_MULTI_PROC_INTRPT   0
+
+/* 3.2 USB Physical Layer Interface Parameters */
+#define OTG_HSPHY_INTERFACE     0
+#define OTG_FSPHY_INTERFACE     1
+#define OTG_ENABLE_IC_USB       0
+#define OTG_I2C_INTERFACE       0
+#define OTG_ADP_SUPPORT         0
+#define OTG_BC_SUPPORT          0
+
+/* 3.3 Device Endpoint Configuration Parameters */
+#define OTG_NUM_EPS         6
+#define OTG_NUM_IN_EPS      5
+#define OTG_NUM_CRL_EPS     0
+
+/* 3.4 Host Endpoint Configuration Parameters */
+#define OTG_NUM_HOST_CHAN   8
+#define OTG_EN_PERIO_HOST   1
+
+/* 3.5 Endpoint Channel FIFO Configuration Parameters */
+#define OTG_DFIFO_DEPTH             256
+#define OTG_DFIFO_DYNAMIC           1
+#define OTG_RX_DFIFO_DEPTH          256
+#define OTG_TX_HNPERIO_DFIFO_DEPTH  256
+#define OTG_TX_NPERIO_DFIFO_DEPTH   256
+#define OTG_TX_HPERIO_DFIFO_DEPTH   256
+#define OTG_NPERIO_TX_QUEUE_DEPTH   4
+#define OTG_PERIO_TX_QUEUE_DEPTH    8
+
+/* 3.6 Additional Configuration Options Parameters */
+#define OTG_TRANS_COUNT_WIDTH       16
+#define OTG_PACKET_COUNT_WIDTH      7
+#define OTG_RM_OPT_FEATURES         1
+#define OTG_EN_PWROPT               1
+#define OTG_SYNC_RESET_TYPE         0
+#define OTG_EN_IDDIG_FILTER         1
+#define OTG_EN_VBUSVALID_FILTER     1
+#define OTG_EN_A_VALID_FILTER       1
+#define OTG_EN_B_VALID_FILTER       1
+#define OTG_EN_SESSIONEND_FILTER    1
+#define OTG_EXCP_CNTL_XFER_FLOW     1
+#define OTG_PWR_CLAMP               0
+#define OTG_PWR_SWITCH_POLARITY     0
+
+/* 3.7 Endpoint Direction Parameters */
+#define OTG_EP_DIR_1    0
+#define OTG_EP_DIR_2    0
+#define OTG_EP_DIR_3    0
+#define OTG_EP_DIR_4    0
+#define OTG_EP_DIR_5    0
+#define OTG_EP_DIR_6    0
+
+/* 3.8 Device Periodic FIFO Depth Parameters */
+
+/* 3.9 Device IN Endpoint FIFO Depth Parameters */
+#define OTG_TX_DINEP_DFIFO_DEPTH_1  256
+#define OTG_TX_DINEP_DFIFO_DEPTH_2  256
+#define OTG_TX_DINEP_DFIFO_DEPTH_3  256
+#define OTG_TX_DINEP_DFIFO_DEPTH_4  256
+
+/* 3.10 UTMI-To-UTMI Bridge Component Parameters */
+#define U2UB_EN     0
+
+#ifdef __cplusplus
+}
+#endif