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Merge branch 'feature/ulp_i2c_reg' into 'master'
 soc,ulp: add register definitions of RTC_I2C peripheral See merge request !1762
2 parents 16391c2 + dba2914 commit 914ab07

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‎components/soc/esp32/include/soc/rtc_i2c_reg.h

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// Copyright 2016-2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include "soc.h"
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/**
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* This file lists peripheral registers of an I2C controller which is part of the RTC.
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* ULP coprocessor uses this controller to implement I2C_RD and I2C_WR instructions.
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*
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* Part of the functionality of this controller (such as slave mode, and multi-byte
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* transfers) is not wired to the ULP, and is such, is not available to the
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* ULP programs.
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*/
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#define RTC_I2C_SCL_LOW_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x000)
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/* RTC_I2C_SCL_LOW_PERIOD : R/W ;bitpos:[18:0] ;default: 19'b0 ; */
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/*description: number of cycles that scl == 0 */
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#define RTC_I2C_SCL_LOW_PERIOD 0x1FFFFFF
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#define RTC_I2C_SCL_LOW_PERIOD_M ((RTC_I2C_SCL_LOW_PERIOD_V)<<(RTC_I2C_SCL_LOW_PERIOD_S))
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#define RTC_I2C_SCL_LOW_PERIOD_V 0x1FFFFFF
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#define RTC_I2C_SCL_LOW_PERIOD_S 0
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#define RTC_I2C_CTRL_REG (DR_REG_RTC_I2C_BASE + 0x004)
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/* RTC_I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'b0 ; */
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/*description: Send LSB first */
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#define RTC_I2C_RX_LSB_FIRST BIT(7)
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#define RTC_I2C_RX_LSB_FIRST_M BIT(7)
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#define RTC_I2C_RX_LSB_FIRST_V (1)
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#define RTC_I2C_RX_LSB_FIRST_S (7)
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/* RTC_I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */
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/*description: Receive LSB first */
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#define RTC_I2C_TX_LSB_FIRST BIT(6)
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#define RTC_I2C_TX_LSB_FIRST_M BIT(6)
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#define RTC_I2C_TX_LSB_FIRST_V (1)
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#define RTC_I2C_TX_LSB_FIRST_S (6)
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/* RTC_I2C_TRANS_START : R/W ;bitpos:[5] ;default: 1'b0 ; */
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/*description: Force to generate start condition */
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#define RTC_I2C_TRANS_START BIT(5)
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#define RTC_I2C_TRANS_START_M BIT(5)
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#define RTC_I2C_TRANS_START_V (1)
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#define RTC_I2C_TRANS_START_S (5)
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/* RTC_I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */
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/*description: Master (1) or slave (0) */
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#define RTC_I2C_MS_MODE BIT(4)
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#define RTC_I2C_MS_MODE_M BIT(4)
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#define RTC_I2C_MS_MODE_V (1)
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#define RTC_I2C_MS_MODE_S (4)
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/* RTC_I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */
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/*description: SCL is push-pull (1) or open-drain (0) */
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#define RTC_I2C_SCL_FORCE_OUT BIT(1)
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#define RTC_I2C_SCL_FORCE_OUT_M BIT(1)
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#define RTC_I2C_SCL_FORCE_OUT_V (1)
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#define RTC_I2C_SCL_FORCE_OUT_S (1)
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/* RTC_I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b0 ; */
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/*description: SDA is push-pull (1) or open-drain (0) */
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#define RTC_I2C_SDA_FORCE_OUT BIT(0)
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#define RTC_I2C_SDA_FORCE_OUT_M BIT(0)
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#define RTC_I2C_SDA_FORCE_OUT_V (1)
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#define RTC_I2C_SDA_FORCE_OUT_S (0)
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#define RTC_I2C_DEBUG_STATUS_REG (DR_REG_RTC_I2C_BASE + 0x008)
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/* RTC_I2C_SCL_STATE : R/W ;bitpos:[30:28] ;default: 3'b0 ; */
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/*description: state of SCL state machine */
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#define RTC_I2C_SCL_STATE 0x7
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#define RTC_I2C_SCL_STATE_M ((RTC_I2C_SCL_STATE_V)<<(RTC_I2C_SCL_STATE_S))
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#define RTC_I2C_SCL_STATE_V 0x7
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#define RTC_I2C_SCL_STATE_S 28
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/* RTC_I2C_MAIN_STATE : R/W ;bitpos:[27:25] ;default: 3'b0 ; */
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/*description: state of the main state machine */
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#define RTC_I2C_MAIN_STATE 0x7
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#define RTC_I2C_MAIN_STATE_M ((RTC_I2C_MAIN_STATE_V)<<(RTC_I2C_MAIN_STATE_S))
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#define RTC_I2C_MAIN_STATE_V 0x7
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#define RTC_I2C_MAIN_STATE_S 25
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/* RTC_I2C_BYTE_TRANS : R/W ;bitpos:[6] ;default: 1'b0 ; */
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/*description: 8 bit transmit done */
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#define RTC_I2C_BYTE_TRANS BIT(6)
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#define RTC_I2C_BYTE_TRANS_M BIT(6)
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#define RTC_I2C_BYTE_TRANS_V (1)
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#define RTC_I2C_BYTE_TRANS_S (6)
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/* RTC_I2C_SLAVE_ADDR_MATCH : R/W ;bitpos:[5] ;default: 1'b0 ; */
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/*description: When working as a slave, whether address was matched */
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#define RTC_I2C_SLAVE_ADDR_MATCH BIT(5)
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#define RTC_I2C_SLAVE_ADDR_MATCH_M BIT(5)
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#define RTC_I2C_SLAVE_ADDR_MATCH_V (1)
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#define RTC_I2C_SLAVE_ADDR_MATCH_S (5)
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/* RTC_I2C_BUS_BUSY : R/W ;bitpos:[4] ;default: 1'b0 ; */
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/*description: operation is in progress */
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#define RTC_I2C_BUS_BUSY BIT(4)
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#define RTC_I2C_BUS_BUSY_M BIT(4)
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#define RTC_I2C_BUS_BUSY_V (1)
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#define RTC_I2C_BUS_BUSY_S (4)
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/* RTC_I2C_ARB_LOST : R/W ;bitpos:[3] ;default: 1'b0 ; */
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/*description: When working as a master, lost control of I2C bus */
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#define RTC_I2C_ARB_LOST BIT(3)
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#define RTC_I2C_ARB_LOST_M BIT(3)
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#define RTC_I2C_ARB_LOST_V (1)
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#define RTC_I2C_ARB_LOST_S (3)
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/* RTC_I2C_TIMED_OUT : R/W ;bitpos:[2] ;default: 1'b0 ; */
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/*description: Transfer has timed out */
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#define RTC_I2C_TIMED_OUT BIT(2)
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#define RTC_I2C_TIMED_OUT_M BIT(2)
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#define RTC_I2C_TIMED_OUT_V (1)
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#define RTC_I2C_TIMED_OUT_S (2)
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/* RTC_I2C_SLAVE_RW : R/W ;bitpos:[1] ;default: 1'b0 ; */
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/*description: When working as a slave, the value of R/W bit received */
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#define RTC_I2C_SLAVE_RW BIT(1)
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#define RTC_I2C_SLAVE_RW_M BIT(1)
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#define RTC_I2C_SLAVE_RW_V (1)
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#define RTC_I2C_SLAVE_RW_S (1)
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/* RTC_I2C_ACK_VAL : R/W ;bitpos:[0] ;default: 1'b0 ; */
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/*description: The value of an acknowledge signal on the bus */
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#define RTC_I2C_ACK_VAL BIT(0)
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#define RTC_I2C_ACK_VAL_M BIT(0)
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#define RTC_I2C_ACK_VAL_V (1)
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#define RTC_I2C_ACK_VAL_S (0)
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#define RTC_I2C_TIMEOUT_REG (DR_REG_RTC_I2C_BASE + 0x00c)
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/* RTC_I2C_TIMEOUT : R/W ;bitpos:[19:0] ;default: 20'b0 ; */
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/*description: Maximum number of FAST_CLK cycles that the transmission can take */
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#define RTC_I2C_TIMEOUT 0xFFFFF
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#define RTC_I2C_TIMEOUT_M ((RTC_I2C_TIMEOUT_V)<<(RTC_I2C_TIMEOUT_S))
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#define RTC_I2C_TIMEOUT_V 0xFFFFF
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#define RTC_I2C_TIMEOUT_S 0
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#define RTC_I2C_SLAVE_ADDR_REG (DR_REG_RTC_I2C_BASE + 0x010)
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/* RTC_I2C_SLAVE_ADDR_10BIT : R/W ;bitpos:[31] ;default: 1'b0 ; */
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/*description: Set if local slave address is 10-bit */
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#define RTC_I2C_SLAVE_ADDR_10BIT BIT(31)
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#define RTC_I2C_SLAVE_ADDR_10BIT_M BIT(31)
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#define RTC_I2C_SLAVE_ADDR_10BIT_V (1)
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#define RTC_I2C_SLAVE_ADDR_10BIT_S (31)
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/* RTC_I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */
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/*description: local slave address */
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#define RTC_I2C_SLAVE_ADDR 0x7FFF
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#define RTC_I2C_SLAVE_ADDR_M ((RTC_I2C_SLAVE_ADDR_V)<<(RTC_I2C_SLAVE_ADDR_S))
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#define RTC_I2C_SLAVE_ADDR_V 0x7FFF
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#define RTC_I2C_SLAVE_ADDR_S 0
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/* Result of last read operation. Not used directly as the data will be
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* returned to the ULP. Listed for debugging purposes.
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*/
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#define RTC_I2C_DATA_REG (DR_REG_RTC_I2C_BASE + 0x01c)
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/* Interrupt registers; since the interrupt from RTC_I2C is not connected,
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* these registers are only listed for debugging purposes.
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*/
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/* Interrupt raw status register */
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#define RTC_I2C_INT_RAW_REG (DR_REG_RTC_I2C_BASE + 0x020)
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/* RTC_I2C_TIME_OUT_INT_RAW : R/O ;bitpos:[7] ;default: 1'b0 ; */
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/*description: time out interrupt raw status */
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#define RTC_I2C_TIME_OUT_INT_RAW BIT(7)
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#define RTC_I2C_TIME_OUT_INT_RAW_M BIT(7)
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#define RTC_I2C_TIME_OUT_INT_RAW_V (1)
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#define RTC_I2C_TIME_OUT_INT_RAW_S (7)
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/* RTC_I2C_TRANS_COMPLETE_INT_RAW : R/W ;bitpos:[6] ;default: 1'b0 ; */
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/*description: Stop condition has been detected interrupt raw status */
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#define RTC_I2C_TRANS_COMPLETE_INT_RAW BIT(6)
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#define RTC_I2C_TRANS_COMPLETE_INT_RAW_M BIT(6)
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#define RTC_I2C_TRANS_COMPLETE_INT_RAW_V (1)
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#define RTC_I2C_TRANS_COMPLETE_INT_RAW_S (6)
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/* RTC_I2C_MASTER_TRANS_COMPLETE_INT_RAW : R/W ;bitpos:[5] ;default: 1'b0 ; */
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/*description: */
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#define RTC_I2C_MASTER_TRANS_COMPLETE_INT_RAW BIT(5)
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#define RTC_I2C_MASTER_TRANS_COMPLETE_INT_RAW_M BIT(5)
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#define RTC_I2C_MASTER_TRANS_COMPLETE_INT_RAW_V (1)
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#define RTC_I2C_MASTER_TRANS_COMPLETE_INT_RAW_S (5)
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/* RTC_I2C_ARBITRATION_LOST_INT_RAW : R/W ;bitpos:[4] ;default: 1'b0 ; */
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/*description: Master lost arbitration */
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#define RTC_I2C_ARBITRATION_LOST_INT_RAW BIT(4)
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#define RTC_I2C_ARBITRATION_LOST_INT_RAW_M BIT(4)
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#define RTC_I2C_ARBITRATION_LOST_INT_RAW_V (1)
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#define RTC_I2C_ARBITRATION_LOST_INT_RAW_S (4)
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/* RTC_I2C_SLAVE_TRANS_COMPLETE_INT_RAW : R/W ;bitpos:[3] ;default: 1'b0 ; */
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/*description: Slave accepted 1 byte and address matched */
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#define RTC_I2C_SLAVE_TRANS_COMPLETE_INT_RAW BIT(3)
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#define RTC_I2C_SLAVE_TRANS_COMPLETE_INT_RAW_M BIT(3)
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#define RTC_I2C_SLAVE_TRANS_COMPLETE_INT_RAW_V (1)
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#define RTC_I2C_SLAVE_TRANS_COMPLETE_INT_RAW_S (3)
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/* Interrupt clear register */
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#define RTC_I2C_INT_CLR_REG (DR_REG_RTC_I2C_BASE + 0x024)
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/* RTC_I2C_TIME_OUT_INT_CLR : W/O ;bitpos:[8] ;default: 1'b0 ; */
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/*description: */
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#define RTC_I2C_TIME_OUT_INT_CLR BIT(8)
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#define RTC_I2C_TIME_OUT_INT_CLR_M BIT(8)
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#define RTC_I2C_TIME_OUT_INT_CLR_V (1)
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#define RTC_I2C_TIME_OUT_INT_CLR_S (8)
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/* RTC_I2C_TRANS_COMPLETE_INT_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */
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/*description: */
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#define RTC_I2C_TRANS_COMPLETE_INT_CLR BIT(7)
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#define RTC_I2C_TRANS_COMPLETE_INT_CLR_M BIT(7)
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#define RTC_I2C_TRANS_COMPLETE_INT_CLR_V (1)
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#define RTC_I2C_TRANS_COMPLETE_INT_CLR_S (7)
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/* RTC_I2C_MASTER_TRANS_COMPLETE_INT_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */
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/*description: */
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#define RTC_I2C_MASTER_TRANS_COMPLETE_INT_CLR BIT(6)
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#define RTC_I2C_MASTER_TRANS_COMPLETE_INT_CLR_M BIT(6)
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#define RTC_I2C_MASTER_TRANS_COMPLETE_INT_CLR_V (1)
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#define RTC_I2C_MASTER_TRANS_COMPLETE_INT_CLR_S (6)
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/* RTC_I2C_ARBITRATION_LOST_INT_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */
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/*description: */
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#define RTC_I2C_ARBITRATION_LOST_INT_CLR BIT(5)
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#define RTC_I2C_ARBITRATION_LOST_INT_CLR_M BIT(5)
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#define RTC_I2C_ARBITRATION_LOST_INT_CLR_V (1)
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#define RTC_I2C_ARBITRATION_LOST_INT_CLR_S (5)
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/* RTC_I2C_SLAVE_TRANS_COMPLETE_INT_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
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/*description: */
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#define RTC_I2C_SLAVE_TRANS_COMPLETE_INT_CLR BIT(4)
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#define RTC_I2C_SLAVE_TRANS_COMPLETE_INT_CLR_M BIT(4)
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#define RTC_I2C_SLAVE_TRANS_COMPLETE_INT_CLR_V (1)
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#define RTC_I2C_SLAVE_TRANS_COMPLETE_INT_CLR_S (4)
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/* Interrupt enable register.
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* Bit definitions are not given here, because interrupt functionality
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* of RTC_I2C is not used.
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*/
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#define RTC_I2C_INT_EN_REG (DR_REG_RTC_I2C_BASE + 0x028)
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/* Masked interrupt status register.
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* Bit definitions are not given here, because interrupt functionality
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* of RTC_I2C is not used.
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*/
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#define RTC_I2C_INT_ST_REG (DR_REG_RTC_I2C_BASE + 0x02c)
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#define RTC_I2C_SDA_DUTY_REG (DR_REG_RTC_I2C_BASE + 0x030)
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/* RTC_I2C_SDA_DUTY : R/W ;bitpos:[19:0] ;default: 20'b0 ; */
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/*description: Number of FAST_CLK cycles SDA will switch after falling edge of SCL */
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#define RTC_I2C_SDA_DUTY 0xFFFFF
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#define RTC_I2C_SDA_DUTY_M ((RTC_I2C_SDA_DUTY_V)<<(RTC_I2C_SDA_DUTY_S))
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#define RTC_I2C_SDA_DUTY_V 0xFFFFF
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#define RTC_I2C_SDA_DUTY_S 0
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#define RTC_I2C_SCL_HIGH_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x038)
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/* RTC_I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b0 ; */
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/*description: Number of FAST_CLK cycles for SCL to be high */
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#define RTC_I2C_SCL_HIGH_PERIOD 0xFFFFF
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#define RTC_I2C_SCL_HIGH_PERIOD_M ((RTC_I2C_SCL_HIGH_PERIOD_V)<<(RTC_I2C_SCL_HIGH_PERIOD_S))
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#define RTC_I2C_SCL_HIGH_PERIOD_V 0xFFFFF
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#define RTC_I2C_SCL_HIGH_PERIOD_S 0
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#define RTC_I2C_SCL_START_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x040)
256+
/* RTC_I2C_SCL_START_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b0 ; */
257+
/*description: Number of FAST_CLK cycles to wait before generating start condition */
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#define RTC_I2C_SCL_START_PERIOD 0xFFFFF
259+
#define RTC_I2C_SCL_START_PERIOD_M ((RTC_I2C_SCL_START_PERIOD_V)<<(RTC_I2C_SCL_START_PERIOD_S))
260+
#define RTC_I2C_SCL_START_PERIOD_V 0xFFFFF
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#define RTC_I2C_SCL_START_PERIOD_S 0
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#define RTC_I2C_SCL_STOP_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x044)
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/* RTC_I2C_SCL_STOP_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b0 ; */
265+
/*description: Number of FAST_CLK cycles to wait before generating stop condition */
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#define RTC_I2C_SCL_STOP_PERIOD 0xFFFFF
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#define RTC_I2C_SCL_STOP_PERIOD_M ((RTC_I2C_SCL_STOP_PERIOD_V)<<(RTC_I2C_SCL_STOP_PERIOD_S))
268+
#define RTC_I2C_SCL_STOP_PERIOD_V 0xFFFFF
269+
#define RTC_I2C_SCL_STOP_PERIOD_S 0
270+
271+
/* A block of 16 RTC_I2C_CMD registers which describe I2C operation to be
272+
* performed. Unused when ULP is controlling RTC_I2C.
273+
*/
274+
#define RTC_I2C_CMD_REG_COUNT 16
275+
#define RTC_I2C_CMD_REG(i) (DR_REG_RTC_I2C_BASE + 0x048 + (i) * 4)
276+
/* RTC_I2C_CMD_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
277+
/*description: Bit is set by HW when command is done */
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#define RTC_I2C_CMD_DONE BIT(31)
279+
#define RTC_I2C_CMD_DONE_M BIT(31)
280+
#define RTC_I2C_CMD_DONE_V (1)
281+
#define RTC_I2C_CMD_DONE_S (31)
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/* RTC_I2C_VAL : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
283+
/*description: Command content */
284+
#define RTC_I2C_VAL 0
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#define RTC_I2C_VAL_M ((RTC_I2C_VAL_V)<<(RTC_I2C_VAL_S))
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#define RTC_I2C_VAL_V 0x3FFF
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#define RTC_I2C_VAL_S 0
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‎components/soc/esp32/include/soc/soc.h

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
// Copyright 2010-2017 Espressif Systems (Shanghai) PTE LTD
1+
// Copyright 2010-2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
44
// you may not use this file except in compliance with the License.
@@ -89,11 +89,8 @@
8989
#define DR_REG_RTCCNTL_BASE 0x3ff48000
9090
#define DR_REG_RTCIO_BASE 0x3ff48400
9191
#define DR_REG_SENS_BASE 0x3ff48800
92+
#define DR_REG_RTC_I2C_BASE 0x3ff48C00
9293
#define DR_REG_IO_MUX_BASE 0x3ff49000
93-
#define DR_REG_RTCMEM0_BASE 0x3ff61000
94-
#define DR_REG_RTCMEM1_BASE 0x3ff62000
95-
#define DR_REG_RTCMEM2_BASE 0x3ff63000
96-
#define DR_REG_SYSCON_BASE 0x3ff66000
9794
#define DR_REG_HINF_BASE 0x3ff4B000
9895
#define DR_REG_UHCI1_BASE 0x3ff4C000
9996
#define DR_REG_I2S_BASE 0x3ff4F000
@@ -113,9 +110,13 @@
113110
#define DR_REG_PWM_BASE 0x3ff5E000
114111
#define DR_REG_TIMERGROUP0_BASE 0x3ff5F000
115112
#define DR_REG_TIMERGROUP1_BASE 0x3ff60000
113+
#define DR_REG_RTCMEM0_BASE 0x3ff61000
114+
#define DR_REG_RTCMEM1_BASE 0x3ff62000
115+
#define DR_REG_RTCMEM2_BASE 0x3ff63000
116116
#define DR_REG_SPI2_BASE 0x3ff64000
117117
#define DR_REG_SPI3_BASE 0x3ff65000
118-
#define DR_REG_APB_CTRL_BASE 0x3ff66000
118+
#define DR_REG_SYSCON_BASE 0x3ff66000
119+
#define DR_REG_APB_CTRL_BASE 0x3ff66000 /* Old name for SYSCON, to be removed */
119120
#define DR_REG_I2C1_EXT_BASE 0x3ff67000
120121
#define DR_REG_SDMMC_BASE 0x3ff68000
121122
#define DR_REG_EMAC_BASE 0x3ff69000

‎components/soc/esp32/include/soc/soc_ulp.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@
2626
#define MASK_TO_WIDTH_HELPER32(m, i) (MASK_TO_WIDTH_HELPER16(m, i) + MASK_TO_WIDTH_HELPER16(m, i + 16))
2727

2828
// Peripheral register access macros, build around REG_RD and REG_WR instructions.
29-
// Registers defined in rtc_cntl_reg.h, rtc_io_reg.h, and sens_reg.h are usable with these macros.
29+
// Registers defined in rtc_cntl_reg.h, rtc_io_reg.h, sens_reg.h, and rtc_i2c_reg.h are usable with these macros.
3030

3131
// Read from rtc_reg[low_bit + bit_width - 1 : low_bit] into R0, bit_width <= 16
3232
#define READ_RTC_REG(rtc_reg, low_bit, bit_width) \

‎components/ulp/include/esp32/ulp.h

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
// Copyright 2016 Espressif Systems (Shanghai) PTE LTD
1+
// Copyright 2016-2018 Espressif Systems (Shanghai) PTE LTD
22
//
33
// Licensed under the Apache License, Version 2.0 (the "License");
44
// you may not use this file except in compliance with the License.
@@ -50,6 +50,7 @@ extern "C" {
5050
#define RD_REG_PERIPH_RTC_CNTL 0 /*!< Identifier of RTC_CNTL peripheral for RD_REG and WR_REG instructions */
5151
#define RD_REG_PERIPH_RTC_IO 1 /*!< Identifier of RTC_IO peripheral for RD_REG and WR_REG instructions */
5252
#define RD_REG_PERIPH_SENS 2 /*!< Identifier of SARADC peripheral for RD_REG and WR_REG instructions */
53+
#define RD_REG_PERIPH_RTC_I2C 3 /*!< Identifier of RTC_I2C peripheral for RD_REG and WR_REG instructions */
5354

5455
#define OPCODE_I2C 3 /*!< Instruction: read/write I2C (not implemented yet) */
5556

@@ -286,7 +287,7 @@ _Static_assert(sizeof(ulp_insn_t) == 4, "ULP coprocessor instruction size should
286287
* Map SoC peripheral register to periph_sel field of RD_REG and WR_REG
287288
* instructions.
288289
*
289-
* @param reg peripheral register in RTC_CNTL_, RTC_IO_, SENS_ peripherals.
290+
* @param reg peripheral register in RTC_CNTL_, RTC_IO_, SENS_, RTC_I2C peripherals.
290291
* @return periph_sel value for the peripheral to which this register belongs.
291292
*/
292293
static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
@@ -297,8 +298,10 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
297298
ret = RD_REG_PERIPH_RTC_CNTL;
298299
} else if (reg < DR_REG_SENS_BASE) {
299300
ret = RD_REG_PERIPH_RTC_IO;
300-
} else if (reg < DR_REG_RTCMEM0_BASE){
301+
} else if (reg < DR_REG_RTC_I2C_BASE){
301302
ret = RD_REG_PERIPH_SENS;
303+
} else if (reg < DR_REG_IO_MUX_BASE){
304+
ret = RD_REG_PERIPH_RTC_I2C;
302305
} else {
303306
assert(0 && "invalid register base");
304307
}
@@ -309,7 +312,7 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
309312
* Write literal value to a peripheral register
310313
*
311314
* reg[high_bit : low_bit] = val
312-
* This instruction can access RTC_CNTL_, RTC_IO_, and SENS_ peripheral registers.
315+
* This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers.
313316
*/
314317
#define I_WR_REG(reg, low_bit, high_bit, val) {.wr_reg = {\
315318
.addr = (reg & 0xff) / sizeof(uint32_t), \
@@ -323,7 +326,7 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
323326
* Read from peripheral register into R0
324327
*
325328
* R0 = reg[high_bit : low_bit]
326-
* This instruction can access RTC_CNTL_, RTC_IO_, and SENS_ peripheral registers.
329+
* This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers.
327330
*/
328331
#define I_RD_REG(reg, low_bit, high_bit) {.rd_reg = {\
329332
.addr = (reg & 0xff) / sizeof(uint32_t), \
@@ -337,7 +340,7 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
337340
* Set or clear a bit in the peripheral register.
338341
*
339342
* Sets bit (1 << shift) of register reg to value val.
340-
* This instruction can access RTC_CNTL_, RTC_IO_, and SENS_ peripheral registers.
343+
* This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers.
341344
*/
342345
#define I_WR_REG_BIT(reg, shift, val) I_WR_REG(reg, shift, shift, val)
343346

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