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suda-morrissuda-morris
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Merge branch 'refactor/remove_ets_sys_from_public_header' into 'master'
esp_rom: remove ets_sys.h dependency from public header files See merge request espressif/esp-idf!16919
2 parents c143090 + ef00bd5 commit 5810ed1

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50 files changed

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‎components/bootloader_support/src/bootloader_utility.c

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,6 @@
3131
#elif CONFIG_IDF_TARGET_ESP32C3
3232
#include "esp32c3/rom/cache.h"
3333
#include "esp32c3/rom/efuse.h"
34-
#include "esp32c3/rom/ets_sys.h"
3534
#include "esp32c3/rom/crc.h"
3635
#include "esp32c3/rom/uart.h"
3736
#include "esp32c3/rom/gpio.h"
@@ -41,7 +40,6 @@
4140
#elif CONFIG_IDF_TARGET_ESP32H2
4241
#include "esp32h2/rom/cache.h"
4342
#include "esp32h2/rom/efuse.h"
44-
#include "esp32h2/rom/ets_sys.h"
4543
#include "esp32h2/rom/crc.h"
4644
#include "esp32h2/rom/uart.h"
4745
#include "esp32h2/rom/gpio.h"
@@ -51,7 +49,6 @@
5149
#elif CONFIG_IDF_TARGET_ESP32C2
5250
#include "esp32c2/rom/cache.h"
5351
#include "esp32c2/rom/efuse.h"
54-
#include "esp32c2/rom/ets_sys.h"
5552
#include "esp32c2/rom/crc.h"
5653
#include "esp32c2/rom/rtc.h"
5754
#include "esp32c2/rom/uart.h"

‎components/bt/common/include/bt_common.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@
88
#define _BT_COMMON_H_
99

1010
#include <assert.h>
11+
#include <stdbool.h>
1112
#include "bt_user_config.h"
1213
#include "esp_log.h"
1314

‎components/bt/controller/esp32s3/bt.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,7 @@
3737
#include "esp_coexist_internal.h"
3838
#include "esp_timer.h"
3939
#include "esp_sleep.h"
40+
#include "esp_rom_sys.h"
4041

4142
#if CONFIG_BT_ENABLED
4243

@@ -431,7 +432,7 @@ static inline void esp_bt_power_domain_off(void)
431432

432433
static void interrupt_set_wrapper(int32_t cpu_no, int32_t intr_source, int32_t intr_num, int32_t intr_prio)
433434
{
434-
intr_matrix_set(cpu_no, intr_source, intr_num);
435+
esp_rom_route_intr_matrix(cpu_no, intr_source, intr_num);
435436
}
436437

437438
static void interrupt_clear_wrapper(int32_t intr_source, int32_t intr_num)

‎components/driver/test/test_gpio.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -171,7 +171,7 @@ static void prompt_to_continue(const char *str)
171171
char sign[5] = {0};
172172
while (strlen(sign) == 0) {
173173
/* Flush anything already in the RX buffer */
174-
while (esp_rom_uart_rx_one_char((uint8_t *) sign) == ETS_OK) {
174+
while (esp_rom_uart_rx_one_char((uint8_t *) sign) == 0) {
175175
}
176176
/* Read line */
177177
esp_rom_uart_rx_string((uint8_t *) sign, sizeof(sign) - 1);

‎components/esp_http_client/lib/http_header.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@
1010
#include <ctype.h>
1111
#include <stdio.h>
1212
#include <stdarg.h>
13+
#include <stdbool.h>
1314
#include "esp_log.h"
1415
#include "esp_check.h"
1516
#include "http_header.h"

‎components/esp_hw_support/esp_clk.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@
1212
#include "soc/rtc.h"
1313
#include "soc/soc_caps.h"
1414
#include "esp_rom_caps.h"
15+
#include "esp_rom_sys.h"
1516
#include "esp_private/esp_clk.h"
1617

1718
#if CONFIG_IDF_TARGET_ESP32
@@ -23,7 +24,6 @@
2324
#elif CONFIG_IDF_TARGET_ESP32S3
2425
#include "esp32s3/rom/rtc.h"
2526
#include "esp32s3/rtc.h"
26-
#include "esp32s3/rom/ets_sys.h"
2727
#elif CONFIG_IDF_TARGET_ESP32C3
2828
#include "esp32c3/rom/rtc.h"
2929
#include "esp32c3/rtc.h"
@@ -53,7 +53,7 @@ static RTC_DATA_ATTR uint64_t s_esp_rtc_time_us = 0, s_rtc_last_ticks = 0;
5353
inline static int IRAM_ATTR s_get_cpu_freq_mhz(void)
5454
{
5555
#if ESP_ROM_GET_CLK_FREQ
56-
return ets_get_cpu_frequency();
56+
return esp_rom_get_cpu_ticks_per_us();
5757
#else
5858
return g_ticks_per_us_pro;
5959
#endif

‎components/esp_hw_support/include/esp_mac.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,11 @@
99
#include "esp_err.h"
1010
#include "sdkconfig.h"
1111

12+
#ifndef MAC2STR
13+
#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
14+
#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
15+
#endif
16+
1217
#ifdef __cplusplus
1318
extern "C" {
1419
#endif

‎components/esp_hw_support/include/soc_log.h

Lines changed: 0 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -24,20 +24,6 @@
2424
#define SOC_LOGV(tag, fmt, ...) ESP_EARLY_LOGV(tag, fmt, ##__VA_ARGS__)
2525

2626
#else
27-
#include "sdkconfig.h"
28-
#ifdef CONFIG_IDF_TARGET_ESP32
29-
#include "esp32/rom/ets_sys.h" // will be removed in idf v5.0
30-
#elif CONFIG_IDF_TARGET_ESP32S2
31-
#include "esp32s2/rom/ets_sys.h"
32-
#elif CONFIG_IDF_TARGET_ESP32S3
33-
#include "esp32s3/rom/ets_sys.h"
34-
#elif CONFIG_IDF_TARGET_ESP32C3
35-
#include "esp32c3/rom/ets_sys.h"
36-
#elif CONFIG_IDF_TARGET_ESP32H2
37-
#include "esp32h2/rom/ets_sys.h"
38-
#elif CONFIG_IDF_TARGET_ESP32C2
39-
#include "esp32c2/rom/ets_sys.h"
40-
#endif
4127

4228
#define SOC_LOGE(tag, fmt, ...) esp_rom_printf("%s(err): " fmt, tag, ##__VA_ARGS__)
4329
#define SOC_LOGW(tag, fmt, ...) esp_rom_printf("%s(warn): " fmt, tag, ##__VA_ARGS__)

‎components/esp_hw_support/intr_alloc.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -560,7 +560,7 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre
560560
non_iram_int_mask[cpu]|=(1<<intr);
561561
}
562562
if (source>=0) {
563-
intr_matrix_set(cpu, source, intr);
563+
esp_rom_route_intr_matrix(cpu, source, intr);
564564
}
565565

566566
//Fill return handle data.
@@ -735,7 +735,7 @@ esp_err_t IRAM_ATTR esp_intr_enable(intr_handle_t handle)
735735
}
736736
if (source >= 0) {
737737
//Disabled using int matrix; re-connect to enable
738-
intr_matrix_set(handle->vector_desc->cpu, source, handle->vector_desc->intno);
738+
esp_rom_route_intr_matrix(handle->vector_desc->cpu, source, handle->vector_desc->intno);
739739
} else {
740740
//Re-enable using cpu int ena reg
741741
if (handle->vector_desc->cpu!=cpu_hal_get_core_id()) return ESP_ERR_INVALID_ARG; //Can only enable these ints on this cpu
@@ -771,7 +771,7 @@ esp_err_t IRAM_ATTR esp_intr_disable(intr_handle_t handle)
771771
if (source >= 0) {
772772
if ( disabled ) {
773773
//Disable using int matrix
774-
intr_matrix_set(handle->vector_desc->cpu, source, INT_MUX_DISABLED_INTNO);
774+
esp_rom_route_intr_matrix(handle->vector_desc->cpu, source, INT_MUX_DISABLED_INTNO);
775775
}
776776
} else {
777777
//Disable using per-cpu regs

‎components/esp_hw_support/port/esp32c3/esp_memprot.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@
1010
#include "esp_intr_alloc.h"
1111
#include "hal/memprot_ll.h"
1212
#include "riscv/interrupt.h"
13-
#include "esp32c3/rom/ets_sys.h"
13+
#include "esp_rom_sys.h"
1414
#include "esp_cpu.h"
1515
#include "esp_fault.h"
1616
#include "esp_attr.h"
@@ -616,13 +616,13 @@ static esp_err_t esp_mprot_set_intr_matrix(const esp_mprot_mem_t mem_type)
616616

617617
switch (mem_type) {
618618
case MEMPROT_TYPE_IRAM0_SRAM:
619-
intr_matrix_set(PRO_CPU_NUM, memprot_ll_iram0_get_intr_source_num(), ETS_MEMPROT_ERR_INUM);
619+
esp_rom_route_intr_matrix(PRO_CPU_NUM, memprot_ll_iram0_get_intr_source_num(), ETS_MEMPROT_ERR_INUM);
620620
break;
621621
case MEMPROT_TYPE_DRAM0_SRAM:
622-
intr_matrix_set(PRO_CPU_NUM, memprot_ll_dram0_get_intr_source_num(), ETS_MEMPROT_ERR_INUM);
622+
esp_rom_route_intr_matrix(PRO_CPU_NUM, memprot_ll_dram0_get_intr_source_num(), ETS_MEMPROT_ERR_INUM);
623623
break;
624624
case MEMPROT_TYPE_IRAM0_RTCFAST:
625-
intr_matrix_set(PRO_CPU_NUM, memprot_ll_rtcfast_get_intr_source_num(), ETS_MEMPROT_ERR_INUM);
625+
esp_rom_route_intr_matrix(PRO_CPU_NUM, memprot_ll_rtcfast_get_intr_source_num(), ETS_MEMPROT_ERR_INUM);
626626
break;
627627
default:
628628
return ESP_ERR_MEMPROT_MEMORY_TYPE_INVALID;

‎components/esp_hw_support/port/esp32s2/memprot.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@
1919
#include "esp32s2/memprot.h"
2020
#include "esp_fault.h"
2121
#include "esp_cpu.h"
22-
#include "esp32s2/rom/ets_sys.h"
22+
#include "esp_rom_sys.h"
2323

2424
extern int _iram_text_end;
2525
extern int _data_start;
@@ -125,18 +125,18 @@ esp_err_t esp_memprot_intr_init(mem_type_prot_t mem_type)
125125
switch (mem_type) {
126126
case MEMPROT_IRAM0_SRAM:
127127
case MEMPROT_IRAM0_RTCFAST:
128-
intr_matrix_set(PRO_CPU_NUM, memprot_ll_iram0_get_intr_source_num(), ETS_MEMACCESS_ERR_INUM);
128+
esp_rom_route_intr_matrix(PRO_CPU_NUM, memprot_ll_iram0_get_intr_source_num(), ETS_MEMACCESS_ERR_INUM);
129129
break;
130130
case MEMPROT_DRAM0_SRAM:
131131
case MEMPROT_DRAM0_RTCFAST:
132-
intr_matrix_set(PRO_CPU_NUM, memprot_ll_dram0_get_intr_source_num(), ETS_MEMACCESS_ERR_INUM);
132+
esp_rom_route_intr_matrix(PRO_CPU_NUM, memprot_ll_dram0_get_intr_source_num(), ETS_MEMACCESS_ERR_INUM);
133133
break;
134134
case MEMPROT_PERI1_RTCSLOW:
135-
intr_matrix_set(PRO_CPU_NUM, memprot_ll_peri1_get_intr_source_num(), ETS_MEMACCESS_ERR_INUM);
135+
esp_rom_route_intr_matrix(PRO_CPU_NUM, memprot_ll_peri1_get_intr_source_num(), ETS_MEMACCESS_ERR_INUM);
136136
break;
137137
case MEMPROT_PERI2_RTCSLOW_0:
138138
case MEMPROT_PERI2_RTCSLOW_1:
139-
intr_matrix_set(PRO_CPU_NUM, memprot_ll_peri2_get_intr_source_num(), ETS_MEMACCESS_ERR_INUM);
139+
esp_rom_route_intr_matrix(PRO_CPU_NUM, memprot_ll_peri2_get_intr_source_num(), ETS_MEMACCESS_ERR_INUM);
140140
break;
141141
default:
142142
return ESP_ERR_NOT_SUPPORTED;

‎components/esp_rom/esp32/ld/esp32.rom.api.ld

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,8 @@ PROVIDE ( esp_rom_printf = ets_printf );
4343
PROVIDE ( esp_rom_delay_us = ets_delay_us );
4444
PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf );
4545
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
46+
PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set );
47+
PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
4648

4749
PROVIDE ( esp_rom_spiflash_set_bp = esp_rom_spiflash_lock );
4850
PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable);

‎components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,8 @@ PROVIDE ( esp_rom_mbedtls_md5_finish_ret = 0x40002a3c );
3737
PROVIDE ( esp_rom_printf = ets_printf );
3838
PROVIDE ( esp_rom_delay_us = ets_delay_us );
3939
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
40+
PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set );
41+
PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
4042

4143
PROVIDE( esp_rom_spiflash_attach = spi_flash_attach );
4244
PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );

‎components/esp_rom/esp32c3/ld/esp32c3.rom.api.ld

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,8 @@ PROVIDE ( esp_rom_md5_final = MD5Final );
4040
PROVIDE ( esp_rom_printf = ets_printf );
4141
PROVIDE ( esp_rom_delay_us = ets_delay_us );
4242
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
43+
PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set );
44+
PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
4345

4446
PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
4547
PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable);

‎components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.api.ld

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,8 @@ PROVIDE ( esp_rom_md5_final = MD5Final );
4343
PROVIDE ( esp_rom_printf = ets_printf );
4444
PROVIDE ( esp_rom_delay_us = ets_delay_us );
4545
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
46+
PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set );
47+
PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
4648

4749
PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
4850
PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable);

‎components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.api.ld

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,8 @@ PROVIDE ( esp_rom_md5_final = MD5Final );
4343
PROVIDE ( esp_rom_printf = ets_printf );
4444
PROVIDE ( esp_rom_delay_us = ets_delay_us );
4545
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
46+
PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set );
47+
PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
4648

4749
PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
4850
PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable);

‎components/esp_rom/esp32s2/ld/esp32s2.rom.api.ld

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,8 @@ PROVIDE ( esp_rom_printf = ets_printf );
3737
PROVIDE ( esp_rom_delay_us = ets_delay_us );
3838
PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf );
3939
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
40+
PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set );
41+
PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
4042

4143
PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
4244
PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable);

‎components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,8 @@ PROVIDE ( esp_rom_printf = ets_printf );
4343
PROVIDE ( esp_rom_delay_us = ets_delay_us );
4444
PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf );
4545
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
46+
PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set );
47+
PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
4648

4749
PROVIDE( esp_rom_spiflash_attach = spi_flash_attach );
4850
PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );

‎components/esp_rom/include/esp_rom_sys.h

Lines changed: 27 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1,16 +1,8 @@
1-
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
2-
//
3-
// Licensed under the Apache License, Version 2.0 (the "License");
4-
// you may not use this file except in compliance with the License.
5-
// You may obtain a copy of the License at
6-
//
7-
// http://www.apache.org/licenses/LICENSE-2.0
8-
//
9-
// Unless required by applicable law or agreed to in writing, software
10-
// distributed under the License is distributed on an "AS IS" BASIS,
11-
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12-
// See the License for the specific language governing permissions and
13-
// limitations under the License.
1+
/*
2+
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
146

157
#pragma once
168
#include "sdkconfig.h"
@@ -60,6 +52,28 @@ void esp_rom_install_uart_printf(void);
6052
*/
6153
soc_reset_reason_t esp_rom_get_reset_reason(int cpu_no);
6254

55+
/**
56+
* @brief Route peripheral interrupt sources to CPU's interrupt port by matrix
57+
*
58+
* Usually there're 4 steps to use an interrupt:
59+
* 1. Route peripheral interrupt source to CPU. e.g. esp_rom_route_intr_matrix(0, ETS_WIFI_MAC_INTR_SOURCE, ETS_WMAC_INUM)
60+
* 2. Set interrupt handler for CPU
61+
* 3. Enable CPU interupt
62+
* 4. Enable peripheral interrupt
63+
*
64+
* @param cpu_core The CPU number, which the peripheral interupt will inform to
65+
* @param periph_intr_id The peripheral interrupt source number
66+
* @param cpu_intr_num The CPU interrupt number
67+
*/
68+
void esp_rom_route_intr_matrix(int cpu_core, uint32_t periph_intr_id, uint32_t cpu_intr_num);
69+
70+
/**
71+
* @brief Get the real CPU ticks per us
72+
*
73+
* @return CPU ticks per us
74+
*/
75+
uint32_t esp_rom_get_cpu_ticks_per_us(void);
76+
6377
#ifdef __cplusplus
6478
}
6579
#endif

‎components/esp_system/int_wdt.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -149,7 +149,7 @@ void esp_int_wdt_cpu_init(void)
149149
ESP_INTR_DISABLE(WDT_INT_NUM);
150150

151151
#if SOC_TIMER_GROUPS > 1
152-
intr_matrix_set(cpu_hal_get_core_id(), ETS_TG1_WDT_LEVEL_INTR_SOURCE, WDT_INT_NUM);
152+
esp_rom_route_intr_matrix(cpu_hal_get_core_id(), ETS_TG1_WDT_LEVEL_INTR_SOURCE, WDT_INT_NUM);
153153
#else
154154
// TODO: Clean up code for ESP32-C2, IDF-4114
155155
ESP_EARLY_LOGW("INT_WDT", "ESP32-C2 only has one timer group");

‎components/esp_system/port/arch/xtensa/esp_ipc_isr.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,7 @@ void esp_ipc_isr_init(void)
6565
const uint32_t cpuid = xPortGetCoreID();
6666
uint32_t intr_source = ETS_FROM_CPU_INTR2_SOURCE + cpuid; // ETS_FROM_CPU_INTR2_SOURCE and ETS_FROM_CPU_INTR3_SOURCE
6767
ESP_INTR_DISABLE(ETS_IPC_ISR_INUM);
68-
intr_matrix_set(cpuid, intr_source, ETS_IPC_ISR_INUM);
68+
esp_rom_route_intr_matrix(cpuid, intr_source, ETS_IPC_ISR_INUM);
6969
ESP_INTR_ENABLE(ETS_IPC_ISR_INUM);
7070

7171
if (cpuid != 0) {

‎components/esp_system/port/cpu_start.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -138,7 +138,7 @@ static void core_intr_matrix_clear(void)
138138
uint32_t core_id = cpu_hal_get_core_id();
139139

140140
for (int i = 0; i < ETS_MAX_INTR_SOURCE; i++) {
141-
intr_matrix_set(core_id, i, ETS_INVALID_INUM);
141+
esp_rom_route_intr_matrix(core_id, i, ETS_INVALID_INUM);
142142
}
143143
}
144144

‎components/esp_system/port/soc/esp32/cache_err_int.c

Lines changed: 7 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1,16 +1,8 @@
1-
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
1+
/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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The cache has an interrupt that can be raised as soon as an access to a cached
@@ -32,7 +24,7 @@
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#include "hal/cpu_hal.h"
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#include "esp32/dport_access.h"
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#include "esp32/rom/ets_sys.h" // for intr_matrix_set
27+
#include "esp_rom_sys.h"
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#include "sdkconfig.h"
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@@ -45,7 +37,7 @@ void esp_cache_err_int_init(void)
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// level 4 which is not serviceable from C. Instead, xtensa_vectors.S has
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// a call to the panic handler for
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// this interrupt.
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intr_matrix_set(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_MEMACCESS_ERR_INUM);
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esp_rom_route_intr_matrix(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_MEMACCESS_ERR_INUM);
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// Enable invalid cache access interrupt when the cache is disabled.
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// When the interrupt happens, we can not determine the CPU where the

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