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bugfix(uart): workaround for uart fifo reset issue
Reported from github: #1219 #1202 After providing a simple code to digital team, they confirmed that this is a hardware bug. Root cause: The fifo reset signal is incorrectly connected If we want to reset tx fifo of UART2, we have to set txfifo_rst bit of both UART1 and UART2 If we want to reset rx fifo of UART2, we have to set rxfifo_rst bit of both UART1 and UART2 Workaround: we don't use fifo rst bit in driver. Documentation: Digital team would update TRM and give more explanation about this issue.
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components/driver/uart.c

Lines changed: 11 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -268,15 +268,13 @@ esp_err_t uart_get_hw_flow_ctrl(uart_port_t uart_num, uart_hw_flowcontrol_t* flo
268268
return ESP_OK;
269269
}
270270

271-
static esp_err_t uart_reset_fifo(uart_port_t uart_num)
271+
static esp_err_t uart_reset_rx_fifo(uart_port_t uart_num)
272272
{
273273
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
274-
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
275-
UART[uart_num]->conf0.rxfifo_rst = 1;
276-
UART[uart_num]->conf0.rxfifo_rst = 0;
277-
UART[uart_num]->conf0.txfifo_rst = 1;
278-
UART[uart_num]->conf0.txfifo_rst = 0;
279-
UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
274+
// Read all data from the FIFO
275+
while (UART[uart_num]->status.rxfifo_cnt) {
276+
READ_PERI_REG(UART_FIFO_REG(uart_num));
277+
}
280278
return ESP_OK;
281279
}
282280

@@ -695,8 +693,11 @@ static void uart_rx_intr_handler_default(void *param)
695693
}
696694
} else if(uart_intr_status & UART_RXFIFO_OVF_INT_ST_M) {
697695
UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
698-
uart_reg->conf0.rxfifo_rst = 1;
699-
uart_reg->conf0.rxfifo_rst = 0;
696+
// Read all data from the FIFO
697+
rx_fifo_len = uart_reg->status.rxfifo_cnt;
698+
for (int i = 0; i < rx_fifo_len; i++) {
699+
READ_PERI_REG(UART_FIFO_REG(uart_num));
700+
}
700701
uart_reg->int_clr.rxfifo_ovf = 1;
701702
UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
702703
uart_event.type = UART_FIFO_OVF;
@@ -1009,7 +1010,7 @@ esp_err_t uart_flush(uart_port_t uart_num)
10091010
p_uart->rx_ptr = NULL;
10101011
p_uart->rx_cur_remain = 0;
10111012
p_uart->rx_head_ptr = NULL;
1012-
uart_reset_fifo(uart_num);
1013+
uart_reset_rx_fifo(uart_num);
10131014
uart_enable_rx_intr(p_uart_obj[uart_num]->uart_num);
10141015
xSemaphoreGive(p_uart->rx_mux);
10151016
return ESP_OK;

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