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i2s.c
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/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include <stdbool.h>
#include <math.h>
#include <esp_types.h>
#include "freertos/FreeRTOS.h"
#include "freertos/queue.h"
#include "freertos/semphr.h"
#include "soc/lldesc.h"
#include "driver/gpio.h"
#include "driver/i2s.h"
#include "hal/gpio_hal.h"
#include "hal/i2s_hal.h"
#if SOC_I2S_SUPPORTS_DAC
#include "driver/dac.h"
#endif // SOC_I2S_SUPPORTS_DAC
#if SOC_I2S_SUPPORTS_ADC
#include "adc1_private.h"
#endif // SOC_I2S_SUPPORTS_ADC
#if SOC_GDMA_SUPPORTED
#include "esp_private/gdma.h"
#endif
#include "soc/clk_ctrl_os.h"
#include "esp_intr_alloc.h"
#include "esp_err.h"
#include "esp_check.h"
#include "esp_attr.h"
#include "esp_log.h"
#include "esp_pm.h"
#include "esp_efuse.h"
#include "esp_rom_gpio.h"
#include "esp_private/i2s_platform.h"
#include "esp_private/sar_periph_ctrl.h"
#include "sdkconfig.h"
static const char *TAG = "I2S";
#define I2S_ENTER_CRITICAL_ISR(i2s_num) portENTER_CRITICAL_ISR(&i2s_spinlock[i2s_num])
#define I2S_EXIT_CRITICAL_ISR(i2s_num) portEXIT_CRITICAL_ISR(&i2s_spinlock[i2s_num])
#define I2S_ENTER_CRITICAL(i2s_num) portENTER_CRITICAL(&i2s_spinlock[i2s_num])
#define I2S_EXIT_CRITICAL(i2s_num) portEXIT_CRITICAL(&i2s_spinlock[i2s_num])
#define I2S_DMA_BUFFER_MAX_SIZE 4092
#if !SOC_GDMA_SUPPORTED
#define I2S_INTR_IN_SUC_EOF BIT(9)
#define I2S_INTR_OUT_EOF BIT(12)
#define I2S_INTR_IN_DSCR_ERR BIT(13)
#define I2S_INTR_OUT_DSCR_ERR BIT(14)
#define I2S_INTR_MAX (~0)
#endif
/**
* @brief DMA buffer object
*
*/
typedef struct {
char **buf;
int buf_size;
volatile int rw_pos;
volatile void *curr_ptr;
SemaphoreHandle_t mux;
xQueueHandle queue;
lldesc_t **desc;
} i2s_dma_t;
/**
* @brief I2S object instance
*
*/
typedef struct {
i2s_port_t i2s_num; /*!< I2S port number*/
int queue_size; /*!< I2S event queue size*/
QueueHandle_t i2s_queue; /*!< I2S queue handler*/
int dma_buf_count; /*!< DMA buffer count, number of buffer*/
int dma_buf_len; /*!< DMA buffer length, length of each buffer*/
uint32_t last_buf_size; /*!< DMA last buffer size */
i2s_dma_t *tx; /*!< DMA Tx buffer*/
i2s_dma_t *rx; /*!< DMA Rx buffer*/
#if SOC_GDMA_SUPPORTED
gdma_channel_handle_t rx_dma_chan; /*!< I2S rx gDMA channel handle*/
gdma_channel_handle_t tx_dma_chan; /*!< I2S tx gDMA channel handle*/
#else
i2s_isr_handle_t i2s_isr_handle; /*!< I2S Interrupt handle*/
#endif
bool tx_desc_auto_clear; /*!< I2S auto clear tx descriptor on underflow */
bool use_apll; /*!< I2S use APLL clock */
int fixed_mclk; /*!< I2S fixed MLCK clock */
i2s_mclk_multiple_t mclk_multiple; /*!< The multiple of I2S master clock(MCLK) to sample rate */
#ifdef CONFIG_PM_ENABLE
esp_pm_lock_handle_t pm_lock;
#endif
i2s_hal_context_t hal; /*!< I2S hal context*/
i2s_channel_fmt_t init_chan_fmt; /*!< The initial channel format while installing, used for keep left or right mono when switch between mono and stereo */
i2s_hal_config_t hal_cfg; /*!< I2S hal configurations*/
} i2s_obj_t;
static i2s_obj_t *p_i2s[SOC_I2S_NUM];
static portMUX_TYPE i2s_platform_spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
static portMUX_TYPE i2s_spinlock[SOC_I2S_NUM] = {
[0 ... SOC_I2S_NUM - 1] = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED,
};
#if SOC_I2S_SUPPORTS_ADC
static int _i2s_adc_unit = -1;
static int _i2s_adc_channel = -1;
#endif
/*
* This block is an overview of APIs in i2s.c
* Functions with [main] tag are summary functions that provide main i2s service
* Functions with [helper] tag are helper functions that served for summary functions
* Functions with [intr] tag are interrupt handling functions or interrupt callback functions
-------------------------------------------------------------
I2S GPIO operation
-------------------------------------------------------------
- [helper] gpio_matrix_out_check_and_set
- [helper] gpio_matrix_in_check_and_set
- [helper] i2s_check_set_mclk
- [main] i2s_set_pin
-------------------------------------------------------------
I2S DMA operation
-------------------------------------------------------------
- [intr] i2s_dma_rx_callback
- [intr] i2s_dma_tx_callback
- [intr] i2s_intr_handler_default
- [helper] i2s_dma_intr_init
- [helper] i2s_tx_reset
- [helper] i2s_rx_reset
- [helper] i2s_tx_start
- [helper] i2s_rx_start
- [helper] i2s_tx_stop
- [helper] i2s_rx_stop
-------------------------------------------------------------
I2S buffer operation
-------------------------------------------------------------
- [helper] i2s_get_buf_size
- [helper] i2s_delete_dma_buffer
- [helper] i2s_alloc_dma_buffer
- [main] i2s_realloc_dma_buffer
- [main] i2s_destroy_dma_object
- [main] i2s_create_dma_object
- [main] i2s_zero_dma_buffer
-------------------------------------------------------------
I2S clock operation
-------------------------------------------------------------
- [helper] i2s_config_source_clock
- [helper] i2s_calculate_adc_dac_clock
- [helper] i2s_calculate_pdm_tx_clock
- [helper] i2s_calculate_pdm_rx_clock
- [helper] i2s_calculate_common_clock
- [main] i2s_calculate_clock
-------------------------------------------------------------
I2S configuration
-------------------------------------------------------------
- [helper] i2s_get_max_channel_num
- [helper] i2s_get_active_channel_num
- [helper] i2s_set_dac_mode
- [helper] _i2s_adc_mode_recover
- [main] i2s_set_adc_mode
- [main] i2s_adc_enable
- [main] i2s_adc_disable
- [helper] i2s_set_sample_rates
- [main] i2s_pcm_config
- [helper] i2s_set_pdm_rx_down_sample
- [helper] i2s_set_pdm_tx_up_sample
- [helper] i2s_check_cfg_validity
- [helper] i2s_tx_set_clk_and_channel
- [helper] i2s_rx_set_clk_and_channel
- [main] i2s_get_clk
- [main] i2s_set_clk
-------------------------------------------------------------
I2S driver operation
-------------------------------------------------------------
- [main] i2s_start
- [main] i2s_stop
- [helper] i2s_driver_init
- [helper] i2s_dma_object_init
- [main] i2s_driver_install
- [main] i2s_driver_uninstall
- [main] i2s_write
- [main] i2s_write_expand
- [main] i2s_read
-------------------------------------------------------------*/
/*-------------------------------------------------------------
I2S GPIO operation
-------------------------------------------------------------*/
/**
* @brief I2S GPIO matrix set ouput
*
* @param gpio GPIO number
* @param singal_idx GPIO singnal ID, refer to 'gpio_sig_map.h'
* @param out_inv Output invert enable
* @param oen_inv Output eanble control invert enable
*/
static void gpio_matrix_out_check_and_set(gpio_num_t gpio, uint32_t signal_idx, bool out_inv, bool oen_inv)
{
//if pin = -1, do not need to configure
if (gpio != -1) {
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio], PIN_FUNC_GPIO);
gpio_set_direction(gpio, GPIO_MODE_OUTPUT);
esp_rom_gpio_connect_out_signal(gpio, signal_idx, out_inv, oen_inv);
}
}
/**
* @brief I2S GPIO matrix set input
*
* @param gpio GPIO number
* @param singal_idx GPIO singnal ID, refer to 'gpio_sig_map.h'
* @param out_inv Output invert enable
* @param oen_inv Output eanble control invert enable
*/
static void gpio_matrix_in_check_and_set(gpio_num_t gpio, uint32_t signal_idx, bool inv)
{
if (gpio != -1) {
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio], PIN_FUNC_GPIO);
/* Set direction, for some GPIOs, the input function are not enabled as default */
gpio_set_direction(gpio, GPIO_MODE_INPUT);
esp_rom_gpio_connect_in_signal(gpio, signal_idx, inv);
}
}
/**
* @brief I2S set GPIO for mclk
*
* @param i2s_num I2S device number
* @param gpio_num GPIO number for mclk
* @return
* - ESP_OK Check or set success
* - ESP_ERR_INVALID_ARG GPIO is not available
*/
static esp_err_t i2s_check_set_mclk(i2s_port_t i2s_num, gpio_num_t gpio_num)
{
if (gpio_num == -1) {
return ESP_OK;
}
#if CONFIG_IDF_TARGET_ESP32
ESP_RETURN_ON_FALSE((gpio_num == GPIO_NUM_0 || gpio_num == GPIO_NUM_1 || gpio_num == GPIO_NUM_3),
ESP_ERR_INVALID_ARG, TAG,
"ESP32 only support to set GPIO0/GPIO1/GPIO3 as mclk signal, error GPIO number:%d", gpio_num);
bool is_i2s0 = i2s_num == I2S_NUM_0;
if (gpio_num == GPIO_NUM_0) {
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO0_U, FUNC_GPIO0_CLK_OUT1);
WRITE_PERI_REG(PIN_CTRL, is_i2s0 ? 0xFFF0 : 0xFFFF);
} else if (gpio_num == GPIO_NUM_1) {
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD_CLK_OUT3);
WRITE_PERI_REG(PIN_CTRL, is_i2s0 ? 0xF0F0 : 0xF0FF);
} else {
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0RXD_U, FUNC_U0RXD_CLK_OUT2);
WRITE_PERI_REG(PIN_CTRL, is_i2s0 ? 0xFF00 : 0xFF0F);
}
#else
ESP_RETURN_ON_FALSE(GPIO_IS_VALID_GPIO(gpio_num), ESP_ERR_INVALID_ARG, TAG, "mck_io_num invalid");
gpio_matrix_out_check_and_set(gpio_num, i2s_periph_signal[i2s_num].mck_out_sig, 0, 0);
#endif
ESP_LOGI(TAG, "I2S%d, MCLK output by GPIO%d", i2s_num, gpio_num);
return ESP_OK;
}
/**
* @brief Set gpio pins for I2S
*
* @param i2s_num I2S device number
* @param pin Pin configuration
* @return
* - ESP_OK Set pin success
* - ESP_ERR_INVALID_ARG GPIO is not available
*/
esp_err_t i2s_set_pin(i2s_port_t i2s_num, const i2s_pin_config_t *pin)
{
ESP_RETURN_ON_FALSE((i2s_num < I2S_NUM_MAX), ESP_ERR_INVALID_ARG, TAG, "i2s_num error");
if (pin == NULL) {
#if SOC_I2S_SUPPORTS_DAC
return i2s_set_dac_mode(I2S_DAC_CHANNEL_BOTH_EN);
#else
return ESP_ERR_INVALID_ARG;
#endif
}
/* Check validity of selected pins */
ESP_RETURN_ON_FALSE((pin->bck_io_num == -1 || GPIO_IS_VALID_GPIO(pin->bck_io_num)),
ESP_ERR_INVALID_ARG, TAG, "bck_io_num invalid");
ESP_RETURN_ON_FALSE((pin->ws_io_num == -1 || GPIO_IS_VALID_GPIO(pin->ws_io_num)),
ESP_ERR_INVALID_ARG, TAG, "ws_io_num invalid");
ESP_RETURN_ON_FALSE((pin->data_out_num == -1 || GPIO_IS_VALID_GPIO(pin->data_out_num)),
ESP_ERR_INVALID_ARG, TAG, "data_out_num invalid");
ESP_RETURN_ON_FALSE((pin->data_in_num == -1 || GPIO_IS_VALID_GPIO(pin->data_in_num)),
ESP_ERR_INVALID_ARG, TAG, "data_in_num invalid");
if (p_i2s[i2s_num]->hal_cfg.mode & I2S_MODE_SLAVE) {
/* For "tx + rx + slave" or "rx + slave" mode, we should select RX signal index for ws and bck */
if (p_i2s[i2s_num]->hal_cfg.mode & I2S_MODE_RX) {
gpio_matrix_in_check_and_set(pin->ws_io_num, i2s_periph_signal[i2s_num].s_rx_ws_sig, 0);
gpio_matrix_in_check_and_set(pin->bck_io_num, i2s_periph_signal[i2s_num].s_rx_bck_sig, 0);
/* For "tx + slave" mode, we should select TX signal index for ws and bck */
} else {
gpio_matrix_in_check_and_set(pin->ws_io_num, i2s_periph_signal[i2s_num].s_tx_ws_sig, 0);
gpio_matrix_in_check_and_set(pin->bck_io_num, i2s_periph_signal[i2s_num].s_tx_bck_sig, 0);
}
} else {
/* mclk only available in master mode */
ESP_RETURN_ON_ERROR(i2s_check_set_mclk(i2s_num, pin->mck_io_num), TAG, "mclk config failed");
/* For "tx + rx + master" or "tx + master" mode, we should select TX signal index for ws and bck */
if (p_i2s[i2s_num]->hal_cfg.mode & I2S_MODE_TX) {
gpio_matrix_out_check_and_set(pin->ws_io_num, i2s_periph_signal[i2s_num].m_tx_ws_sig, 0, 0);
gpio_matrix_out_check_and_set(pin->bck_io_num, i2s_periph_signal[i2s_num].m_tx_bck_sig, 0, 0);
/* For "rx + master" mode, we should select RX signal index for ws and bck */
} else {
gpio_matrix_out_check_and_set(pin->ws_io_num, i2s_periph_signal[i2s_num].m_rx_ws_sig, 0, 0);
gpio_matrix_out_check_and_set(pin->bck_io_num, i2s_periph_signal[i2s_num].m_rx_bck_sig, 0, 0);
}
}
/* Set data input/ouput GPIO */
gpio_matrix_out_check_and_set(pin->data_out_num, i2s_periph_signal[i2s_num].data_out_sig, 0, 0);
gpio_matrix_in_check_and_set(pin->data_in_num, i2s_periph_signal[i2s_num].data_in_sig, 0);
return ESP_OK;
}
/*-------------------------------------------------------------
I2S DMA operation
-------------------------------------------------------------*/
#if SOC_GDMA_SUPPORTED
/**
* @brief GDMA rx callback function
* @note This function is called by GDMA default ISR handler
*
* @param dma_chan GDMA channel handler
* @param event_data GDMA rx event data
* @param user_data GDMA user data
* @return
* - true need yield
* - false no need
*/
static bool IRAM_ATTR i2s_dma_rx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
{
i2s_obj_t *p_i2s = (i2s_obj_t *) user_data;
portBASE_TYPE need_awoke = 0;
portBASE_TYPE tmp = 0;
int dummy;
i2s_event_t i2s_event;
uint32_t finish_desc;
if (p_i2s->rx) {
finish_desc = event_data->rx_eof_desc_addr;
i2s_event.size = ((lldesc_t *)finish_desc)->size;
if (xQueueIsQueueFullFromISR(p_i2s->rx->queue)) {
xQueueReceiveFromISR(p_i2s->rx->queue, &dummy, &tmp);
need_awoke |= tmp;
if (p_i2s->i2s_queue) {
i2s_event.type = I2S_EVENT_RX_Q_OVF;
xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
need_awoke |= tmp;
}
}
xQueueSendFromISR(p_i2s->rx->queue, &(((lldesc_t *)finish_desc)->buf), &tmp);
need_awoke |= tmp;
if (p_i2s->i2s_queue) {
i2s_event.type = I2S_EVENT_RX_DONE;
xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
need_awoke |= tmp;
}
}
return need_awoke;
}
/**
* @brief GDMA tx callback function
* @note This function is called by GDMA default ISR handler
*
* @param dma_chan GDMA channel handler
* @param event_data GDMA tx event data
* @param user_data GDMA user data
* @return
* - whether need yield
*/
static bool IRAM_ATTR i2s_dma_tx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
{
i2s_obj_t *p_i2s = (i2s_obj_t *) user_data;
portBASE_TYPE need_awoke = 0;
portBASE_TYPE tmp = 0;
int dummy;
i2s_event_t i2s_event;
uint32_t finish_desc;
if (p_i2s->tx) {
finish_desc = event_data->tx_eof_desc_addr;
i2s_event.size = ((lldesc_t *)finish_desc)->size;
if (xQueueIsQueueFullFromISR(p_i2s->tx->queue)) {
xQueueReceiveFromISR(p_i2s->tx->queue, &dummy, &tmp);
need_awoke |= tmp;
if (p_i2s->i2s_queue) {
i2s_event.type = I2S_EVENT_TX_Q_OVF;
i2s_event.size = p_i2s->tx->buf_size;
xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
need_awoke |= tmp;
}
}
if (p_i2s->tx_desc_auto_clear) {
memset((void *) (((lldesc_t *)finish_desc)->buf), 0, p_i2s->tx->buf_size);
}
xQueueSendFromISR(p_i2s->tx->queue, &(((lldesc_t *)finish_desc)->buf), &tmp);
need_awoke |= tmp;
if (p_i2s->i2s_queue) {
i2s_event.type = I2S_EVENT_TX_DONE;
xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
need_awoke |= tmp;
}
}
return need_awoke;
}
#else
/**
* @brief I2S defalut interrupt handler
* @note This function is triggered by I2S dedicated DMA interrupt
*
* @param arg Argument transport to ISR, here is the pointer to I2S object
*/
static void IRAM_ATTR i2s_intr_handler_default(void *arg)
{
i2s_obj_t *p_i2s = (i2s_obj_t *) arg;
uint32_t status = i2s_hal_get_intr_status(&(p_i2s->hal));
if (status == 0) {
//Avoid spurious interrupt
return;
}
i2s_event_t i2s_event;
int dummy;
portBASE_TYPE need_awoke = 0;
portBASE_TYPE tmp = 0;
uint32_t finish_desc = 0;
if ((status & I2S_INTR_OUT_DSCR_ERR) || (status & I2S_INTR_IN_DSCR_ERR)) {
ESP_EARLY_LOGE(TAG, "dma error, interrupt status: 0x%08x", status);
if (p_i2s->i2s_queue) {
i2s_event.type = I2S_EVENT_DMA_ERROR;
if (xQueueIsQueueFullFromISR(p_i2s->i2s_queue)) {
xQueueReceiveFromISR(p_i2s->i2s_queue, &dummy, &tmp);
need_awoke |= tmp;
}
xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
need_awoke |= tmp;
}
}
if ((status & I2S_INTR_OUT_EOF) && p_i2s->tx) {
i2s_hal_get_out_eof_des_addr(&(p_i2s->hal), &finish_desc);
i2s_event.size = ((lldesc_t *)finish_desc)->size;
// All buffers are empty. This means we have an underflow on our hands.
if (xQueueIsQueueFullFromISR(p_i2s->tx->queue)) {
xQueueReceiveFromISR(p_i2s->tx->queue, &dummy, &tmp);
need_awoke |= tmp;
if (p_i2s->i2s_queue) {
i2s_event.type = I2S_EVENT_TX_Q_OVF;
xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
need_awoke |= tmp;
}
}
// See if tx descriptor needs to be auto cleared:
// This will avoid any kind of noise that may get introduced due to transmission
// of previous data from tx descriptor on I2S line.
if (p_i2s->tx_desc_auto_clear) {
memset((void *) (((lldesc_t *)finish_desc)->buf), 0, p_i2s->tx->buf_size);
}
xQueueSendFromISR(p_i2s->tx->queue, &(((lldesc_t *)finish_desc)->buf), &tmp);
need_awoke |= tmp;
if (p_i2s->i2s_queue) {
i2s_event.type = I2S_EVENT_TX_DONE;
xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
need_awoke |= tmp;
}
}
if ((status & I2S_INTR_IN_SUC_EOF) && p_i2s->rx) {
// All buffers are full. This means we have an overflow.
i2s_hal_get_in_eof_des_addr(&(p_i2s->hal), &finish_desc);
i2s_event.size = ((lldesc_t *)finish_desc)->size;
if (xQueueIsQueueFullFromISR(p_i2s->rx->queue)) {
xQueueReceiveFromISR(p_i2s->rx->queue, &dummy, &tmp);
need_awoke |= tmp;
if (p_i2s->i2s_queue) {
i2s_event.type = I2S_EVENT_RX_Q_OVF;
xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
need_awoke |= tmp;
}
}
xQueueSendFromISR(p_i2s->rx->queue, &(((lldesc_t *)finish_desc)->buf), &tmp);
need_awoke |= tmp;
if (p_i2s->i2s_queue) {
i2s_event.type = I2S_EVENT_RX_DONE;
xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
need_awoke |= tmp;
}
}
i2s_hal_clear_intr_status(&(p_i2s->hal), status);
if (need_awoke == pdTRUE) {
portYIELD_FROM_ISR();
}
}
#endif
/**
* @brief I2S DMA interrupt initialization
* @note I2S will use GDMA if chip supports, and the interrupt is triggered by GDMA.
*
* @param i2s_num I2S device number
* @return
* - ESP_OK I2S DMA interrupt initialize success
* - ESP_ERR_NOT_FOUND GDMA channel not found
* - ESP_ERR_INVALID_ARG Invalid arguments
* - ESP_ERR_INVALID_STATE GDMA state error
*/
static esp_err_t i2s_dma_intr_init(i2s_port_t i2s_num, int intr_flag)
{
#if SOC_GDMA_SUPPORTED
/* Set GDMA trigger module */
gdma_trigger_t trig = {.periph = GDMA_TRIG_PERIPH_I2S};
switch (i2s_num) {
#if SOC_I2S_NUM > 1
case I2S_NUM_1:
trig.instance_id = SOC_GDMA_TRIG_PERIPH_I2S1;
break;
#endif
default:
trig.instance_id = SOC_GDMA_TRIG_PERIPH_I2S0;
break;
}
/* Set GDMA config */
gdma_channel_alloc_config_t dma_cfg = {};
if ( p_i2s[i2s_num]->hal_cfg.mode & I2S_MODE_TX) {
dma_cfg.direction = GDMA_CHANNEL_DIRECTION_TX;
/* Register a new GDMA tx channel */
ESP_RETURN_ON_ERROR(gdma_new_channel(&dma_cfg, &p_i2s[i2s_num]->tx_dma_chan), TAG, "Register tx dma channel error");
ESP_RETURN_ON_ERROR(gdma_connect(p_i2s[i2s_num]->tx_dma_chan, trig), TAG, "Connect tx dma channel error");
gdma_tx_event_callbacks_t cb = {.on_trans_eof = i2s_dma_tx_callback};
/* Set callback function for GDMA, the interrupt is triggered by GDMA, then the GDMA ISR will call the callback function */
gdma_register_tx_event_callbacks(p_i2s[i2s_num]->tx_dma_chan, &cb, p_i2s[i2s_num]);
}
if ( p_i2s[i2s_num]->hal_cfg.mode & I2S_MODE_RX) {
dma_cfg.direction = GDMA_CHANNEL_DIRECTION_RX;
/* Register a new GDMA rx channel */
ESP_RETURN_ON_ERROR(gdma_new_channel(&dma_cfg, &p_i2s[i2s_num]->rx_dma_chan), TAG, "Register rx dma channel error");
ESP_RETURN_ON_ERROR(gdma_connect(p_i2s[i2s_num]->rx_dma_chan, trig), TAG, "Connect rx dma channel error");
gdma_rx_event_callbacks_t cb = {.on_recv_eof = i2s_dma_rx_callback};
/* Set callback function for GDMA, the interrupt is triggered by GDMA, then the GDMA ISR will call the callback function */
gdma_register_rx_event_callbacks(p_i2s[i2s_num]->rx_dma_chan, &cb, p_i2s[i2s_num]);
}
#else
/* Initial I2S module interrupt */
ESP_RETURN_ON_ERROR(esp_intr_alloc(i2s_periph_signal[i2s_num].irq, intr_flag, i2s_intr_handler_default, p_i2s[i2s_num], &p_i2s[i2s_num]->i2s_isr_handle), TAG, "Register I2S Interrupt error");
#endif // SOC_GDMA_SUPPORTED
return ESP_OK;
}
/**
* @brief I2S tx reset
*
* @param i2s_num I2S device number
*/
static void i2s_tx_reset(i2s_port_t i2s_num)
{
p_i2s[i2s_num]->tx->curr_ptr = NULL;
p_i2s[i2s_num]->tx->rw_pos = 0;
i2s_hal_reset_tx(&(p_i2s[i2s_num]->hal));
#if SOC_GDMA_SUPPORTED
gdma_reset(p_i2s[i2s_num]->tx_dma_chan);
#else
i2s_hal_reset_txdma(&(p_i2s[i2s_num]->hal));
#endif
i2s_hal_reset_tx_fifo(&(p_i2s[i2s_num]->hal));
}
/**
* @brief I2S rx reset
*
* @param i2s_num I2S device number
*/
static void i2s_rx_reset(i2s_port_t i2s_num)
{
p_i2s[i2s_num]->rx->curr_ptr = NULL;
p_i2s[i2s_num]->rx->rw_pos = 0;
i2s_hal_reset_rx(&(p_i2s[i2s_num]->hal));
#if SOC_GDMA_SUPPORTED
gdma_reset(p_i2s[i2s_num]->rx_dma_chan);
#else
i2s_hal_reset_rxdma(&(p_i2s[i2s_num]->hal));
#endif
i2s_hal_reset_rx_fifo(&(p_i2s[i2s_num]->hal));
}
/**
* @brief I2S tx start
*
* @param i2s_num I2S device number
*/
static void i2s_tx_start(i2s_port_t i2s_num)
{
#if SOC_GDMA_SUPPORTED
gdma_start(p_i2s[i2s_num]->tx_dma_chan, (uint32_t) p_i2s[i2s_num]->tx->desc[0]);
#else
i2s_hal_enable_tx_dma(&(p_i2s[i2s_num]->hal));
i2s_hal_enable_tx_intr(&(p_i2s[i2s_num]->hal));
i2s_hal_start_tx_link(&(p_i2s[i2s_num]->hal), (uint32_t) p_i2s[i2s_num]->tx->desc[0]);
#endif
i2s_hal_start_tx(&(p_i2s[i2s_num]->hal));
}
/**
* @brief I2S rx start
*
* @param i2s_num I2S device number
*/
static void i2s_rx_start(i2s_port_t i2s_num)
{
#if SOC_GDMA_SUPPORTED
gdma_start(p_i2s[i2s_num]->rx_dma_chan, (uint32_t) p_i2s[i2s_num]->rx->desc[0]);
#else
i2s_hal_enable_rx_dma(&(p_i2s[i2s_num]->hal));
i2s_hal_enable_rx_intr(&(p_i2s[i2s_num]->hal));
i2s_hal_start_rx_link(&(p_i2s[i2s_num]->hal), (uint32_t) p_i2s[i2s_num]->rx->desc[0]);
#endif
i2s_hal_start_rx(&(p_i2s[i2s_num]->hal));
}
/**
* @brief I2S tx stop
*
* @param i2s_num I2S device number
*/
static void i2s_tx_stop(i2s_port_t i2s_num)
{
i2s_hal_stop_tx(&(p_i2s[i2s_num]->hal));
#if SOC_GDMA_SUPPORTED
gdma_stop(p_i2s[i2s_num]->tx_dma_chan);
#else
i2s_hal_stop_tx_link(&(p_i2s[i2s_num]->hal));
i2s_hal_disable_tx_intr(&(p_i2s[i2s_num]->hal));
i2s_hal_disable_tx_dma(&(p_i2s[i2s_num]->hal));
#endif
}
/**
* @brief I2S rx stop
*
* @param i2s_num I2S device number
*/
static void i2s_rx_stop(i2s_port_t i2s_num)
{
i2s_hal_stop_rx(&(p_i2s[i2s_num]->hal));
#if SOC_GDMA_SUPPORTED
gdma_stop(p_i2s[i2s_num]->rx_dma_chan);
#else
i2s_hal_stop_rx_link(&(p_i2s[i2s_num]->hal));
i2s_hal_disable_rx_intr(&(p_i2s[i2s_num]->hal));
i2s_hal_disable_rx_dma(&(p_i2s[i2s_num]->hal));
#endif
}
/*-------------------------------------------------------------
I2S buffer operation
-------------------------------------------------------------*/
/**
* @brief I2S get DMA buffer size
*
* @param i2s_num I2S device number
* @return
* - DMA buffer size
*/
static inline uint32_t i2s_get_buf_size(i2s_port_t i2s_num)
{
/* Calculate bytes per sample, align to 16 bit */
uint32_t bytes_per_sample = ((p_i2s[i2s_num]->hal_cfg.sample_bits + 15) / 16) * 2;
/* The DMA buffer limitation is 4092 bytes */
uint32_t bytes_per_frame = bytes_per_sample * p_i2s[i2s_num]->hal_cfg.active_chan;
p_i2s[i2s_num]->dma_buf_len = (p_i2s[i2s_num]->dma_buf_len * bytes_per_frame > I2S_DMA_BUFFER_MAX_SIZE) ?
I2S_DMA_BUFFER_MAX_SIZE / bytes_per_frame : p_i2s[i2s_num]->dma_buf_len;
return p_i2s[i2s_num]->dma_buf_len * bytes_per_frame;
}
/**
* @brief Delete DMA buffer and descriptor
*
* @param i2s_num I2S device number
* @param dma_obj DMA object
* @return
* - ESP_OK DMA buffer delete success
* - ESP_ERR_INVALID_ARG dma_obj is NULL
*/
static esp_err_t i2s_delete_dma_buffer(i2s_port_t i2s_num, i2s_dma_t *dma_obj)
{
ESP_RETURN_ON_FALSE(dma_obj, ESP_ERR_INVALID_ARG, TAG, "I2S DMA object can't be NULL");
/* Loop to destroy every descriptor and buffer */
for (int cnt = 0; cnt < p_i2s[i2s_num]->dma_buf_count; cnt++) {
if (dma_obj->desc && dma_obj->desc[cnt]) {
free(dma_obj->desc[cnt]);
dma_obj->desc[cnt] = NULL;
}
if (dma_obj->buf && dma_obj->buf[cnt]) {
free(dma_obj->buf[cnt]);
dma_obj->buf[cnt] = NULL;
}
}
return ESP_OK;
}
/**
* @brief Allocate memory for DMA buffer and descriptor
*
* @param i2s_num I2S device number
* @param dma_obj DMA object
* @return
* - ESP_OK Allocate success
* - ESP_ERR_NO_MEM No memory for DMA buffer
*/
static esp_err_t i2s_alloc_dma_buffer(i2s_port_t i2s_num, i2s_dma_t *dma_obj)
{
esp_err_t ret = ESP_OK;
ESP_GOTO_ON_FALSE(dma_obj, ESP_ERR_INVALID_ARG, err, TAG, "I2S DMA object can't be NULL");
uint32_t buf_cnt = p_i2s[i2s_num]->dma_buf_count;
for (int cnt = 0; cnt < buf_cnt; cnt++) {
/* Allocate DMA buffer */
dma_obj->buf[cnt] = (char *) heap_caps_calloc(dma_obj->buf_size, sizeof(char), MALLOC_CAP_DMA);
ESP_GOTO_ON_FALSE(dma_obj->buf[cnt], ESP_ERR_NO_MEM, err, TAG, "Error malloc dma buffer");
/* Initialize DMA buffer to 0 */
memset(dma_obj->buf[cnt], 0, dma_obj->buf_size);
ESP_LOGD(TAG, "Addr[%d] = %d", cnt, (int)dma_obj->buf[cnt]);
/* Allocate DMA descpriptor */
dma_obj->desc[cnt] = (lldesc_t *) heap_caps_calloc(1, sizeof(lldesc_t), MALLOC_CAP_DMA);
ESP_GOTO_ON_FALSE(dma_obj->desc[cnt], ESP_ERR_NO_MEM, err, TAG, "Error malloc dma description entry");
}
/* DMA descriptor must be initialize after all descriptor has been created, otherwise they can't be linked together as a chain */
for (int cnt = 0; cnt < buf_cnt; cnt++) {
/* Initialize DMA descriptor */
dma_obj->desc[cnt]->owner = 1;
dma_obj->desc[cnt]->eof = 1;
dma_obj->desc[cnt]->sosf = 0;
dma_obj->desc[cnt]->length = dma_obj->buf_size;
dma_obj->desc[cnt]->size = dma_obj->buf_size;
dma_obj->desc[cnt]->buf = (uint8_t *) dma_obj->buf[cnt];
dma_obj->desc[cnt]->offset = 0;
/* Link to the next descriptor */
dma_obj->desc[cnt]->empty = (uint32_t)((cnt < (buf_cnt - 1)) ? (dma_obj->desc[cnt + 1]) : dma_obj->desc[0]);
}
ESP_LOGI(TAG, "DMA Malloc info, datalen=blocksize=%d, dma_buf_count=%d", dma_obj->buf_size, buf_cnt);
return ESP_OK;
err:
/* Delete DMA buffer if failed to allocate memory */
i2s_delete_dma_buffer(i2s_num, dma_obj);
return ret;
}
/**
* @brief Realloc I2S dma buffer
*
* @param i2s_num I2S device number
* @param dma_obj DMA object
*
* @return
* - ESP_OK Success
* - ESP_ERR_NO_MEM No memory for I2S tx dma buffer
*/
static esp_err_t i2s_realloc_dma_buffer(i2s_port_t i2s_num, i2s_dma_t *dma_obj)
{
ESP_RETURN_ON_FALSE(dma_obj, ESP_ERR_INVALID_ARG, TAG, "I2S DMA object can't be NULL");
/* Destroy old dma descriptor and buffer */
i2s_delete_dma_buffer(i2s_num, dma_obj);
/* Alloc new dma descriptor and buffer */
ESP_RETURN_ON_ERROR(i2s_alloc_dma_buffer(i2s_num, dma_obj), TAG, "Failed to allocate dma buffer");
return ESP_OK;
}
/**
* @brief I2S destroy the whole DMA object
*
* @param i2s_num I2S device number
* @param dma Secondary pointer to the DMA object
* @return
* - ESP_OK I2S DMA buffer has been destroyed successfully
* - ESP_ERR_INVALID_ARG I2S driver has not installed yet
*/
static esp_err_t i2s_destroy_dma_object(i2s_port_t i2s_num, i2s_dma_t **dma)
{
/* Check if DMA truely need destroy */
ESP_RETURN_ON_FALSE(p_i2s[i2s_num], ESP_ERR_INVALID_ARG, TAG, "I2S not initialized yet");
if (!(*dma)) {
return ESP_OK;
}
/* Destroy every descriptor and buffer */
i2s_delete_dma_buffer(i2s_num, (*dma));
/* Destroy descriptor pointer */
if ((*dma)->desc) {
free((*dma)->desc);
(*dma)->desc = NULL;
}
/* Destroy buffer pointer */
if ((*dma)->buf) {
free((*dma)->buf);
(*dma)->buf = NULL;
}
/* Delete DMA mux */
vSemaphoreDelete((*dma)->mux);
/* Delete DMA queue */
vQueueDelete((*dma)->queue);
/* Free DMA structure */
free(*dma);
*dma = NULL;
ESP_LOGI(TAG, "DMA queue destroyed");
return ESP_OK;
}
/**
* @brief Create I2S DMA object
* @note This function only create I2S DMA object but will not allocate memory
* for DMA descriptor and buffer, call 'i2s_alloc_dma_buffer' additionally to
* allocate DMA buffer
*
* @param i2s_num I2S device number
* @param dma The secondary pointer of DMA object
* @return
* - ESP_OK The pointer of DMA object
* - ESP_ERR_INVALID_ARG NULL pointer error or DMA object has been created
* - ESP_ERR_NO_MEM No memory for new DMA object
*/
static esp_err_t i2s_create_dma_object(i2s_port_t i2s_num, i2s_dma_t **dma)
{
ESP_RETURN_ON_FALSE(dma, ESP_ERR_INVALID_ARG, TAG, "DMA object secondary pointer is NULL");
ESP_RETURN_ON_FALSE((*dma == NULL), ESP_ERR_INVALID_ARG, TAG, "DMA object has been created");
uint32_t buf_cnt = p_i2s[i2s_num]->dma_buf_count;
/* Allocate new DMA structure */
*dma = (i2s_dma_t *) malloc(sizeof(i2s_dma_t));
ESP_RETURN_ON_FALSE(*dma, ESP_ERR_NO_MEM, TAG, "DMA object allocate failed");
/* Allocate DMA buffer poiter */
(*dma)->buf = (char **)heap_caps_calloc(buf_cnt, sizeof(char *), MALLOC_CAP_DMA);
if (!(*dma)->buf) {
goto err;
}
/* Allocate secondary pointer of DMA descriptor chain */
(*dma)->desc = (lldesc_t **)heap_caps_calloc(buf_cnt, sizeof(lldesc_t *), MALLOC_CAP_DMA);
if (!(*dma)->desc) {
goto err;
}
/* Create queue and mutex */
(*dma)->queue = xQueueCreate(buf_cnt - 1, sizeof(char *));
if (!(*dma)->queue) {
goto err;
}
(*dma)->mux = xSemaphoreCreateMutex();
if (!(*dma)->mux) {
goto err;
}
return ESP_OK;
err:
ESP_LOGE(TAG, "I2S DMA object create failed, preparing to uninstall");
/* Destroy DMA queue if failed to allocate memory */
i2s_destroy_dma_object(i2s_num, dma);
return ESP_ERR_NO_MEM;
}
/**
* @brief Zero the contents of the TX DMA buffer.
* @note Pushes zero-byte samples into the TX DMA buffer, until it is full.
*
* @param i2s_num I2S device number
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t i2s_zero_dma_buffer(i2s_port_t i2s_num)
{
ESP_RETURN_ON_FALSE((i2s_num < I2S_NUM_MAX), ESP_ERR_INVALID_ARG, TAG, "i2s_num error");
/* Clear I2S RX DMA buffer */
if (p_i2s[i2s_num]->rx && p_i2s[i2s_num]->rx->buf != NULL && p_i2s[i2s_num]->rx->buf_size != 0) {
for (int i = 0; i < p_i2s[i2s_num]->dma_buf_count; i++) {
memset(p_i2s[i2s_num]->rx->buf[i], 0, p_i2s[i2s_num]->rx->buf_size);
}
}
/* Clear I2S TX DMA buffer */
if (p_i2s[i2s_num]->tx && p_i2s[i2s_num]->tx->buf != NULL && p_i2s[i2s_num]->tx->buf_size != 0) {
/* Finish to write all tx data */
int bytes_left = (p_i2s[i2s_num]->tx->buf_size - p_i2s[i2s_num]->tx->rw_pos) % 4;
if (bytes_left) {
size_t zero_bytes = 0, bytes_written;
i2s_write(i2s_num, (void *)&zero_bytes, bytes_left, &bytes_written, portMAX_DELAY);
}
for (int i = 0; i < p_i2s[i2s_num]->dma_buf_count; i++) {
memset(p_i2s[i2s_num]->tx->buf[i], 0, p_i2s[i2s_num]->tx->buf_size);
}
}
return ESP_OK;
}
/*-------------------------------------------------------------
I2S clock operation
-------------------------------------------------------------*/
#if SOC_I2S_SUPPORTS_APLL
static esp_err_t i2s_set_apll_freq(uint32_t expt_freq, uint32_t *real_freq)
{
uint32_t rtc_xtal_freq = (uint32_t)rtc_clk_xtal_freq_get();
ESP_RETURN_ON_FALSE(rtc_xtal_freq, ESP_ERR_INVALID_STATE, TAG, "Get xtal clock frequency failed, it has not been set yet");
/* Reference formula: apll_freq = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536) / ((o_div + 2) * 2)
* ---------------------------------------------- -----------------
* 350 MHz <= Numerator <= 500 MHz Denominator
*/
int o_div = 0; // range: 0~31
int sdm0 = 0; // range: 0~255
int sdm1 = 0; // range: 0~255
int sdm2 = 0; // range: 0~63
/* Firstly try to satisfy the condition that the operation frequency of numerator should be greater than 350 MHz,
* i.e. xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536) >= 350 MHz, '+1' in the following code is to get the ceil value.
* With this condition, as we know the 'o_div' can't be greater than 31, then we can calculate the APLL minimum support frequency is
* 350 MHz / ((31 + 2) * 2) = 5303031 Hz (for ceil) */
o_div = (int)(SOC_APLL_MULTIPLIER_OUT_MIN_HZ / (float)(expt_freq * 2) + 1) - 2;
ESP_RETURN_ON_FALSE(o_div < 32, ESP_ERR_INVALID_ARG, TAG, "Expected frequency is too small");
if (o_div < 0) {
/* Try to satisfy the condition that the operation frequency of numerator should be smaller than 500 MHz,
* i.e. xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536) <= 500 MHz, we need to get the floor value in the following code.
* With this condition, as we know the 'o_div' can't be smaller than 0, then we can calculate the APLL maximum support frequency is
* 500 MHz / ((0 + 2) * 2) = 125000000 Hz */
o_div = (int)(SOC_APLL_MULTIPLIER_OUT_MAX_HZ / (float)(expt_freq * 2)) - 2;
ESP_RETURN_ON_FALSE(o_div >= 0, ESP_ERR_INVALID_ARG, TAG, "Expected frequency is too small");
}
// sdm2 = (int)(((o_div + 2) * 2) * apll_freq / xtal_freq) - 4
sdm2 = (int)(((o_div + 2) * 2 * expt_freq) / (rtc_xtal_freq * 1000000)) - 4;
// numrator = (((o_div + 2) * 2) * apll_freq / xtal_freq) - 4 - sdm2
float numrator = (((o_div + 2) * 2 * expt_freq) / ((float)rtc_xtal_freq * 1000000)) - 4 - sdm2;
// If numrator is bigger than 255/256 + 255/65536 + (1/65536)/2 = 1 - (1 / 65536)/2, carry bit to sdm2
if (numrator > 1.0 - (1.0 / 65536.0) / 2.0) {
sdm2++;
}
// If numrator is smaller than (1/65536)/2, keep sdm0 = sdm1 = 0, otherwise calculate sdm0 and sdm1
else if (numrator > (1.0 / 65536.0) / 2.0) {
// Get the closest sdm1
sdm1 = (int)(numrator * 65536.0 + 0.5) / 256;
// Get the closest sdm0
sdm0 = (int)(numrator * 65536.0 + 0.5) % 256;
}
rtc_clk_apll_enable(true, sdm0, sdm1, sdm2, o_div);
*real_freq = (uint32_t)(rtc_xtal_freq * 1000000 * (4 + sdm2 + (float)sdm1/256.0 + (float)sdm0/65536.0) / (((float)o_div + 2) * 2));
return ESP_OK;
}
#endif
/**
* @brief Config I2S source clock and get its frequency
*
* @param i2s_num I2S device number
* @param use_apll Whether use apll, only take effect when chip supports
* @param mclk module clock
*
* @return
* - 0 use I2S_CLK_APLL as clock source, no I2S system clock to set
* - I2S_LL_BASE_CLK use I2S_CLK_D2CLK as clock source, return APB clock frequency
*/
static uint32_t i2s_config_source_clock(i2s_port_t i2s_num, bool use_apll, uint32_t mclk)
{
#if SOC_I2S_SUPPORTS_APLL
if (use_apll) {
/* Calculate the expected APLL */
int div = (int)((SOC_APLL_MIN_HZ / mclk) + 1);
/* apll_freq = mclk * div
* when div = 1, hardware will still divide 2
* when div = 0, the final mclk will be unpredictable
* So the div here should be at least 2 */
div = div < 2 ? 2 : div;
uint32_t expt_freq = mclk * div;
/* Set APLL coefficients to the given frequency */
uint32_t real_freq = 0;
esp_err_t ret = i2s_set_apll_freq(expt_freq, &real_freq);
if (ret != ESP_OK) {
ESP_LOGE(TAG, "set APLL coefficients failed");
return 0;
}
ESP_LOGI(TAG, "APLL expected frequency is %d Hz, real frequency is %d Hz", expt_freq, real_freq);
/* Set I2S_APLL as I2S module clock source */
i2s_hal_set_clock_src(&(p_i2s[i2s_num]->hal), I2S_CLK_APLL);