From ea74850848d4e6bccbfa2b8707f77cebcc31ef03 Mon Sep 17 00:00:00 2001 From: me-no-dev Date: Mon, 3 Jun 2024 11:09:53 +0300 Subject: [PATCH] fix(esp): Fix getFlashChipMode breaking on S3 and C3 --- cores/esp32/Esp.cpp | 5 +++-- cores/esp32/chip-debug-report.cpp | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/cores/esp32/Esp.cpp b/cores/esp32/Esp.cpp index efe100b3475..a463fc16ba0 100644 --- a/cores/esp32/Esp.cpp +++ b/cores/esp32/Esp.cpp @@ -71,9 +71,10 @@ extern "C" { // REG_SPI_BASE is not defined for S3/C3 ?? #if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 -#ifndef REG_SPI_BASE -#define REG_SPI_BASE(i) (DR_REG_SPI1_BASE + (((i) > 1) ? (((i) * 0x1000) + 0x20000) : (((~(i)) & 1) * 0x1000))) +#ifdef REG_SPI_BASE +#undef REG_SPI_BASE #endif // REG_SPI_BASE +#define REG_SPI_BASE(i) (DR_REG_SPI1_BASE + (((i) > 1) ? (((i) * 0x1000) + 0x20000) : (((~(i)) & 1) * 0x1000))) #endif // TARGET /** diff --git a/cores/esp32/chip-debug-report.cpp b/cores/esp32/chip-debug-report.cpp index 8a3b8f58190..982b01ffa8f 100644 --- a/cores/esp32/chip-debug-report.cpp +++ b/cores/esp32/chip-debug-report.cpp @@ -113,9 +113,10 @@ static void printFlashInfo(void) { #endif // REG_SPI_BASE is not defined for S3/C3 ?? #if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 -#ifndef REG_SPI_BASE -#define REG_SPI_BASE(i) (DR_REG_SPI1_BASE + (((i) > 1) ? (((i) * 0x1000) + 0x20000) : (((~(i)) & 1) * 0x1000))) +#ifdef REG_SPI_BASE +#undef REG_SPI_BASE #endif // REG_SPI_BASE +#define REG_SPI_BASE(i) (DR_REG_SPI1_BASE + (((i) > 1) ? (((i) * 0x1000) + 0x20000) : (((~(i)) & 1) * 0x1000))) #endif // TARGET chip_report_printf("Flash Info:\n");