From c9e1366f41588348989d93510c288205e5f88774 Mon Sep 17 00:00:00 2001 From: Rodrigo Garcia Date: Wed, 21 Jun 2023 08:21:18 -0300 Subject: [PATCH 1/2] Fixes RMT Source Clock setting --- cores/esp32/esp32-hal-rmt.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/cores/esp32/esp32-hal-rmt.c b/cores/esp32/esp32-hal-rmt.c index 63ce3aa5956..6f6c6445f1a 100644 --- a/cores/esp32/esp32-hal-rmt.c +++ b/cores/esp32/esp32-hal-rmt.c @@ -478,11 +478,8 @@ bool rmtInit(int pin, rmt_ch_dir_t channel_direction, rmt_reserve_memsize_t mem_ // TX Channel rmt_tx_channel_config_t tx_cfg; tx_cfg.gpio_num = pin; -#if CONFIG_IDF_TARGET_ESP32C6 + // CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F80M for C6 -- CLK_XTAL for H2 tx_cfg.clk_src = RMT_CLK_SRC_DEFAULT; -#else - tx_cfg.clk_src = RMT_CLK_SRC_APB; -#endif tx_cfg.resolution_hz = frequency_Hz; tx_cfg.mem_block_symbols = SOC_RMT_MEM_WORDS_PER_CHANNEL * mem_size; tx_cfg.trans_queue_depth = 10; // maximum allowed @@ -507,11 +504,8 @@ bool rmtInit(int pin, rmt_ch_dir_t channel_direction, rmt_reserve_memsize_t mem_ // RX Channel rmt_rx_channel_config_t rx_cfg; rx_cfg.gpio_num = pin; -#if CONFIG_IDF_TARGET_ESP32C6 + // CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F80M for C6 -- CLK_XTAL for H2 rx_cfg.clk_src = RMT_CLK_SRC_DEFAULT; -#else - rx_cfg.clk_src = RMT_CLK_SRC_APB; -#endif rx_cfg.resolution_hz = frequency_Hz; rx_cfg.mem_block_symbols = SOC_RMT_MEM_WORDS_PER_CHANNEL * mem_size; rx_cfg.flags.invert_in = 0; From ba8317a1b8237c2170b77277ee0d5d0d301ff1f9 Mon Sep 17 00:00:00 2001 From: Rodrigo Garcia Date: Wed, 21 Jun 2023 08:27:15 -0300 Subject: [PATCH 2/2] Fixes UART Source Clock setting --- cores/esp32/esp32-hal-uart.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/cores/esp32/esp32-hal-uart.c b/cores/esp32/esp32-hal-uart.c index da3c2183ba8..efa618597e4 100644 --- a/cores/esp32/esp32-hal-uart.c +++ b/cores/esp32/esp32-hal-uart.c @@ -192,11 +192,8 @@ uart_t* uartBegin(uint8_t uart_nr, uint32_t baudrate, uint32_t config, int8_t rx uart_config.flow_ctrl = UART_HW_FLOWCTRL_DISABLE; uart_config.rx_flow_ctrl_thresh = rxfifo_full_thrhd; uart_config.baud_rate = baudrate; -#if CONFIG_IDF_TARGET_ESP32C6 + // CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F40M for C2 -- CLK_PLL_F48M for H2 -- CLK_PLL_F80M for C6 uart_config.source_clk = UART_SCLK_DEFAULT; -#else - uart_config.source_clk = UART_SCLK_APB; -#endif ESP_ERROR_CHECK(uart_driver_install(uart_nr, rx_buffer_size, tx_buffer_size, 20, &(uart->uart_event_queue), 0)); ESP_ERROR_CHECK(uart_param_config(uart_nr, &uart_config)); ESP_ERROR_CHECK(uart_set_pin(uart_nr, txPin, rxPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE));