diff --git a/cores/esp32/Esp.cpp b/cores/esp32/Esp.cpp index 4759697588d..dd2ae2d9521 100644 --- a/cores/esp32/Esp.cpp +++ b/cores/esp32/Esp.cpp @@ -268,7 +268,7 @@ uint8_t EspClass::getChipRevision(void) const char * EspClass::getChipModel(void) { #if CONFIG_IDF_TARGET_ESP32 - uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG); + uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_PACKAGE); uint32_t pkg_ver = chip_ver & 0x7; switch (pkg_ver) { case EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6 : diff --git a/cores/esp32/esp32-hal-psram.c b/cores/esp32/esp32-hal-psram.c index 1e8a681a9ee..0fda6e0d74d 100644 --- a/cores/esp32/esp32-hal-psram.c +++ b/cores/esp32/esp32-hal-psram.c @@ -50,7 +50,7 @@ bool psramInit(){ return false; } #if CONFIG_IDF_TARGET_ESP32 - uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG); + uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_PACKAGE); uint32_t pkg_ver = chip_ver & 0x7; if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 || pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) { spiramFailed = true; diff --git a/package/package_esp32_index.template.json b/package/package_esp32_index.template.json index 544a1868048..d698016d643 100644 --- a/package/package_esp32_index.template.json +++ b/package/package_esp32_index.template.json @@ -69,7 +69,7 @@ { "packager": "esp32", "name": "openocd-esp32", - "version": "v0.11.0-esp32-20221026" + "version": "v0.12.0-esp32-20230313" }, { "packager": "esp32", @@ -464,56 +464,56 @@ }, { "name": "openocd-esp32", - "version": "v0.11.0-esp32-20221026", + "version": "v0.12.0-esp32-20230313", "systems": [ { "host": "x86_64-pc-linux-gnu", - "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.11.0-esp32-20221026/openocd-esp32-linux-amd64-0.11.0-esp32-20221026.tar.gz", - "archiveFileName": "openocd-esp32-linux-amd64-0.11.0-esp32-20221026.tar.gz", - "checksum": "SHA-256:ce63e9b1dfab60cc62da5dc2abcc22ba7036c42afe74671c787eb026744e7d0b", - "size": "2051435" + "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20230313/openocd-esp32-linux-amd64-0.12.0-esp32-20230313.tar.gz", + "archiveFileName": "openocd-esp32-linux-amd64-0.12.0-esp32-20230313.tar.gz", + "checksum": "SHA-256:a62e560eba02eeca82d52b8eea8ef1e432e083242ce6b01033815e9afad4343e", + "size": "2087489" }, { "host": "aarch64-linux-gnu", - "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.11.0-esp32-20221026/openocd-esp32-linux-arm64-0.11.0-esp32-20221026.tar.gz", - "archiveFileName": "openocd-esp32-linux-arm64-0.11.0-esp32-20221026.tar.gz", - "checksum": "SHA-256:fe60a3a603e8c6bee47367e40fcb8c0da3a38e01163e9674ebc919b067700506", - "size": "1993843" + "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20230313/openocd-esp32-linux-arm64-0.12.0-esp32-20230313.tar.gz", + "archiveFileName": "openocd-esp32-linux-arm64-0.12.0-esp32-20230313.tar.gz", + "checksum": "SHA-256:12570d3513ace5a8f6f4afb53605abc2ed572243fa36f1c797ae7f7a8558deed", + "size": "1984119" }, { "host": "arm-linux-gnueabihf", - "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.11.0-esp32-20221026/openocd-esp32-linux-armel-0.11.0-esp32-20221026.tar.gz", - "archiveFileName": "openocd-esp32-linux-armel-0.11.0-esp32-20221026.tar.gz", - "checksum": "SHA-256:6ef76101cca196a4be30fc74f191eff34abb423e32930a383012b866c9b76135", - "size": "2092111" + "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20230313/openocd-esp32-linux-armel-0.12.0-esp32-20230313.tar.gz", + "archiveFileName": "openocd-esp32-linux-armel-0.12.0-esp32-20230313.tar.gz", + "checksum": "SHA-256:e1b300a87f83a665d33ae9d8f7a47b883f1d0a20a90c30cdaa9ed0750ddc7a61", + "size": "2126878" }, { "host": "x86_64-apple-darwin", - "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.11.0-esp32-20221026/openocd-esp32-macos-0.11.0-esp32-20221026.tar.gz", - "archiveFileName": "openocd-esp32-macos-0.11.0-esp32-20221026.tar.gz", - "checksum": "SHA-256:8edc666a0a230432554b73df7c62e0b5ec21fb018e7fda13b11a7ca8b6c1763b", - "size": "2199855" + "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20230313/openocd-esp32-macos-0.12.0-esp32-20230313.tar.gz", + "archiveFileName": "openocd-esp32-macos-0.12.0-esp32-20230313.tar.gz", + "checksum": "SHA-256:3c462379fdca456eb9fcd696f68b489602cd51d80ebc7b45fc9f0c41404f382a", + "size": "2191546" }, { "host": "arm64-apple-darwin", - "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.11.0-esp32-20221026/openocd-esp32-macos-arm64-0.11.0-esp32-20221026.tar.gz", - "archiveFileName": "openocd-esp32-macos-arm64-0.11.0-esp32-20221026.tar.gz", - "checksum": "SHA-256:c426c0158ba6488e2f432f7c5b22e79155b5b0fae6d1ad5bbd7894723b43aa12", - "size": "2247179" + "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20230313/openocd-esp32-macos-arm64-0.12.0-esp32-20230313.tar.gz", + "archiveFileName": "openocd-esp32-macos-arm64-0.12.0-esp32-20230313.tar.gz", + "checksum": "SHA-256:d19628bd64008298180a93c36fb8a3f0586c13800f5bb66c0a0f25c7eb9a8d6e", + "size": "2239378" }, { "host": "i686-mingw32", - "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.11.0-esp32-20221026/openocd-esp32-win32-0.11.0-esp32-20221026.zip", - "archiveFileName": "openocd-esp32-win32-0.11.0-esp32-20221026.zip", - "checksum": "SHA-256:e0e789d35308c029c6b53457cf4a42a5620cb1a3014740026c089c2ed4fd77b2", - "size": "2493214" + "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20230313/openocd-esp32-win32-0.12.0-esp32-20230313.zip", + "archiveFileName": "openocd-esp32-win32-0.12.0-esp32-20230313.zip", + "checksum": "SHA-256:46580ccb9cc00d76c419636b884c5cc57422124a0a0f755595218f30b92884fa", + "size": "2492151" }, { "host": "x86_64-mingw32", - "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.11.0-esp32-20221026/openocd-esp32-win32-0.11.0-esp32-20221026.zip", - "archiveFileName": "openocd-esp32-win32-0.11.0-esp32-20221026.zip", - "checksum": "SHA-256:e0e789d35308c029c6b53457cf4a42a5620cb1a3014740026c089c2ed4fd77b2", - "size": "2493214" + "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20230313/openocd-esp32-win32-0.12.0-esp32-20230313.zip", + "archiveFileName": "openocd-esp32-win32-0.12.0-esp32-20230313.zip", + "checksum": "SHA-256:46580ccb9cc00d76c419636b884c5cc57422124a0a0f755595218f30b92884fa", + "size": "2492151" } ] }, diff --git a/tools/sdk/esp32/bin/bootloader_dio_40m.elf b/tools/sdk/esp32/bin/bootloader_dio_40m.elf index 131de91ef06..76878b71ad2 100755 Binary files a/tools/sdk/esp32/bin/bootloader_dio_40m.elf and b/tools/sdk/esp32/bin/bootloader_dio_40m.elf differ diff --git a/tools/sdk/esp32/bin/bootloader_dio_80m.elf b/tools/sdk/esp32/bin/bootloader_dio_80m.elf index 8357d15cce7..e33088ce1ab 100755 Binary files a/tools/sdk/esp32/bin/bootloader_dio_80m.elf and b/tools/sdk/esp32/bin/bootloader_dio_80m.elf differ diff --git a/tools/sdk/esp32/bin/bootloader_dout_40m.elf b/tools/sdk/esp32/bin/bootloader_dout_40m.elf index 131de91ef06..76878b71ad2 100755 Binary files a/tools/sdk/esp32/bin/bootloader_dout_40m.elf and b/tools/sdk/esp32/bin/bootloader_dout_40m.elf differ diff --git a/tools/sdk/esp32/bin/bootloader_dout_80m.elf b/tools/sdk/esp32/bin/bootloader_dout_80m.elf index 8357d15cce7..e33088ce1ab 100755 Binary files a/tools/sdk/esp32/bin/bootloader_dout_80m.elf and b/tools/sdk/esp32/bin/bootloader_dout_80m.elf differ diff --git a/tools/sdk/esp32/bin/bootloader_qio_40m.elf b/tools/sdk/esp32/bin/bootloader_qio_40m.elf index 887dce4466c..e1a98c5b614 100755 Binary files a/tools/sdk/esp32/bin/bootloader_qio_40m.elf and b/tools/sdk/esp32/bin/bootloader_qio_40m.elf differ diff --git a/tools/sdk/esp32/bin/bootloader_qio_80m.elf b/tools/sdk/esp32/bin/bootloader_qio_80m.elf index d2bee14a831..f68c263900a 100755 Binary files a/tools/sdk/esp32/bin/bootloader_qio_80m.elf and b/tools/sdk/esp32/bin/bootloader_qio_80m.elf differ diff --git a/tools/sdk/esp32/bin/bootloader_qout_40m.elf b/tools/sdk/esp32/bin/bootloader_qout_40m.elf index 0a16fee3e6a..824d400299f 100755 Binary files a/tools/sdk/esp32/bin/bootloader_qout_40m.elf and b/tools/sdk/esp32/bin/bootloader_qout_40m.elf differ diff --git a/tools/sdk/esp32/bin/bootloader_qout_80m.elf b/tools/sdk/esp32/bin/bootloader_qout_80m.elf index 2b4afab91ed..5f2c347e524 100755 Binary files a/tools/sdk/esp32/bin/bootloader_qout_80m.elf and b/tools/sdk/esp32/bin/bootloader_qout_80m.elf differ diff --git a/tools/sdk/esp32/dio_qspi/include/sdkconfig.h b/tools/sdk/esp32/dio_qspi/include/sdkconfig.h index 094f06e8846..932e79014af 100644 --- a/tools/sdk/esp32/dio_qspi/include/sdkconfig.h +++ b/tools/sdk/esp32/dio_qspi/include/sdkconfig.h @@ -229,6 +229,7 @@ #define CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE 1 #define CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP 1 #define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x10 +#define CONFIG_BOOTLOADER_RESERVE_RTC_MEM 1 #define CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT 1 #define CONFIG_SECURE_BOOT_V1_SUPPORTED 1 #define CONFIG_APP_COMPILE_TIME_DATE 1 @@ -1078,5 +1079,5 @@ #define CONFIG_WARN_WRITE_STRINGS CONFIG_COMPILER_WARN_WRITE_STRINGS #define CONFIG_WPA_MBEDTLS_CRYPTO CONFIG_ESP_WIFI_MBEDTLS_CRYPTO #define CONFIG_WPA_MBEDTLS_TLS_CLIENT CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT -#define CONFIG_ARDUINO_IDF_COMMIT "" +#define CONFIG_ARDUINO_IDF_COMMIT "420ebd208a" #define CONFIG_ARDUINO_IDF_BRANCH "release/v5.1" diff --git a/tools/sdk/esp32/dio_qspi/libspi_flash.a b/tools/sdk/esp32/dio_qspi/libspi_flash.a index 9408645f6b5..930e332824d 100644 Binary files a/tools/sdk/esp32/dio_qspi/libspi_flash.a and b/tools/sdk/esp32/dio_qspi/libspi_flash.a differ diff --git a/tools/sdk/esp32/dout_qspi/include/sdkconfig.h b/tools/sdk/esp32/dout_qspi/include/sdkconfig.h index 539174ee15d..78297d6d8f2 100644 --- a/tools/sdk/esp32/dout_qspi/include/sdkconfig.h +++ b/tools/sdk/esp32/dout_qspi/include/sdkconfig.h @@ -229,6 +229,7 @@ #define CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE 1 #define CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP 1 #define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x10 +#define CONFIG_BOOTLOADER_RESERVE_RTC_MEM 1 #define CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT 1 #define CONFIG_SECURE_BOOT_V1_SUPPORTED 1 #define CONFIG_APP_COMPILE_TIME_DATE 1 @@ -1078,5 +1079,5 @@ #define CONFIG_WARN_WRITE_STRINGS CONFIG_COMPILER_WARN_WRITE_STRINGS #define CONFIG_WPA_MBEDTLS_CRYPTO CONFIG_ESP_WIFI_MBEDTLS_CRYPTO #define CONFIG_WPA_MBEDTLS_TLS_CLIENT CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT -#define CONFIG_ARDUINO_IDF_COMMIT "" +#define CONFIG_ARDUINO_IDF_COMMIT "420ebd208a" #define CONFIG_ARDUINO_IDF_BRANCH "release/v5.1" diff --git a/tools/sdk/esp32/dout_qspi/libspi_flash.a b/tools/sdk/esp32/dout_qspi/libspi_flash.a index e4906f359d1..f1e3bf5dd52 100644 Binary files a/tools/sdk/esp32/dout_qspi/libspi_flash.a and b/tools/sdk/esp32/dout_qspi/libspi_flash.a differ diff --git a/tools/sdk/esp32/flags/defines b/tools/sdk/esp32/flags/defines index 5847d2162fb..2c8b36ae704 100644 --- a/tools/sdk/esp32/flags/defines +++ b/tools/sdk/esp32/flags/defines @@ -1 +1 @@ --DESP_PLATFORM -DIDF_VER=\"v5.1-dev-4124-gbb9200acec\" -DMBEDTLS_CONFIG_FILE=\"mbedtls/esp_config.h\" -DSOC_MMU_PAGE_SIZE=CONFIG_MMU_PAGE_SIZE -DUNITY_INCLUDE_CONFIG_H -D_GNU_SOURCE -D_POSIX_READER_WRITER_LOCKS -DconfigENABLE_FREERTOS_DEBUG_OCDAWARE=1 \ No newline at end of file +-DESP_PLATFORM -DIDF_VER=\"v5.1-dev-4528-g420ebd208a\" -DMBEDTLS_CONFIG_FILE=\"mbedtls/esp_config.h\" -DSOC_MMU_PAGE_SIZE=CONFIG_MMU_PAGE_SIZE -DUNITY_INCLUDE_CONFIG_H -D_GNU_SOURCE -D_POSIX_READER_WRITER_LOCKS -DconfigENABLE_FREERTOS_DEBUG_OCDAWARE=1 \ No newline at end of file diff --git a/tools/sdk/esp32/flags/includes b/tools/sdk/esp32/flags/includes index 774b3b2bec4..4ee14c2dbe6 100644 --- a/tools/sdk/esp32/flags/includes +++ b/tools/sdk/esp32/flags/includes @@ -1 +1 @@ --iwithprefixbefore newlib/platform_include -iwithprefixbefore freertos/FreeRTOS-Kernel/include -iwithprefixbefore freertos/FreeRTOS-Kernel/portable/xtensa/include -iwithprefixbefore freertos/esp_additions/include/freertos -iwithprefixbefore freertos/esp_additions/include -iwithprefixbefore esp_hw_support/include -iwithprefixbefore esp_hw_support/include/soc -iwithprefixbefore esp_hw_support/include/soc/esp32 -iwithprefixbefore esp_hw_support/port/esp32 -iwithprefixbefore heap/include -iwithprefixbefore log/include -iwithprefixbefore soc/include -iwithprefixbefore soc/esp32 -iwithprefixbefore soc/esp32/include -iwithprefixbefore hal/esp32/include -iwithprefixbefore hal/include -iwithprefixbefore hal/platform_port/include -iwithprefixbefore esp_rom/include -iwithprefixbefore esp_rom/include/esp32 -iwithprefixbefore esp_rom/esp32 -iwithprefixbefore esp_common/include -iwithprefixbefore esp_system/include -iwithprefixbefore esp_system/port/soc -iwithprefixbefore esp_system/port/include/private -iwithprefixbefore xtensa/include -iwithprefixbefore xtensa/esp32/include -iwithprefixbefore lwip/include -iwithprefixbefore lwip/include/apps -iwithprefixbefore lwip/include/apps/sntp -iwithprefixbefore lwip/lwip/src/include -iwithprefixbefore lwip/port/include -iwithprefixbefore lwip/port/freertos/include -iwithprefixbefore lwip/port/esp32xx/include -iwithprefixbefore lwip/port/esp32xx/include/arch -iwithprefixbefore espressif__mdns/include -iwithprefixbefore console -iwithprefixbefore vfs/include -iwithprefixbefore esp_netif/include -iwithprefixbefore esp_event/include -iwithprefixbefore esp_ringbuf/include -iwithprefixbefore efuse/include -iwithprefixbefore efuse/esp32/include -iwithprefixbefore driver/include -iwithprefixbefore driver/deprecated -iwithprefixbefore driver/analog_comparator/include -iwithprefixbefore driver/dac/include -iwithprefixbefore driver/gpio/include -iwithprefixbefore driver/gptimer/include -iwithprefixbefore driver/i2c/include -iwithprefixbefore driver/i2s/include -iwithprefixbefore driver/ledc/include -iwithprefixbefore driver/mcpwm/include -iwithprefixbefore driver/parlio/include -iwithprefixbefore driver/pcnt/include -iwithprefixbefore driver/rmt/include -iwithprefixbefore driver/sdio_slave/include -iwithprefixbefore driver/sdmmc/include -iwithprefixbefore driver/sigma_delta/include -iwithprefixbefore driver/spi/include -iwithprefixbefore driver/temperature_sensor/include -iwithprefixbefore driver/touch_sensor/include -iwithprefixbefore driver/twai/include -iwithprefixbefore driver/uart/include -iwithprefixbefore driver/usb_serial_jtag/include -iwithprefixbefore driver/touch_sensor/esp32/include -iwithprefixbefore esp_pm/include -iwithprefixbefore mbedtls/port/include -iwithprefixbefore mbedtls/mbedtls/include -iwithprefixbefore mbedtls/mbedtls/library -iwithprefixbefore mbedtls/esp_crt_bundle/include -iwithprefixbefore esp_app_format/include -iwithprefixbefore bootloader_support/include -iwithprefixbefore bootloader_support/bootloader_flash/include -iwithprefixbefore esp_partition/include -iwithprefixbefore app_update/include -iwithprefixbefore esp_mm/include -iwithprefixbefore spi_flash/include -iwithprefixbefore pthread/include -iwithprefixbefore esp_timer/include -iwithprefixbefore app_trace/include -iwithprefixbefore nvs_flash/include -iwithprefixbefore esp_phy/include -iwithprefixbefore esp_phy/esp32/include -iwithprefixbefore wpa_supplicant/include -iwithprefixbefore wpa_supplicant/port/include -iwithprefixbefore wpa_supplicant/esp_supplicant/include -iwithprefixbefore esp_coex/include -iwithprefixbefore esp_wifi/include -iwithprefixbefore esp_wifi/wifi_apps/include -iwithprefixbefore bt/include/esp32/include -iwithprefixbefore bt/common/osi/include -iwithprefixbefore bt/common/api/include/api -iwithprefixbefore bt/common/btc/profile/esp/blufi/include -iwithprefixbefore bt/common/btc/profile/esp/include -iwithprefixbefore bt/host/bluedroid/api/include/api -iwithprefixbefore bt/esp_ble_mesh/mesh_common/include -iwithprefixbefore bt/esp_ble_mesh/mesh_common/tinycrypt/include -iwithprefixbefore bt/esp_ble_mesh/mesh_core -iwithprefixbefore bt/esp_ble_mesh/mesh_core/include -iwithprefixbefore bt/esp_ble_mesh/mesh_core/storage -iwithprefixbefore bt/esp_ble_mesh/btc/include -iwithprefixbefore bt/esp_ble_mesh/mesh_models/common/include -iwithprefixbefore bt/esp_ble_mesh/mesh_models/client/include -iwithprefixbefore bt/esp_ble_mesh/mesh_models/server/include -iwithprefixbefore bt/esp_ble_mesh/api/core/include -iwithprefixbefore bt/esp_ble_mesh/api/models/include -iwithprefixbefore bt/esp_ble_mesh/api -iwithprefixbefore bt/porting/ext/tinycrypt/include -iwithprefixbefore unity/include -iwithprefixbefore unity/unity/src -iwithprefixbefore cmock/CMock/src -iwithprefixbefore http_parser -iwithprefixbefore esp-tls -iwithprefixbefore esp-tls/esp-tls-crypto -iwithprefixbefore esp_adc/include -iwithprefixbefore esp_adc/interface -iwithprefixbefore esp_adc/esp32/include -iwithprefixbefore esp_adc/deprecated/include -iwithprefixbefore esp_eth/include -iwithprefixbefore esp_gdbstub/include -iwithprefixbefore esp_gdbstub/xtensa -iwithprefixbefore esp_gdbstub/esp32 -iwithprefixbefore esp_hid/include -iwithprefixbefore tcp_transport/include -iwithprefixbefore esp_http_client/include -iwithprefixbefore esp_http_server/include -iwithprefixbefore esp_https_ota/include -iwithprefixbefore esp_https_server/include -iwithprefixbefore esp_lcd/include -iwithprefixbefore esp_lcd/interface -iwithprefixbefore protobuf-c/protobuf-c -iwithprefixbefore protocomm/include/common -iwithprefixbefore protocomm/include/security -iwithprefixbefore protocomm/include/transports -iwithprefixbefore esp_local_ctrl/include -iwithprefixbefore esp_psram/include -iwithprefixbefore espcoredump/include -iwithprefixbefore espcoredump/include/port/xtensa -iwithprefixbefore wear_levelling/include -iwithprefixbefore sdmmc/include -iwithprefixbefore fatfs/diskio -iwithprefixbefore fatfs/vfs -iwithprefixbefore fatfs/src -iwithprefixbefore idf_test/include -iwithprefixbefore idf_test/include/esp32 -iwithprefixbefore ieee802154/include -iwithprefixbefore json/cJSON -iwithprefixbefore mqtt/esp-mqtt/include -iwithprefixbefore perfmon/include -iwithprefixbefore spiffs/include -iwithprefixbefore ulp/ulp_common/include -iwithprefixbefore ulp/ulp_common/include/esp32 -iwithprefixbefore ulp/ulp_fsm/include -iwithprefixbefore ulp/ulp_fsm/include/esp32 -iwithprefixbefore wifi_provisioning/include -iwithprefixbefore cbor/port/include -iwithprefixbefore rmaker_common/include -iwithprefixbefore esp_diagnostics/include -iwithprefixbefore rtc_store/include -iwithprefixbefore esp_insights/include -iwithprefixbefore json_parser/upstream/include -iwithprefixbefore json_parser/upstream -iwithprefixbefore json_generator/upstream -iwithprefixbefore esp_schedule/include -iwithprefixbefore espressif__esp_secure_cert_mgr/include -iwithprefixbefore esp_rainmaker/include -iwithprefixbefore gpio_button/button/include -iwithprefixbefore qrcode/include -iwithprefixbefore ws2812_led -iwithprefixbefore esp_littlefs/include -iwithprefixbefore esp-dl/include -iwithprefixbefore esp-dl/include/tool -iwithprefixbefore esp-dl/include/typedef -iwithprefixbefore esp-dl/include/image -iwithprefixbefore esp-dl/include/math -iwithprefixbefore esp-dl/include/nn -iwithprefixbefore esp-dl/include/layer -iwithprefixbefore esp-dl/include/detect -iwithprefixbefore esp-dl/include/model_zoo -iwithprefixbefore esp-sr/src/include -iwithprefixbefore esp-sr/esp-tts/esp_tts_chinese/include -iwithprefixbefore esp-sr/include/esp32 -iwithprefixbefore esp32-camera/driver/include -iwithprefixbefore esp32-camera/conversions/include -iwithprefixbefore espressif__esp-dsp/modules/dotprod/include -iwithprefixbefore espressif__esp-dsp/modules/support/include -iwithprefixbefore espressif__esp-dsp/modules/windows/include -iwithprefixbefore espressif__esp-dsp/modules/windows/hann/include -iwithprefixbefore espressif__esp-dsp/modules/windows/blackman/include -iwithprefixbefore espressif__esp-dsp/modules/windows/blackman_harris/include -iwithprefixbefore espressif__esp-dsp/modules/windows/blackman_nuttall/include -iwithprefixbefore espressif__esp-dsp/modules/windows/nuttall/include -iwithprefixbefore espressif__esp-dsp/modules/windows/flat_top/include -iwithprefixbefore espressif__esp-dsp/modules/iir/include -iwithprefixbefore espressif__esp-dsp/modules/fir/include -iwithprefixbefore espressif__esp-dsp/modules/math/include -iwithprefixbefore espressif__esp-dsp/modules/math/add/include -iwithprefixbefore espressif__esp-dsp/modules/math/sub/include -iwithprefixbefore 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esp-sr/src/include -iwithprefixbefore esp-sr/esp-tts/esp_tts_chinese/include -iwithprefixbefore esp-sr/include/esp32 -iwithprefixbefore esp32-camera/driver/include -iwithprefixbefore esp32-camera/conversions/include -iwithprefixbefore fb_gfx/include \ No newline at end of file diff --git a/tools/sdk/esp32/flags/ld_flags b/tools/sdk/esp32/flags/ld_flags index e4982703cc4..250e991e625 100644 --- a/tools/sdk/esp32/flags/ld_flags +++ b/tools/sdk/esp32/flags/ld_flags @@ -1 +1 @@ --mlongcalls -Wno-frame-address -Wl,--cref -Wl,--defsym=IDF_TARGET_ESP32=0 -Wl,--no-warn-rwx-segments -fno-rtti -fno-lto -Wl,--gc-sections -Wl,--warn-common -Wl,--wrap=esp_log_write -Wl,--wrap=esp_log_writev -Wl,--wrap=log_printf -u ld_include_hli_vectors_bt -u _Z5setupv -u _Z4loopv -u esp_app_desc -u pthread_include_pthread_impl -u pthread_include_pthread_cond_impl -u pthread_include_pthread_local_storage_impl -u pthread_include_pthread_rwlock_impl -u ld_include_highint_hdl -u start_app -u start_app_other_cores -u __ubsan_include -Wl,--wrap=longjmp -u __assert_func -u esp_dport_access_reg_read -Wl,--undefined=uxTopUsedPriority -Wl,--undefined=FreeRTOS_openocd_params -u app_main -u newlib_include_heap_impl -u newlib_include_syscalls_impl -u newlib_include_pthread_impl -u newlib_include_assert_impl -u __cxa_guard_dummy -u include_esp_phy_override -u vfs_include_syscalls_impl \ No newline at end of file +-mlongcalls -Wno-frame-address -Wl,--cref -Wl,--defsym=IDF_TARGET_ESP32=0 -Wl,--no-warn-rwx-segments -fno-rtti -fno-lto -Wl,--gc-sections -Wl,--warn-common -Wl,--wrap=esp_log_write -Wl,--wrap=esp_log_writev -Wl,--wrap=log_printf -u ld_include_hli_vectors_bt -u _Z5setupv -u _Z4loopv -u esp_app_desc -u pthread_include_pthread_impl -u pthread_include_pthread_cond_impl -u pthread_include_pthread_local_storage_impl -u pthread_include_pthread_rwlock_impl -u pthread_include_pthread_semaphore_impl -u ld_include_highint_hdl -u start_app -u start_app_other_cores -u __ubsan_include -Wl,--wrap=longjmp -u __assert_func -u esp_dport_access_reg_read -Wl,--undefined=uxTopUsedPriority -Wl,--undefined=FreeRTOS_openocd_params -u app_main -u newlib_include_heap_impl -u newlib_include_syscalls_impl -u newlib_include_pthread_impl -u newlib_include_assert_impl -u __cxa_guard_dummy -u include_esp_phy_override -u vfs_include_syscalls_impl \ No newline at end of file diff --git a/tools/sdk/esp32/flags/ld_libs b/tools/sdk/esp32/flags/ld_libs index e66b82a2da9..5488324f271 100644 --- a/tools/sdk/esp32/flags/ld_libs +++ b/tools/sdk/esp32/flags/ld_libs @@ -1 +1 @@ --lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lapp_trace -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lbt -lunity -lcmock -lconsole -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -lesp_hid -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_https_server -lesp_lcd -lprotobuf-c -lprotocomm -lesp_local_ctrl -lesp_psram -lespcoredump -lwear_levelling -lsdmmc -lfatfs -ljson -lmqtt -lperfmon -lspiffs -lulp -lwifi_provisioning -lespressif__mdns -lcbor -lrmaker_common -lesp_diagnostics -lrtc_store -lesp_insights -ljson_parser -ljson_generator -lesp_schedule -lespressif__esp_secure_cert_mgr -lesp_rainmaker -lgpio_button -lqrcode -lws2812_led -lesp-sr -lesp32-camera -lesp_littlefs -lespressif__esp-dsp -lfb_gfx -lapp_trace -lapp_trace -lcmock -lunity -lesp_lcd -lperfmon -lesp_hid -lfatfs -lwear_levelling -lsdmmc -lesp_insights -lcbor -lesp_diagnostics -lrtc_store -lesp_rainmaker -lesp_local_ctrl -lesp_https_server -lwifi_provisioning -lprotocomm -lbt -lbtdm_app -lprotobuf-c -lespressif__mdns -ljson_parser -ljson_generator -lesp_schedule -lespressif__esp_secure_cert_mgr -lqrcode -lrmaker_common -lconsole -lmqtt -lcat_face_detect -lhuman_face_detect -lcolor_detect -lmfn -ldl -lmultinet -lesp_audio_processor -lesp_audio_front_end -lwakenet -lesp-sr -lmultinet -lesp_audio_processor -lesp_audio_front_end -lwakenet -ljson -lspiffs -ldl_lib -lc_speech_features -lwakeword_model -lmultinet2_ch -lesp_tts_chinese -lvoice_set_xiaole -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxt_hal -lc -lm -lnewlib -lstdc++ -lpthread -lgcc -lcxx -lphy -lrtc -lesp_phy -lphy -lrtc -lesp_phy -lphy -lrtc \ No newline at end of file +-lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lapp_trace -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lbt -lunity -lcmock -lconsole -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -lesp_hid -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_https_server -lesp_psram -lesp_lcd -lprotobuf-c -lprotocomm -lesp_local_ctrl -lespcoredump -lwear_levelling -lsdmmc -lfatfs -ljson -lmqtt -lperfmon -lspiffs -lulp -lwifi_provisioning -lespressif__mdns -lcbor -lrmaker_common -lesp_diagnostics -lrtc_store -lesp_insights -ljson_parser -ljson_generator -lesp_schedule -lespressif__esp_secure_cert_mgr -lesp_rainmaker -lgpio_button -lqrcode -lws2812_led -lespressif__esp-dsp -lesp-sr -lesp32-camera -lesp_littlefs -lfb_gfx -lapp_trace -lapp_trace -lcmock -lunity -lesp_lcd -lperfmon -lesp_hid -lfatfs -lwear_levelling -lsdmmc -lesp_insights -lcbor -lesp_diagnostics -lrtc_store -lesp_rainmaker -lesp_local_ctrl -lesp_https_server -lwifi_provisioning -lprotocomm -lbt -lbtdm_app -lprotobuf-c -lespressif__mdns -ljson_parser -ljson_generator -lesp_schedule -lespressif__esp_secure_cert_mgr -lqrcode -lrmaker_common -lconsole -lmqtt -lcat_face_detect -lhuman_face_detect -lcolor_detect -lmfn -ldl -lmultinet -lesp_audio_processor -lesp_audio_front_end -lwakenet -lesp-sr -lmultinet -lesp_audio_processor -lesp_audio_front_end -lwakenet -ljson -lspiffs -lespressif__esp-dsp -ldl_lib -lc_speech_features -lwakeword_model -lmultinet2_ch -lesp_tts_chinese -lvoice_set_xiaole -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxt_hal -lc -lm -lnewlib -lstdc++ -lpthread -lgcc -lcxx -lphy -lrtc -lesp_phy -lphy -lrtc -lesp_phy -lphy -lrtc \ No newline at end of file diff --git a/tools/sdk/esp32/include/bootloader_support/include/bootloader_common.h b/tools/sdk/esp32/include/bootloader_support/include/bootloader_common.h index 6145a72ef8e..b74acf560c7 100644 --- a/tools/sdk/esp32/include/bootloader_support/include/bootloader_common.h +++ b/tools/sdk/esp32/include/bootloader_support/include/bootloader_common.h @@ -173,7 +173,7 @@ esp_err_t bootloader_common_check_chip_validity(const esp_image_header_t* img_hd */ void bootloader_common_vddsdio_configure(void); -#if defined( CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP ) || defined( CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC ) +#if CONFIG_BOOTLOADER_RESERVE_RTC_MEM /** * @brief Returns partition from rtc_retain_mem * @@ -223,6 +223,21 @@ void bootloader_common_reset_rtc_retain_mem(void); */ uint16_t bootloader_common_get_rtc_retain_mem_reboot_counter(void); +/** + * @brief Returns True if Factory reset has happened + * + * Reset the status after reading it. + * + * @return True: Factory reset has happened + * False: No Factory reset + */ +bool bootloader_common_get_rtc_retain_mem_factory_reset_state(void); + +/** + * @brief Sets Factory reset status + */ +void bootloader_common_set_rtc_retain_mem_factory_reset_state(void); + /** * @brief Returns rtc_retain_mem * @@ -233,7 +248,7 @@ uint16_t bootloader_common_get_rtc_retain_mem_reboot_counter(void); */ rtc_retain_mem_t* bootloader_common_get_rtc_retain_mem(void); -#endif +#endif // CONFIG_BOOTLOADER_RESERVE_RTC_MEM #ifdef __cplusplus } diff --git a/tools/sdk/esp32/include/bootloader_support/include/esp_image_format.h b/tools/sdk/esp32/include/bootloader_support/include/esp_image_format.h index 20545f5d7f6..5ec2ff0282f 100644 --- a/tools/sdk/esp32/include/bootloader_support/include/esp_image_format.h +++ b/tools/sdk/esp32/include/bootloader_support/include/esp_image_format.h @@ -47,7 +47,14 @@ typedef enum { typedef struct { esp_partition_pos_t partition; /*!< Partition of application which worked before goes to the deep sleep. */ uint16_t reboot_counter; /*!< Reboot counter. Reset only when power is off. */ - uint16_t reserve; /*!< Reserve */ + union { + struct { + uint8_t factory_reset_state : 1; /* True when Factory reset has occurred */ + uint8_t reserve : 7; /* Reserve */ + }; + uint8_t val; + } flags; + uint8_t reserve; /*!< Reserve */ #ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC uint8_t custom[CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE]; /*!< Reserve for custom propose */ #endif @@ -57,6 +64,8 @@ typedef struct { ESP_STATIC_ASSERT(offsetof(rtc_retain_mem_t, crc) == sizeof(rtc_retain_mem_t) - sizeof(uint32_t), "CRC field must be the last field of rtc_retain_mem_t structure"); +#ifdef CONFIG_BOOTLOADER_RESERVE_RTC_MEM + #ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC ESP_STATIC_ASSERT(CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE % 4 == 0, "CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE must be a multiple of 4 bytes"); /* The custom field must be the penultimate field */ @@ -64,19 +73,16 @@ ESP_STATIC_ASSERT(offsetof(rtc_retain_mem_t, custom) == sizeof(rtc_retain_mem_t) "custom field in rtc_retain_mem_t structure must be the field before the CRC one"); #endif -#if defined(CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP) || defined(CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC) ESP_STATIC_ASSERT(CONFIG_BOOTLOADER_RESERVE_RTC_SIZE % 4 == 0, "CONFIG_BOOTLOADER_RESERVE_RTC_SIZE must be a multiple of 4 bytes"); -#endif #ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC #define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE + CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE) -#elif defined(CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP) +#else #define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE) #endif -#if defined(CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP) || defined(CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC) ESP_STATIC_ASSERT(sizeof(rtc_retain_mem_t) <= ESP_BOOTLOADER_RESERVE_RTC, "Reserved RTC area must exceed size of rtc_retain_mem_t"); -#endif +#endif // CONFIG_BOOTLOADER_RESERVE_RTC_MEM /** * @brief Verify an app image. diff --git a/tools/sdk/esp32/include/bt/host/bluedroid/api/include/api/esp_gap_bt_api.h b/tools/sdk/esp32/include/bt/host/bluedroid/api/include/api/esp_gap_bt_api.h index 76197f81a3e..78d31125ce8 100644 --- a/tools/sdk/esp32/include/bt/host/bluedroid/api/include/api/esp_gap_bt_api.h +++ b/tools/sdk/esp32/include/bt/host/bluedroid/api/include/api/esp_gap_bt_api.h @@ -576,7 +576,9 @@ esp_err_t esp_bt_gap_config_eir_data(esp_bt_eir_data_t *eir_data); /** * @brief This function is called to set class of device. * The structure esp_bt_gap_cb_t will be called with ESP_BT_GAP_SET_COD_EVT after set COD ends. - * Some profile have special restrictions on class of device, changes may cause these profile do not work. + * This function should be called after Bluetooth profiles are initialized, otherwise the user configured + * class of device can be overwritten. + * Some profiles have special restrictions on class of device, and changes may make these profiles unable to work. * * @param[in] cod - class of device * @param[in] mode - setting mode diff --git a/tools/sdk/esp32/include/driver/include/esp_private/spi_common_internal.h b/tools/sdk/esp32/include/driver/include/esp_private/spi_common_internal.h index 83b9c1ad6b3..6cc711b5224 100644 --- a/tools/sdk/esp32/include/driver/include/esp_private/spi_common_internal.h +++ b/tools/sdk/esp32/include/driver/include/esp_private/spi_common_internal.h @@ -13,6 +13,10 @@ #include "freertos/FreeRTOS.h" #include "hal/spi_types.h" #include "esp_pm.h" +#if SOC_GDMA_SUPPORTED +#include "esp_private/gdma.h" +#endif + #ifdef __cplusplus extern "C" @@ -130,6 +134,22 @@ esp_err_t spicommon_dma_chan_alloc(spi_host_device_t host_id, spi_dma_chan_t dma */ esp_err_t spicommon_dma_chan_free(spi_host_device_t host_id); +#if SOC_GDMA_SUPPORTED +/** + * @brief Get SPI GDMA Handle for GMDA Supported Chip + * + * @param host_id SPI host ID + * @param gdma_handle GDMA Handle to Return + * @param gdma_direction GDMA Channel Direction in Enum + * - GDMA_CHANNEL_DIRECTION_TX + * - GDMA_CHANNEL_DIRECTION_RX + * + * @return + * - ESP_OK: On success + */ +esp_err_t spicommon_gdma_get_handle(spi_host_device_t host_id, gdma_channel_handle_t *gdma_handle, gdma_channel_direction_t gdma_direction); +#endif + /** * @brief Connect a SPI peripheral to GPIO pins * diff --git a/tools/sdk/esp32/include/driver/ledc/include/driver/ledc.h b/tools/sdk/esp32/include/driver/ledc/include/driver/ledc.h index 509b81634d3..c0e2f14530f 100644 --- a/tools/sdk/esp32/include/driver/ledc/include/driver/ledc.h +++ b/tools/sdk/esp32/include/driver/ledc/include/driver/ledc.h @@ -450,10 +450,10 @@ esp_err_t ledc_fade_start(ledc_mode_t speed_mode, ledc_channel_t channel, ledc_f #if SOC_LEDC_SUPPORT_FADE_STOP /** - * @brief Stop LEDC fading. Duty of the channel will stay at its present vlaue. + * @brief Stop LEDC fading. The duty of the channel is garanteed to be fixed at most one PWM cycle after the function returns. * @note This API can be called if a new fixed duty or a new fade want to be set while the last fade operation is still running in progress. * @note Call this API will abort the fading operation only if it was started by calling ledc_fade_start with LEDC_FADE_NO_WAIT mode. - * @note If a fade was started with LEDC_FADE_WAIT_DONE mode, calling this API afterwards is no use in stopping the fade. Fade will continue until it reachs the target duty. + * @note If a fade was started with LEDC_FADE_WAIT_DONE mode, calling this API afterwards HAS no use in stopping the fade. Fade will continue until it reachs the target duty. * @param speed_mode Select the LEDC channel group with specified speed mode. Note that not all targets support high speed mode. * @param channel LEDC channel number * diff --git a/tools/sdk/esp32/include/driver/rmt/include/driver/rmt_rx.h b/tools/sdk/esp32/include/driver/rmt/include/driver/rmt_rx.h index c750a59a734..ddb409d94a7 100644 --- a/tools/sdk/esp32/include/driver/rmt/include/driver/rmt_rx.h +++ b/tools/sdk/esp32/include/driver/rmt/include/driver/rmt_rx.h @@ -29,10 +29,12 @@ typedef struct { * @brief RMT RX channel specific configuration */ typedef struct { - int gpio_num; /*!< GPIO number used by RMT RX channel. Set to -1 if unused */ + gpio_num_t gpio_num; /*!< GPIO number used by RMT RX channel. Set to -1 if unused */ rmt_clock_source_t clk_src; /*!< Clock source of RMT RX channel, channels in the same group must use the same clock source */ uint32_t resolution_hz; /*!< Channel clock resolution, in Hz */ - size_t mem_block_symbols; /*!< Size of memory block, in number of `rmt_symbol_word_t`, must be an even */ + size_t mem_block_symbols; /*!< Size of memory block, in number of `rmt_symbol_word_t`, must be an even. + In the DMA mode, this field controls the DMA buffer size, it can be set to a large value (e.g. 1024); + In the normal mode, this field controls the number of RMT memory block that will be used by the channel. */ struct { uint32_t invert_in: 1; /*!< Whether to invert the incoming RMT channel signal */ uint32_t with_dma: 1; /*!< If set, the driver will allocate an RMT channel with DMA capability */ diff --git a/tools/sdk/esp32/include/driver/rmt/include/driver/rmt_tx.h b/tools/sdk/esp32/include/driver/rmt/include/driver/rmt_tx.h index 83b1cef392e..9444ae3aabc 100644 --- a/tools/sdk/esp32/include/driver/rmt/include/driver/rmt_tx.h +++ b/tools/sdk/esp32/include/driver/rmt/include/driver/rmt_tx.h @@ -30,10 +30,12 @@ typedef struct { * @brief RMT TX channel specific configuration */ typedef struct { - int gpio_num; /*!< GPIO number used by RMT TX channel. Set to -1 if unused */ + gpio_num_t gpio_num; /*!< GPIO number used by RMT TX channel. Set to -1 if unused */ rmt_clock_source_t clk_src; /*!< Clock source of RMT TX channel, channels in the same group must use the same clock source */ uint32_t resolution_hz; /*!< Channel clock resolution, in Hz */ - size_t mem_block_symbols; /*!< Size of memory block, in number of `rmt_symbol_word_t`, must be an even */ + size_t mem_block_symbols; /*!< Size of memory block, in number of `rmt_symbol_word_t`, must be an even. + In the DMA mode, this field controls the DMA buffer size, it can be set to a large value; + In the normal mode, this field controls the number of RMT memory block that will be used by the channel. */ size_t trans_queue_depth; /*!< Depth of internal transfer queue, increase this value can support more transfers pending in the background */ struct { uint32_t invert_out: 1; /*!< Whether to invert the RMT channel signal before output to GPIO pad */ diff --git a/tools/sdk/esp32/include/driver/rmt/include/driver/rmt_types.h b/tools/sdk/esp32/include/driver/rmt/include/driver/rmt_types.h index 2dea896ea67..63032d4d994 100644 --- a/tools/sdk/esp32/include/driver/rmt/include/driver/rmt_types.h +++ b/tools/sdk/esp32/include/driver/rmt/include/driver/rmt_types.h @@ -10,6 +10,7 @@ #include #include #include "hal/rmt_types.h" +#include "hal/gpio_types.h" // for gpio_num_t #ifdef __cplusplus extern "C" { diff --git a/tools/sdk/esp32/include/driver/sdmmc/include/driver/sdmmc_host.h b/tools/sdk/esp32/include/driver/sdmmc/include/driver/sdmmc_host.h index 1a4beb892a4..46b6f6af366 100644 --- a/tools/sdk/esp32/include/driver/sdmmc/include/driver/sdmmc_host.h +++ b/tools/sdk/esp32/include/driver/sdmmc/include/driver/sdmmc_host.h @@ -40,6 +40,7 @@ extern "C" { .get_bus_width = &sdmmc_host_get_slot_width, \ .set_bus_ddr_mode = &sdmmc_host_set_bus_ddr_mode, \ .set_card_clk = &sdmmc_host_set_card_clk, \ + .set_cclk_always_on = &sdmmc_host_set_cclk_always_on, \ .do_transaction = &sdmmc_host_do_transaction, \ .deinit = &sdmmc_host_deinit, \ .io_int_enable = sdmmc_host_io_int_enable, \ @@ -204,6 +205,19 @@ esp_err_t sdmmc_host_set_card_clk(int slot, uint32_t freq_khz); */ esp_err_t sdmmc_host_set_bus_ddr_mode(int slot, bool ddr_enabled); +/** + * @brief Enable or disable always-on card clock + * When cclk_always_on is false, the host controller is allowed to shut down + * the card clock between the commands. When cclk_always_on is true, the clock + * is generated even if no command is in progress. + * @param slot slot number + * @param cclk_always_on enable or disable always-on clock + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_ARG if the slot number is invalid + */ +esp_err_t sdmmc_host_set_cclk_always_on(int slot, bool cclk_always_on); + /** * @brief Send command to the card and get response * diff --git a/tools/sdk/esp32/include/driver/sdmmc/include/driver/sdmmc_types.h b/tools/sdk/esp32/include/driver/sdmmc/include/driver/sdmmc_types.h index 8a38d792e3a..bc74a38c1d5 100644 --- a/tools/sdk/esp32/include/driver/sdmmc/include/driver/sdmmc_types.h +++ b/tools/sdk/esp32/include/driver/sdmmc/include/driver/sdmmc_types.h @@ -175,6 +175,7 @@ typedef struct { size_t (*get_bus_width)(int slot); /*!< host function to get bus width */ esp_err_t (*set_bus_ddr_mode)(int slot, bool ddr_enable); /*!< host function to set DDR mode */ esp_err_t (*set_card_clk)(int slot, uint32_t freq_khz); /*!< host function to set card clock frequency */ + esp_err_t (*set_cclk_always_on)(int slot, bool cclk_always_on); /*!< host function to set whether the clock is always enabled */ esp_err_t (*do_transaction)(int slot, sdmmc_command_t* cmdinfo); /*!< host function to do a transaction */ union { esp_err_t (*deinit)(void); /*!< host function to deinitialize the driver */ diff --git a/tools/sdk/esp32/include/driver/spi/include/driver/sdspi_host.h b/tools/sdk/esp32/include/driver/spi/include/driver/sdspi_host.h index 3b127fbfefb..146cff69cd3 100644 --- a/tools/sdk/esp32/include/driver/spi/include/driver/sdspi_host.h +++ b/tools/sdk/esp32/include/driver/spi/include/driver/sdspi_host.h @@ -45,6 +45,7 @@ typedef int sdspi_dev_handle_t; .get_bus_width = NULL, \ .set_bus_ddr_mode = NULL, \ .set_card_clk = &sdspi_host_set_card_clk, \ + .set_cclk_always_on = NULL, \ .do_transaction = &sdspi_host_do_transaction, \ .deinit_p = &sdspi_host_remove_device, \ .io_int_enable = &sdspi_host_io_int_enable, \ diff --git a/tools/sdk/esp32/include/driver/uart/include/driver/uart.h b/tools/sdk/esp32/include/driver/uart/include/driver/uart.h index ba5f49306ea..314adf172dd 100644 --- a/tools/sdk/esp32/include/driver/uart/include/driver/uart.h +++ b/tools/sdk/esp32/include/driver/uart/include/driver/uart.h @@ -766,8 +766,10 @@ esp_err_t uart_get_collision_flag(uart_port_t uart_num, bool* collision_flag); * The character that triggers wakeup is not received by UART (i.e. it can not * be obtained from UART FIFO). Depending on the baud rate, a few characters * after that will also not be received. Note that when the chip enters and exits - * light sleep mode, APB frequency will be changing. To make sure that UART has - * correct baud rate all the time, select UART_SCLK_REF_TICK or UART_SCLK_XTAL as UART clock source in uart_config_t::source_clk. + * light sleep mode, APB frequency will be changing. To ensure that UART has + * correct Baud rate all the time, it is necessary to select a source clock which has + * a fixed frequency and remains active during sleep. For the supported clock sources + * of the chips, please refer to `uart_sclk_t` or `soc_periph_uart_clk_src_legacy_t` * * @note in ESP32, the wakeup signal can only be input via IO_MUX (i.e. * GPIO3 should be configured as function_1 to wake up UART0, diff --git a/tools/sdk/esp32/include/efuse/esp32/include/esp_efuse_table.h b/tools/sdk/esp32/include/efuse/esp32/include/esp_efuse_table.h index ab896d1b9ce..89e51532bf5 100644 --- a/tools/sdk/esp32/include/efuse/esp32/include/esp_efuse_table.h +++ b/tools/sdk/esp32/include/efuse/esp32/include/esp_efuse_table.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,55 +10,163 @@ extern "C" { #include "esp_efuse.h" -// md5_digest_table 6256f9b7c6783e0b651bf52b5b162aa8 +// md5_digest_table 2e197b7b14eec62fa5bdf94c6d71e87a // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. // To show efuse_table run the command 'show_efuse_table'. -extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[]; -extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY_CRC[]; -extern const esp_efuse_desc_t* ESP_EFUSE_MAC_CUSTOM_CRC[]; -extern const esp_efuse_desc_t* ESP_EFUSE_MAC_CUSTOM[]; -extern const esp_efuse_desc_t* ESP_EFUSE_MAC_CUSTOM_VER[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ABS_DONE_0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ABS_DONE_1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ENCRYPT_FLASH_KEY[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ENCRYPT_CONFIG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_DL_ENCRYPT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_DL_DECRYPT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_DL_CACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[]; +#define ESP_EFUSE_WR_DIS_EFUSE_RD_DISABLE ESP_EFUSE_WR_DIS_RD_DIS +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WR_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CRYPT_CNT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_DOWNLOAD_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[]; +#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_CRC[]; +#define ESP_EFUSE_WR_DIS_MAC_FACTORY_CRC ESP_EFUSE_WR_DIS_MAC_CRC +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_APP_CPU[]; +#define ESP_EFUSE_WR_DIS_CHIP_VER_DIS_APP_CPU ESP_EFUSE_WR_DIS_DISABLE_APP_CPU +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BT[]; +#define ESP_EFUSE_WR_DIS_CHIP_VER_DIS_BT ESP_EFUSE_WR_DIS_DISABLE_BT +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_CACHE[]; +#define ESP_EFUSE_WR_DIS_CHIP_VER_DIS_CACHE ESP_EFUSE_WR_DIS_DIS_CACHE +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VOL_LEVEL_HP_INV[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CLK8M_FREQ[]; +#define ESP_EFUSE_WR_DIS_CK8M_FREQ ESP_EFUSE_WR_DIS_CLK8M_FREQ +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC_VREF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XPD_SDIO_REG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XPD_SDIO_TIEH[]; +#define ESP_EFUSE_WR_DIS_SDIO_TIEH ESP_EFUSE_WR_DIS_XPD_SDIO_TIEH +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XPD_SDIO_FORCE[]; +#define ESP_EFUSE_WR_DIS_SDIO_FORCE ESP_EFUSE_WR_DIS_XPD_SDIO_FORCE +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CLK[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_Q[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CS0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK1[]; +#define ESP_EFUSE_WR_DIS_ENCRYPT_FLASH_KEY ESP_EFUSE_WR_DIS_BLOCK1 +#define ESP_EFUSE_WR_DIS_BLK1 ESP_EFUSE_WR_DIS_BLOCK1 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK2[]; +#define ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY ESP_EFUSE_WR_DIS_BLOCK2 +#define ESP_EFUSE_WR_DIS_BLK2 ESP_EFUSE_WR_DIS_BLOCK2 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK3[]; +#define ESP_EFUSE_WR_DIS_BLK3 ESP_EFUSE_WR_DIS_BLOCK3 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC_CRC[]; +#define ESP_EFUSE_WR_DIS_MAC_CUSTOM_CRC ESP_EFUSE_WR_DIS_CUSTOM_MAC_CRC +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[]; +#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_TP_LOW[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_TP_HIGH[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_TP_LOW[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_TP_HIGH[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_VERSION[]; +#define ESP_EFUSE_WR_DIS_MAC_CUSTOM_VER ESP_EFUSE_WR_DIS_MAC_VERSION +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK3_PART_RESERVE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CRYPT_CONFIG[]; +#define ESP_EFUSE_WR_DIS_ENCRYPT_CONFIG ESP_EFUSE_WR_DIS_FLASH_CRYPT_CONFIG +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CODING_SCHEME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_STATUS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ABS_DONE_0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ABS_DONE_1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_DISABLE[]; +#define ESP_EFUSE_WR_DIS_DISABLE_JTAG ESP_EFUSE_WR_DIS_JTAG_DISABLE +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CONSOLE_DEBUG_DISABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_DL_ENCRYPT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_DL_DECRYPT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_DL_CACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK1[]; +#define ESP_EFUSE_RD_DIS_ENCRYPT_FLASH_KEY ESP_EFUSE_RD_DIS_BLOCK1 +#define ESP_EFUSE_RD_DIS_BLK1 ESP_EFUSE_RD_DIS_BLOCK1 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK2[]; +#define ESP_EFUSE_RD_DIS_SECURE_BOOT_KEY ESP_EFUSE_RD_DIS_BLOCK2 +#define ESP_EFUSE_RD_DIS_BLK2 ESP_EFUSE_RD_DIS_BLOCK2 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK3[]; +#define ESP_EFUSE_RD_DIS_BLK3 ESP_EFUSE_RD_DIS_BLOCK3 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_CUSTOM_MAC_CRC[]; +#define ESP_EFUSE_RD_DIS_MAC_CUSTOM_CRC ESP_EFUSE_RD_DIS_CUSTOM_MAC_CRC +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_CUSTOM_MAC[]; +#define ESP_EFUSE_RD_DIS_MAC_CUSTOM ESP_EFUSE_RD_DIS_CUSTOM_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_TP_LOW[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_TP_HIGH[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_TP_LOW[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_TP_HIGH[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SECURE_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_MAC_VERSION[]; +#define ESP_EFUSE_RD_DIS_MAC_CUSTOM_VER ESP_EFUSE_RD_DIS_MAC_VERSION +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLK3_PART_RESERVE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_FLASH_CRYPT_CONFIG[]; +#define ESP_EFUSE_RD_DIS_ENCRYPT_CONFIG ESP_EFUSE_RD_DIS_FLASH_CRYPT_CONFIG +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_CODING_SCHEME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY_STATUS[]; extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CRYPT_CNT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_JTAG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_CONSOLE_DEBUG_DISABLE[]; extern const esp_efuse_desc_t* ESP_EFUSE_UART_DOWNLOAD_DIS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_EFUSE_RD_DISABLE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CRYPT_CNT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLK1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLK2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLK3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_DIS_APP_CPU[]; -extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_DIS_BT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_PKG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_MAC[]; +#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_MAC_CRC[]; +#define ESP_EFUSE_MAC_FACTORY_CRC ESP_EFUSE_MAC_CRC +extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_APP_CPU[]; +#define ESP_EFUSE_CHIP_VER_DIS_APP_CPU ESP_EFUSE_DISABLE_APP_CPU +extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BT[]; +#define ESP_EFUSE_CHIP_VER_DIS_BT ESP_EFUSE_DISABLE_BT +extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_PACKAGE_4BIT[]; +#define ESP_EFUSE_CHIP_VER_PKG_4BIT ESP_EFUSE_CHIP_PACKAGE_4BIT +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_CACHE[]; +#define ESP_EFUSE_CHIP_VER_DIS_CACHE ESP_EFUSE_DIS_CACHE +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_PACKAGE[]; +#define ESP_EFUSE_CHIP_VER_PKG ESP_EFUSE_CHIP_PACKAGE extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_CPU_FREQ_LOW[]; extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_CPU_FREQ_RATED[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BLK3_PART_RESERVE[]; extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_REV1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_CLK8M_FREQ[]; +#define ESP_EFUSE_CK8M_FREQ ESP_EFUSE_CLK8M_FREQ +extern const esp_efuse_desc_t* ESP_EFUSE_ADC_VREF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_XPD_SDIO_REG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_XPD_SDIO_TIEH[]; +#define ESP_EFUSE_SDIO_TIEH ESP_EFUSE_XPD_SDIO_TIEH +extern const esp_efuse_desc_t* ESP_EFUSE_XPD_SDIO_FORCE[]; +#define ESP_EFUSE_SDIO_FORCE ESP_EFUSE_XPD_SDIO_FORCE +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS0[]; extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_REV2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_VOL_LEVEL_HP_INV[]; extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_XPD_SDIO_REG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SDIO_TIEH[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SDIO_FORCE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC_VREF_AND_SDIO_DREF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CRYPT_CONFIG[]; +#define ESP_EFUSE_ENCRYPT_CONFIG ESP_EFUSE_FLASH_CRYPT_CONFIG +extern const esp_efuse_desc_t* ESP_EFUSE_CODING_SCHEME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_CONSOLE_DEBUG_DISABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_SDIO_HOST[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ABS_DONE_0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ABS_DONE_1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_DISABLE[]; +#define ESP_EFUSE_DISABLE_JTAG ESP_EFUSE_JTAG_DISABLE +extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_DL_ENCRYPT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_DL_DECRYPT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_DL_CACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_STATUS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK1[]; +#define ESP_EFUSE_ENCRYPT_FLASH_KEY ESP_EFUSE_BLOCK1 +extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK2[]; +#define ESP_EFUSE_SECURE_BOOT_KEY ESP_EFUSE_BLOCK2 +extern const esp_efuse_desc_t* ESP_EFUSE_CUSTOM_MAC_CRC[]; +#define ESP_EFUSE_MAC_CUSTOM_CRC ESP_EFUSE_CUSTOM_MAC_CRC +extern const esp_efuse_desc_t* ESP_EFUSE_MAC_CUSTOM[]; +#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_MAC_CUSTOM extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_TP_LOW[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_TP_LOW[]; extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_TP_HIGH[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_TP_LOW[]; extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_TP_HIGH[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_MAC_VERSION[]; +#define ESP_EFUSE_MAC_CUSTOM_VER ESP_EFUSE_MAC_VERSION #ifdef __cplusplus } diff --git a/tools/sdk/esp32/include/esp-tls/esp_tls.h b/tools/sdk/esp32/include/esp-tls/esp_tls.h index 3ada350379e..0efe587b53b 100644 --- a/tools/sdk/esp32/include/esp-tls/esp_tls.h +++ b/tools/sdk/esp32/include/esp-tls/esp_tls.h @@ -71,6 +71,15 @@ typedef struct tls_keep_alive_cfg { int keep_alive_count; /*!< Keep-alive packet retry send count */ } tls_keep_alive_cfg_t; +/* +* @brief ESP-TLS Address families +*/ +typedef enum esp_tls_addr_family { + ESP_TLS_AF_UNSPEC = 0, /**< Unspecified address family. */ + ESP_TLS_AF_INET, /**< IPv4 address family. */ + ESP_TLS_AF_INET6, /**< IPv6 address family. */ +} esp_tls_addr_family_t; + /** * @brief ESP-TLS configuration parameters * @@ -182,6 +191,8 @@ typedef struct esp_tls_cfg { #ifdef CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS esp_tls_client_session_t *client_session; /*! Pointer for the client session ticket context. */ #endif /* CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS */ + + esp_tls_addr_family_t addr_family; /*!< The address family to use when connecting to a host. */ } esp_tls_cfg_t; #ifdef CONFIG_ESP_TLS_SERVER diff --git a/tools/sdk/esp32/include/esp_coex/include/esp_coexist.h b/tools/sdk/esp32/include/esp_coex/include/esp_coexist.h index e3fb019d420..9ed897c28a7 100644 --- a/tools/sdk/esp32/include/esp_coex/include/esp_coexist.h +++ b/tools/sdk/esp32/include/esp_coex/include/esp_coexist.h @@ -201,6 +201,14 @@ esp_err_t esp_external_coex_set_validate_high(bool is_high_valid); #endif #endif +#if CONFIG_ESP_COEX_SW_COEXIST_ENABLE && CONFIG_SOC_IEEE802154_SUPPORTED +/** + * @brief Enable Wi-Fi and 802.15.4 coexistence. + * @return : ESP_OK - success, other - failed + */ +esp_err_t esp_coex_wifi_i154_enable(void); +#endif + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32/include/esp_coex/include/esp_coexist_adapter.h b/tools/sdk/esp32/include/esp_coex/include/esp_coexist_adapter.h index 11bf54d9b5e..fde83d1111d 100644 --- a/tools/sdk/esp32/include/esp_coex/include/esp_coexist_adapter.h +++ b/tools/sdk/esp32/include/esp_coex/include/esp_coexist_adapter.h @@ -38,7 +38,10 @@ typedef struct { void (* _free)(void *p); int64_t (* _esp_timer_get_time)(void); bool (* _env_is_chip)(void); +#if CONFIG_IDF_TARGET_ESP32C2 + // this function is only used on esp32c2 uint32_t (* _slowclk_cal_get)(void); +#endif void (* _timer_disarm)(void *timer); void (* _timer_done)(void *ptimer); void (* _timer_setfn)(void *ptimer, void *pfunction, void *parg); diff --git a/tools/sdk/esp32/include/esp_http_client/include/esp_http_client.h b/tools/sdk/esp32/include/esp_http_client/include/esp_http_client.h index 5638b7c6817..e1dbd5c8f1c 100644 --- a/tools/sdk/esp32/include/esp_http_client/include/esp_http_client.h +++ b/tools/sdk/esp32/include/esp_http_client/include/esp_http_client.h @@ -382,6 +382,34 @@ esp_err_t esp_http_client_set_password(esp_http_client_handle_t client, const ch */ esp_err_t esp_http_client_set_authtype(esp_http_client_handle_t client, esp_http_client_auth_type_t auth_type); +/** + * @brief Get http request user_data. + * The value stored from the esp_http_client_config_t will be written + * to the address passed into data. + * + * @param[in] client The esp_http_client handle + * @param[out] data A pointer to the pointer that will be set to user_data. + * + * @return + * - ESP_OK + * - ESP_ERR_INVALID_ARG + */ +esp_err_t esp_http_client_get_user_data(esp_http_client_handle_t client, void **data); + +/** + * @brief Set http request user_data. + * The value passed in +data+ will be available during event callbacks. + * No memory management will be performed on the user's behalf. + * + * @param[in] client The esp_http_client handle + * @param[in] data The pointer to the user data + * + * @return + * - ESP_OK + * - ESP_ERR_INVALID_ARG + */ +esp_err_t esp_http_client_set_user_data(esp_http_client_handle_t client, void *data); + /** * @brief Get HTTP client session errno * diff --git a/tools/sdk/esp32/include/esp_http_server/include/esp_http_server.h b/tools/sdk/esp32/include/esp_http_server/include/esp_http_server.h index 3826a40c9a3..39c2a82a31f 100644 --- a/tools/sdk/esp32/include/esp_http_server/include/esp_http_server.h +++ b/tools/sdk/esp32/include/esp_http_server/include/esp_http_server.h @@ -15,6 +15,7 @@ #include #include #include +#include #ifdef __cplusplus extern "C" { diff --git a/tools/sdk/esp32/include/esp_hw_support/include/esp_private/esp_modem_clock.h b/tools/sdk/esp32/include/esp_hw_support/include/esp_private/esp_modem_clock.h index 8b406550c66..bc678e039c3 100644 --- a/tools/sdk/esp32/include/esp_hw_support/include/esp_private/esp_modem_clock.h +++ b/tools/sdk/esp32/include/esp_hw_support/include/esp_private/esp_modem_clock.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,6 +10,7 @@ #include #include +#include "soc/soc_caps.h" #include "soc/periph_defs.h" #include "hal/modem_clock_types.h" diff --git a/tools/sdk/esp32/include/esp_hw_support/include/esp_private/gdma.h b/tools/sdk/esp32/include/esp_hw_support/include/esp_private/gdma.h index d71f3c6fc8a..bf5d97dd324 100644 --- a/tools/sdk/esp32/include/esp_hw_support/include/esp_private/gdma.h +++ b/tools/sdk/esp32/include/esp_hw_support/include/esp_private/gdma.h @@ -177,14 +177,28 @@ esp_err_t gdma_set_transfer_ability(gdma_channel_handle_t dma_chan, const gdma_t /** * @brief Apply channel strategy for GDMA channel * - * @param dma_chan GDMA channel handle, allocated by `gdma_new_channel` - * @param config Configuration of GDMA channel strategy + * @param[in] dma_chan GDMA channel handle, allocated by `gdma_new_channel` + * @param[in] config Configuration of GDMA channel strategy * - ESP_OK: Apply channel strategy successfully * - ESP_ERR_INVALID_ARG: Apply channel strategy failed because of invalid argument * - ESP_FAIL: Apply channel strategy failed because of other error */ esp_err_t gdma_apply_strategy(gdma_channel_handle_t dma_chan, const gdma_strategy_config_t *config); +/** + * @brief Set GDMA channel priority + * + * @note By default, all GDMA channels are with the same priority: 0. Channels with the same priority are served in round-robin manner. + * + * @param[in] dma_chan GDMA channel handle, allocated by `gdma_new_channel` + * @param[in] priority Priority of GDMA channel, higher value means higher priority + * @return + * - ESP_OK: Set GDMA channel priority successfully + * - ESP_ERR_INVALID_ARG: Set GDMA channel priority failed because of invalid argument, e.g. priority out of range [0,GDMA_LL_CHANNEL_MAX_PRIORITY] + * - ESP_FAIL: Set GDMA channel priority failed because of other error + */ +esp_err_t gdma_set_priority(gdma_channel_handle_t dma_chan, uint32_t priority); + /** * @brief Delete GDMA channel * @note If you call `gdma_new_channel` several times for a same peripheral, make sure you call this API the same times. @@ -251,6 +265,7 @@ esp_err_t gdma_register_rx_event_callbacks(gdma_channel_handle_t dma_chan, gdma_ * @return * - ESP_OK: Start DMA engine successfully * - ESP_ERR_INVALID_ARG: Start DMA engine failed because of invalid argument + * - ESP_ERR_INVALID_STATE: Start DMA engine failed because of invalid state, e.g. the channel is controlled by ETM, so can't start it manually * - ESP_FAIL: Start DMA engine failed because of other error */ esp_err_t gdma_start(gdma_channel_handle_t dma_chan, intptr_t desc_base_addr); @@ -265,6 +280,7 @@ esp_err_t gdma_start(gdma_channel_handle_t dma_chan, intptr_t desc_base_addr); * @return * - ESP_OK: Stop DMA engine successfully * - ESP_ERR_INVALID_ARG: Stop DMA engine failed because of invalid argument + * - ESP_ERR_INVALID_STATE: Stop DMA engine failed because of invalid state, e.g. the channel is controlled by ETM, so can't stop it manually * - ESP_FAIL: Stop DMA engine failed because of other error */ esp_err_t gdma_stop(gdma_channel_handle_t dma_chan); @@ -333,6 +349,7 @@ typedef struct { * @brief Get the ETM task for GDMA channel * * @note The created ETM task object can be deleted later by calling `esp_etm_del_task` + * @note If the GDMA task (e.g. start/stop) is controlled by ETM, then you can't use `gdma_start`/`gdma_stop` to control it. * * @param[in] dma_chan GDMA channel handle, allocated by `gdma_new_channel` * @param[in] config GDMA ETM task configuration diff --git a/tools/sdk/esp32/include/esp_hw_support/include/esp_private/sleep_modem.h b/tools/sdk/esp32/include/esp_hw_support/include/esp_private/sleep_modem.h index 7e11d88a9e6..7601aeebd82 100644 --- a/tools/sdk/esp32/include/esp_hw_support/include/esp_private/sleep_modem.h +++ b/tools/sdk/esp32/include/esp_hw_support/include/esp_private/sleep_modem.h @@ -42,6 +42,13 @@ void mac_bb_power_up_cb_execute(void); #if SOC_PM_SUPPORT_PMU_MODEM_STATE +/** + * @brief The retention action in the modem state of WiFi PHY module + * + * @param restore true for restore the PHY context, false for backup the PHY context + */ +void sleep_modem_wifi_do_phy_retention(bool restore); + /** * @brief Get WiFi modem state * diff --git a/tools/sdk/esp32/include/esp_hw_support/include/soc/esp32c2/memprot.h b/tools/sdk/esp32/include/esp_hw_support/include/soc/esp32c2/memprot.h deleted file mode 100644 index c7b1ad461e8..00000000000 --- a/tools/sdk/esp32/include/esp_hw_support/include/soc/esp32c2/memprot.h +++ /dev/null @@ -1,440 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - - -/* INTERNAL API - * generic interface to PMS memory protection features - */ - -#pragma once - -#include -#include -#include "esp_attr.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef IRAM_SRAM_START -#define IRAM_SRAM_START 0x4037C000 -#endif - -#ifndef DRAM_SRAM_START -#define DRAM_SRAM_START 0x3FC7C000 -#endif - -typedef enum { - MEMPROT_NONE = 0x00000000, - MEMPROT_IRAM0_SRAM = 0x00000001, - MEMPROT_DRAM0_SRAM = 0x00000002, - MEMPROT_ALL = 0xFFFFFFFF -} mem_type_prot_t; - -typedef enum { - MEMPROT_SPLITLINE_NONE = 0, - MEMPROT_IRAM0_DRAM0_SPLITLINE, - MEMPROT_IRAM0_LINE_0_SPLITLINE, - MEMPROT_IRAM0_LINE_1_SPLITLINE, - MEMPROT_DRAM0_DMA_LINE_0_SPLITLINE, - MEMPROT_DRAM0_DMA_LINE_1_SPLITLINE -} split_line_t; - -typedef enum { - MEMPROT_PMS_AREA_NONE = 0, - MEMPROT_IRAM0_PMS_AREA_0, - MEMPROT_IRAM0_PMS_AREA_1, - MEMPROT_IRAM0_PMS_AREA_2, - MEMPROT_IRAM0_PMS_AREA_3, - MEMPROT_DRAM0_PMS_AREA_0, - MEMPROT_DRAM0_PMS_AREA_1, - MEMPROT_DRAM0_PMS_AREA_2, - MEMPROT_DRAM0_PMS_AREA_3 -} pms_area_t; - -typedef enum -{ - MEMPROT_PMS_WORLD_0 = 0, - MEMPROT_PMS_WORLD_1, - MEMPROT_PMS_WORLD_2, - MEMPROT_PMS_WORLD_INVALID = 0xFFFFFFFF -} pms_world_t; - -typedef enum -{ - MEMPROT_PMS_OP_READ = 0, - MEMPROT_PMS_OP_WRITE, - MEMPROT_PMS_OP_FETCH, - MEMPROT_PMS_OP_INVALID = 0xFFFFFFFF -} pms_operation_type_t; - -/** - * @brief Converts Memory protection type to string - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - */ -const char *esp_memprot_mem_type_to_str(mem_type_prot_t mem_type); - -/** - * @brief Converts Split line type to string - * - * @param line_type Split line type (see split_line_t enum) - */ -const char *esp_memprot_split_line_to_str(split_line_t line_type); - -/** - * @brief Converts PMS Area type to string - * - * @param area_type PMS Area type (see pms_area_t enum) - */ -const char *esp_memprot_pms_to_str(pms_area_t area_type); - -/** - * @brief Returns PMS splitting address for given Split line type - * - * The value is taken from PMS configuration registers (IRam0 range) - * For details on split lines see 'esp_memprot_set_prot_int' function description - * - * @param line_type Split line type (see split_line_t enum) - * - * @return appropriate split line address - */ -uint32_t *esp_memprot_get_split_addr(split_line_t line_type); - -/** - * @brief Returns default main IRAM/DRAM splitting address - * - * The address value is given by _iram_text_end global (IRam0 range) - - * @return Main I/D split line (IRam0_DRam0_Split_Addr) - */ -void *esp_memprot_get_default_main_split_addr(void); - -/** - * @brief Sets a lock for the main IRAM/DRAM splitting address - * - * Locks can be unlocked only by digital system reset - */ -void esp_memprot_set_split_line_lock(void); - -/** - * @brief Gets a lock status for the main IRAM/DRAM splitting address - * - * @return true/false (locked/unlocked) - */ -bool esp_memprot_get_split_line_lock(void); - -/** - * @brief Sets required split line address - * - * @param line_type Split line type (see split_line_t enum) - * @param line_addr target address from a memory range relevant to given line_type (IRAM/DRAM) - */ -void esp_memprot_set_split_line(split_line_t line_type, const void *line_addr); - -/** - * @brief Sets a lock for PMS Area settings of required Memory type - * - * Locks can be unlocked only by digital system reset - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - */ -void esp_memprot_set_pms_lock(mem_type_prot_t mem_type); - -/** - * @brief Gets a lock status for PMS Area settings of required Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return true/false (locked/unlocked) - */ -bool esp_memprot_get_pms_lock(mem_type_prot_t mem_type); - -/** - * @brief Sets permissions for given PMS Area in IRam0 memory range (MEMPROT_IRAM0_SRAM) - * - * @param area_type IRam0 PMS Area type (see pms_area_t enum) - * @param r Read permission flag - * @param w Write permission flag - * @param x Execute permission flag - */ -void esp_memprot_iram_set_pms_area(pms_area_t area_type, bool r, bool w, bool x); - -/** - * @brief Gets current permissions for given PMS Area in IRam0 memory range (MEMPROT_IRAM0_SRAM) - * - * @param area_type IRam0 PMS Area type (see pms_area_t enum) - * @param r Read permission flag holder - * @param w Write permission flag holder - * @param x Execute permission flag holder - */ -void esp_memprot_iram_get_pms_area(pms_area_t area_type, bool *r, bool *w, bool *x); - -/** - * @brief Sets permissions for given PMS Area in DRam0 memory range (MEMPROT_DRAM0_SRAM) - * - * @param area_type DRam0 PMS Area type (see pms_area_t enum) - * @param r Read permission flag - * @param w Write permission flag - */ -void esp_memprot_dram_set_pms_area(pms_area_t area_type, bool r, bool w); - -/** - * @brief Gets current permissions for given PMS Area in DRam0 memory range (MEMPROT_DRAM0_SRAM) - * - * @param area_type DRam0 PMS Area type (see pms_area_t enum) - * @param r Read permission flag holder - * @param w Write permission flag holder - */ -void esp_memprot_dram_get_pms_area(pms_area_t area_type, bool *r, bool *w); - -/** - * @brief Sets a lock for PMS interrupt monitor settings of required Memory type - * - * Locks can be unlocked only by digital system reset - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - */ -void esp_memprot_set_monitor_lock(mem_type_prot_t mem_type); - -/** - * @brief Gets a lock status for PMS interrupt monitor settings of required Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return true/false (locked/unlocked) - */ -bool esp_memprot_get_monitor_lock(mem_type_prot_t mem_type); - -/** - * @brief Enable PMS violation interrupt monitoring of required Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * @param enable/disable - */ -void esp_memprot_set_monitor_en(mem_type_prot_t mem_type, bool enable); - -/** - * @brief Gets enable/disable status for PMS interrupt monitor settings of required Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return true/false (enabled/disabled) - */ -bool esp_memprot_get_monitor_en(mem_type_prot_t mem_type); - -/** - * @brief Gets CPU ID for currently active PMS violation interrupt - * - * @return CPU ID (CPU_PRO for ESP32-C2) - */ -int IRAM_ATTR esp_memprot_intr_get_cpuid(void); - -/** - * @brief Clears current interrupt ON flag for given Memory type - * - * Interrupt clearing happens in two steps: - * 1. Interrupt CLR flag is set (to clear the interrupt ON status) - * 2. Interrupt CLR flag is reset (to allow further monitoring) - * This operation is non-atomic by PMS module design - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - */ -void IRAM_ATTR esp_memprot_monitor_clear_intr(mem_type_prot_t mem_type); - -/** - * @brief Returns active PMS violation interrupt (if any) - * - * This function iterates through supported Memory type status registers - * and returns the first interrupt-on flag. If none is found active, - * MEMPROT_NONE is returned. - * Order of checking (in current version): - * 1. MEMPROT_IRAM0_SRAM - * 2. MEMPROT_DRAM0_SRAM - * - * @return mem_type Memory protection type related to active interrupt found (see mem_type_prot_t enum) - */ -mem_type_prot_t IRAM_ATTR esp_memprot_get_active_intr_memtype(void); - -/** - * @brief Checks whether any violation interrupt is active - * - * @return true/false (yes/no) - */ -bool IRAM_ATTR esp_memprot_is_locked_any(void); - -/** - * @brief Checks whether any violation interrupt is enabled - * - * @return true/false (yes/no) - */ -bool IRAM_ATTR esp_memprot_is_intr_ena_any(void); - -/** - * @brief Checks whether any violation interrupt is enabled - * - * @return true/false (yes/no) - */ -bool IRAM_ATTR esp_memprot_get_violate_intr_on(mem_type_prot_t mem_type); - -/** - * @brief Returns the address which caused the violation interrupt (if any) - * - * The address is taken from appropriate PMS violation status register, based given Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return faulting address - */ -uint32_t IRAM_ATTR esp_memprot_get_violate_addr(mem_type_prot_t mem_type); - -/** - * @brief Returns the World identifier of the code causing the violation interrupt (if any) - * - * The value is taken from appropriate PMS violation status register, based given Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return World identifier (see pms_world_t enum) - */ -pms_world_t IRAM_ATTR esp_memprot_get_violate_world(mem_type_prot_t mem_type); - -/** - * @brief Returns Read or Write operation type which caused the violation interrupt (if any) - * - * The value (bit) is taken from appropriate PMS violation status register, based given Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return PMS operation type relevant to mem_type parameter (se pms_operation_type_t) - */ -pms_operation_type_t IRAM_ATTR esp_memprot_get_violate_wr(mem_type_prot_t mem_type); - -/** - * @brief Returns LoadStore flag of the operation type which caused the violation interrupt (if any) - * - * The value (bit) is taken from appropriate PMS violation status register, based given Memory type - * Effective only on IRam0 access - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return true/false (LoadStore bit on/off) - */ -bool IRAM_ATTR esp_memprot_get_violate_loadstore(mem_type_prot_t mem_type); - -/** - * @brief Returns byte-enables for the address which caused the violation interrupt (if any) - * - * The value is taken from appropriate PMS violation status register, based given Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return byte-enables - */ -uint32_t IRAM_ATTR esp_memprot_get_violate_byte_en(mem_type_prot_t mem_type); - -/** - * @brief Returns raw contents of DRam0 status register 1 - * - * @return 32-bit register value - */ -uint32_t IRAM_ATTR esp_memprot_get_dram_status_reg_1(void); - -/** - * @brief Returns raw contents of DRam0 status register 2 - * - * @return 32-bit register value - */ -uint32_t IRAM_ATTR esp_memprot_get_dram_status_reg_2(void); - -/** - * @brief Returns raw contents of IRam0 status register - * - * @return 32-bit register value - */ -uint32_t IRAM_ATTR esp_memprot_get_iram_status_reg(void); - -/** - * @brief Register PMS violation interrupt in global interrupt matrix for given Memory type - * - * Memory protection components uses specific interrupt number, see ETS_MEMPROT_ERR_INUM - * The registration makes the panic-handler routine being called when the interrupt appears - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - */ -void esp_memprot_set_intr_matrix(mem_type_prot_t mem_type); - -/** - * @brief Convenient routine for setting the PMS defaults - * - * Called on application startup, depending on CONFIG_ESP_SYSTEM_MEMPROT_FEATURE Kconfig settings - * For implementation details see 'esp_memprot_set_prot_int' description - * - * @param invoke_panic_handler register all interrupts for panic handling (true/false) - * @param lock_feature lock the defaults to prevent further PMS settings changes (true/false) - * @param mem_type_mask 32-bit field of specific PMS parts to configure (see 'esp_memprot_set_prot_int') - */ -void esp_memprot_set_prot(bool invoke_panic_handler, bool lock_feature, uint32_t *mem_type_mask); - -/** - * @brief Internal routine for setting the PMS defaults - * - * Called on application startup from within 'esp_memprot_set_prot'. Allows setting a specific splitting address - * (main I/D split line) - see the parameter 'split_addr'. If the 'split_addr' equals to NULL, default I/D split line - * is used (&_iram_text_end) and all the remaining lines share the same address. - * The function sets all the split lines and PMS areas to the same space, - * ie there is a single instruction space and single data space at the end. - * The PMS split lines and permission areas scheme described below: - * - * DRam0/DMA IRam0 - * ----------------------------------------------- - * ... | IRam0_PMS_0 | - * DRam0_PMS_0 ----------------------------------------------- IRam0_line1_Split_addr - * ... | IRam0_PMS_1 | - * ... ----------------------------------------------- IRam0_line0_Split_addr - * | IRam0_PMS_2 | - * =============================================== IRam0_DRam0_Split_addr (main I/D) - * | DRam0_PMS_1 | - * DRam0_DMA_line0_Split_addr ----------------------------------------------- ... - * | DRam0_PMS_2 | ... - * DRam0_DMA_line1_Split_addr ----------------------------------------------- IRam0_PMS_3 - * | DRam0_PMS_3 | ... - * ----------------------------------------------- - * - * Default settings provided by 'esp_memprot_set_prot_int' are as follows: - * - * DRam0/DMA IRam0 - * ----------------------------------------------- - * | IRam0_PMS_0 = IRam0_PMS_1 = IRam0_PMS_2 | - * | DRam0_PMS_0 | IRam0_line1_Split_addr - * DRam0_DMA_line0_Split_addr | | = - * = =============================================== IRam0_line0_Split_addr - * DRam0_DMA_line1_Split_addr | | = - * | DRam0_PMS_1 = DRam0_PMS_2 = DRam0_PMS_3 | IRam0_DRam0_Split_addr (main I/D) - * | IRam0_PMS_3 | - * ----------------------------------------------- - * - * Once the memprot feature is locked, it can be unlocked only by digital system reset - * - * @param invoke_panic_handler register all the violation interrupts for panic handling (true/false) - * @param lock_feature lock the defaults to prevent further PMS settings changes (true/false) - * @param split_addr specific main I/D adrees or NULL to use default ($_iram_text_end) - * @param mem_type_mask 32-bit field of specific PMS parts to configure (members of mem_type_prot_t) - */ -void esp_memprot_set_prot_int(bool invoke_panic_handler, bool lock_feature, void *split_addr, uint32_t *mem_type_mask); - -/** - * @brief Returns raw contents of PMS interrupt monitor register for given Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return 32-bit register value - */ -uint32_t esp_memprot_get_monitor_enable_reg(mem_type_prot_t mem_type); - -#ifdef __cplusplus -} -#endif diff --git a/tools/sdk/esp32/include/esp_hw_support/include/soc/esp32s2/memprot.h b/tools/sdk/esp32/include/esp_hw_support/include/soc/esp32s2/memprot.h index 0ebd6474578..596633ac7f2 100644 --- a/tools/sdk/esp32/include/esp_hw_support/include/soc/esp32s2/memprot.h +++ b/tools/sdk/esp32/include/esp_hw_support/include/soc/esp32s2/memprot.h @@ -68,7 +68,7 @@ typedef enum { * The address is given by region-specific global symbol exported from linker script, * it is not read out from related configuration register. */ -uint32_t *IRAM_ATTR esp_memprot_get_split_addr(mem_type_prot_t mem_type); +uint32_t * esp_memprot_get_split_addr(mem_type_prot_t mem_type); /** * @brief Initializes illegal memory access control for required memory section. @@ -116,7 +116,7 @@ esp_err_t esp_memprot_clear_intr(mem_type_prot_t mem_type); * * @return Memory protection area type (see mem_type_prot_t enum) */ -mem_type_prot_t IRAM_ATTR esp_memprot_get_active_intr_memtype(void); +mem_type_prot_t esp_memprot_get_active_intr_memtype(void); /** * @brief Gets interrupt status register contents for specified memory region @@ -141,7 +141,7 @@ esp_err_t esp_memprot_get_fault_reg(mem_type_prot_t mem_type, uint32_t *fault_re * DRAM0: 0 - non-atomic operation, 1 - atomic operation * @return ESP_OK on success, ESP_ERR_INVALID_ARG on failure */ -esp_err_t IRAM_ATTR esp_memprot_get_fault_status(mem_type_prot_t mem_type, uint32_t **faulting_address, uint32_t *op_type, uint32_t *op_subtype); +esp_err_t esp_memprot_get_fault_status(mem_type_prot_t mem_type, uint32_t **faulting_address, uint32_t *op_type, uint32_t *op_subtype); /** * @brief Gets string representation of required memory region identifier @@ -150,7 +150,7 @@ esp_err_t IRAM_ATTR esp_memprot_get_fault_status(mem_type_prot_t mem_type, uint3 * * @return mem_type as string */ -const char *IRAM_ATTR esp_memprot_type_to_str(mem_type_prot_t mem_type); +const char * esp_memprot_type_to_str(mem_type_prot_t mem_type); /** * @brief Detects whether any of the interrupt locks is active (requires digital system reset to unlock) diff --git a/tools/sdk/esp32/include/esp_lcd/include/esp_lcd_panel_commands.h b/tools/sdk/esp32/include/esp_lcd/include/esp_lcd_panel_commands.h index 091ef1cffef..5917c3e8774 100644 --- a/tools/sdk/esp32/include/esp_lcd/include/esp_lcd_panel_commands.h +++ b/tools/sdk/esp32/include/esp_lcd/include/esp_lcd_panel_commands.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -31,7 +31,7 @@ #define LCD_CMD_RAMRD 0x2E // Read frame memory #define LCD_CMD_PTLAR 0x30 // Define the partial area #define LCD_CMD_VSCRDEF 0x33 // Vertical scrolling definition -#define LCD_CMD_TEOFF 0x34 // Turns of tearing effect +#define LCD_CMD_TEOFF 0x34 // Turns off tearing effect #define LCD_CMD_TEON 0x35 // Turns on tearing effect #define LCD_CMD_MADCTL 0x36 // Memory data access control @@ -48,7 +48,7 @@ #define LCD_CMD_COLMOD 0x3A // Defines the format of RGB picture data #define LCD_CMD_RAMWRC 0x3C // Memory write continue #define LCD_CMD_RAMRDC 0x3E // Memory read continue -#define LCD_CMD_STE 0x44 // Set tear scanline, tearing effect output signal when display module reaches line N -#define LCD_CMD_GDCAN 0x45 // Get scanline +#define LCD_CMD_STE 0x44 // Set tear scan line, tearing effect output signal when display module reaches line N +#define LCD_CMD_GDCAN 0x45 // Get scan line #define LCD_CMD_WRDISBV 0x51 // Write display brightness #define LCD_CMD_RDDISBV 0x52 // Read display brightness value diff --git a/tools/sdk/esp32/include/esp_lcd/include/esp_lcd_panel_io.h b/tools/sdk/esp32/include/esp_lcd/include/esp_lcd_panel_io.h index c01fe3e441f..de7b434b5f8 100644 --- a/tools/sdk/esp32/include/esp_lcd/include/esp_lcd_panel_io.h +++ b/tools/sdk/esp32/include/esp_lcd/include/esp_lcd_panel_io.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -71,7 +71,7 @@ esp_err_t esp_lcd_panel_io_rx_param(esp_lcd_panel_io_handle_t io, int lcd_cmd, v * this function will wait until they are finished and the queue is empty before sending the command(s). * * @param[in] io LCD panel IO handle, which is created by other factory API like `esp_lcd_new_panel_io_spi()` - * @param[in] lcd_cmd The specific LCD command (set to -1 if no command needed - only in SPI and I2C) + * @param[in] lcd_cmd The specific LCD command, set to -1 if no command needed * @param[in] param Buffer that holds the command specific parameters, set to NULL if no parameter is needed for the command * @param[in] param_size Size of `param` in memory, in bytes, set to zero if no parameter is needed for the command * @return diff --git a/tools/sdk/esp32/include/esp_mm/include/esp_cache.h b/tools/sdk/esp32/include/esp_mm/include/esp_cache.h index 800e8865695..af51a18ed72 100644 --- a/tools/sdk/esp32/include/esp_mm/include/esp_cache.h +++ b/tools/sdk/esp32/include/esp_mm/include/esp_cache.h @@ -41,9 +41,9 @@ extern "C" { * @note You should not call this during any Flash operations (e.g. esp_flash APIs, nvs and some other APIs that are based on esp_flash APIs) * @note If XIP_From_PSRAM is enabled (by enabling both CONFIG_SPIRAM_FETCH_INSTRUCTIONS and CONFIG_SPIRAM_RODATA), you can call this API during Flash operations * - * @param[in] Starting address to do the msync - * @param[in] Size to do the msync - * @param[in] Flags, see `ESP_CACHE_MSYNC_FLAG_x` + * @param[in] addr Starting address to do the msync + * @param[in] size Size to do the msync + * @param[in] flags Flags, see `ESP_CACHE_MSYNC_FLAG_x` * * @return * - ESP_OK: diff --git a/tools/sdk/esp32/include/esp_mm/include/esp_mmu_map.h b/tools/sdk/esp32/include/esp_mm/include/esp_mmu_map.h index 33d3396441d..355b0c97501 100644 --- a/tools/sdk/esp32/include/esp_mm/include/esp_mmu_map.h +++ b/tools/sdk/esp32/include/esp_mm/include/esp_mmu_map.h @@ -47,7 +47,7 @@ extern "C" { * - the to-be-mapped paddr block is overlapped with an already mapped paddr block. * - the to-be-mapped paddr block encloses an already mapped paddr block. * 2. If the to-be-mapped paddr block is enclosed by an already mapped paddr block, no new mapping will happen, return ESP_ERR_INVALID_STATE. The out pointer will be the already mapped paddr corresponding vaddr. - * 3. If the to-be-mapped paddr block is totally the same as an already mapped paddr block, no new mapping will happen, return ESP_ERR_INVALID_STATE. The out pointer will be the corresponding vaddr. + * 3. If the to-be-mapped paddr block is identical with an already mapped paddr block, no new mapping will happen, return ESP_ERR_INVALID_STATE. The out pointer will be the corresponding vaddr. * * - If this flag isn't set, overlapped, enclosed or same to-be-mapped paddr block will lead to ESP_ERR_INVALID_ARG. */ @@ -77,7 +77,7 @@ typedef uint32_t esp_paddr_t; * - ESP_ERR_NOT_FOUND: No enough size free block to use * - ESP_ERR_NO_MEM: Out of memory, this API will allocate some heap memory for internal usage * - ESP_ERR_INVALID_STATE: Paddr is mapped already, this API will return corresponding vaddr_start of the previously mapped block. - * Only to-be-mapped paddr block is totally enclosed by a previously mapped block will lead to this error: + * Only to-be-mapped paddr block is totally enclosed by a previously mapped block will lead to this error. (Identical scenario will behave similarly) * new_block_start new_block_end * |-------- New Block --------| * |--------------- Block ---------------| @@ -156,6 +156,20 @@ esp_err_t esp_mmu_vaddr_to_paddr(void *vaddr, esp_paddr_t *out_paddr, mmu_target */ esp_err_t esp_mmu_paddr_to_vaddr(esp_paddr_t paddr, mmu_target_t target, mmu_vaddr_t type, void **out_vaddr); +/** + * @brief If the physical address is mapped, this API will provide the capabilities of the virtual address where the physical address is mapped to. + * + * @note: Only return value is ESP_OK(which means physically address is successfully mapped), then caps you get make sense. + * @note This API only check one page (see CONFIG_MMU_PAGE_SIZE), starting from the `paddr` + * + * @param[in] paddr Physical address + * @param[out] out_caps Bitwise OR of MMU_MEM_CAP_* flags indicating the capabilities of a virtual address where the physical address is mapped to. + * @return + * - ESP_OK: Physical address successfully mapped. + * - ESP_ERR_INVALID_ARG: Null pointer + * - ESP_ERR_NOT_FOUND: Physical address is not mapped successfully. + */ +esp_err_t esp_mmu_paddr_find_caps(const esp_paddr_t paddr, mmu_mem_caps_t *out_caps); #ifdef __cplusplus } diff --git a/tools/sdk/esp32/include/esp_netif/include/esp_netif.h b/tools/sdk/esp32/include/esp_netif/include/esp_netif.h index 9372b6d1506..2510a1eefee 100644 --- a/tools/sdk/esp32/include/esp_netif/include/esp_netif.h +++ b/tools/sdk/esp32/include/esp_netif/include/esp_netif.h @@ -523,6 +523,34 @@ int esp_netif_get_netif_impl_index(esp_netif_t *esp_netif); */ esp_err_t esp_netif_get_netif_impl_name(esp_netif_t *esp_netif, char* name); +/** + * @brief Enable NAPT on an interface + * + * @note Enable operation can be performed only on one interface at a time. + * NAPT cannot be enabled on multiple interfaces according to this implementation. + * + * @param[in] esp_netif Handle to esp-netif instance + * + * @return + * - ESP_OK + * - ESP_FAIL + * - ESP_ERR_NOT_SUPPORTED +*/ + +esp_err_t esp_netif_napt_enable(esp_netif_t *esp_netif); + +/** + * @brief Disable NAPT on an interface. + * + * @param[in] esp_netif Handle to esp-netif instance + * + * @return + * - ESP_OK + * - ESP_FAIL + * - ESP_ERR_NOT_SUPPORTED +*/ +esp_err_t esp_netif_napt_disable(esp_netif_t *esp_netif); + /** * @} */ diff --git a/tools/sdk/esp32/include/esp_phy/include/esp_phy_init.h b/tools/sdk/esp32/include/esp_phy/include/esp_phy_init.h index 4f30c7795fc..4813e5bdee6 100644 --- a/tools/sdk/esp32/include/esp_phy/include/esp_phy_init.h +++ b/tools/sdk/esp32/include/esp_phy/include/esp_phy_init.h @@ -180,6 +180,15 @@ void esp_phy_disable(void); */ void esp_btbb_enable(void); +/** + * @brief Disable BTBB module + * + * Dsiable BTBB module, used by IEEE802154 or Bluetooth. + * Users should not call this API in their application. + * + */ +void esp_btbb_disable(void); + /** * @brief Load calibration data from NVS and initialize PHY and RF module */ diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32/rom/ets_sys.h b/tools/sdk/esp32/include/esp_rom/include/esp32/rom/ets_sys.h index 6f9688fcf18..549db8ffc63 100644 --- a/tools/sdk/esp32/include/esp_rom/include/esp32/rom/ets_sys.h +++ b/tools/sdk/esp32/include/esp_rom/include/esp32/rom/ets_sys.h @@ -48,7 +48,10 @@ extern "C" { typedef enum { ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1 /**< return failed in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, } ETS_STATUS; typedef uint32_t ETSSignal; @@ -621,13 +624,16 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); #define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) typedef enum { OK = 0, FAIL, PENDING, BUSY, CANCEL, -} STATUS; +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif /** * @} diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32/rom/uart.h b/tools/sdk/esp32/include/esp_rom/include/esp32/rom/uart.h index 3eb59f30f96..3bd0d38f484 100644 --- a/tools/sdk/esp32/include/esp_rom/include/esp32/rom/uart.h +++ b/tools/sdk/esp32/include/esp_rom/include/esp32/rom/uart.h @@ -227,7 +227,7 @@ void uart_buff_switch(uint8_t uart_no); * * @return OK. */ -STATUS uart_tx_one_char(uint8_t TxChar); +ETS_STATUS uart_tx_one_char(uint8_t TxChar); /** * @brief Output a char to message exchange channel, wait until fifo not full. @@ -237,7 +237,7 @@ STATUS uart_tx_one_char(uint8_t TxChar); * * @return OK. */ -STATUS uart_tx_one_char2(uint8_t TxChar); +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); /** * @brief Wait until uart tx full empty. @@ -273,7 +273,7 @@ static inline void IRAM_ATTR uart_tx_wait_idle(uint8_t uart_no) { * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_one_char(uint8_t *pRxChar); +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); /** * @brief Get an input char from message channel, wait until successful. @@ -295,7 +295,7 @@ char uart_rx_one_char_block(void); * * @return OK. */ -STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); /** * @brief Process uart received information in the interrupt handler. @@ -318,7 +318,7 @@ void uart_rx_intr_handler(void *para); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); /** * @brief Get all chars from receive buffer. @@ -329,7 +329,7 @@ STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); * @return OK for successful. * FAIL for failed. */ -STATUS UartGetCmdLn(uint8_t *pCmdLn); +ETS_STATUS UartGetCmdLn(uint8_t *pCmdLn); /** * @brief Get uart configuration struct. @@ -379,7 +379,7 @@ int recv_packet(uint8_t *p, int len, uint8_t is_sync); * @return OK for successful. * FAIL for failed. */ -STATUS SendMsg(uint8_t *pData, uint16_t DataLen); +ETS_STATUS SendMsg(uint8_t *pData, uint16_t DataLen); /** * @brief Receive an packet from download tool, with SLIP escaping. @@ -395,7 +395,7 @@ STATUS SendMsg(uint8_t *pData, uint16_t DataLen); * @return OK for successful. * FAIL for failed. */ -STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync); +ETS_STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync); extern UartDevice UartDev; diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32c2/rom/ets_sys.h b/tools/sdk/esp32/include/esp_rom/include/esp32c2/rom/ets_sys.h index 6d2e3a4ef4e..ad642fcc460 100644 --- a/tools/sdk/esp32/include/esp_rom/include/esp32c2/rom/ets_sys.h +++ b/tools/sdk/esp32/include/esp_rom/include/esp32c2/rom/ets_sys.h @@ -43,7 +43,10 @@ extern "C" { typedef enum { ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1 /**< return failed in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, } ETS_STATUS; typedef ETS_STATUS ets_status_t; @@ -438,13 +441,16 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); #define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) typedef enum { OK = 0, FAIL, PENDING, BUSY, CANCEL, -} STATUS; +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif /** * @} diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32c2/rom/uart.h b/tools/sdk/esp32/include/esp_rom/include/esp32c2/rom/uart.h index 8a4507e8108..454e0d83a11 100644 --- a/tools/sdk/esp32/include/esp_rom/include/esp32c2/rom/uart.h +++ b/tools/sdk/esp32/include/esp_rom/include/esp32c2/rom/uart.h @@ -205,7 +205,7 @@ void uart_tx_switch(uint8_t uart_no); * * @return OK. */ -STATUS uart_tx_one_char(uint8_t TxChar); +ETS_STATUS uart_tx_one_char(uint8_t TxChar); /** * @brief Output a char to message exchange channel, wait until fifo not full. @@ -215,7 +215,7 @@ STATUS uart_tx_one_char(uint8_t TxChar); * * @return OK. */ -STATUS uart_tx_one_char2(uint8_t TxChar); +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); /** * @brief Wait until uart tx full empty. @@ -245,7 +245,7 @@ void uart_tx_wait_idle(uint8_t uart_no); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_one_char(uint8_t *pRxChar); +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); /** * @brief Get an input char from message channel, wait until successful. @@ -267,7 +267,7 @@ char uart_rx_one_char_block(void); * * @return OK. */ -STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); /** * @brief Get an char from receive buffer. @@ -280,7 +280,7 @@ STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); /** * @brief Get all chars from receive buffer. @@ -291,7 +291,7 @@ STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); * @return OK for successful. * FAIL for failed. */ -STATUS UartGetCmdLn(uint8_t *pCmdLn); +ETS_STATUS UartGetCmdLn(uint8_t *pCmdLn); /** * @brief Get uart configuration struct. diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32c3/rom/ets_sys.h b/tools/sdk/esp32/include/esp_rom/include/esp32c3/rom/ets_sys.h index d5489bd835d..06b3b47d8c2 100644 --- a/tools/sdk/esp32/include/esp_rom/include/esp32c3/rom/ets_sys.h +++ b/tools/sdk/esp32/include/esp_rom/include/esp32c3/rom/ets_sys.h @@ -43,7 +43,10 @@ extern "C" { typedef enum { ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1 /**< return failed in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, } ETS_STATUS; typedef ETS_STATUS ets_status_t; @@ -430,13 +433,16 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); #define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) typedef enum { OK = 0, FAIL, PENDING, BUSY, CANCEL, -} STATUS; +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif /** * @} diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32c3/rom/uart.h b/tools/sdk/esp32/include/esp_rom/include/esp32c3/rom/uart.h index 0cd91b06d57..a4fbd52077f 100644 --- a/tools/sdk/esp32/include/esp_rom/include/esp32c3/rom/uart.h +++ b/tools/sdk/esp32/include/esp_rom/include/esp32c3/rom/uart.h @@ -195,7 +195,7 @@ void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue); * * @return OK. */ -STATUS uart_tx_one_char(uint8_t TxChar); +ETS_STATUS uart_tx_one_char(uint8_t TxChar); /** * @brief Output a char to message exchange channel, wait until fifo not full. @@ -205,7 +205,7 @@ STATUS uart_tx_one_char(uint8_t TxChar); * * @return OK. */ -STATUS uart_tx_one_char2(uint8_t TxChar); +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); /** * @brief Wait until uart tx full empty. @@ -235,7 +235,7 @@ void uart_tx_wait_idle(uint8_t uart_no); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_one_char(uint8_t *pRxChar); +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); /** * @brief Get an input char from message channel, wait until successful. @@ -257,7 +257,7 @@ char uart_rx_one_char_block(void); * * @return OK. */ -STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); /** * @brief Get an char from receive buffer. @@ -270,7 +270,7 @@ STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); /** * @brief Get uart configuration struct. diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32c6/rom/ets_sys.h b/tools/sdk/esp32/include/esp_rom/include/esp32c6/rom/ets_sys.h index 48a724d54b8..7c04af3a54c 100644 --- a/tools/sdk/esp32/include/esp_rom/include/esp32c6/rom/ets_sys.h +++ b/tools/sdk/esp32/include/esp_rom/include/esp32c6/rom/ets_sys.h @@ -43,7 +43,10 @@ extern "C" { typedef enum { ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1 /**< return failed in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, } ETS_STATUS; typedef ETS_STATUS ets_status_t; @@ -407,13 +410,16 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); #define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) typedef enum { OK = 0, FAIL, PENDING, BUSY, CANCEL, -} STATUS; +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif /** * @} diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32c6/rom/uart.h b/tools/sdk/esp32/include/esp_rom/include/esp32c6/rom/uart.h index 380f19a4e56..9045c42f6f6 100644 --- a/tools/sdk/esp32/include/esp_rom/include/esp32c6/rom/uart.h +++ b/tools/sdk/esp32/include/esp_rom/include/esp32c6/rom/uart.h @@ -205,7 +205,7 @@ void uart_tx_switch(uint8_t uart_no); * * @return OK. */ -STATUS uart_tx_one_char(uint8_t TxChar); +ETS_STATUS uart_tx_one_char(uint8_t TxChar); /** * @brief Output a char to message exchange channel, wait until fifo not full. @@ -215,7 +215,7 @@ STATUS uart_tx_one_char(uint8_t TxChar); * * @return OK. */ -STATUS uart_tx_one_char2(uint8_t TxChar); +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); /** * @brief Wait until uart tx full empty. @@ -245,7 +245,7 @@ void uart_tx_wait_idle(uint8_t uart_no); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_one_char(uint8_t *pRxChar); +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); /** * @brief Get an input char from message channel, wait until successful. @@ -267,7 +267,7 @@ char uart_rx_one_char_block(void); * * @return OK. */ -STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); /** * @brief Process uart recevied information in the interrupt handler. @@ -290,7 +290,7 @@ void uart_rx_intr_handler(void *para); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); /** * @brief Get all chars from receive buffer. @@ -301,7 +301,7 @@ STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); * @return OK for successful. * FAIL for failed. */ -STATUS UartGetCmdLn(uint8_t *pCmdLn); +ETS_STATUS UartGetCmdLn(uint8_t *pCmdLn); /** * @brief Get uart configuration struct. diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32h2/rom/efuse.h b/tools/sdk/esp32/include/esp_rom/include/esp32h2/rom/efuse.h index 6cd9f4b377e..dc612dff4b8 100644 --- a/tools/sdk/esp32/include/esp_rom/include/esp32h2/rom/efuse.h +++ b/tools/sdk/esp32/include/esp_rom/include/esp32h2/rom/efuse.h @@ -27,7 +27,8 @@ extern "C" { typedef enum { ETS_EFUSE_KEY_PURPOSE_USER = 0, - ETS_EFUSE_KEY_PURPOSE_RESERVED = 1, + ETS_EFUSE_KEY_PURPOSE_ECDSA_KEY = 1, + ETS_EFUSE_KEY_PURPOSE_RESERVED = 2, ETS_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32h2/rom/ets_sys.h b/tools/sdk/esp32/include/esp_rom/include/esp32h2/rom/ets_sys.h index b9ac5a13f41..b9247bc3bdf 100644 --- a/tools/sdk/esp32/include/esp_rom/include/esp32h2/rom/ets_sys.h +++ b/tools/sdk/esp32/include/esp_rom/include/esp32h2/rom/ets_sys.h @@ -43,7 +43,10 @@ extern "C" { typedef enum { ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1 /**< return failed in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, } ETS_STATUS; typedef ETS_STATUS ets_status_t; @@ -406,13 +409,16 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); #define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) typedef enum { OK = 0, FAIL, PENDING, BUSY, CANCEL, -} STATUS; +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif /** * @} diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32h2/rom/uart.h b/tools/sdk/esp32/include/esp_rom/include/esp32h2/rom/uart.h index 380f19a4e56..9045c42f6f6 100644 --- a/tools/sdk/esp32/include/esp_rom/include/esp32h2/rom/uart.h +++ b/tools/sdk/esp32/include/esp_rom/include/esp32h2/rom/uart.h @@ -205,7 +205,7 @@ void uart_tx_switch(uint8_t uart_no); * * @return OK. */ -STATUS uart_tx_one_char(uint8_t TxChar); +ETS_STATUS uart_tx_one_char(uint8_t TxChar); /** * @brief Output a char to message exchange channel, wait until fifo not full. @@ -215,7 +215,7 @@ STATUS uart_tx_one_char(uint8_t TxChar); * * @return OK. */ -STATUS uart_tx_one_char2(uint8_t TxChar); +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); /** * @brief Wait until uart tx full empty. @@ -245,7 +245,7 @@ void uart_tx_wait_idle(uint8_t uart_no); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_one_char(uint8_t *pRxChar); +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); /** * @brief Get an input char from message channel, wait until successful. @@ -267,7 +267,7 @@ char uart_rx_one_char_block(void); * * @return OK. */ -STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); /** * @brief Process uart recevied information in the interrupt handler. @@ -290,7 +290,7 @@ void uart_rx_intr_handler(void *para); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); /** * @brief Get all chars from receive buffer. @@ -301,7 +301,7 @@ STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); * @return OK for successful. * FAIL for failed. */ -STATUS UartGetCmdLn(uint8_t *pCmdLn); +ETS_STATUS UartGetCmdLn(uint8_t *pCmdLn); /** * @brief Get uart configuration struct. diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32h4/rom/ets_sys.h b/tools/sdk/esp32/include/esp_rom/include/esp32h4/rom/ets_sys.h index 902127abfbb..91544de628a 100644 --- a/tools/sdk/esp32/include/esp_rom/include/esp32h4/rom/ets_sys.h +++ b/tools/sdk/esp32/include/esp_rom/include/esp32h4/rom/ets_sys.h @@ -43,7 +43,10 @@ extern "C" { typedef enum { ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1 /**< return failed in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, } ETS_STATUS; typedef ETS_STATUS ets_status_t; @@ -441,13 +444,16 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); #define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) typedef enum { OK = 0, FAIL, PENDING, BUSY, CANCEL, -} STATUS; +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif /** * @} diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32h4/rom/uart.h b/tools/sdk/esp32/include/esp_rom/include/esp32h4/rom/uart.h index d271893d761..28677ac4097 100644 --- a/tools/sdk/esp32/include/esp_rom/include/esp32h4/rom/uart.h +++ b/tools/sdk/esp32/include/esp_rom/include/esp32h4/rom/uart.h @@ -205,7 +205,7 @@ void uart_tx_switch(uint8_t uart_no); * * @return OK. */ -STATUS uart_tx_one_char(uint8_t TxChar); +ETS_STATUS uart_tx_one_char(uint8_t TxChar); /** * @brief Output a char to message exchange channel, wait until fifo not full. @@ -215,7 +215,7 @@ STATUS uart_tx_one_char(uint8_t TxChar); * * @return OK. */ -STATUS uart_tx_one_char2(uint8_t TxChar); +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); /** * @brief Wait until uart tx full empty. @@ -245,7 +245,7 @@ void uart_tx_wait_idle(uint8_t uart_no); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_one_char(uint8_t *pRxChar); +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); /** * @brief Get an input char from message channel, wait until successful. @@ -267,7 +267,7 @@ char uart_rx_one_char_block(void); * * @return OK. */ -STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); /** * @brief Get an char from receive buffer. @@ -280,7 +280,7 @@ STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); /** * @brief Get all chars from receive buffer. @@ -291,7 +291,7 @@ STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); * @return OK for successful. * FAIL for failed. */ -STATUS UartGetCmdLn(uint8_t *pCmdLn); +ETS_STATUS UartGetCmdLn(uint8_t *pCmdLn); /** * @brief Get uart configuration struct. diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/ets_sys.h b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/ets_sys.h index a2cf1adce34..19c1994de71 100644 --- a/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/ets_sys.h +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/ets_sys.h @@ -45,7 +45,10 @@ extern "C" { typedef enum { ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1 /**< return failed in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, } ETS_STATUS; typedef ETS_STATUS ets_status_t; @@ -556,13 +559,16 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); #define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) typedef enum { OK = 0, FAIL, PENDING, BUSY, CANCEL, -} STATUS; +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif /** * @} diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/uart.h b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/uart.h index 899413f3171..491d2c28fbe 100644 --- a/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/uart.h +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/uart.h @@ -1,16 +1,8 @@ -// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _ROM_UART_H_ #define _ROM_UART_H_ @@ -251,7 +243,7 @@ void uart_buff_switch(uint8_t uart_no); * * @return OK. */ -STATUS uart_tx_one_char(uint8_t TxChar); +ETS_STATUS uart_tx_one_char(uint8_t TxChar); /** * @brief Output a char to message exchange channel, wait until fifo not full. @@ -261,7 +253,7 @@ STATUS uart_tx_one_char(uint8_t TxChar); * * @return OK. */ -STATUS uart_tx_one_char2(uint8_t TxChar); +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); /** * @brief Wait until uart tx full empty. @@ -291,7 +283,7 @@ void uart_tx_wait_idle(uint8_t uart_no); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_one_char(uint8_t *pRxChar); +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); /** * @brief Get an input char from message channel, wait until successful. @@ -313,7 +305,7 @@ char uart_rx_one_char_block(void); * * @return OK. */ -STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); /** * @brief Process uart recevied information in the interrupt handler. @@ -336,7 +328,7 @@ void uart_rx_intr_handler(void *para); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); /** * @brief Get all chars from receive buffer. @@ -347,7 +339,7 @@ STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); * @return OK for successful. * FAIL for failed. */ -STATUS UartGetCmdLn(uint8_t *pCmdLn); +ETS_STATUS UartGetCmdLn(uint8_t *pCmdLn); /** * @brief Get uart configuration struct. @@ -397,7 +389,7 @@ int recv_packet(uint8_t *p, int len, uint8_t is_sync); * @return OK for successful. * FAIL for failed. */ -STATUS SendMsg(uint8_t *pData, uint16_t DataLen); +ETS_STATUS SendMsg(uint8_t *pData, uint16_t DataLen); /** * @brief Receive an packet from download tool, with SLIP escaping. @@ -413,7 +405,7 @@ STATUS SendMsg(uint8_t *pData, uint16_t DataLen); * @return OK for successful. * FAIL for failed. */ -STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync); +ETS_STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync); /** * @brief Check if this UART is in download connection. diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/ets_sys.h b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/ets_sys.h index 9047442c36e..83c93b2eb6a 100644 --- a/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/ets_sys.h +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/ets_sys.h @@ -43,7 +43,10 @@ extern "C" { typedef enum { ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1 /**< return failed in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, } ETS_STATUS; typedef ETS_STATUS ets_status_t; @@ -543,13 +546,16 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); #define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) typedef enum { OK = 0, FAIL, PENDING, BUSY, CANCEL, -} STATUS; +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif /** * @} diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/uart.h b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/uart.h index 3486886ad54..864563f7883 100644 --- a/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/uart.h +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/uart.h @@ -203,7 +203,7 @@ void uart_tx_switch(uint8_t uart_no); * * @return OK. */ -STATUS uart_tx_one_char(uint8_t TxChar); +ETS_STATUS uart_tx_one_char(uint8_t TxChar); /** * @brief Output a char to message exchange channel, wait until fifo not full. @@ -213,7 +213,7 @@ STATUS uart_tx_one_char(uint8_t TxChar); * * @return OK. */ -STATUS uart_tx_one_char2(uint8_t TxChar); +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); /** * @brief Wait until uart tx full empty. @@ -243,7 +243,7 @@ void uart_tx_wait_idle(uint8_t uart_no); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_one_char(uint8_t *pRxChar); +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); /** * @brief Get an input char from message channel, wait until successful. @@ -265,7 +265,7 @@ char uart_rx_one_char_block(void); * * @return OK. */ -STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); /** * @brief Get an char from receive buffer. @@ -278,7 +278,7 @@ STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); /** * @brief Get uart configuration struct. diff --git a/tools/sdk/esp32/include/esp_wifi/include/esp_mesh.h b/tools/sdk/esp32/include/esp_wifi/include/esp_mesh.h index 78f65945051..5ba707b527e 100644 --- a/tools/sdk/esp32/include/esp_wifi/include/esp_mesh.h +++ b/tools/sdk/esp32/include/esp_wifi/include/esp_mesh.h @@ -174,7 +174,8 @@ typedef enum { MESH_EVENT_PARENT_DISCONNECTED, /**< parent is disconnected on station interface */ MESH_EVENT_NO_PARENT_FOUND, /**< no parent found */ MESH_EVENT_LAYER_CHANGE, /**< layer changes over the mesh network */ - MESH_EVENT_TODS_STATE, /**< state represents whether the root is able to access external IP network */ + MESH_EVENT_TODS_STATE, /**< state represents whether the root is able to access external IP network. + This state is a manual event that needs to be triggered with esp_mesh_post_toDS_state(). */ MESH_EVENT_VOTE_STARTED, /**< the process of voting a new root is started either by children or by the root */ MESH_EVENT_VOTE_STOPPED, /**< the process of voting a new root is stopped */ MESH_EVENT_ROOT_ADDRESS, /**< the root address is obtained. It is posted by mesh stack automatically. */ @@ -1175,7 +1176,10 @@ esp_err_t esp_mesh_get_rx_pending(mesh_rx_pending_t *pending); int esp_mesh_available_txupQ_num(const mesh_addr_t *addr, uint32_t *xseqno_in); /** - * @brief Set the number of queue + * @brief Set the number of RX queue for the node, the average number of window allocated to one of + * its child node is: wnd = xon_qsize / (2 * max_connection + 1). + * However, the window of each child node is not strictly equal to the average value, + * it is affected by the traffic also. * * @attention This API shall be called before mesh is started. * diff --git a/tools/sdk/esp32/include/esp_wifi/include/esp_wifi.h b/tools/sdk/esp32/include/esp_wifi/include/esp_wifi.h index 863ebb7d702..3c0ade914b1 100644 --- a/tools/sdk/esp32/include/esp_wifi/include/esp_wifi.h +++ b/tools/sdk/esp32/include/esp_wifi/include/esp_wifi.h @@ -660,10 +660,10 @@ esp_err_t esp_wifi_get_country(wifi_country_t *country); /** - * @brief Set MAC address of WiFi station or the soft-AP interface. + * @brief Set MAC address of WiFi station, soft-AP or NAN interface. * * @attention 1. This API can only be called when the interface is disabled - * @attention 2. Soft-AP and station have different MAC addresses, do not set them to be the same. + * @attention 2. Above mentioned interfaces have different MAC addresses, do not set them to be the same. * @attention 3. The bit 0 of the first byte of MAC address can not be 1. For example, the MAC address * can set to be "1a:XX:XX:XX:XX:XX", but can not be "15:XX:XX:XX:XX:XX". * @@ -1151,6 +1151,7 @@ esp_err_t esp_wifi_set_inactive_time(wifi_interface_t ifx, uint16_t sec); * @return * - ESP_OK: succeed * - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init + * - ESP_ERR_WIFI_NOT_STARTED: WiFi is not started by esp_wifi_start * - ESP_ERR_WIFI_ARG: invalid argument */ esp_err_t esp_wifi_get_inactive_time(wifi_interface_t ifx, uint16_t *sec); @@ -1348,6 +1349,19 @@ esp_err_t esp_wifi_sta_get_aid(uint16_t *aid); */ esp_err_t esp_wifi_sta_get_negotiated_phymode(wifi_phy_mode_t *phymode); +/** + * @brief Config dynamic carrier sense + * + * @attention This API should be called after esp_wifi_start(). + * + * @param enabled Dynamic carrier sense is enabled or not. + * + * @return + * - ESP_OK: succeed + * - others: failed + */ +esp_err_t esp_wifi_set_dynamic_cs(bool enabled); + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32/include/esp_wifi/include/esp_wifi_types.h b/tools/sdk/esp32/include/esp_wifi/include/esp_wifi_types.h index ac12c34b497..614bcd2cb5b 100644 --- a/tools/sdk/esp32/include/esp_wifi/include/esp_wifi_types.h +++ b/tools/sdk/esp32/include/esp_wifi/include/esp_wifi_types.h @@ -129,6 +129,7 @@ typedef enum { WIFI_REASON_AP_TSF_RESET = 206, WIFI_REASON_ROAMING = 207, WIFI_REASON_ASSOC_COMEBACK_TIME_TOO_LONG = 208, + WIFI_REASON_SA_QUERY_TIMEOUT = 209, } wifi_err_reason_t; typedef enum { diff --git a/tools/sdk/esp32/include/esp_wifi/wifi_apps/include/esp_nan.h b/tools/sdk/esp32/include/esp_wifi/wifi_apps/include/esp_nan.h index 0fba2bf5f57..9be6bbb6659 100644 --- a/tools/sdk/esp32/include/esp_wifi/wifi_apps/include/esp_nan.h +++ b/tools/sdk/esp32/include/esp_wifi/wifi_apps/include/esp_nan.h @@ -120,8 +120,8 @@ esp_err_t esp_wifi_nan_cancel_service(uint8_t service_id); * @param req NAN Datapath Request parameters. * * @return - * - non-zero: NAN Datapath Identifier - * - zero: failed + * - non-zero NAN Datapath identifier: If NAN datapath req was accepted by publisher + * - zero: If NAN datapath req was rejected by publisher or a timeout occurs */ uint8_t esp_wifi_nan_datapath_req(wifi_nan_datapath_req_t *req); diff --git a/tools/sdk/esp32/include/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/portmacro.h b/tools/sdk/esp32/include/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/portmacro.h index a1adffbd4f3..660c48a950e 100644 --- a/tools/sdk/esp32/include/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/portmacro.h +++ b/tools/sdk/esp32/include/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/portmacro.h @@ -523,6 +523,14 @@ extern void _frxt_setup_switch( void ); //Defined in portasm.S #define portALT_GET_RUN_TIME_COUNTER_VALUE(x) do {x = (uint32_t)esp_timer_get_time();} while(0) #endif +// --------------------- TCB Cleanup ----------------------- + +#if CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP +/* If enabled, users must provide an implementation of vPortCleanUpTCB() */ +extern void vPortCleanUpTCB ( void *pxTCB ); +#define portCLEAN_UP_TCB( pxTCB ) vPortCleanUpTCB( pxTCB ) +#endif /* CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP */ + // -------------- Optimized Task Selection ----------------- #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 @@ -627,7 +635,7 @@ FORCE_INLINE_ATTR BaseType_t xPortGetCoreID(void) /* ------------------------------------------------------ Misc --------------------------------------------------------- * - Miscellaneous porting macros - * - These are not port of the FreeRTOS porting interface, but are used by other FreeRTOS dependent components + * - These are not part of the FreeRTOS porting interface, but are used by other FreeRTOS dependent components * ------------------------------------------------------------------------------------------------------------------ */ // -------------------- Co-Processor ----------------------- diff --git a/tools/sdk/esp32/include/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/FreeRTOSConfig_arch.h b/tools/sdk/esp32/include/freertos/esp_additions/arch/xtensa/include/freertos/FreeRTOSConfig_arch.h similarity index 50% rename from tools/sdk/esp32/include/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/FreeRTOSConfig_arch.h rename to tools/sdk/esp32/include/freertos/esp_additions/arch/xtensa/include/freertos/FreeRTOSConfig_arch.h index cb0c78ec1f8..a7ed6d5e4a3 100644 --- a/tools/sdk/esp32/include/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/FreeRTOSConfig_arch.h +++ b/tools/sdk/esp32/include/freertos/esp_additions/arch/xtensa/include/freertos/FreeRTOSConfig_arch.h @@ -1,18 +1,17 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef FREERTOS_CONFIG_XTENSA_H -#define FREERTOS_CONFIG_XTENSA_H +#pragma once -//Xtensa Archiecture specific configuration. This file is included in the common FreeRTOSConfig.h. +/* Xtensa Architecture specific configuration. This file is included in the common FreeRTOSConfig.h. */ #include "sdkconfig.h" /* Required for configuration-dependent settings. */ -#include "xtensa_config.h" +#include "freertos/xtensa_config.h" /* -------------------------------------------- Xtensa Additional Config ---------------------------------------------- * - Provide Xtensa definitions usually given by -D option when building with xt-make (see readme_xtensa.txt) @@ -27,29 +26,55 @@ * - XT_USE_SWPRI We don't define this (unused) * ------------------------------------------------------------------------------------------------------------------ */ -#define configXT_SIMULATOR 0 -#define configXT_BOARD 1 /* Board mode */ +#define configXT_SIMULATOR 0 +#define configXT_BOARD 1 /* Board mode */ #if CONFIG_FREERTOS_CORETIMER_0 -#define configXT_TIMER_INDEX 0 + #define configXT_TIMER_INDEX 0 #elif CONFIG_FREERTOS_CORETIMER_1 -#define configXT_TIMER_INDEX 1 + #define configXT_TIMER_INDEX 1 #endif -#define configXT_INTEXC_HOOKS 0 +#define configXT_INTEXC_HOOKS 0 -#define configBENCHMARK 0 +#define configBENCHMARK 0 /* ------------------------------------------------- FreeRTOS Config --------------------------------------------------- * - All Vanilla FreeRTOS configuration goes into this section * ------------------------------------------------------------------------------------------------------------------ */ -// ------------------ Scheduler Related -------------------- +/* ------------------ Scheduler Related -------------------- */ +#define configMAX_PRIORITIES ( 25 ) #ifdef CONFIG_FREERTOS_OPTIMIZED_SCHEDULER -#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #else -#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 -#endif -#define configMAX_API_CALL_INTERRUPT_PRIORITY XCHAL_EXCM_LEVEL + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#endif /* CONFIG_FREERTOS_OPTIMIZED_SCHEDULER */ +#define configMINIMAL_STACK_SIZE ( CONFIG_FREERTOS_IDLE_TASK_STACKSIZE + configSTACK_OVERHEAD_TOTAL ) +#define configMAX_API_CALL_INTERRUPT_PRIORITY XCHAL_EXCM_LEVEL + +/* ----------------------- System -------------------------- */ + +#define configUSE_NEWLIB_REENTRANT 1 +#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1 + +/* ----------------------- Memory ------------------------- */ + +/* This isn't used as FreeRTOS will only allocate from internal memory (see + * heap_idf.c). We simply define this macro to span all non-statically-allocated + * shared RAM. */ +#define configTOTAL_HEAP_SIZE ( &_heap_end - &_heap_start ) + +/* ------------------- Run-time Stats ---------------------- */ + +#if CONFIG_FREERTOS_USE_TRACE_FACILITY + /* Used by uxTaskGetSystemState(), and other trace facility functions */ + #define configUSE_TRACE_FACILITY 1 +#endif /* CONFIG_FREERTOS_USE_TRACE_FACILITY */ + +/* -------------------- API Includes ----------------------- */ + +#define INCLUDE_xTaskDelayUntil 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 /* ------------------------------------------------ ESP-IDF Additions -------------------------------------------------- * @@ -60,9 +85,7 @@ * Size needs to be aligned to the stack increment, since the location of * the stack for the 2nd CPU will be calculated using configISR_STACK_SIZE. */ -#define configSTACK_ALIGNMENT 16 +#define configSTACK_ALIGNMENT 16 #ifndef configISR_STACK_SIZE -#define configISR_STACK_SIZE ((CONFIG_FREERTOS_ISR_STACKSIZE + configSTACK_ALIGNMENT - 1) & (~(configSTACK_ALIGNMENT - 1))) + #define configISR_STACK_SIZE ( ( CONFIG_FREERTOS_ISR_STACKSIZE + configSTACK_ALIGNMENT - 1 ) & ( ~( configSTACK_ALIGNMENT - 1 ) ) ) #endif - -#endif // FREERTOS_CONFIG_XTENSA_H diff --git a/tools/sdk/esp32/include/freertos/esp_additions/include/esp_private/freertos_idf_additions_priv.h b/tools/sdk/esp32/include/freertos/esp_additions/include/esp_private/freertos_idf_additions_priv.h new file mode 100644 index 00000000000..c6e6ba81c08 --- /dev/null +++ b/tools/sdk/esp32/include/freertos/esp_additions/include/esp_private/freertos_idf_additions_priv.h @@ -0,0 +1,99 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/* + * This file is like "idf_additions.h" but for private API (i.e., only meant to + * be called by other internally by other + * ESP-IDF components. + */ + +#include "sdkconfig.h" +#include "freertos/FreeRTOS.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/* ----------------------------------------------------------------------------- + * Priority Raise/Restore + * - Special functions to forcefully raise and restore a task's priority + * - Used by cache_utils.c when disabling/enabling the cache + * -------------------------------------------------------------------------- */ + +#if ( INCLUDE_vTaskPrioritySet == 1 ) + + typedef struct + { + UBaseType_t uxPriority; + #if ( configUSE_MUTEXES == 1 ) + UBaseType_t uxBasePriority; + #endif + } prvTaskSavedPriority_t; + +/** + * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be + * available. See the configuration section for more information. + * + * Saves the current priority and current base priority of a task, then + * raises the task's current and base priority to uxNewPriority if + * uxNewPriority is of a higher priority. + * + * Once a task's priority has been raised with this function, the priority + * can be restored by calling prvTaskPriorityRestore() + * + * - Note that this function differs from vTaskPrioritySet() as the task's + * current priority will be modified even if the task has already + * inherited a priority. + * - This function is intended for special circumstance where a task must be + * forced immediately to a higher priority. + * + * For configUSE_MUTEXES == 0: A context switch will occur before the + * function returns if the priority being set is higher than the currently + * executing task. + * + * @note This functions is private and should only be called internally + * within various IDF components. Users should never call this function from + * their application. + * + * @note vTaskPrioritySet() should not be called while a task's priority is + * already raised via this function + * + * @param pxSavedPriority returns base and current priorities + * + * @param uxNewPriority The priority to which the task's priority will be + * set. + */ + void prvTaskPriorityRaise( prvTaskSavedPriority_t * pxSavedPriority, + UBaseType_t uxNewPriority ); + +/** + * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be + * available. + * See the configuration section for more information. + * + * Restore a task's priority that was previously raised by + * prvTaskPriorityRaise(). + * + * For configUSE_MUTEXES == 0: A context switch will occur before the function + * returns if the priority + * being set is higher than the currently executing task. + * + * @note This functions is private and should only be called internally within + * various IDF components. Users should never call this function from their + * application. + * + * @param pxSavedPriority previously saved base and current priorities that need + * to be restored + */ + void prvTaskPriorityRestore( prvTaskSavedPriority_t * pxSavedPriority ); + +#endif // ( INCLUDE_vTaskPrioritySet == 1) + +#ifdef __cplusplus + } +#endif diff --git a/tools/sdk/esp32/include/freertos/esp_additions/include/freertos/FreeRTOSConfig.h b/tools/sdk/esp32/include/freertos/esp_additions/include/freertos/FreeRTOSConfig.h index 182ca817180..3a3c10ea253 100644 --- a/tools/sdk/esp32/include/freertos/esp_additions/include/freertos/FreeRTOSConfig.h +++ b/tools/sdk/esp32/include/freertos/esp_additions/include/freertos/FreeRTOSConfig.h @@ -1,293 +1,285 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H +#pragma once #include "sdkconfig.h" -/* -This file gets pulled into assembly sources. Therefore, some includes need to be wrapped in #ifndef __ASSEMBLER__ -*/ +/* This file gets pulled into assembly sources. Therefore, some includes need to + * be wrapped in #ifndef __ASSEMBLER__ */ #ifndef __ASSEMBLER__ -#include //For configASSERT() + /* For configASSERT() */ + #include #endif /* def __ASSEMBLER__ */ -#ifdef CONFIG_FREERTOS_SMP - -// Pull in the SMP configuration -#include "freertos/FreeRTOSConfig_smp.h" - -#else // CONFIG_FREERTOS_SMP - -// The arch-specific FreeRTOSConfig_arch.h in port//include. -#include "freertos/FreeRTOSConfig_arch.h" - -#if !(defined(FREERTOS_CONFIG_XTENSA_H) \ - || defined(FREERTOS_CONFIG_RISCV_H) \ - || defined(FREERTOS_CONFIG_LINUX_H)) -#error "Needs architecture-speific FreeRTOSConfig.h!" -#endif - /* ----------------------------------------------------- Helpers ------------------------------------------------------- * - Macros that the FreeRTOS configuration macros depend on * ------------------------------------------------------------------------------------------------------------------ */ /* Higher stack checker modes cause overhead on each function call */ #if CONFIG_STACK_CHECK_ALL || CONFIG_STACK_CHECK_STRONG -#define STACK_OVERHEAD_CHECKER 256 + #define STACK_OVERHEAD_CHECKER 256 #else -#define STACK_OVERHEAD_CHECKER 0 + #define STACK_OVERHEAD_CHECKER 0 #endif /* with optimizations disabled, scheduler uses additional stack */ #if CONFIG_COMPILER_OPTIMIZATION_NONE -#define STACK_OVERHEAD_OPTIMIZATION 320 + #define STACK_OVERHEAD_OPTIMIZATION 320 #else -#define STACK_OVERHEAD_OPTIMIZATION 0 + #define STACK_OVERHEAD_OPTIMIZATION 0 #endif /* apptrace mdule increases minimum stack usage */ #if CONFIG_APPTRACE_ENABLE -#define STACK_OVERHEAD_APPTRACE 1280 + #define STACK_OVERHEAD_APPTRACE 1280 #else -#define STACK_OVERHEAD_APPTRACE 0 + #define STACK_OVERHEAD_APPTRACE 0 #endif /* Stack watchpoint decreases minimum usable stack size by up to 60 bytes. - See FreeRTOS FREERTOS_WATCHPOINT_END_OF_STACK option in Kconfig. */ + * See FreeRTOS FREERTOS_WATCHPOINT_END_OF_STACK option in Kconfig. */ #if CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK -#define STACK_OVERHEAD_WATCHPOINT 60 + #define STACK_OVERHEAD_WATCHPOINT 60 #else -#define STACK_OVERHEAD_WATCHPOINT 0 + #define STACK_OVERHEAD_WATCHPOINT 0 #endif -#define configSTACK_OVERHEAD_TOTAL ( \ - STACK_OVERHEAD_CHECKER + \ - STACK_OVERHEAD_OPTIMIZATION + \ - STACK_OVERHEAD_APPTRACE + \ - STACK_OVERHEAD_WATCHPOINT \ - ) +#define configSTACK_OVERHEAD_TOTAL \ + ( \ + STACK_OVERHEAD_CHECKER + \ + STACK_OVERHEAD_OPTIMIZATION + \ + STACK_OVERHEAD_APPTRACE + \ + STACK_OVERHEAD_WATCHPOINT \ + ) + +/* The arch-specific FreeRTOSConfig_arch.h in esp_additions/arch_include/. + * Placed here due to configSTACK_OVERHEAD_TOTAL. Todo: IDF-5712. */ +#include "freertos/FreeRTOSConfig_arch.h" /* ------------------------------------------------- FreeRTOS Config --------------------------------------------------- * - All Vanilla FreeRTOS configuration goes into this section * - Keep this section in-sync with the corresponding version of single-core upstream version of FreeRTOS - * - Don't put any SMP or ESP-IDF exclusive FreeRTOS configurations here. Those go into the next section + * - Don't put any Amazon SMP FreeRTOS or IDF FreeRTOS configurations here. Those go into the next section * - Not all FreeRTOS configuration are listed. Some configurations have default values set in FreeRTOS.h thus don't * need to be explicitly defined. * ------------------------------------------------------------------------------------------------------------------ */ /*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - * - * See http://www.freertos.org/a00110.html - *----------------------------------------------------------*/ - -// ------------------ Scheduler Related -------------------- - -#define configUSE_PREEMPTION 1 -#define configUSE_TICKLESS_IDLE CONFIG_FREERTOS_USE_TICKLESS_IDLE +* Application specific definitions. +* +* These definitions should be adjusted for your particular hardware and +* application requirements. +* +* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE +* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. +* +* See http://www.freertos.org/a00110.html +*----------------------------------------------------------*/ + +/* ------------------ Scheduler Related -------------------- */ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE CONFIG_FREERTOS_USE_TICKLESS_IDLE #if configUSE_TICKLESS_IDLE -#define configEXPECTED_IDLE_TIME_BEFORE_SLEEP CONFIG_FREERTOS_IDLE_TIME_BEFORE_SLEEP -#endif //configUSE_TICKLESS_IDLE -#define configCPU_CLOCK_HZ (CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ * 1000000) -#define configTICK_RATE_HZ CONFIG_FREERTOS_HZ -#ifdef CONFIG_IDF_TARGET_LINUX -#define configMAX_PRIORITIES ( 7 ) // Default in upstream simulator -/* The stack allocated by FreeRTOS will be passed to a pthread. - pthread has a minimal stack size which currently is 16KB. - The rest is for additional structures of the POSIX/Linux port. - This is a magic number since PTHREAD_STACK_MIN seems to not be a constant. */ -#define configMINIMAL_STACK_SIZE ( ( unsigned short ) (0x4000 + 40) / sizeof(portSTACK_TYPE) ) -#else -#define configMAX_PRIORITIES ( 25 ) //This has impact on speed of search for highest priority -#define configMINIMAL_STACK_SIZE ( CONFIG_FREERTOS_IDLE_TASK_STACKSIZE + configSTACK_OVERHEAD_TOTAL ) -#endif -#define configUSE_TIME_SLICING 1 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 0 -#define configKERNEL_INTERRUPT_PRIORITY 1 //Todo: This currently isn't used anywhere - -// ------------- Synchronization Primitives ---------------- - -#define configUSE_MUTEXES 1 -#define configUSE_RECURSIVE_MUTEXES 1 -#define configUSE_COUNTING_SEMAPHORES 1 -#define configUSE_QUEUE_SETS 1 -#define configQUEUE_REGISTRY_SIZE CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE -#define configUSE_TASK_NOTIFICATIONS 1 -#define configTASK_NOTIFICATION_ARRAY_ENTRIES CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES - -// ----------------------- System -------------------------- - -#define configMAX_TASK_NAME_LEN CONFIG_FREERTOS_MAX_TASK_NAME_LEN -#define configNUM_THREAD_LOCAL_STORAGE_POINTERS CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS -#define configSTACK_DEPTH_TYPE uint32_t -#ifndef CONFIG_IDF_TARGET_LINUX -#define configUSE_NEWLIB_REENTRANT 1 -#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1 -#else -#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0 // Default in upstream simulator -#endif + #define configEXPECTED_IDLE_TIME_BEFORE_SLEEP CONFIG_FREERTOS_IDLE_TIME_BEFORE_SLEEP +#endif /* configUSE_TICKLESS_IDLE */ +#define configCPU_CLOCK_HZ ( CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ * 1000000 ) +#define configTICK_RATE_HZ CONFIG_FREERTOS_HZ +#define configUSE_TIME_SLICING 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configKERNEL_INTERRUPT_PRIORITY 1 /*Todo: This currently isn't used anywhere */ + +/* ------------- Synchronization Primitives ---------------- */ + +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_QUEUE_SETS 1 +#define configQUEUE_REGISTRY_SIZE CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE +#define configUSE_TASK_NOTIFICATIONS 1 +#define configTASK_NOTIFICATION_ARRAY_ENTRIES CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES + +/* ----------------------- System -------------------------- */ + +#define configMAX_TASK_NAME_LEN CONFIG_FREERTOS_MAX_TASK_NAME_LEN +#if CONFIG_FREERTOS_SMP +/* Number of TLSP is doubled to store TLSP deletion callbacks */ + #define configNUM_THREAD_LOCAL_STORAGE_POINTERS ( CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS * 2 ) +#else /* CONFIG_FREERTOS_SMP */ + #define configNUM_THREAD_LOCAL_STORAGE_POINTERS CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS +#endif /* CONFIG_FREERTOS_SMP */ +#define configSTACK_DEPTH_TYPE uint32_t #if CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY -#define configENABLE_BACKWARD_COMPATIBILITY 1 -#else -#define configENABLE_BACKWARD_COMPATIBILITY 0 -#endif -#define configASSERT(a) assert(a) - -// ----------------------- Memory ------------------------- - -#define configSUPPORT_STATIC_ALLOCATION 1 -#define configSUPPORT_DYNAMIC_ALLOCATION 1 -#ifdef CONFIG_IDF_TARGET_LINUX -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 65 * 1024 ) ) // Default in upstream simulator -#else -//We define the heap to span all of the non-statically-allocated shared RAM. ToDo: Make sure there -//is some space left for the app and main cpu when running outside of a thread. -#define configTOTAL_HEAP_SIZE (&_heap_end - &_heap_start)//( ( size_t ) (64 * 1024) ) -#endif -#define configAPPLICATION_ALLOCATED_HEAP 1 -#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 - -// ------------------------ Hooks -------------------------- - -#define configUSE_IDLE_HOOK CONFIG_FREERTOS_USE_IDLE_HOOK -#define configUSE_TICK_HOOK CONFIG_FREERTOS_USE_TICK_HOOK + #define configENABLE_BACKWARD_COMPATIBILITY 1 +#else /* CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY */ + #define configENABLE_BACKWARD_COMPATIBILITY 0 +#endif /* CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY */ +#define configASSERT( a ) assert( a ) + +/* ----------------------- Memory ------------------------- */ + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configAPPLICATION_ALLOCATED_HEAP 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +/* ------------------------ Hooks -------------------------- */ + +#if CONFIG_FREERTOS_USE_IDLE_HOOK + #define configUSE_IDLE_HOOK 1 +#else /* CONFIG_FREERTOS_USE_IDLE_HOOK */ + #define configUSE_IDLE_HOOK 0 +#endif /* CONFIG_FREERTOS_USE_IDLE_HOOK */ +#if CONFIG_FREERTOS_USE_TICK_HOOK + #define configUSE_TICK_HOOK 1 +#else /* CONFIG_FREERTOS_USE_TICK_HOOK */ + #define configUSE_TICK_HOOK 0 +#endif /* CONFIG_FREERTOS_USE_TICK_HOOK */ #if CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE -#define configCHECK_FOR_STACK_OVERFLOW 0 + #define configCHECK_FOR_STACK_OVERFLOW 0 #elif CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL -#define configCHECK_FOR_STACK_OVERFLOW 1 + #define configCHECK_FOR_STACK_OVERFLOW 1 #elif CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY -#define configCHECK_FOR_STACK_OVERFLOW 2 -#endif -#define configRECORD_STACK_HIGH_ADDRESS 1 // This must be set as the port requires TCB.pxEndOfStack + #define configCHECK_FOR_STACK_OVERFLOW 2 +#endif /* CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE */ +#define configRECORD_STACK_HIGH_ADDRESS 1 /* This must be set as the port requires TCB.pxEndOfStack */ -// ------------------- Run-time Stats ---------------------- +/* ------------------- Run-time Stats ---------------------- */ #ifdef CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS -#define configGENERATE_RUN_TIME_STATS 1 /* Used by vTaskGetRunTimeStats() */ -#endif -#ifdef CONFIG_IDF_TARGET_LINUX -#define configUSE_TRACE_FACILITY 1 -#else -#ifdef CONFIG_FREERTOS_USE_TRACE_FACILITY -#define configUSE_TRACE_FACILITY 1 /* Used by uxTaskGetSystemState(), and other trace facility functions */ -#endif -#endif + #define configGENERATE_RUN_TIME_STATS 1 /* Used by vTaskGetRunTimeStats() */ +#endif /* CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS */ #ifdef CONFIG_FREERTOS_USE_STATS_FORMATTING_FUNCTIONS -#define configUSE_STATS_FORMATTING_FUNCTIONS 1 /* Used by vTaskList() */ -#endif + #define configUSE_STATS_FORMATTING_FUNCTIONS 1 /* Used by vTaskList() */ +#endif /* CONFIG_FREERTOS_USE_STATS_FORMATTING_FUNCTIONS */ -// -------------------- Co-routines ----------------------- +/* -------------------- Co-routines ----------------------- */ -#define configUSE_CO_ROUTINES 0 // CO_ROUTINES are not supported in ESP-IDF -#define configMAX_CO_ROUTINE_PRIORITIES 2 +#define configUSE_CO_ROUTINES 0 /* CO_ROUTINES are not supported in ESP-IDF */ +#define configMAX_CO_ROUTINE_PRIORITIES 2 -// ------------------- Software Timer ---------------------- +/* ------------------- Software Timer ---------------------- */ -#define configUSE_TIMERS 1 -#define configTIMER_TASK_PRIORITY CONFIG_FREERTOS_TIMER_TASK_PRIORITY -#define configTIMER_QUEUE_LENGTH CONFIG_FREERTOS_TIMER_QUEUE_LENGTH -#define configTIMER_TASK_STACK_DEPTH CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY CONFIG_FREERTOS_TIMER_TASK_PRIORITY +#define configTIMER_QUEUE_LENGTH CONFIG_FREERTOS_TIMER_QUEUE_LENGTH +#define configTIMER_TASK_STACK_DEPTH CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH -// -------------------- API Includes ----------------------- +/* -------------------- API Includes ----------------------- */ #if CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY -#define configENABLE_BACKWARD_COMPATIBILITY 1 -#else -#define configENABLE_BACKWARD_COMPATIBILITY 0 -#endif - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelay 1 -#define INCLUDE_xTaskGetIdleTaskHandle 1 -#define INCLUDE_xTaskAbortDelay 1 -#define INCLUDE_xSemaphoreGetMutexHolder 1 -#define INCLUDE_xTaskGetHandle 1 -#define INCLUDE_uxTaskGetStackHighWaterMark 1 -#define INCLUDE_uxTaskGetStackHighWaterMark2 1 -#define INCLUDE_eTaskGetState 1 -#define INCLUDE_xTaskResumeFromISR 1 -#define INCLUDE_xTimerPendFunctionCall 1 -#define INCLUDE_xTaskGetSchedulerState 1 -#ifdef CONFIG_IDF_TARGET_LINUX -#define INCLUDE_xTaskGetCurrentTaskHandle 0 // not defined in POSIX simulator -#define INCLUDE_vTaskDelayUntil 1 -#else -#define INCLUDE_xTaskDelayUntil 1 -#define INCLUDE_xTaskGetCurrentTaskHandle 1 -#endif -//Unlisted -#define INCLUDE_pxTaskGetStackStart 1 - -// -------------------- Trace Macros ----------------------- + #define configENABLE_BACKWARD_COMPATIBILITY 1 +#else /* CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY */ + #define configENABLE_BACKWARD_COMPATIBILITY 0 +#endif /* CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetIdleTaskHandle 1 +#define INCLUDE_xTaskAbortDelay 1 +#define INCLUDE_xSemaphoreGetMutexHolder 1 +#define INCLUDE_xTaskGetHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_uxTaskGetStackHighWaterMark2 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTaskResumeFromISR 1 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskGetSchedulerState 1 +/* Unlisted */ +#define INCLUDE_pxTaskGetStackStart 1 + +/* -------------------- Trace Macros ----------------------- */ /* -For trace macros. -Note: Include trace macros here and not above as trace macros are dependent on some of the FreeRTOS configs -*/ + * For trace macros. + * Note: Include trace macros here and not above as trace macros are dependent on some of the FreeRTOS configs + */ #ifndef __ASSEMBLER__ -#if CONFIG_SYSVIEW_ENABLE -#include "SEGGER_SYSVIEW_FreeRTOS.h" -#undef INLINE // to avoid redefinition -#endif //CONFIG_SYSVIEW_ENABLE + #if CONFIG_SYSVIEW_ENABLE + #include "SEGGER_SYSVIEW_FreeRTOS.h" + #undef INLINE /* to avoid redefinition */ + #endif /* CONFIG_SYSVIEW_ENABLE */ + + #if CONFIG_FREERTOS_SMP + +/* Default values for trace macros added to ESP-IDF implementation of SYSVIEW + * that is not part of Amazon SMP FreeRTOS. */ + #ifndef traceISR_EXIT + #define traceISR_EXIT() + #endif + #ifndef traceISR_ENTER + #define traceISR_ENTER( _n_ ) + #endif + + #ifndef traceQUEUE_GIVE_FROM_ISR + #define traceQUEUE_GIVE_FROM_ISR( pxQueue ) + #endif + + #ifndef traceQUEUE_GIVE_FROM_ISR_FAILED + #define traceQUEUE_GIVE_FROM_ISR_FAILED( pxQueue ) + #endif + + #ifndef traceQUEUE_SEMAPHORE_RECEIVE + #define traceQUEUE_SEMAPHORE_RECEIVE( pxQueue ) + #endif + #endif /* CONFIG_FREERTOS_SMP */ #endif /* def __ASSEMBLER__ */ -/* ------------------------------------------------ ESP-IDF Additions -------------------------------------------------- - * - All FreeRTOS related configurations no part of Vanilla FreeRTOS goes into this section - * - FreeRTOS configurations related to SMP and ESP-IDF additions go into this section +/* ----------------------------------------------- Amazon SMP FreeRTOS ------------------------------------------------- + * - All Amazon SMP FreeRTOS specific configurations * ------------------------------------------------------------------------------------------------------------------ */ -// ------------------------- SMP --------------------------- - -#ifndef CONFIG_FREERTOS_UNICORE -#define portNUM_PROCESSORS 2 -#else -#define portNUM_PROCESSORS 1 -#endif -#define configNUM_CORES portNUM_PROCESSORS -#ifdef CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID -#define configTASKLIST_INCLUDE_COREID 1 -#endif - -// ---------------------- Features ------------------------- - -#ifdef CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS -#define configTHREAD_LOCAL_STORAGE_DELETE_CALLBACKS 1 -#endif - -#if CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER -#define configCHECK_MUTEX_GIVEN_BY_OWNER 1 -#else -#define configCHECK_MUTEX_GIVEN_BY_OWNER 0 -#endif - -#ifndef __ASSEMBLER__ -#if CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP -extern void vPortCleanUpTCB ( void *pxTCB ); -#define portCLEAN_UP_TCB( pxTCB ) vPortCleanUpTCB( pxTCB ) -#endif -#endif - -// -------------------- Compatibility ---------------------- +#if CONFIG_FREERTOS_SMP + #ifdef CONFIG_FREERTOS_UNICORE + #define configNUM_CORES 1 + #else + #define configNUM_CORES 2 + #endif /* CONFIG_FREERTOS_UNICORE */ + #define configUSE_CORE_AFFINITY 1 + #define configRUN_MULTIPLE_PRIORITIES 1 + #define configUSE_TASK_PREEMPTION_DISABLE 1 + +/* This is always enabled to call IDF style idle hooks, by can be "--Wl,--wrap" + * if users enable CONFIG_FREERTOS_USE_MINIMAL_IDLE_HOOK. */ + #define configUSE_MINIMAL_IDLE_HOOK 1 + +/* IDF Newlib supports dynamic reentrancy. We provide our own __getreent() + * function. */ + #define configNEWLIB_REENTRANT_IS_DYNAMIC 1 +#endif /* CONFIG_FREERTOS_SMP */ + +/* -------------------------------------------------- IDF FreeRTOS ----------------------------------------------------- + * - All IDF FreeRTOS specific configurations + * ------------------------------------------------------------------------------------------------------------------ */ -// backward compatibility for 4.4 -#define xTaskRemoveFromUnorderedEventList vTaskRemoveFromUnorderedEventList +#if !CONFIG_FREERTOS_SMP + #ifdef CONFIG_FREERTOS_UNICORE + #define configNUM_CORES 1 + #else + #define configNUM_CORES 2 + #endif /* CONFIG_FREERTOS_UNICORE */ + #ifdef CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID + #define configTASKLIST_INCLUDE_COREID 1 + #endif /* CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID */ + #ifdef CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS + #define configTHREAD_LOCAL_STORAGE_DELETE_CALLBACKS 1 + #endif /* CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS */ + #if CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER + #define configCHECK_MUTEX_GIVEN_BY_OWNER 1 + #endif /* CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER */ +#endif /* !CONFIG_FREERTOS_SMP */ -#endif // CONFIG_FREERTOS_SMP +/* ------------------------------------------------ ESP-IDF Additions -------------------------------------------------- + * - Any other macros required by the rest of ESP-IDF + * ------------------------------------------------------------------------------------------------------------------ */ -#endif /* FREERTOS_CONFIG_H */ +#define portNUM_PROCESSORS configNUM_CORES diff --git a/tools/sdk/esp32/include/freertos/esp_additions/include/freertos/idf_additions.h b/tools/sdk/esp32/include/freertos/esp_additions/include/freertos/idf_additions.h index 6523575c8da..22aac424b74 100644 --- a/tools/sdk/esp32/include/freertos/esp_additions/include/freertos/idf_additions.h +++ b/tools/sdk/esp32/include/freertos/esp_additions/include/freertos/idf_additions.h @@ -1,45 +1,65 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ +#pragma once + +/* + * This file contains the function prototypes of ESP-IDF specific API additions + * to the FreeRTOS kernel. These API additions are not part of Vanilla (i.e., + * upstream) FreeRTOS and include things such as.... + * - Various helper functions + * - API for ESP-IDF feature additions to FreeRTOS (such as TSLP deletion + * call backs) + */ + #include "sdkconfig.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" -#include "idf_additions_inc.h" -#if CONFIG_FREERTOS_SMP || __DOXYGEN__ +#ifdef __cplusplus + extern "C" { +#endif -/* ------------------------------------------------ Helper Functions --------------------------------------------------- +/* ----------------------------------------------------------------------------- + * SMP related API additions to FreeRTOS * - * ------------------------------------------------------------------------------------------------------------------ */ + * Todo: Move IDF FreeRTOS SMP related additions to this header as well (see + * IDF-7201) + * -------------------------------------------------------------------------- */ + +#if CONFIG_FREERTOS_SMP || __DOXYGEN__ /** * @brief Create a new task that is pinned to a particular core * - * Helper function to create a task that is pinned to a particular core, or has no affinity. In other wrods, the created - * task will have an affinity mask of: + * Helper function to create a task that is pinned to a particular core, or has + * no affinity. In other wrods, the created task will have an affinity mask of: * - (1 << xCoreID) if it is pinned to a particular core * - Set to tskNO_AFFINITY if it has no affinity * * @param pxTaskCode Pointer to the task entry function. * @param pcName A descriptive name for the task. * @param usStackDepth The size of the task stack. - * @param pvParameters Pointer that will be used as the parameter for the task being created. + * @param pvParameters Pointer that will be used as the parameter for the task + * being created. * @param uxPriority The priority at which the task should run. - * @param pxCreatedTask Used to pass back a handle by which the created task can be referenced. - * @param xCoreID The core to which the task is pinned to, or tskNO_AFFINITY if the task has no core affinity - * @return pdPASS if the task was successfully created and added to a ready list, otherwise an error code defined in the - * file projdefs.h + * @param pxCreatedTask Used to pass back a handle by which the created task can + * be referenced. + * @param xCoreID The core to which the task is pinned to, or tskNO_AFFINITY if + * the task has no core affinity + * @return pdPASS if the task was successfully created and added to a ready + * list, otherwise an error code defined in the file projdefs.h */ -BaseType_t xTaskCreatePinnedToCore( TaskFunction_t pxTaskCode, - const char * const pcName, - const uint32_t usStackDepth, - void * const pvParameters, - UBaseType_t uxPriority, - TaskHandle_t * const pxCreatedTask, - const BaseType_t xCoreID); + BaseType_t xTaskCreatePinnedToCore( TaskFunction_t pxTaskCode, + const char * const pcName, + const uint32_t usStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask, + const BaseType_t xCoreID ); /** @@ -50,142 +70,118 @@ BaseType_t xTaskCreatePinnedToCore( TaskFunction_t pxTaskCode, * @param pxTaskCode Pointer to the task entry function. * @param pcName A descriptive name for the task. * @param ulStackDepth The size of the task stack. - * @param pvParameters Pointer that will be used as the parameter for the task being created. + * @param pvParameters Pointer that will be used as the parameter for the task + * being created. * @param uxPriority The priority at which the task should run. - * @param puxStackBuffer Must point to a StackType_t array that has at least ulStackDepth indexes - * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will then be used to hold the task's data structures, - * @param xCoreID The core to which the task is pinned to, or tskNO_AFFINITY if the task has no core affinity + * @param puxStackBuffer Must point to a StackType_t array that has at least + * ulStackDepth indexes + * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will + * then be used to hold the task's data structures, + * @param xCoreID The core to which the task is pinned to, or tskNO_AFFINITY if + * the task has no core affinity * @return The task handle if the task was created, NULL otherwise. */ -#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) -TaskHandle_t xTaskCreateStaticPinnedToCore( TaskFunction_t pxTaskCode, - const char * const pcName, - const uint32_t ulStackDepth, - void * const pvParameters, - UBaseType_t uxPriority, - StackType_t * const puxStackBuffer, - StaticTask_t * const pxTaskBuffer, - const BaseType_t xCoreID ); -#endif /* configSUPPORT_STATIC_ALLOCATION */ + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + TaskHandle_t xTaskCreateStaticPinnedToCore( TaskFunction_t pxTaskCode, + const char * const pcName, + const uint32_t ulStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer, + const BaseType_t xCoreID ); + #endif /* configSUPPORT_STATIC_ALLOCATION */ /** * @brief Get the handle of the task running on a certain core * - * Because of the nature of SMP processing, there is no guarantee that this value will still be valid on return and - * should only be used for debugging purposes. + * Because of the nature of SMP processing, there is no guarantee that this + * value will still be valid on return and should only be used for debugging + * purposes. * - * [refactor-todo] Mark this function as deprecated, call xTaskGetCurrentTaskHandleCPU() instead + * [refactor-todo] Mark this function as deprecated, call + * xTaskGetCurrentTaskHandleCPU() instead * * @param xCoreID The core to query * @return Handle of the current task running on the queried core */ -TaskHandle_t xTaskGetCurrentTaskHandleForCPU( BaseType_t xCoreID ); + TaskHandle_t xTaskGetCurrentTaskHandleForCPU( BaseType_t xCoreID ); /** * @brief Get the handle of idle task for the given CPU. * - * [refactor-todo] Mark this function as deprecated, call xTaskGetIdleTaskHandle() instead + * [refactor-todo] Mark this function as deprecated, call + * xTaskGetIdleTaskHandle() instead * * @param xCoreID The core to query * @return Handle of the idle task for the queried core */ -TaskHandle_t xTaskGetIdleTaskHandleForCPU( BaseType_t xCoreID ); + TaskHandle_t xTaskGetIdleTaskHandleForCPU( BaseType_t xCoreID ); /** * @brief Get the current core affintiy of a particular task * - * Helper function to get the core affinity of a particular task. If the task is pinned to a particular core, the core - * ID is returned. If the task is not pinned to a particular core, tskNO_AFFINITY is returned. + * Helper function to get the core affinity of a particular task. If the task is + * pinned to a particular core, the core ID is returned. If the task is not + * pinned to a particular core, tskNO_AFFINITY is returned. * - * [refactor-todo] Mark this function as deprecated, call vTaskCoreAffinityGet() instead + * [refactor-todo] Mark this function as deprecated, call vTaskCoreAffinityGet() + * instead * * @param xTask The task to query * @return The tasks coreID or tskNO_AFFINITY */ -BaseType_t xTaskGetAffinity( TaskHandle_t xTask ); - -#if ( CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS ) - - /** - * Prototype of local storage pointer deletion callback. - */ - typedef void (*TlsDeleteCallbackFunction_t)( int, void * ); - - /** - * Set local storage pointer and deletion callback. - * - * Each task contains an array of pointers that is dimensioned by the - * configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h. - * The kernel does not use the pointers itself, so the application writer - * can use the pointers for any purpose they wish. - * - * Local storage pointers set for a task can reference dynamically - * allocated resources. This function is similar to - * vTaskSetThreadLocalStoragePointer, but provides a way to release - * these resources when the task gets deleted. For each pointer, - * a callback function can be set. This function will be called - * when task is deleted, with the local storage pointer index - * and value as arguments. - * - * @param xTaskToSet Task to set thread local storage pointer for - * @param xIndex The index of the pointer to set, from 0 to - * configNUM_THREAD_LOCAL_STORAGE_POINTERS - 1. - * @param pvValue Pointer value to set. - * @param pvDelCallback Function to call to dispose of the local - * storage pointer when the task is deleted. - */ - void vTaskSetThreadLocalStoragePointerAndDelCallback( - TaskHandle_t xTaskToSet, - BaseType_t xIndex, - void *pvValue, - TlsDeleteCallbackFunction_t pvDelCallback); -#endif // CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS + BaseType_t xTaskGetAffinity( TaskHandle_t xTask ); #endif // CONFIG_FREERTOS_SMP || __DOXYGEN__ -#if ( INCLUDE_vTaskPrioritySet == 1 ) +/* ----------------------------------------------------------------------------- + * TLSP Deletion Callback related API additions + * + * Todo: Move IDF FreeRTOS TLSP Deletion Callback related additions to this + * header as well (see IDF-7201) + * -------------------------------------------------------------------------- */ + +#if CONFIG_FREERTOS_SMP || __DOXYGEN__ + + #if ( CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS ) /** - * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Saves the current priority and current base priority of a task, then raises the tasks - * current and base priority to uxNewPriority if uxNewPriority is of a higher priority. - * Once a task's priority has been raised with this function, the priority can be restored - * by calling prvTaskPriorityRestore() - * - Note that this function differs from vTaskPrioritySet() as the task's current priority - * will be modified even if the task has already inherited a priority. - * - This function is intended for special circumstance where a task must be forced immediately - * to a higher priority. - * - * For configUSE_MUTEXES == 0: A context switch will occur before the function returns if the priority - * being set is higher than the currently executing task. - * - * @note This functions is private is only be called internally within various IDF components. - * Users should never call this function from their application. - * - * @note vTaskPrioritySet() should not be called while a task's priority is already raised via this function - * - * @param pxSavedPriority returns base and current priorities - * - * @param uxNewPriority The priority to which the task will be set. + * Prototype of local storage pointer deletion callback. */ -void prvTaskPriorityRaise( prvTaskSavedPriority_t * pxSavedPriority, UBaseType_t uxNewPriority ); + typedef void (* TlsDeleteCallbackFunction_t)( int, + void * ); /** - * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Restore a task's priority that was previously raised by prvTaskPriorityRaise(). - * - * For configUSE_MUTEXES == 0: A context switch will occur before the function returns if the priority - * being set is higher than the currently executing task. - * - * @note This functions is private is only be called internally within various IDF components. - * Users should never call this function from their application. - * - * @param pxSavedPriority previously saved base and current priorities that need to be restored + * Set local storage pointer and deletion callback. + * + * Each task contains an array of pointers that is dimensioned by the + * configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h. The + * kernel does not use the pointers itself, so the application writer can use + * the pointers for any purpose they wish. + * + * Local storage pointers set for a task can reference dynamically allocated + * resources. This function is similar to vTaskSetThreadLocalStoragePointer, but + * provides a way to release these resources when the task gets deleted. For + * each pointer, a callback function can be set. This function will be called + * when task is deleted, with the local storage pointer index and value as + * arguments. + * + * @param xTaskToSet Task to set thread local storage pointer for + * @param xIndex The index of the pointer to set, from 0 to + * configNUM_THREAD_LOCAL_STORAGE_POINTERS - 1. + * @param pvValue Pointer value to set. + * @param pvDelCallback Function to call to dispose of the local storage + * pointer when the task is deleted. */ -void prvTaskPriorityRestore( prvTaskSavedPriority_t * pxSavedPriority ); + void vTaskSetThreadLocalStoragePointerAndDelCallback( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue, + TlsDeleteCallbackFunction_t pvDelCallback ); + #endif // CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS + +#endif // CONFIG_FREERTOS_SMP || __DOXYGEN__ -#endif // ( INCLUDE_vTaskPrioritySet == 1) +#ifdef __cplusplus + } +#endif diff --git a/tools/sdk/esp32/include/freertos/esp_additions/include/freertos/idf_additions_inc.h b/tools/sdk/esp32/include/freertos/esp_additions/include/freertos/idf_additions_inc.h deleted file mode 100644 index 25b0b6d9a4d..00000000000 --- a/tools/sdk/esp32/include/freertos/esp_additions/include/freertos/idf_additions_inc.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - - -#ifndef FREERTOS_ADDITITIONS_INC_H_ -#define FREERTOS_ADDITITIONS_INC_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "sdkconfig.h" -#include "freertos/FreeRTOS.h" - -#if ( INCLUDE_vTaskPrioritySet == 1 ) - -typedef struct { - UBaseType_t uxPriority; -#if ( configUSE_MUTEXES == 1 ) - UBaseType_t uxBasePriority; -#endif -} prvTaskSavedPriority_t; - -#endif // ( INCLUDE_vTaskPrioritySet == 1) - -#ifdef __cplusplus -} -#endif - -#endif //FREERTOS_ADDITITIONS_INC_H_ diff --git a/tools/sdk/esp32/include/hal/esp32/include/hal/cache_ll.h b/tools/sdk/esp32/include/hal/esp32/include/hal/cache_ll.h index 263a168bf0f..6255d48a1df 100644 --- a/tools/sdk/esp32/include/hal/esp32/include/hal/cache_ll.h +++ b/tools/sdk/esp32/include/hal/esp32/include/hal/cache_ll.h @@ -99,6 +99,38 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma } } +/** + * Returns enabled buses for a given core + * + * @param cache_id cache ID (when l1 cache is per core) + * + * @return State of enabled buses + */ +__attribute__((always_inline)) +static inline cache_bus_mask_t cache_ll_l1_get_enabled_bus(uint32_t cache_id) +{ + cache_bus_mask_t mask = 0; + HAL_ASSERT(cache_id == 0 || cache_id == 1); + if (cache_id == 0) { + uint32_t bus_mask= DPORT_REG_READ(DPORT_PRO_CACHE_CTRL1_REG); + mask |= (!(bus_mask & DPORT_PRO_CACHE_MASK_IRAM0)) ? CACHE_BUS_IBUS0 : 0; + mask |= (!(bus_mask & DPORT_PRO_CACHE_MASK_IRAM1)) ? CACHE_BUS_IBUS1 : 0; + mask |= (!(bus_mask & DPORT_PRO_CACHE_MASK_IROM0)) ? CACHE_BUS_IBUS2 : 0; + + mask |= (!(bus_mask & DPORT_PRO_CACHE_MASK_DROM0)) ? CACHE_BUS_DBUS0 : 0; + mask |= (!(bus_mask & DPORT_PRO_CACHE_MASK_DRAM1)) ? CACHE_BUS_DBUS1 : 0; + } else { + uint32_t bus_mask= DPORT_REG_READ(DPORT_APP_CACHE_CTRL1_REG); + mask |= (!(bus_mask & DPORT_APP_CACHE_MASK_IRAM0)) ? CACHE_BUS_IBUS0 : 0; + mask |= (!(bus_mask & DPORT_APP_CACHE_MASK_IRAM1)) ? CACHE_BUS_IBUS1 : 0; + mask |= (!(bus_mask & DPORT_APP_CACHE_MASK_IROM0)) ? CACHE_BUS_IBUS2 : 0; + + mask |= (!(bus_mask & DPORT_APP_CACHE_MASK_DROM0)) ? CACHE_BUS_DBUS0 : 0; + mask |= (!(bus_mask & DPORT_APP_CACHE_MASK_DRAM1)) ? CACHE_BUS_DBUS1 : 0; + } + return mask; +} + /** * Disable the Cache Buses * diff --git a/tools/sdk/esp32/include/hal/esp32/include/hal/efuse_ll.h b/tools/sdk/esp32/include/hal/esp32/include/hal/efuse_ll.h index 9cb76f00400..17cdd2b133d 100644 --- a/tools/sdk/esp32/include/hal/esp32/include/hal/efuse_ll.h +++ b/tools/sdk/esp32/include/hal/esp32/include/hal/efuse_ll.h @@ -23,97 +23,95 @@ extern "C" { __attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void) { - return REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_RD_FLASH_CRYPT_CNT); + return EFUSE.blk0_rdata0.rd_flash_crypt_cnt; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void) { - return REG_READ(EFUSE_BLK0_RDATA1_REG); + return EFUSE.blk0_rdata1.rd_mac; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void) { - return REG_GET_FIELD(EFUSE_BLK0_RDATA2_REG, EFUSE_RD_WIFI_MAC_CRC_HIGH) & 0x0000FFFF; + return EFUSE.blk0_rdata2.rd_mac_1; } __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v1_en(void) { - return REG_GET_BIT(EFUSE_BLK0_RDATA6_REG, EFUSE_RD_ABS_DONE_0); + return EFUSE.blk0_rdata6.rd_abs_done_0; } __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void) { - return REG_GET_BIT(EFUSE_BLK0_RDATA6_REG, EFUSE_RD_ABS_DONE_1); + return EFUSE.blk0_rdata6.rd_abs_done_1; } __attribute__((always_inline)) static inline bool efuse_ll_get_sdio_force(void) { - return REG_GET_BIT(EFUSE_BLK0_RDATA4_REG, EFUSE_RD_SDIO_FORCE); + return EFUSE.blk0_rdata4.rd_xpd_sdio_force; } __attribute__((always_inline)) static inline bool efuse_ll_get_xpd_sdio(void) { - return REG_GET_BIT(EFUSE_BLK0_RDATA4_REG, EFUSE_RD_XPD_SDIO_REG); + return EFUSE.blk0_rdata4.rd_xpd_sdio_reg; } __attribute__((always_inline)) static inline bool efuse_ll_get_sdio_tieh(void) { - return REG_GET_BIT(EFUSE_BLK0_RDATA4_REG, EFUSE_RD_SDIO_TIEH); + return EFUSE.blk0_rdata4.rd_xpd_sdio_tieh; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefh(void) { - return REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_RD_SDIO_DREFH); + return (EFUSE.blk0_rdata4.val >> 8) & 0x3; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefm(void) { - return REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_RD_SDIO_DREFM); + return (EFUSE.blk0_rdata4.val >> 10) & 0x3; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefl(void) { - return REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_RD_SDIO_DREFL); + return (EFUSE.blk0_rdata4.val >> 12) & 0x3; } __attribute__((always_inline)) static inline bool efuse_ll_get_blk3_part_reserve(void) { - return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_BLK3_PART_RESERVE); + return EFUSE.blk0_rdata3.rd_blk3_part_reserve; } __attribute__((always_inline)) static inline bool efuse_ll_get_chip_cpu_freq_rated(void) { - return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_RATED); + return EFUSE.blk0_rdata3.rd_chip_cpu_freq_rated; } __attribute__((always_inline)) static inline bool efuse_ll_get_chip_cpu_freq_low(void) { - return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_LOW); + return EFUSE.blk0_rdata3.rd_chip_cpu_freq_low; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void) { - uint32_t pkg_version = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG); - uint32_t pkg_version_4bit = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG_4BIT); - return (pkg_version_4bit << 3) | pkg_version; + return (EFUSE.blk0_rdata3.rd_chip_package_4bit << 3) | EFUSE.blk0_rdata3.rd_chip_package; } // use efuse_hal_get_major_chip_version() to get full major chip version __attribute__((always_inline)) static inline bool efuse_ll_get_chip_ver_rev1(void) { - return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_REV1); + return EFUSE.blk0_rdata3.rd_chip_ver_rev1; } // use efuse_hal_get_major_chip_version() to get full major chip version __attribute__((always_inline)) static inline bool efuse_ll_get_chip_ver_rev2(void) { - return REG_GET_BIT(EFUSE_BLK0_RDATA5_REG, EFUSE_RD_CHIP_VER_REV2); + return EFUSE.blk0_rdata5.rd_chip_ver_rev2; } // use efuse_hal_get_minor_chip_version() to get minor chip version __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void) { - return REG_GET_FIELD(EFUSE_BLK0_RDATA5_REG, EFUSE_RD_WAFER_VERSION_MINOR); + return EFUSE.blk0_rdata5.rd_wafer_version_minor; } __attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void) @@ -123,47 +121,47 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_ver __attribute__((always_inline)) static inline uint32_t efuse_ll_get_coding_scheme(void) { - return REG_GET_FIELD(EFUSE_BLK0_RDATA6_REG, EFUSE_CODING_SCHEME); + return EFUSE.blk0_rdata6.rd_coding_scheme; } __attribute__((always_inline)) static inline bool efuse_ll_get_disable_app_cpu(void) { - return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_DIS_APP_CPU); + return EFUSE.blk0_rdata3.rd_disable_app_cpu; } __attribute__((always_inline)) static inline bool efuse_ll_get_disable_bt(void) { - return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_DIS_BT); + return EFUSE.blk0_rdata3.rd_disable_bt; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_vol_level_hp_inv(void) { - return REG_GET_FIELD(EFUSE_BLK0_RDATA5_REG, EFUSE_RD_VOL_LEVEL_HP_INV); + return EFUSE.blk0_rdata5.rd_vol_level_hp_inv; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_adc_vref(void) { - return REG_GET_FIELD(EFUSE_BLK0_RDATA4_REG, EFUSE_RD_ADC_VREF); + return EFUSE.blk0_rdata4.rd_adc_vref; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_adc1_tp_low(void) { - return REG_GET_FIELD(EFUSE_BLK3_RDATA3_REG, EFUSE_RD_ADC1_TP_LOW); + return EFUSE.blk3_rdata3.rd_adc1_tp_low; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_adc2_tp_low(void) { - return REG_GET_FIELD(EFUSE_BLK3_RDATA3_REG, EFUSE_RD_ADC2_TP_LOW); + return EFUSE.blk3_rdata3.rd_adc2_tp_low; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_adc1_tp_high(void) { - return REG_GET_FIELD(EFUSE_BLK3_RDATA3_REG, EFUSE_RD_ADC1_TP_HIGH); + return EFUSE.blk3_rdata3.rd_adc1_tp_high; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_adc2_tp_high(void) { - return REG_GET_FIELD(EFUSE_BLK3_RDATA3_REG, EFUSE_RD_ADC2_TP_HIGH); + return EFUSE.blk3_rdata3.rd_adc2_tp_high; } __attribute__((always_inline)) static inline bool efuse_ll_get_dec_warnings(unsigned block) @@ -171,7 +169,7 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_dec_warnings(unsi if (block == 0 || block > 4) { return false; } - uint32_t error_reg = REG_GET_FIELD(EFUSE_DEC_STATUS_REG, EFUSE_DEC_WARNINGS); + uint32_t error_reg = EFUSE.dec_status.dec_warnings; return ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block - 1) != 0; } @@ -179,42 +177,42 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_dec_warnings(unsi __attribute__((always_inline)) static inline bool efuse_ll_get_cmd(void) { - return REG_READ(EFUSE_CMD_REG); + return EFUSE.cmd.val; } __attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void) { - REG_WRITE(EFUSE_CMD_REG, EFUSE_READ_CMD); + EFUSE.cmd.read_cmd = 1; } __attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(void) { - REG_WRITE(EFUSE_CMD_REG, EFUSE_PGM_CMD); + EFUSE.cmd.pgm_cmd = 1; } __attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void) { - REG_WRITE(EFUSE_CONF_REG, EFUSE_READ_OP_CODE); + EFUSE.conf.op_code = EFUSE_READ_OP_CODE; } __attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void) { - REG_WRITE(EFUSE_CONF_REG, EFUSE_WRITE_OP_CODE); + EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE; } __attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_div(uint32_t value) { - REG_SET_FIELD(EFUSE_DAC_CONF_REG, EFUSE_DAC_CLK_DIV, value); + EFUSE.dac_conf.dac_clk_div = value; } __attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_sel0(uint32_t value) { - REG_SET_FIELD(EFUSE_CLK_REG, EFUSE_CLK_SEL0, value); + EFUSE.clk.clk_sel0 = value; } __attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_sel1(uint32_t value) { - REG_SET_FIELD(EFUSE_CLK_REG, EFUSE_CLK_SEL1, value); + EFUSE.clk.clk_sel1 = value; } /******************* eFuse control functions *************************/ diff --git a/tools/sdk/esp32/include/hal/include/hal/ecdsa_hal.h b/tools/sdk/esp32/include/hal/include/hal/ecdsa_hal.h new file mode 100644 index 00000000000..d7244b3dc05 --- /dev/null +++ b/tools/sdk/esp32/include/hal/include/hal/ecdsa_hal.h @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/******************************************************************************* + * NOTICE + * The HAL is not public api, don't use in application code. + * See readme.md in soc/README.md + ******************************************************************************/ + +#pragma once + +#include +#include "hal/ecdsa_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * ECDSA peripheral config structure + */ +typedef struct { + ecdsa_mode_t mode; /* Mode of operation */ + ecdsa_curve_t curve; /* Curve to use for operation */ + ecdsa_k_mode_t k_mode; /* Source of K */ + ecdsa_sha_mode_t sha_mode; /* Source of SHA that needs to be signed */ +} ecdsa_hal_config_t; + +/** + * @brief Generate ECDSA signature + * + * @param conf Configuration for ECDSA operation, see ``ecdsa_hal_config_t`` + * @param k Value of K used internally. Set this to NULL if K is generated by hardware + * @param hash Hash that is to be signed + * @param r_out Buffer that will contain `R` component of ECDSA signature + * @param s_out Buffer that will contain `S` component of ECDSA signature + * @param len Length of the r_out and s_out buffer (32 bytes for SECP256R1, 24 for SECP192R1) + */ +void ecdsa_hal_gen_signature(ecdsa_hal_config_t *conf, const uint8_t *k, const uint8_t *hash, + uint8_t *r_out, uint8_t *s_out, uint16_t len); + +/** + * @brief Verify given ECDSA signature + * + * @param conf Configuration for ECDSA operation, see ``ecdsa_hal_config_t`` + * @param hash Hash that was signed + * @param r `R` component of ECDSA signature + * @param s `S` component of ECDSA signature + * @param pub_x X coordinate of public key + * @param pub_y Y coordinate of public key + * @param len Length of r and s buffer (32 bytes for SECP256R1, 24 for SECP192R1) + * + * @return - 0, if the signature matches + * - -1, if verification fails + */ +int ecdsa_hal_verify_signature(ecdsa_hal_config_t *conf, const uint8_t *hash, const uint8_t *r, const uint8_t *s, + const uint8_t *pub_x, const uint8_t *pub_y, uint16_t len); +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/hal/include/hal/ecdsa_types.h b/tools/sdk/esp32/include/hal/include/hal/ecdsa_types.h new file mode 100644 index 00000000000..fdb2f3d3cf0 --- /dev/null +++ b/tools/sdk/esp32/include/hal/include/hal/ecdsa_types.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief ECDSA peripheral work modes + */ +typedef enum { + ECDSA_MODE_SIGN_VERIFY, + ECDSA_MODE_SIGN_GEN, +} ecdsa_mode_t; + +/** + * @brief ECDSA curve options + */ +typedef enum { + ECDSA_CURVE_SECP192R1, + ECDSA_CURVE_SECP256R1, +} ecdsa_curve_t; + +/** + * @brief Source of 'K' used internally for generating signature + */ +typedef enum { + ECDSA_K_USE_TRNG, + ECDSA_K_USER_PROVIDED, +} ecdsa_k_mode_t; + +/** + * @brief Source of SHA message that is to be signed/verified + */ +typedef enum { + ECDSA_Z_USE_SHA_PERI, + ECDSA_Z_USER_PROVIDED, +} ecdsa_sha_mode_t; + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/hal/include/hal/efuse_hal.h b/tools/sdk/esp32/include/hal/include/hal/efuse_hal.h index 2f141b74404..bb11c9ae7b3 100644 --- a/tools/sdk/esp32/include/hal/include/hal/efuse_hal.h +++ b/tools/sdk/esp32/include/hal/include/hal/efuse_hal.h @@ -26,6 +26,15 @@ void efuse_hal_get_mac(uint8_t *mac); */ uint32_t efuse_hal_chip_revision(void); +/** + * @brief Is flash encryption currently enabled in hardware? + * + * Flash encryption is enabled if the FLASH_CRYPT_CNT efuse has an odd number of bits set. + * + * @return true if flash encryption is enabled. + */ +bool efuse_hal_flash_encryption_enabled(void); + /** * @brief Returns major chip version */ diff --git a/tools/sdk/esp32/include/hal/include/hal/modem_clock_hal.h b/tools/sdk/esp32/include/hal/include/hal/modem_clock_hal.h new file mode 100644 index 00000000000..9912308f5eb --- /dev/null +++ b/tools/sdk/esp32/include/hal/include/hal/modem_clock_hal.h @@ -0,0 +1,48 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The HAL layer for MODEM CLOCK + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc/soc_caps.h" +#include "hal/modem_syscon_ll.h" +#include "hal/modem_lpcon_ll.h" +#include "hal/modem_clock_types.h" + +typedef struct { + modem_syscon_dev_t *syscon_dev; + modem_lpcon_dev_t *lpcon_dev; +} modem_clock_hal_context_t; + +#if MAC_SUPPORT_PMU_MODEM_STATE +void modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain, uint32_t bitmap); +#endif + +void modem_clock_hal_enable_fe_clock(modem_clock_hal_context_t *hal, bool enable); + +#if SOC_BT_SUPPORTED +void modem_clock_hal_set_ble_rtc_timer_divisor_value(modem_clock_hal_context_t *hal, uint32_t divider); +void modem_clock_hal_enable_ble_rtc_timer_clock(modem_clock_hal_context_t *hal, bool enable); +void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src); +void modem_clock_hal_deselect_all_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t *hal); +#endif + +void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src); +void modem_clock_hal_deselect_all_coex_lpclk_source(modem_clock_hal_context_t *hal); + +#if SOC_WIFI_SUPPORTED +void modem_clock_hal_select_wifi_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src); +void modem_clock_hal_deselect_all_wifi_lpclk_source(modem_clock_hal_context_t *hal); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/hal/include/hal/rmt_types.h b/tools/sdk/esp32/include/hal/include/hal/rmt_types.h index 1082761d87a..7650c78bb70 100644 --- a/tools/sdk/esp32/include/hal/include/hal/rmt_types.h +++ b/tools/sdk/esp32/include/hal/include/hal/rmt_types.h @@ -1,11 +1,12 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once +#include #include "soc/clk_tree_defs.h" #include "soc/soc_caps.h" @@ -28,12 +29,12 @@ typedef int rmt_clock_source_t; */ typedef union { struct { - unsigned int duration0 : 15; /*!< Duration of level0 */ - unsigned int level0 : 1; /*!< Level of the first part */ - unsigned int duration1 : 15; /*!< Duration of level1 */ - unsigned int level1 : 1; /*!< Level of the second part */ + uint16_t duration0 : 15; /*!< Duration of level0 */ + uint16_t level0 : 1; /*!< Level of the first part */ + uint16_t duration1 : 15; /*!< Duration of level1 */ + uint16_t level1 : 1; /*!< Level of the second part */ }; - unsigned int val; /*!< Equivalent unsigned value for the RMT symbol */ + uint32_t val; /*!< Equivalent unsigned value for the RMT symbol */ } rmt_symbol_word_t; #ifdef __cplusplus diff --git a/tools/sdk/esp32/include/hal/include/hal/spi_slave_hd_hal.h b/tools/sdk/esp32/include/hal/include/hal/spi_slave_hd_hal.h index 099139cc015..d426f97e970 100644 --- a/tools/sdk/esp32/include/hal/include/hal/spi_slave_hd_hal.h +++ b/tools/sdk/esp32/include/hal/include/hal/spi_slave_hd_hal.h @@ -1,16 +1,8 @@ -// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ /******************************************************************************* * NOTICE @@ -258,8 +250,7 @@ int spi_slave_hd_hal_get_rxlen(spi_slave_hd_hal_context_t *hal); */ int spi_slave_hd_hal_get_last_addr(spi_slave_hd_hal_context_t *hal); -#if CONFIG_IDF_TARGET_ESP32S2 -//Append mode is only supported on ESP32S2 now + //////////////////////////////////////////////////////////////////////////////// // Append Mode //////////////////////////////////////////////////////////////////////////////// @@ -315,4 +306,3 @@ esp_err_t spi_slave_hd_hal_txdma_append(spi_slave_hd_hal_context_t *hal, uint8_t * - ESP_ERR_INVALID_STATE: Function called in invalid state. */ esp_err_t spi_slave_hd_hal_rxdma_append(spi_slave_hd_hal_context_t *hal, uint8_t *data, size_t len, void *arg); -#endif //#if CONFIG_IDF_TARGET_ESP32S2 diff --git a/tools/sdk/esp32/include/heap/include/esp_heap_caps.h b/tools/sdk/esp32/include/heap/include/esp_heap_caps.h index e5adf162b83..f3d1026c8b5 100644 --- a/tools/sdk/esp32/include/heap/include/esp_heap_caps.h +++ b/tools/sdk/esp32/include/heap/include/esp_heap_caps.h @@ -11,6 +11,7 @@ #include "multi_heap.h" #include #include "esp_err.h" +#include "esp_attr.h" #ifdef __cplusplus extern "C" { @@ -53,6 +54,26 @@ typedef void (*esp_alloc_failed_hook_t) (size_t size, uint32_t caps, const char */ esp_err_t heap_caps_register_failed_alloc_callback(esp_alloc_failed_hook_t callback); +#ifdef CONFIG_HEAP_USE_HOOKS +/** + * @brief callback called after every allocation + * @param ptr the allocated memory + * @param size in bytes of the allocation + * @param caps Bitwise OR of MALLOC_CAP_* flags indicating the type of memory allocated. + * @note this hook is called on the same thread as the allocation, which may be within a low level operation. + * You should refrain from doing heavy work, logging, flash writes, or any locking. + */ +__attribute__((weak)) IRAM_ATTR void esp_heap_trace_alloc_hook(void* ptr, size_t size, uint32_t caps); + +/** + * @brief callback called after every free + * @param ptr the memory that was freed + * @note this hook is called on the same thread as the allocation, which may be within a low level operation. + * You should refrain from doing heavy work, logging, flash writes, or any locking. + */ +__attribute__((weak)) IRAM_ATTR void esp_heap_trace_free_hook(void* ptr); +#endif + /** * @brief Allocate a chunk of memory which has the given capabilities * diff --git a/tools/sdk/esp32/include/heap/include/esp_heap_trace.h b/tools/sdk/esp32/include/heap/include/esp_heap_trace.h index b1c5d476e4c..2b0daa2e4c6 100644 --- a/tools/sdk/esp32/include/heap/include/esp_heap_trace.h +++ b/tools/sdk/esp32/include/heap/include/esp_heap_trace.h @@ -36,8 +36,11 @@ typedef struct heap_trace_record_t { size_t size; ///< Size of the allocation void *alloced_by[CONFIG_HEAP_TRACING_STACK_DEPTH]; ///< Call stack of the caller which allocated the memory. void *freed_by[CONFIG_HEAP_TRACING_STACK_DEPTH]; ///< Call stack of the caller which freed the memory (all zero if not freed.) -#ifdef CONFIG_HEAP_TRACING_STANDALONE - TAILQ_ENTRY(heap_trace_record_t) tailq; ///< Linked list: prev & next records +#if CONFIG_HEAP_TRACING_STANDALONE + TAILQ_ENTRY(heap_trace_record_t) tailq_list; ///< Linked list: prev & next records +#if CONFIG_HEAP_TRACE_HASH_MAP + TAILQ_ENTRY(heap_trace_record_t) tailq_hashmap; ///< Linked list: prev & next in hashmap entry list +#endif // CONFIG_HEAP_TRACE_HASH_MAP #endif // CONFIG_HEAP_TRACING_STANDALONE } heap_trace_record_t; @@ -52,6 +55,10 @@ typedef struct { size_t capacity; ///< The capacity of the internal buffer size_t high_water_mark; ///< The maximum value that 'count' got to size_t has_overflowed; ///< True if the internal buffer overflowed at some point +#if CONFIG_HEAP_TRACE_HASH_MAP + size_t total_hashmap_hits; ///< If hashmap is used, the total number of hits + size_t total_hashmap_miss; ///< If hashmap is used, the total number of misses (possibly due to overflow) +#endif } heap_trace_summary_t; /** diff --git a/tools/sdk/esp32/include/mbedtls/port/include/ecdsa/ecdsa_alt.h b/tools/sdk/esp32/include/mbedtls/port/include/ecdsa/ecdsa_alt.h new file mode 100644 index 00000000000..9e2620b3126 --- /dev/null +++ b/tools/sdk/esp32/include/mbedtls/port/include/ecdsa/ecdsa_alt.h @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "sdkconfig.h" +#include "mbedtls/pk.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef CONFIG_MBEDTLS_HARDWARE_ECDSA_SIGN + +/** + * @brief Initialize MPI to notify mbedtls_ecdsa_sign to use the private key in efuse + * We break the MPI struct of the private key in order to + * differentiate between hardware key and software key + * + * @note Currently, `efuse_blk` is not used internally. + * Hardware will choose the efuse block that has purpose set to ECDSA_KEY. + * In case of multiple ECDSA_KEY burnt in efuse, hardware will choose the + * greater efuse block number as the private key. + * + * @param key The MPI in which this functions stores the hardware context. + * This must be uninitialized + * @param efuse_blk The efuse key block that should be used as the private key. + * The key purpose of this block must be ECDSA_KEY + * + * @return - 0 if successful + * - -1 otherwise + * + */ +int esp_ecdsa_privkey_load_mpi(mbedtls_mpi *key, int efuse_blk); + +/** + * @brief Initialize PK context to notify mbedtls_ecdsa_sign to use the private key in efuse + * We break the MPI struct used to represent the private key `d` in ECP keypair + * in order to differentiate between hardware key and software key + * + * @note Currently, `efuse_blk` is not used internally. + * Hardware will choose the efuse block that has purpose set to ECDSA_KEY. + * In case of multiple ECDSA_KEY burnt in efuse, hardware will choose the + * greater efuse block number as the private key. + * + * @param key_ctx The context in which this functions stores the hardware context. + * This must be uninitialized + * @param efuse_blk The efuse key block that should be used as the private key. + * The key purpose of this block must be ECDSA_KEY + * + * @return - 0 if successful + * - -1 otherwise + */ +int esp_ecdsa_privkey_load_pk_context(mbedtls_pk_context *key_ctx, int efuse_blk); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/mbedtls/port/include/mbedtls/esp_config.h b/tools/sdk/esp32/include/mbedtls/port/include/mbedtls/esp_config.h index 71905d8cb3c..ea2efa243ad 100644 --- a/tools/sdk/esp32/include/mbedtls/port/include/mbedtls/esp_config.h +++ b/tools/sdk/esp32/include/mbedtls/port/include/mbedtls/esp_config.h @@ -224,6 +224,7 @@ #undef MBEDTLS_ECP_VERIFY_ALT #undef MBEDTLS_ECP_VERIFY_ALT_SOFT_FALLBACK #endif + /** * \def MBEDTLS_ENTROPY_HARDWARE_ALT * diff --git a/tools/sdk/esp32/include/pthread/include/semaphore.h b/tools/sdk/esp32/include/pthread/include/semaphore.h new file mode 100644 index 00000000000..5a7ef56b971 --- /dev/null +++ b/tools/sdk/esp32/include/pthread/include/semaphore.h @@ -0,0 +1,73 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef unsigned int sem_t; + +/** + * This is the maximum value to which any POSIX semaphore can count on ESP chips. + */ +#define SEM_VALUE_MAX 0x7FFF + +/** + * This is a POSIX function, please refer to the POSIX specification for a detailed description. + * + * Must NOT be called if threads are still blocked on semaphore! + */ +int sem_destroy(sem_t *sem); + +/** + * This is a POSIX function, please refer to the POSIX specification for a detailed description. + * + * Note that on ESP chips, pshared is ignored. Semaphores can always be shared between FreeRTOS tasks. + */ +int sem_init(sem_t *sem, int pshared, unsigned value); + +/** + * This is a POSIX function, please refer to the POSIX specification for a detailed description. + * + * Note that, unlike specified in POSIX, this implementation returns -1 and sets errno to + * EAGAIN if the semaphore can not be unlocked (posted) due to its value being SEM_VALUE_MAX. + */ +int sem_post(sem_t *sem); + +/** + * This is a POSIX function, please refer to the POSIX specification for a detailed description. + * + * Note the following three deviations/issues originating from the underlying FreeRTOS implementation: + * * The time value passed by abstime will be rounded up to the next FreeRTOS tick. + * * The actual timeout will happen after the tick the time was rounded to + * and before the following tick. + * * It is possible, though unlikely, that the task is preempted directly after the timeout calculation, + * delaying timeout of the following blocking operating system call by the duration of the preemption. + */ +int sem_timedwait(sem_t * restrict semaphore, const struct timespec *restrict abstime); + +/** + * This is a POSIX function, please refer to the POSIX specification for a detailed description. + */ +int sem_trywait(sem_t *sem); + +/** + * This is a POSIX function, please refer to the POSIX specification for a detailed description. + */ +int sem_wait(sem_t *sem); + +/** + * This is a POSIX function, please refer to the POSIX specification for a detailed description. + */ +int sem_getvalue(sem_t *restrict sem, int *restrict sval); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/soc/esp32/include/soc/efuse_defs.h b/tools/sdk/esp32/include/soc/esp32/include/soc/efuse_defs.h new file mode 100644 index 00000000000..182e5f0a20e --- /dev/null +++ b/tools/sdk/esp32/include/soc/esp32/include/soc/efuse_defs.h @@ -0,0 +1,51 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define EFUSE_WRITE_OP_CODE 0x5a5a +#define EFUSE_READ_OP_CODE 0x5aa5 + +/* Write disable bits */ +#define EFUSE_WR_DIS_RD_DIS (1<<0) /*< disable writing read disable reg */ +#define EFUSE_WR_DIS_WR_DIS (1<<1) /*< disable writing write disable reg */ +#define EFUSE_WR_DIS_FLASH_CRYPT_CNT (1<<2) +#define EFUSE_WR_DIS_MAC_SPI_CONFIG_HD (1<<3) /*< disable writing MAC & SPI config hd efuses */ +#define EFUSE_WR_DIS_XPD_SDIO (1<<5) /*< disable writing SDIO config efuses */ +#define EFUSE_WR_DIS_SPI_PAD_CONFIG (1<<6) /*< disable writing SPI_PAD_CONFIG efuses */ +#define EFUSE_WR_DIS_BLK1 (1<<7) /*< disable writing BLK1 efuses */ +#define EFUSE_WR_DIS_BLK2 (1<<8) /*< disable writing BLK2 efuses */ +#define EFUSE_WR_DIS_BLK3 (1<<9) /*< disable writing BLK3 efuses */ +#define EFUSE_WR_DIS_FLASH_CRYPT_CODING_SCHEME (1<<10) /*< disable writing FLASH_CRYPT_CONFIG and CODING_SCHEME efuses */ +#define EFUSE_WR_DIS_ABS_DONE_0 (1<<12) /*< disable writing ABS_DONE_0 efuse */ +#define EFUSE_WR_DIS_ABS_DONE_1 (1<<13) /*< disable writing ABS_DONE_1 efuse */ +#define EFUSE_WR_DIS_JTAG_DISABLE (1<<14) /*< disable writing JTAG_DISABLE efuse */ +#define EFUSE_WR_DIS_CONSOLE_DL_DISABLE (1<<15) /*< disable writing CONSOLE_DEBUG_DISABLE, DISABLE_DL_ENCRYPT, DISABLE_DL_DECRYPT and DISABLE_DL_CACHE efuses */ + +/* Read disable bits for efuse blocks 1-3 */ +#define EFUSE_RD_DIS_BLK1 (1<<16) +#define EFUSE_RD_DIS_BLK2 (1<<17) +#define EFUSE_RD_DIS_BLK3 (1<<18) + +#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6 0 +#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5 1 +#define EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 2 +#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 4 /* Deprecated: this chip was never mass produced */ +#define EFUSE_RD_CHIP_VER_PKG_ESP32U4WDH 4 +#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 5 +#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302 6 +#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDR2V3 7 + +#define EFUSE_CODING_SCHEME_VAL_NONE 0x0 +#define EFUSE_CODING_SCHEME_VAL_34 0x1 +#define EFUSE_CODING_SCHEME_VAL_REPEAT 0x2 + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/soc/esp32/include/soc/efuse_reg.h b/tools/sdk/esp32/include/soc/esp32/include/soc/efuse_reg.h index f687938a52f..f8c9e01806e 100644 --- a/tools/sdk/esp32/include/soc/esp32/include/soc/efuse_reg.h +++ b/tools/sdk/esp32/include/soc/esp32/include/soc/efuse_reg.h @@ -1,1181 +1,1394 @@ -/* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_EFUSE_REG_H_ -#define _SOC_EFUSE_REG_H_ - - -#include "soc.h" -#define EFUSE_BLK0_RDATA0_REG (DR_REG_EFUSE_BASE + 0x000) -/* EFUSE_RD_FLASH_CRYPT_CNT : RO ;bitpos:[26:20] ;default: 7'b0 ; */ -/*description: read for flash_crypt_cnt*/ -#define EFUSE_RD_FLASH_CRYPT_CNT 0x0000007F -#define EFUSE_RD_FLASH_CRYPT_CNT_M ((EFUSE_RD_FLASH_CRYPT_CNT_V)<<(EFUSE_RD_FLASH_CRYPT_CNT_S)) -#define EFUSE_RD_FLASH_CRYPT_CNT_V 0x7F -#define EFUSE_RD_FLASH_CRYPT_CNT_S 20 -/* EFUSE_RD_EFUSE_RD_DIS : RO ;bitpos:[19:16] ;default: 4'b0 ; */ -/*description: read for efuse_rd_disable*/ -#define EFUSE_RD_EFUSE_RD_DIS 0x0000000F -#define EFUSE_RD_EFUSE_RD_DIS_M ((EFUSE_RD_EFUSE_RD_DIS_V)<<(EFUSE_RD_EFUSE_RD_DIS_S)) -#define EFUSE_RD_EFUSE_RD_DIS_V 0xF -#define EFUSE_RD_EFUSE_RD_DIS_S 16 - -/* Read disable bits for efuse blocks 1-3 */ -#define EFUSE_RD_DIS_BLK1 (1<<16) -#define EFUSE_RD_DIS_BLK2 (1<<17) -#define EFUSE_RD_DIS_BLK3 (1<<18) -/* Read disable FLASH_CRYPT_CONFIG, CODING_SCHEME & KEY_STATUS - in efuse block 0 -*/ -#define EFUSE_RD_DIS_BLK0_PARTIAL (1<<19) - -/* EFUSE_RD_EFUSE_WR_DIS : RO ;bitpos:[15:0] ;default: 16'b0 ; */ -/*description: read for efuse_wr_disable*/ -#define EFUSE_RD_EFUSE_WR_DIS 0x0000FFFF -#define EFUSE_RD_EFUSE_WR_DIS_M ((EFUSE_RD_EFUSE_WR_DIS_V)<<(EFUSE_RD_EFUSE_WR_DIS_S)) -#define EFUSE_RD_EFUSE_WR_DIS_V 0xFFFF +#pragma once + +#include +#include "soc/soc.h" +#include "efuse_defs.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** EFUSE_BLK0_RDATA0_REG register */ +#define EFUSE_BLK0_RDATA0_REG (DR_REG_EFUSE_BASE + 0x0) +/** EFUSE_RD_EFUSE_WR_DIS : R; bitpos: [15:0]; default: 0; + * read for efuse_wr_disable + */ +#define EFUSE_RD_EFUSE_WR_DIS 0x0000FFFFU +#define EFUSE_RD_EFUSE_WR_DIS_M (EFUSE_RD_EFUSE_WR_DIS_V << EFUSE_RD_EFUSE_WR_DIS_S) +#define EFUSE_RD_EFUSE_WR_DIS_V 0x0000FFFFU #define EFUSE_RD_EFUSE_WR_DIS_S 0 - -/* Write disable bits */ -#define EFUSE_WR_DIS_RD_DIS (1<<0) /*< disable writing read disable reg */ -#define EFUSE_WR_DIS_WR_DIS (1<<1) /*< disable writing write disable reg */ -#define EFUSE_WR_DIS_FLASH_CRYPT_CNT (1<<2) -#define EFUSE_WR_DIS_MAC_SPI_CONFIG_HD (1<<3) /*< disable writing MAC & SPI config hd efuses */ -#define EFUSE_WR_DIS_XPD_SDIO (1<<5) /*< disable writing SDIO config efuses */ -#define EFUSE_WR_DIS_SPI_PAD_CONFIG (1<<6) /*< disable writing SPI_PAD_CONFIG efuses */ -#define EFUSE_WR_DIS_BLK1 (1<<7) /*< disable writing BLK1 efuses */ -#define EFUSE_WR_DIS_BLK2 (1<<8) /*< disable writing BLK2 efuses */ -#define EFUSE_WR_DIS_BLK3 (1<<9) /*< disable writing BLK3 efuses */ -#define EFUSE_WR_DIS_FLASH_CRYPT_CODING_SCHEME (1<<10) /*< disable writing FLASH_CRYPT_CONFIG and CODING_SCHEME efuses */ -#define EFUSE_WR_DIS_ABS_DONE_0 (1<<12) /*< disable writing ABS_DONE_0 efuse */ -#define EFUSE_WR_DIS_ABS_DONE_1 (1<<13) /*< disable writing ABS_DONE_1 efuse */ -#define EFUSE_WR_DIS_JTAG_DISABLE (1<<14) /*< disable writing JTAG_DISABLE efuse */ -#define EFUSE_WR_DIS_CONSOLE_DL_DISABLE (1<<15) /*< disable writing CONSOLE_DEBUG_DISABLE, DISABLE_DL_ENCRYPT, DISABLE_DL_DECRYPT and DISABLE_DL_CACHE efuses */ - -#define EFUSE_BLK0_RDATA1_REG (DR_REG_EFUSE_BASE + 0x004) -/* EFUSE_RD_WIFI_MAC_CRC_LOW : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: read for low 32bit WIFI_MAC_Address*/ -#define EFUSE_RD_WIFI_MAC_CRC_LOW 0xFFFFFFFF -#define EFUSE_RD_WIFI_MAC_CRC_LOW_M ((EFUSE_RD_WIFI_MAC_CRC_LOW_V)<<(EFUSE_RD_WIFI_MAC_CRC_LOW_S)) -#define EFUSE_RD_WIFI_MAC_CRC_LOW_V 0xFFFFFFFF -#define EFUSE_RD_WIFI_MAC_CRC_LOW_S 0 - -#define EFUSE_BLK0_RDATA2_REG (DR_REG_EFUSE_BASE + 0x008) -/* EFUSE_RD_WIFI_MAC_CRC_HIGH : RO ;bitpos:[23:0] ;default: 24'b0 ; */ -/*description: read for high 24bit WIFI_MAC_Address*/ -#define EFUSE_RD_WIFI_MAC_CRC_HIGH 0x00FFFFFF -#define EFUSE_RD_WIFI_MAC_CRC_HIGH_M ((EFUSE_RD_WIFI_MAC_CRC_HIGH_V)<<(EFUSE_RD_WIFI_MAC_CRC_HIGH_S)) -#define EFUSE_RD_WIFI_MAC_CRC_HIGH_V 0xFFFFFF -#define EFUSE_RD_WIFI_MAC_CRC_HIGH_S 0 - -#define EFUSE_BLK0_RDATA3_REG (DR_REG_EFUSE_BASE + 0x00c) -/* EFUSE_RD_CHIP_VER_REV1 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: bit is set to 1 for rev1 silicon*/ -#define EFUSE_RD_CHIP_VER_REV1 (BIT(15)) -#define EFUSE_RD_CHIP_VER_REV1_M ((EFUSE_RD_CHIP_VER_REV1_V)<<(EFUSE_RD_CHIP_VER_REV1_S)) -#define EFUSE_RD_CHIP_VER_REV1_V 0x1 -#define EFUSE_RD_CHIP_VER_REV1_S 15 -/* EFUSE_RD_BLK3_PART_RESERVE : R/W ; bitpos:[14] ; default: 1'b0; */ -/*description: If set, this bit indicates that BLOCK3[143:96] is reserved for internal use*/ -#define EFUSE_RD_BLK3_PART_RESERVE (BIT(14)) -#define EFUSE_RD_BLK3_PART_RESERVE_M ((EFUSE_RD_BLK3_PART_RESERVE_V)<<(EFUSE_RD_BLK3_PART_RESERVE_S)) -#define EFUSE_RD_BLK3_PART_RESERVE_V 0x1 -#define EFUSE_RD_BLK3_PART_RESERVE_S 14 -/* EFUSE_RD_CHIP_CPU_FREQ_RATED : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: If set, the ESP32's maximum CPU frequency has been rated*/ -#define EFUSE_RD_CHIP_CPU_FREQ_RATED (BIT(13)) -#define EFUSE_RD_CHIP_CPU_FREQ_RATED_M ((EFUSE_RD_CHIP_CPU_FREQ_RATED_V)<<(EFUSE_RD_CHIP_CPU_FREQ_RATED_S)) -#define EFUSE_RD_CHIP_CPU_FREQ_RATED_V 0x1 -#define EFUSE_RD_CHIP_CPU_FREQ_RATED_S 13 -/* EFUSE_RD_CHIP_CPU_FREQ_LOW : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise*/ -#define EFUSE_RD_CHIP_CPU_FREQ_LOW (BIT(12)) -#define EFUSE_RD_CHIP_CPU_FREQ_LOW_M ((EFUSE_RD_CHIP_CPU_FREQ_LOW_V)<<(EFUSE_RD_CHIP_CPU_FREQ_LOW_S)) -#define EFUSE_RD_CHIP_CPU_FREQ_LOW_V 0x1 -#define EFUSE_RD_CHIP_CPU_FREQ_LOW_S 12 -/* EFUSE_RD_CHIP_VER_PKG : R/W ;bitpos:[11:9] ;default: 3'b0 ; */ -/*description: least significant bits of chip package */ -#define EFUSE_RD_CHIP_VER_PKG 0x00000007 -#define EFUSE_RD_CHIP_VER_PKG_M ((EFUSE_RD_CHIP_VER_PKG_V)<<(EFUSE_RD_CHIP_VER_PKG_S)) -#define EFUSE_RD_CHIP_VER_PKG_V 0x7 -#define EFUSE_RD_CHIP_VER_PKG_S 9 -#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6 0 -#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5 1 -#define EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 2 -#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 4 /* Deprecated: this chip was never mass produced */ -#define EFUSE_RD_CHIP_VER_PKG_ESP32U4WDH 4 -#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 5 -#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302 6 -#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDR2V3 7 -/* EFUSE_RD_SPI_PAD_CONFIG_HD : RO ;bitpos:[8:4] ;default: 5'b0 ; */ -/*description: read for SPI_pad_config_hd*/ -#define EFUSE_RD_SPI_PAD_CONFIG_HD 0x0000001F -#define EFUSE_RD_SPI_PAD_CONFIG_HD_M ((EFUSE_RD_SPI_PAD_CONFIG_HD_V)<<(EFUSE_RD_SPI_PAD_CONFIG_HD_S)) -#define EFUSE_RD_SPI_PAD_CONFIG_HD_V 0x1F +/** EFUSE_RD_EFUSE_RD_DIS : R; bitpos: [19:16]; default: 0; + * read for efuse_rd_disable + */ +#define EFUSE_RD_EFUSE_RD_DIS 0x0000000FU +#define EFUSE_RD_EFUSE_RD_DIS_M (EFUSE_RD_EFUSE_RD_DIS_V << EFUSE_RD_EFUSE_RD_DIS_S) +#define EFUSE_RD_EFUSE_RD_DIS_V 0x0000000FU +#define EFUSE_RD_EFUSE_RD_DIS_S 16 +/** EFUSE_RD_FLASH_CRYPT_CNT : R; bitpos: [26:20]; default: 0; + * read for flash_crypt_cnt + */ +#define EFUSE_RD_FLASH_CRYPT_CNT 0x0000007FU +#define EFUSE_RD_FLASH_CRYPT_CNT_M (EFUSE_RD_FLASH_CRYPT_CNT_V << EFUSE_RD_FLASH_CRYPT_CNT_S) +#define EFUSE_RD_FLASH_CRYPT_CNT_V 0x0000007FU +#define EFUSE_RD_FLASH_CRYPT_CNT_S 20 +/** EFUSE_RD_UART_DOWNLOAD_DIS : R; bitpos: [27]; default: 0; + * Disable UART download mode. Valid for ESP32 V3 and newer, only + */ +#define EFUSE_RD_UART_DOWNLOAD_DIS (BIT(27)) +#define EFUSE_RD_UART_DOWNLOAD_DIS_M (EFUSE_RD_UART_DOWNLOAD_DIS_V << EFUSE_RD_UART_DOWNLOAD_DIS_S) +#define EFUSE_RD_UART_DOWNLOAD_DIS_V 0x00000001U +#define EFUSE_RD_UART_DOWNLOAD_DIS_S 27 +/** EFUSE_RESERVED_0_28 : R; bitpos: [31:28]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_0_28 0x0000000FU +#define EFUSE_RESERVED_0_28_M (EFUSE_RESERVED_0_28_V << EFUSE_RESERVED_0_28_S) +#define EFUSE_RESERVED_0_28_V 0x0000000FU +#define EFUSE_RESERVED_0_28_S 28 + +/** EFUSE_BLK0_RDATA1_REG register */ +#define EFUSE_BLK0_RDATA1_REG (DR_REG_EFUSE_BASE + 0x4) +/** EFUSE_RD_MAC : R; bitpos: [31:0]; default: 0; + * MAC address + */ +#define EFUSE_RD_MAC 0xFFFFFFFFU +#define EFUSE_RD_MAC_M (EFUSE_RD_MAC_V << EFUSE_RD_MAC_S) +#define EFUSE_RD_MAC_V 0xFFFFFFFFU +#define EFUSE_RD_MAC_S 0 + +/** EFUSE_BLK0_RDATA2_REG register */ +#define EFUSE_BLK0_RDATA2_REG (DR_REG_EFUSE_BASE + 0x8) +/** EFUSE_RD_MAC_1 : R; bitpos: [15:0]; default: 0; + * MAC address + */ +#define EFUSE_RD_MAC_1 0x0000FFFFU +#define EFUSE_RD_MAC_1_M (EFUSE_RD_MAC_1_V << EFUSE_RD_MAC_1_S) +#define EFUSE_RD_MAC_1_V 0x0000FFFFU +#define EFUSE_RD_MAC_1_S 0 +/** EFUSE_RD_MAC_CRC : R; bitpos: [23:16]; default: 0; + * CRC8 for MAC address + */ +#define EFUSE_RD_MAC_CRC 0x000000FFU +#define EFUSE_RD_MAC_CRC_M (EFUSE_RD_MAC_CRC_V << EFUSE_RD_MAC_CRC_S) +#define EFUSE_RD_MAC_CRC_V 0x000000FFU +#define EFUSE_RD_MAC_CRC_S 16 +/** EFUSE_RD_RESERVE_0_88 : RW; bitpos: [31:24]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_88 0x000000FFU +#define EFUSE_RD_RESERVE_0_88_M (EFUSE_RD_RESERVE_0_88_V << EFUSE_RD_RESERVE_0_88_S) +#define EFUSE_RD_RESERVE_0_88_V 0x000000FFU +#define EFUSE_RD_RESERVE_0_88_S 24 + +/** EFUSE_BLK0_RDATA3_REG register */ +#define EFUSE_BLK0_RDATA3_REG (DR_REG_EFUSE_BASE + 0xc) +/** EFUSE_RD_DISABLE_APP_CPU : R; bitpos: [0]; default: 0; + * Disables APP CPU + */ +#define EFUSE_RD_DISABLE_APP_CPU (BIT(0)) +#define EFUSE_RD_DISABLE_APP_CPU_M (EFUSE_RD_DISABLE_APP_CPU_V << EFUSE_RD_DISABLE_APP_CPU_S) +#define EFUSE_RD_DISABLE_APP_CPU_V 0x00000001U +#define EFUSE_RD_DISABLE_APP_CPU_S 0 +/** EFUSE_RD_DISABLE_BT : R; bitpos: [1]; default: 0; + * Disables Bluetooth + */ +#define EFUSE_RD_DISABLE_BT (BIT(1)) +#define EFUSE_RD_DISABLE_BT_M (EFUSE_RD_DISABLE_BT_V << EFUSE_RD_DISABLE_BT_S) +#define EFUSE_RD_DISABLE_BT_V 0x00000001U +#define EFUSE_RD_DISABLE_BT_S 1 +/** EFUSE_RD_CHIP_PACKAGE_4BIT : R; bitpos: [2]; default: 0; + * Chip package identifier #4bit + */ +#define EFUSE_RD_CHIP_PACKAGE_4BIT (BIT(2)) +#define EFUSE_RD_CHIP_PACKAGE_4BIT_M (EFUSE_RD_CHIP_PACKAGE_4BIT_V << EFUSE_RD_CHIP_PACKAGE_4BIT_S) +#define EFUSE_RD_CHIP_PACKAGE_4BIT_V 0x00000001U +#define EFUSE_RD_CHIP_PACKAGE_4BIT_S 2 +/** EFUSE_RD_DIS_CACHE : R; bitpos: [3]; default: 0; + * Disables cache + */ +#define EFUSE_RD_DIS_CACHE (BIT(3)) +#define EFUSE_RD_DIS_CACHE_M (EFUSE_RD_DIS_CACHE_V << EFUSE_RD_DIS_CACHE_S) +#define EFUSE_RD_DIS_CACHE_V 0x00000001U +#define EFUSE_RD_DIS_CACHE_S 3 +/** EFUSE_RD_SPI_PAD_CONFIG_HD : R; bitpos: [8:4]; default: 0; + * read for SPI_pad_config_hd + */ +#define EFUSE_RD_SPI_PAD_CONFIG_HD 0x0000001FU +#define EFUSE_RD_SPI_PAD_CONFIG_HD_M (EFUSE_RD_SPI_PAD_CONFIG_HD_V << EFUSE_RD_SPI_PAD_CONFIG_HD_S) +#define EFUSE_RD_SPI_PAD_CONFIG_HD_V 0x0000001FU #define EFUSE_RD_SPI_PAD_CONFIG_HD_S 4 -/* EFUSE_RD_CHIP_VER_DIS_CACHE : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_CHIP_VER_DIS_CACHE (BIT(3)) -#define EFUSE_RD_CHIP_VER_DIS_CACHE_M (BIT(3)) -#define EFUSE_RD_CHIP_VER_DIS_CACHE_V 0x1 -#define EFUSE_RD_CHIP_VER_DIS_CACHE_S 3 -/* EFUSE_RD_CHIP_VER_PKG_4BIT : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: most significant bit of chip package */ -#define EFUSE_RD_CHIP_VER_PKG_4BIT (BIT(2)) -#define EFUSE_RD_CHIP_VER_PKG_4BIT_M (BIT(2)) -#define EFUSE_RD_CHIP_VER_PKG_4BIT_V 0x1 -#define EFUSE_RD_CHIP_VER_PKG_4BIT_S 2 -/* EFUSE_RD_CHIP_VER_DIS_BT : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_CHIP_VER_DIS_BT (BIT(1)) -#define EFUSE_RD_CHIP_VER_DIS_BT_M (BIT(1)) -#define EFUSE_RD_CHIP_VER_DIS_BT_V 0x1 -#define EFUSE_RD_CHIP_VER_DIS_BT_S 1 -/* EFUSE_RD_CHIP_VER_DIS_APP_CPU : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_CHIP_VER_DIS_APP_CPU (BIT(0)) -#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_M (BIT(0)) -#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_V 0x1 -#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_S 0 - -#define EFUSE_BLK0_RDATA4_REG (DR_REG_EFUSE_BASE + 0x010) -/* EFUSE_RD_SDIO_FORCE : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: read for sdio_force*/ -#define EFUSE_RD_SDIO_FORCE (BIT(16)) -#define EFUSE_RD_SDIO_FORCE_M (BIT(16)) -#define EFUSE_RD_SDIO_FORCE_V 0x1 -#define EFUSE_RD_SDIO_FORCE_S 16 -/* EFUSE_RD_SDIO_TIEH : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: read for SDIO_TIEH*/ -#define EFUSE_RD_SDIO_TIEH (BIT(15)) -#define EFUSE_RD_SDIO_TIEH_M (BIT(15)) -#define EFUSE_RD_SDIO_TIEH_V 0x1 -#define EFUSE_RD_SDIO_TIEH_S 15 -/* EFUSE_RD_XPD_SDIO_REG : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: read for XPD_SDIO_REG*/ -#define EFUSE_RD_XPD_SDIO_REG (BIT(14)) -#define EFUSE_RD_XPD_SDIO_REG_M (BIT(14)) -#define EFUSE_RD_XPD_SDIO_REG_V 0x1 -#define EFUSE_RD_XPD_SDIO_REG_S 14 -/* EFUSE_RD_ADC_VREF : R/W ;bitpos:[12:8] ;default: 5'b0 ; */ -/*description: True ADC reference voltage */ -#define EFUSE_RD_ADC_VREF 0x0000001F -#define EFUSE_RD_ADC_VREF_M ((EFUSE_RD_ADC_VREF_V)<<(EFUSE_RD_ADC_VREF_S)) -#define EFUSE_RD_ADC_VREF_V 0x1F +/** EFUSE_RD_CHIP_PACKAGE : RW; bitpos: [11:9]; default: 0; + * Chip package identifier + */ +#define EFUSE_RD_CHIP_PACKAGE 0x00000007U +#define EFUSE_RD_CHIP_PACKAGE_M (EFUSE_RD_CHIP_PACKAGE_V << EFUSE_RD_CHIP_PACKAGE_S) +#define EFUSE_RD_CHIP_PACKAGE_V 0x00000007U +#define EFUSE_RD_CHIP_PACKAGE_S 9 +/** EFUSE_RD_CHIP_CPU_FREQ_LOW : RW; bitpos: [12]; default: 0; + * If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is + * rated for 160MHz. 240MHz otherwise + */ +#define EFUSE_RD_CHIP_CPU_FREQ_LOW (BIT(12)) +#define EFUSE_RD_CHIP_CPU_FREQ_LOW_M (EFUSE_RD_CHIP_CPU_FREQ_LOW_V << EFUSE_RD_CHIP_CPU_FREQ_LOW_S) +#define EFUSE_RD_CHIP_CPU_FREQ_LOW_V 0x00000001U +#define EFUSE_RD_CHIP_CPU_FREQ_LOW_S 12 +/** EFUSE_RD_CHIP_CPU_FREQ_RATED : RW; bitpos: [13]; default: 0; + * If set, the ESP32's maximum CPU frequency has been rated + */ +#define EFUSE_RD_CHIP_CPU_FREQ_RATED (BIT(13)) +#define EFUSE_RD_CHIP_CPU_FREQ_RATED_M (EFUSE_RD_CHIP_CPU_FREQ_RATED_V << EFUSE_RD_CHIP_CPU_FREQ_RATED_S) +#define EFUSE_RD_CHIP_CPU_FREQ_RATED_V 0x00000001U +#define EFUSE_RD_CHIP_CPU_FREQ_RATED_S 13 +/** EFUSE_RD_BLK3_PART_RESERVE : RW; bitpos: [14]; default: 0; + * If set, this bit indicates that BLOCK3[143:96] is reserved for internal use + */ +#define EFUSE_RD_BLK3_PART_RESERVE (BIT(14)) +#define EFUSE_RD_BLK3_PART_RESERVE_M (EFUSE_RD_BLK3_PART_RESERVE_V << EFUSE_RD_BLK3_PART_RESERVE_S) +#define EFUSE_RD_BLK3_PART_RESERVE_V 0x00000001U +#define EFUSE_RD_BLK3_PART_RESERVE_S 14 +/** EFUSE_RD_CHIP_VER_REV1 : RW; bitpos: [15]; default: 0; + * bit is set to 1 for rev1 silicon + */ +#define EFUSE_RD_CHIP_VER_REV1 (BIT(15)) +#define EFUSE_RD_CHIP_VER_REV1_M (EFUSE_RD_CHIP_VER_REV1_V << EFUSE_RD_CHIP_VER_REV1_S) +#define EFUSE_RD_CHIP_VER_REV1_V 0x00000001U +#define EFUSE_RD_CHIP_VER_REV1_S 15 +/** EFUSE_RD_RESERVE_0_112 : RW; bitpos: [31:16]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_112 0x0000FFFFU +#define EFUSE_RD_RESERVE_0_112_M (EFUSE_RD_RESERVE_0_112_V << EFUSE_RD_RESERVE_0_112_S) +#define EFUSE_RD_RESERVE_0_112_V 0x0000FFFFU +#define EFUSE_RD_RESERVE_0_112_S 16 + +/** EFUSE_BLK0_RDATA4_REG register */ +#define EFUSE_BLK0_RDATA4_REG (DR_REG_EFUSE_BASE + 0x10) +/** EFUSE_RD_CLK8M_FREQ : R; bitpos: [7:0]; default: 0; + * 8MHz clock freq override + */ +#define EFUSE_RD_CLK8M_FREQ 0x000000FFU +#define EFUSE_RD_CLK8M_FREQ_M (EFUSE_RD_CLK8M_FREQ_V << EFUSE_RD_CLK8M_FREQ_S) +#define EFUSE_RD_CLK8M_FREQ_V 0x000000FFU +#define EFUSE_RD_CLK8M_FREQ_S 0 +/** EFUSE_RD_ADC_VREF : RW; bitpos: [12:8]; default: 0; + * True ADC reference voltage + */ +#define EFUSE_RD_ADC_VREF 0x0000001FU +#define EFUSE_RD_ADC_VREF_M (EFUSE_RD_ADC_VREF_V << EFUSE_RD_ADC_VREF_S) +#define EFUSE_RD_ADC_VREF_V 0x0000001FU #define EFUSE_RD_ADC_VREF_S 8 -/* Note: EFUSE_ADC_VREF and SDIO_DREFH/M/L share the same address space. Newer - * versions of ESP32 come with EFUSE_ADC_VREF already burned, therefore - * SDIO_DREFH/M/L is only available in older versions of ESP32 */ -/* EFUSE_RD_SDIO_DREFL : RO ;bitpos:[13:12] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_RD_SDIO_DREFL 0x00000003 -#define EFUSE_RD_SDIO_DREFL_M ((EFUSE_RD_SDIO_DREFL_V)<<(EFUSE_RD_SDIO_DREFL_S)) -#define EFUSE_RD_SDIO_DREFL_V 0x3 -#define EFUSE_RD_SDIO_DREFL_S 12 -/* EFUSE_RD_SDIO_DREFM : RO ;bitpos:[11:10] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_RD_SDIO_DREFM 0x00000003 -#define EFUSE_RD_SDIO_DREFM_M ((EFUSE_RD_SDIO_DREFM_V)<<(EFUSE_RD_SDIO_DREFM_S)) -#define EFUSE_RD_SDIO_DREFM_V 0x3 -#define EFUSE_RD_SDIO_DREFM_S 10 -/* EFUSE_RD_SDIO_DREFH : RO ;bitpos:[9:8] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_RD_SDIO_DREFH 0x00000003 -#define EFUSE_RD_SDIO_DREFH_M ((EFUSE_RD_SDIO_DREFH_V)<<(EFUSE_RD_SDIO_DREFH_S)) -#define EFUSE_RD_SDIO_DREFH_V 0x3 -#define EFUSE_RD_SDIO_DREFH_S 8 -/* EFUSE_RD_CK8M_FREQ : RO ;bitpos:[7:0] ;default: 8'b0 ; */ -/*description: */ -#define EFUSE_RD_CK8M_FREQ 0x000000FF -#define EFUSE_RD_CK8M_FREQ_M ((EFUSE_RD_CK8M_FREQ_V)<<(EFUSE_RD_CK8M_FREQ_S)) -#define EFUSE_RD_CK8M_FREQ_V 0xFF -#define EFUSE_RD_CK8M_FREQ_S 0 - -#define EFUSE_BLK0_RDATA5_REG (DR_REG_EFUSE_BASE + 0x014) -/* EFUSE_RD_FLASH_CRYPT_CONFIG : RO ;bitpos:[31:28] ;default: 4'b0 ; */ -/*description: read for flash_crypt_config*/ -#define EFUSE_RD_FLASH_CRYPT_CONFIG 0x0000000F -#define EFUSE_RD_FLASH_CRYPT_CONFIG_M ((EFUSE_RD_FLASH_CRYPT_CONFIG_V)<<(EFUSE_RD_FLASH_CRYPT_CONFIG_S)) -#define EFUSE_RD_FLASH_CRYPT_CONFIG_V 0xF -#define EFUSE_RD_FLASH_CRYPT_CONFIG_S 28 -/* EFUSE_RD_WAFER_VERSION_MINOR: RO; bitpos:[25:24]; */ -/*descritpion: Wafer version minor*/ -#define EFUSE_RD_WAFER_VERSION_MINOR 0x00000003 -#define EFUSE_RD_WAFER_VERSION_MINOR_M ((EFUSE_RD_WAFER_VERSION_MINOR_V)<<(EFUSE_RD_WAFER_VERSION_MINOR_S)) -#define EFUSE_RD_WAFER_VERSION_MINOR_V 0x03 -#define EFUSE_RD_WAFER_VERSION_MINOR_S 24 -/* EFUSE_RD_VOL_LEVEL_HP_INV: RO; bitpos:[23:22] */ -/*description: This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz. -0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO)*/ -#define EFUSE_RD_VOL_LEVEL_HP_INV 0x03 -#define EFUSE_RD_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V)<<(EFUSE_RD_VOL_LEVEL_HP_INV_S)) -#define EFUSE_RD_VOL_LEVEL_HP_INV_V 0x03 -#define EFUSE_RD_VOL_LEVEL_HP_INV_S 22 -/* EFUSE_RD_CHIP_VER_REV2 : RO ;bitpos:[20] ;default: 8'b0 ; */ -#define EFUSE_RD_CHIP_VER_REV2 (BIT(20)) -#define EFUSE_RD_CHIP_VER_REV2_M ((EFUSE_RD_CHIP_VER_REV2_V)<<(EFUSE_RD_CHIP_VER_REV2_S)) -#define EFUSE_RD_CHIP_VER_REV2_V 0x1 -#define EFUSE_RD_CHIP_VER_REV2_S 20 -/* EFUSE_RD_SPI_PAD_CONFIG_CS0 : RO ;bitpos:[19:15] ;default: 5'b0 ; */ -/*description: read for SPI_pad_config_cs0*/ -#define EFUSE_RD_SPI_PAD_CONFIG_CS0 0x0000001F -#define EFUSE_RD_SPI_PAD_CONFIG_CS0_M ((EFUSE_RD_SPI_PAD_CONFIG_CS0_V)<<(EFUSE_RD_SPI_PAD_CONFIG_CS0_S)) -#define EFUSE_RD_SPI_PAD_CONFIG_CS0_V 0x1F -#define EFUSE_RD_SPI_PAD_CONFIG_CS0_S 15 -/* EFUSE_RD_SPI_PAD_CONFIG_D : RO ;bitpos:[14:10] ;default: 5'b0 ; */ -/*description: read for SPI_pad_config_d*/ -#define EFUSE_RD_SPI_PAD_CONFIG_D 0x0000001F -#define EFUSE_RD_SPI_PAD_CONFIG_D_M ((EFUSE_RD_SPI_PAD_CONFIG_D_V)<<(EFUSE_RD_SPI_PAD_CONFIG_D_S)) -#define EFUSE_RD_SPI_PAD_CONFIG_D_V 0x1F -#define EFUSE_RD_SPI_PAD_CONFIG_D_S 10 -/* EFUSE_RD_SPI_PAD_CONFIG_Q : RO ;bitpos:[9:5] ;default: 5'b0 ; */ -/*description: read for SPI_pad_config_q*/ -#define EFUSE_RD_SPI_PAD_CONFIG_Q 0x0000001F -#define EFUSE_RD_SPI_PAD_CONFIG_Q_M ((EFUSE_RD_SPI_PAD_CONFIG_Q_V)<<(EFUSE_RD_SPI_PAD_CONFIG_Q_S)) -#define EFUSE_RD_SPI_PAD_CONFIG_Q_V 0x1F -#define EFUSE_RD_SPI_PAD_CONFIG_Q_S 5 -/* EFUSE_RD_SPI_PAD_CONFIG_CLK : RO ;bitpos:[4:0] ;default: 5'b0 ; */ -/*description: read for SPI_pad_config_clk*/ -#define EFUSE_RD_SPI_PAD_CONFIG_CLK 0x0000001F -#define EFUSE_RD_SPI_PAD_CONFIG_CLK_M ((EFUSE_RD_SPI_PAD_CONFIG_CLK_V)<<(EFUSE_RD_SPI_PAD_CONFIG_CLK_S)) -#define EFUSE_RD_SPI_PAD_CONFIG_CLK_V 0x1F +/** EFUSE_RD_RESERVE_0_141 : RW; bitpos: [13]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_141 (BIT(13)) +#define EFUSE_RD_RESERVE_0_141_M (EFUSE_RD_RESERVE_0_141_V << EFUSE_RD_RESERVE_0_141_S) +#define EFUSE_RD_RESERVE_0_141_V 0x00000001U +#define EFUSE_RD_RESERVE_0_141_S 13 +/** EFUSE_RD_XPD_SDIO_REG : R; bitpos: [14]; default: 0; + * read for XPD_SDIO_REG + */ +#define EFUSE_RD_XPD_SDIO_REG (BIT(14)) +#define EFUSE_RD_XPD_SDIO_REG_M (EFUSE_RD_XPD_SDIO_REG_V << EFUSE_RD_XPD_SDIO_REG_S) +#define EFUSE_RD_XPD_SDIO_REG_V 0x00000001U +#define EFUSE_RD_XPD_SDIO_REG_S 14 +/** EFUSE_RD_XPD_SDIO_TIEH : R; bitpos: [15]; default: 0; + * If XPD_SDIO_FORCE & XPD_SDIO_REG + */ +#define EFUSE_RD_XPD_SDIO_TIEH (BIT(15)) +#define EFUSE_RD_XPD_SDIO_TIEH_M (EFUSE_RD_XPD_SDIO_TIEH_V << EFUSE_RD_XPD_SDIO_TIEH_S) +#define EFUSE_RD_XPD_SDIO_TIEH_V 0x00000001U +#define EFUSE_RD_XPD_SDIO_TIEH_S 15 +/** EFUSE_RD_XPD_SDIO_FORCE : R; bitpos: [16]; default: 0; + * Ignore MTDI pin (GPIO12) for VDD_SDIO on reset + */ +#define EFUSE_RD_XPD_SDIO_FORCE (BIT(16)) +#define EFUSE_RD_XPD_SDIO_FORCE_M (EFUSE_RD_XPD_SDIO_FORCE_V << EFUSE_RD_XPD_SDIO_FORCE_S) +#define EFUSE_RD_XPD_SDIO_FORCE_V 0x00000001U +#define EFUSE_RD_XPD_SDIO_FORCE_S 16 +/** EFUSE_RD_RESERVE_0_145 : RW; bitpos: [31:17]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_145 0x00007FFFU +#define EFUSE_RD_RESERVE_0_145_M (EFUSE_RD_RESERVE_0_145_V << EFUSE_RD_RESERVE_0_145_S) +#define EFUSE_RD_RESERVE_0_145_V 0x00007FFFU +#define EFUSE_RD_RESERVE_0_145_S 17 + +/** EFUSE_BLK0_RDATA5_REG register */ +#define EFUSE_BLK0_RDATA5_REG (DR_REG_EFUSE_BASE + 0x14) +/** EFUSE_RD_SPI_PAD_CONFIG_CLK : R; bitpos: [4:0]; default: 0; + * read for SPI_pad_config_clk + */ +#define EFUSE_RD_SPI_PAD_CONFIG_CLK 0x0000001FU +#define EFUSE_RD_SPI_PAD_CONFIG_CLK_M (EFUSE_RD_SPI_PAD_CONFIG_CLK_V << EFUSE_RD_SPI_PAD_CONFIG_CLK_S) +#define EFUSE_RD_SPI_PAD_CONFIG_CLK_V 0x0000001FU #define EFUSE_RD_SPI_PAD_CONFIG_CLK_S 0 +/** EFUSE_RD_SPI_PAD_CONFIG_Q : R; bitpos: [9:5]; default: 0; + * read for SPI_pad_config_q + */ +#define EFUSE_RD_SPI_PAD_CONFIG_Q 0x0000001FU +#define EFUSE_RD_SPI_PAD_CONFIG_Q_M (EFUSE_RD_SPI_PAD_CONFIG_Q_V << EFUSE_RD_SPI_PAD_CONFIG_Q_S) +#define EFUSE_RD_SPI_PAD_CONFIG_Q_V 0x0000001FU +#define EFUSE_RD_SPI_PAD_CONFIG_Q_S 5 +/** EFUSE_RD_SPI_PAD_CONFIG_D : R; bitpos: [14:10]; default: 0; + * read for SPI_pad_config_d + */ +#define EFUSE_RD_SPI_PAD_CONFIG_D 0x0000001FU +#define EFUSE_RD_SPI_PAD_CONFIG_D_M (EFUSE_RD_SPI_PAD_CONFIG_D_V << EFUSE_RD_SPI_PAD_CONFIG_D_S) +#define EFUSE_RD_SPI_PAD_CONFIG_D_V 0x0000001FU +#define EFUSE_RD_SPI_PAD_CONFIG_D_S 10 +/** EFUSE_RD_SPI_PAD_CONFIG_CS0 : R; bitpos: [19:15]; default: 0; + * read for SPI_pad_config_cs0 + */ +#define EFUSE_RD_SPI_PAD_CONFIG_CS0 0x0000001FU +#define EFUSE_RD_SPI_PAD_CONFIG_CS0_M (EFUSE_RD_SPI_PAD_CONFIG_CS0_V << EFUSE_RD_SPI_PAD_CONFIG_CS0_S) +#define EFUSE_RD_SPI_PAD_CONFIG_CS0_V 0x0000001FU +#define EFUSE_RD_SPI_PAD_CONFIG_CS0_S 15 +/** EFUSE_RD_CHIP_VER_REV2 : R; bitpos: [20]; default: 0; */ +#define EFUSE_RD_CHIP_VER_REV2 (BIT(20)) +#define EFUSE_RD_CHIP_VER_REV2_M (EFUSE_RD_CHIP_VER_REV2_V << EFUSE_RD_CHIP_VER_REV2_S) +#define EFUSE_RD_CHIP_VER_REV2_V 0x00000001U +#define EFUSE_RD_CHIP_VER_REV2_S 20 +/** EFUSE_RD_RESERVE_0_181 : RW; bitpos: [21]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_181 (BIT(21)) +#define EFUSE_RD_RESERVE_0_181_M (EFUSE_RD_RESERVE_0_181_V << EFUSE_RD_RESERVE_0_181_S) +#define EFUSE_RD_RESERVE_0_181_V 0x00000001U +#define EFUSE_RD_RESERVE_0_181_S 21 +/** EFUSE_RD_VOL_LEVEL_HP_INV : R; bitpos: [23:22]; default: 0; + * This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM + * to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO) + */ +#define EFUSE_RD_VOL_LEVEL_HP_INV 0x00000003U +#define EFUSE_RD_VOL_LEVEL_HP_INV_M (EFUSE_RD_VOL_LEVEL_HP_INV_V << EFUSE_RD_VOL_LEVEL_HP_INV_S) +#define EFUSE_RD_VOL_LEVEL_HP_INV_V 0x00000003U +#define EFUSE_RD_VOL_LEVEL_HP_INV_S 22 +/** EFUSE_RD_WAFER_VERSION_MINOR : R; bitpos: [25:24]; default: 0; */ +#define EFUSE_RD_WAFER_VERSION_MINOR 0x00000003U +#define EFUSE_RD_WAFER_VERSION_MINOR_M (EFUSE_RD_WAFER_VERSION_MINOR_V << EFUSE_RD_WAFER_VERSION_MINOR_S) +#define EFUSE_RD_WAFER_VERSION_MINOR_V 0x00000003U +#define EFUSE_RD_WAFER_VERSION_MINOR_S 24 +/** EFUSE_RD_RESERVE_0_186 : RW; bitpos: [27:26]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_186 0x00000003U +#define EFUSE_RD_RESERVE_0_186_M (EFUSE_RD_RESERVE_0_186_V << EFUSE_RD_RESERVE_0_186_S) +#define EFUSE_RD_RESERVE_0_186_V 0x00000003U +#define EFUSE_RD_RESERVE_0_186_S 26 +/** EFUSE_RD_FLASH_CRYPT_CONFIG : R; bitpos: [31:28]; default: 0; + * read for flash_crypt_config + */ +#define EFUSE_RD_FLASH_CRYPT_CONFIG 0x0000000FU +#define EFUSE_RD_FLASH_CRYPT_CONFIG_M (EFUSE_RD_FLASH_CRYPT_CONFIG_V << EFUSE_RD_FLASH_CRYPT_CONFIG_S) +#define EFUSE_RD_FLASH_CRYPT_CONFIG_V 0x0000000FU +#define EFUSE_RD_FLASH_CRYPT_CONFIG_S 28 -#define EFUSE_BLK0_RDATA6_REG (DR_REG_EFUSE_BASE + 0x018) -/* EFUSE_RD_KEY_STATUS : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: read for key_status*/ -#define EFUSE_RD_KEY_STATUS (BIT(10)) -#define EFUSE_RD_KEY_STATUS_M (BIT(10)) -#define EFUSE_RD_KEY_STATUS_V 0x1 -#define EFUSE_RD_KEY_STATUS_S 10 -/* EFUSE_RD_DISABLE_DL_CACHE : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: read for download_dis_cache*/ -#define EFUSE_RD_DISABLE_DL_CACHE (BIT(9)) -#define EFUSE_RD_DISABLE_DL_CACHE_M (BIT(9)) -#define EFUSE_RD_DISABLE_DL_CACHE_V 0x1 -#define EFUSE_RD_DISABLE_DL_CACHE_S 9 -/* EFUSE_RD_DISABLE_DL_DECRYPT : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: read for download_dis_decrypt*/ -#define EFUSE_RD_DISABLE_DL_DECRYPT (BIT(8)) -#define EFUSE_RD_DISABLE_DL_DECRYPT_M (BIT(8)) -#define EFUSE_RD_DISABLE_DL_DECRYPT_V 0x1 -#define EFUSE_RD_DISABLE_DL_DECRYPT_S 8 -/* EFUSE_RD_DISABLE_DL_ENCRYPT : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: read for download_dis_encrypt*/ -#define EFUSE_RD_DISABLE_DL_ENCRYPT (BIT(7)) -#define EFUSE_RD_DISABLE_DL_ENCRYPT_M (BIT(7)) -#define EFUSE_RD_DISABLE_DL_ENCRYPT_V 0x1 -#define EFUSE_RD_DISABLE_DL_ENCRYPT_S 7 -/* EFUSE_RD_DISABLE_JTAG : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: read for JTAG_disable*/ -#define EFUSE_RD_DISABLE_JTAG (BIT(6)) -#define EFUSE_RD_DISABLE_JTAG_M (BIT(6)) -#define EFUSE_RD_DISABLE_JTAG_V 0x1 -#define EFUSE_RD_DISABLE_JTAG_S 6 -/* EFUSE_RD_ABS_DONE_1 : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: read for abstract_done_1*/ -#define EFUSE_RD_ABS_DONE_1 (BIT(5)) -#define EFUSE_RD_ABS_DONE_1_M (BIT(5)) -#define EFUSE_RD_ABS_DONE_1_V 0x1 -#define EFUSE_RD_ABS_DONE_1_S 5 -/* EFUSE_RD_ABS_DONE_0 : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: read for abstract_done_0*/ -#define EFUSE_RD_ABS_DONE_0 (BIT(4)) -#define EFUSE_RD_ABS_DONE_0_M (BIT(4)) -#define EFUSE_RD_ABS_DONE_0_V 0x1 -#define EFUSE_RD_ABS_DONE_0_S 4 -/* EFUSE_RD_DISABLE_SDIO_HOST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_DISABLE_SDIO_HOST (BIT(3)) -#define EFUSE_RD_DISABLE_SDIO_HOST_M (BIT(3)) -#define EFUSE_RD_DISABLE_SDIO_HOST_V 0x1 -#define EFUSE_RD_DISABLE_SDIO_HOST_S 3 -/* EFUSE_RD_CONSOLE_DEBUG_DISABLE : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: read for console_debug_disable*/ -#define EFUSE_RD_CONSOLE_DEBUG_DISABLE (BIT(2)) -#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_M (BIT(2)) -#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_V 0x1 -#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_S 2 -/* EFUSE_RD_CODING_SCHEME : RO ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: read for coding_scheme*/ -#define EFUSE_RD_CODING_SCHEME 0x00000003 -#define EFUSE_RD_CODING_SCHEME_M ((EFUSE_RD_CODING_SCHEME_V)<<(EFUSE_RD_CODING_SCHEME_S)) -#define EFUSE_RD_CODING_SCHEME_V 0x3 +/** EFUSE_BLK0_RDATA6_REG register */ +#define EFUSE_BLK0_RDATA6_REG (DR_REG_EFUSE_BASE + 0x18) +/** EFUSE_RD_CODING_SCHEME : R; bitpos: [1:0]; default: 0; + * read for coding_scheme + */ +#define EFUSE_RD_CODING_SCHEME 0x00000003U +#define EFUSE_RD_CODING_SCHEME_M (EFUSE_RD_CODING_SCHEME_V << EFUSE_RD_CODING_SCHEME_S) +#define EFUSE_RD_CODING_SCHEME_V 0x00000003U #define EFUSE_RD_CODING_SCHEME_S 0 - -#define EFUSE_CODING_SCHEME_VAL_NONE 0x0 -#define EFUSE_CODING_SCHEME_VAL_34 0x1 -#define EFUSE_CODING_SCHEME_VAL_REPEAT 0x2 - -#define EFUSE_BLK0_WDATA0_REG (DR_REG_EFUSE_BASE + 0x01c) -/* EFUSE_FLASH_CRYPT_CNT : R/W ;bitpos:[26:20] ;default: 7'b0 ; */ -/*description: program for flash_crypt_cnt*/ -#define EFUSE_FLASH_CRYPT_CNT 0x0000007F -#define EFUSE_FLASH_CRYPT_CNT_M ((EFUSE_FLASH_CRYPT_CNT_V)<<(EFUSE_FLASH_CRYPT_CNT_S)) -#define EFUSE_FLASH_CRYPT_CNT_V 0x7F -#define EFUSE_FLASH_CRYPT_CNT_S 20 -/* EFUSE_RD_DIS : R/W ;bitpos:[19:16] ;default: 4'b0 ; */ -/*description: program for efuse_rd_disable*/ -#define EFUSE_RD_DIS 0x0000000F -#define EFUSE_RD_DIS_M ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S)) -#define EFUSE_RD_DIS_V 0xF -#define EFUSE_RD_DIS_S 16 -/* EFUSE_WR_DIS : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ -/*description: program for efuse_wr_disable*/ -#define EFUSE_WR_DIS 0x0000FFFF -#define EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S)) -#define EFUSE_WR_DIS_V 0xFFFF +/** EFUSE_RD_CONSOLE_DEBUG_DISABLE : R; bitpos: [2]; default: 0; + * read for console_debug_disable + */ +#define EFUSE_RD_CONSOLE_DEBUG_DISABLE (BIT(2)) +#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_M (EFUSE_RD_CONSOLE_DEBUG_DISABLE_V << EFUSE_RD_CONSOLE_DEBUG_DISABLE_S) +#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_V 0x00000001U +#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_S 2 +/** EFUSE_RD_DISABLE_SDIO_HOST : R; bitpos: [3]; default: 0; */ +#define EFUSE_RD_DISABLE_SDIO_HOST (BIT(3)) +#define EFUSE_RD_DISABLE_SDIO_HOST_M (EFUSE_RD_DISABLE_SDIO_HOST_V << EFUSE_RD_DISABLE_SDIO_HOST_S) +#define EFUSE_RD_DISABLE_SDIO_HOST_V 0x00000001U +#define EFUSE_RD_DISABLE_SDIO_HOST_S 3 +/** EFUSE_RD_ABS_DONE_0 : R; bitpos: [4]; default: 0; + * read for abstract_done_0 + */ +#define EFUSE_RD_ABS_DONE_0 (BIT(4)) +#define EFUSE_RD_ABS_DONE_0_M (EFUSE_RD_ABS_DONE_0_V << EFUSE_RD_ABS_DONE_0_S) +#define EFUSE_RD_ABS_DONE_0_V 0x00000001U +#define EFUSE_RD_ABS_DONE_0_S 4 +/** EFUSE_RD_ABS_DONE_1 : R; bitpos: [5]; default: 0; + * read for abstract_done_1 + */ +#define EFUSE_RD_ABS_DONE_1 (BIT(5)) +#define EFUSE_RD_ABS_DONE_1_M (EFUSE_RD_ABS_DONE_1_V << EFUSE_RD_ABS_DONE_1_S) +#define EFUSE_RD_ABS_DONE_1_V 0x00000001U +#define EFUSE_RD_ABS_DONE_1_S 5 +/** EFUSE_RD_JTAG_DISABLE : R; bitpos: [6]; default: 0; + * Disable JTAG + */ +#define EFUSE_RD_JTAG_DISABLE (BIT(6)) +#define EFUSE_RD_JTAG_DISABLE_M (EFUSE_RD_JTAG_DISABLE_V << EFUSE_RD_JTAG_DISABLE_S) +#define EFUSE_RD_JTAG_DISABLE_V 0x00000001U +#define EFUSE_RD_JTAG_DISABLE_S 6 +/** EFUSE_RD_DISABLE_DL_ENCRYPT : R; bitpos: [7]; default: 0; + * read for download_dis_encrypt + */ +#define EFUSE_RD_DISABLE_DL_ENCRYPT (BIT(7)) +#define EFUSE_RD_DISABLE_DL_ENCRYPT_M (EFUSE_RD_DISABLE_DL_ENCRYPT_V << EFUSE_RD_DISABLE_DL_ENCRYPT_S) +#define EFUSE_RD_DISABLE_DL_ENCRYPT_V 0x00000001U +#define EFUSE_RD_DISABLE_DL_ENCRYPT_S 7 +/** EFUSE_RD_DISABLE_DL_DECRYPT : R; bitpos: [8]; default: 0; + * read for download_dis_decrypt + */ +#define EFUSE_RD_DISABLE_DL_DECRYPT (BIT(8)) +#define EFUSE_RD_DISABLE_DL_DECRYPT_M (EFUSE_RD_DISABLE_DL_DECRYPT_V << EFUSE_RD_DISABLE_DL_DECRYPT_S) +#define EFUSE_RD_DISABLE_DL_DECRYPT_V 0x00000001U +#define EFUSE_RD_DISABLE_DL_DECRYPT_S 8 +/** EFUSE_RD_DISABLE_DL_CACHE : R; bitpos: [9]; default: 0; + * read for download_dis_cache + */ +#define EFUSE_RD_DISABLE_DL_CACHE (BIT(9)) +#define EFUSE_RD_DISABLE_DL_CACHE_M (EFUSE_RD_DISABLE_DL_CACHE_V << EFUSE_RD_DISABLE_DL_CACHE_S) +#define EFUSE_RD_DISABLE_DL_CACHE_V 0x00000001U +#define EFUSE_RD_DISABLE_DL_CACHE_S 9 +/** EFUSE_RD_KEY_STATUS : R; bitpos: [10]; default: 0; + * read for key_status + */ +#define EFUSE_RD_KEY_STATUS (BIT(10)) +#define EFUSE_RD_KEY_STATUS_M (EFUSE_RD_KEY_STATUS_V << EFUSE_RD_KEY_STATUS_S) +#define EFUSE_RD_KEY_STATUS_V 0x00000001U +#define EFUSE_RD_KEY_STATUS_S 10 +/** EFUSE_RD_RESERVE_0_203 : RW; bitpos: [31:11]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_203 0x001FFFFFU +#define EFUSE_RD_RESERVE_0_203_M (EFUSE_RD_RESERVE_0_203_V << EFUSE_RD_RESERVE_0_203_S) +#define EFUSE_RD_RESERVE_0_203_V 0x001FFFFFU +#define EFUSE_RD_RESERVE_0_203_S 11 + +/** EFUSE_BLK0_WDATA0_REG register */ +#define EFUSE_BLK0_WDATA0_REG (DR_REG_EFUSE_BASE + 0x1c) +/** EFUSE_WR_DIS : RW; bitpos: [15:0]; default: 0; + * program for efuse_wr_disable + */ +#define EFUSE_WR_DIS 0x0000FFFFU +#define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) +#define EFUSE_WR_DIS_V 0x0000FFFFU #define EFUSE_WR_DIS_S 0 +/** EFUSE_RD_DIS : RW; bitpos: [19:16]; default: 0; + * program for efuse_rd_disable + */ +#define EFUSE_RD_DIS 0x0000000FU +#define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) +#define EFUSE_RD_DIS_V 0x0000000FU +#define EFUSE_RD_DIS_S 16 +/** EFUSE_FLASH_CRYPT_CNT : RW; bitpos: [26:20]; default: 0; + * program for flash_crypt_cnt + */ +#define EFUSE_FLASH_CRYPT_CNT 0x0000007FU +#define EFUSE_FLASH_CRYPT_CNT_M (EFUSE_FLASH_CRYPT_CNT_V << EFUSE_FLASH_CRYPT_CNT_S) +#define EFUSE_FLASH_CRYPT_CNT_V 0x0000007FU +#define EFUSE_FLASH_CRYPT_CNT_S 20 -#define EFUSE_BLK0_WDATA1_REG (DR_REG_EFUSE_BASE + 0x020) -/* EFUSE_WIFI_MAC_CRC_LOW : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: program for low 32bit WIFI_MAC_Address*/ -#define EFUSE_WIFI_MAC_CRC_LOW 0xFFFFFFFF -#define EFUSE_WIFI_MAC_CRC_LOW_M ((EFUSE_WIFI_MAC_CRC_LOW_V)<<(EFUSE_WIFI_MAC_CRC_LOW_S)) -#define EFUSE_WIFI_MAC_CRC_LOW_V 0xFFFFFFFF +/** EFUSE_BLK0_WDATA1_REG register */ +#define EFUSE_BLK0_WDATA1_REG (DR_REG_EFUSE_BASE + 0x20) +/** EFUSE_WIFI_MAC_CRC_LOW : RW; bitpos: [31:0]; default: 0; + * program for low 32bit WIFI_MAC_Address + */ +#define EFUSE_WIFI_MAC_CRC_LOW 0xFFFFFFFFU +#define EFUSE_WIFI_MAC_CRC_LOW_M (EFUSE_WIFI_MAC_CRC_LOW_V << EFUSE_WIFI_MAC_CRC_LOW_S) +#define EFUSE_WIFI_MAC_CRC_LOW_V 0xFFFFFFFFU #define EFUSE_WIFI_MAC_CRC_LOW_S 0 -#define EFUSE_BLK0_WDATA2_REG (DR_REG_EFUSE_BASE + 0x024) -/* EFUSE_WIFI_MAC_CRC_HIGH : R/W ;bitpos:[23:0] ;default: 24'b0 ; */ -/*description: program for high 24bit WIFI_MAC_Address*/ -#define EFUSE_WIFI_MAC_CRC_HIGH 0x00FFFFFF -#define EFUSE_WIFI_MAC_CRC_HIGH_M ((EFUSE_WIFI_MAC_CRC_HIGH_V)<<(EFUSE_WIFI_MAC_CRC_HIGH_S)) -#define EFUSE_WIFI_MAC_CRC_HIGH_V 0xFFFFFF +/** EFUSE_BLK0_WDATA2_REG register */ +#define EFUSE_BLK0_WDATA2_REG (DR_REG_EFUSE_BASE + 0x24) +/** EFUSE_WIFI_MAC_CRC_HIGH : RW; bitpos: [23:0]; default: 0; + * program for high 24bit WIFI_MAC_Address + */ +#define EFUSE_WIFI_MAC_CRC_HIGH 0x00FFFFFFU +#define EFUSE_WIFI_MAC_CRC_HIGH_M (EFUSE_WIFI_MAC_CRC_HIGH_V << EFUSE_WIFI_MAC_CRC_HIGH_S) +#define EFUSE_WIFI_MAC_CRC_HIGH_V 0x00FFFFFFU #define EFUSE_WIFI_MAC_CRC_HIGH_S 0 -#define EFUSE_BLK0_WDATA3_REG (DR_REG_EFUSE_BASE + 0x028) -/* EFUSE_CHIP_VER_REV1 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_CHIP_VER_REV1 (BIT(15)) -#define EFUSE_CHIP_VER_REV1_M ((EFUSE_CHIP_VER_REV1_V)<<(EFUSE_CHIP_VER_REV1_S)) -#define EFUSE_CHIP_VER_REV1_V 0x1 -#define EFUSE_CHIP_VER_REV1_S 15 -/* EFUSE_BLK3_PART_RESERVE : R/W ; bitpos:[14] ; default: 1'b0; */ -/*description: If set, this bit indicates that BLOCK3[143:96] is reserved for internal use*/ -#define EFUSE_BLK3_PART_RESERVE (BIT(14)) -#define EFUSE_BLK3_PART_RESERVE_M ((EFUSE_BLK3_PART_RESERVE_V)<<(EFUSE_BLK3_PART_RESERVE_S)) -#define EFUSE_BLK3_PART_RESERVE_V 0x1 -#define EFUSE_BLK3_PART_RESERVE_S 14 -/* EFUSE_CHIP_CPU_FREQ_RATED : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: If set, the ESP32's maximum CPU frequency has been rated*/ -#define EFUSE_CHIP_CPU_FREQ_RATED (BIT(13)) -#define EFUSE_CHIP_CPU_FREQ_RATED_M ((EFUSE_CHIP_CPU_FREQ_RATED_V)<<(EFUSE_CHIP_CPU_FREQ_RATED_S)) -#define EFUSE_CHIP_CPU_FREQ_RATED_V 0x1 -#define EFUSE_CHIP_CPU_FREQ_RATED_S 13 -/* EFUSE_CHIP_CPU_FREQ_LOW : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: If set alongside EFUSE_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise*/ -#define EFUSE_CHIP_CPU_FREQ_LOW (BIT(12)) -#define EFUSE_CHIP_CPU_FREQ_LOW_M ((EFUSE_CHIP_CPU_FREQ_LOW_V)<<(EFUSE_CHIP_CPU_FREQ_LOW_S)) -#define EFUSE_CHIP_CPU_FREQ_LOW_V 0x1 -#define EFUSE_CHIP_CPU_FREQ_LOW_S 12 -/* EFUSE_CHIP_VER_PKG : R/W ;bitpos:[11:9] ;default: 3'b0 ; */ -/*description: least significant bits of chip package */ -#define EFUSE_CHIP_VER_PKG 0x00000007 -#define EFUSE_CHIP_VER_PKG_M ((EFUSE_CHIP_VER_PKG_V)<<(EFUSE_CHIP_VER_PKG_S)) -#define EFUSE_CHIP_VER_PKG_V 0x7 -#define EFUSE_CHIP_VER_PKG_S 9 -#define EFUSE_CHIP_VER_PKG_ESP32D0WDQ6 0 -#define EFUSE_CHIP_VER_PKG_ESP32D0WDQ5 1 -#define EFUSE_CHIP_VER_PKG_ESP32D2WDQ5 2 -#define EFUSE_CHIP_VER_PKG_ESP32PICOD2 4 -#define EFUSE_CHIP_VER_PKG_ESP32PICOD4 5 -#define EFUSE_CHIP_VER_PKG_ESP32PICOV302 6 -/* EFUSE_SPI_PAD_CONFIG_HD : R/W ;bitpos:[8:4] ;default: 5'b0 ; */ -/*description: program for SPI_pad_config_hd*/ -#define EFUSE_SPI_PAD_CONFIG_HD 0x0000001F -#define EFUSE_SPI_PAD_CONFIG_HD_M ((EFUSE_SPI_PAD_CONFIG_HD_V)<<(EFUSE_SPI_PAD_CONFIG_HD_S)) -#define EFUSE_SPI_PAD_CONFIG_HD_V 0x1F +/** EFUSE_BLK0_WDATA3_REG register */ +#define EFUSE_BLK0_WDATA3_REG (DR_REG_EFUSE_BASE + 0x28) +/** EFUSE_DISABLE_APP_CPU : R; bitpos: [0]; default: 0; + * Disables APP CPU + */ +#define EFUSE_DISABLE_APP_CPU (BIT(0)) +#define EFUSE_DISABLE_APP_CPU_M (EFUSE_DISABLE_APP_CPU_V << EFUSE_DISABLE_APP_CPU_S) +#define EFUSE_DISABLE_APP_CPU_V 0x00000001U +#define EFUSE_DISABLE_APP_CPU_S 0 +/** EFUSE_DISABLE_BT : R; bitpos: [1]; default: 0; + * Disables Bluetooth + */ +#define EFUSE_DISABLE_BT (BIT(1)) +#define EFUSE_DISABLE_BT_M (EFUSE_DISABLE_BT_V << EFUSE_DISABLE_BT_S) +#define EFUSE_DISABLE_BT_V 0x00000001U +#define EFUSE_DISABLE_BT_S 1 +/** EFUSE_CHIP_PACKAGE_4BIT : R; bitpos: [2]; default: 0; + * Chip package identifier #4bit + */ +#define EFUSE_CHIP_PACKAGE_4BIT (BIT(2)) +#define EFUSE_CHIP_PACKAGE_4BIT_M (EFUSE_CHIP_PACKAGE_4BIT_V << EFUSE_CHIP_PACKAGE_4BIT_S) +#define EFUSE_CHIP_PACKAGE_4BIT_V 0x00000001U +#define EFUSE_CHIP_PACKAGE_4BIT_S 2 +/** EFUSE_DIS_CACHE : R; bitpos: [3]; default: 0; + * Disables cache + */ +#define EFUSE_DIS_CACHE (BIT(3)) +#define EFUSE_DIS_CACHE_M (EFUSE_DIS_CACHE_V << EFUSE_DIS_CACHE_S) +#define EFUSE_DIS_CACHE_V 0x00000001U +#define EFUSE_DIS_CACHE_S 3 +/** EFUSE_SPI_PAD_CONFIG_HD : R; bitpos: [8:4]; default: 0; + * program for SPI_pad_config_hd + */ +#define EFUSE_SPI_PAD_CONFIG_HD 0x0000001FU +#define EFUSE_SPI_PAD_CONFIG_HD_M (EFUSE_SPI_PAD_CONFIG_HD_V << EFUSE_SPI_PAD_CONFIG_HD_S) +#define EFUSE_SPI_PAD_CONFIG_HD_V 0x0000001FU #define EFUSE_SPI_PAD_CONFIG_HD_S 4 -/* EFUSE_CHIP_VER_DIS_CACHE : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_CHIP_VER_DIS_CACHE (BIT(3)) -#define EFUSE_CHIP_VER_DIS_CACHE_M (BIT(3)) -#define EFUSE_CHIP_VER_DIS_CACHE_V 0x1 -#define EFUSE_CHIP_VER_DIS_CACHE_S 3 -/* EFUSE_CHIP_VER_PKG_4BIT : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: most significant bit of chip package */ -#define EFUSE_CHIP_VER_PKG_4BIT (BIT(2)) -#define EFUSE_CHIP_VER_PKG_4BIT_M (BIT(2)) -#define EFUSE_CHIP_VER_PKG_4BIT_V 0x1 -#define EFUSE_CHIP_VER_PKG_4BIT_S 2 -/* EFUSE_CHIP_VER_DIS_BT : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_CHIP_VER_DIS_BT (BIT(1)) -#define EFUSE_CHIP_VER_DIS_BT_M (BIT(1)) -#define EFUSE_CHIP_VER_DIS_BT_V 0x1 -#define EFUSE_CHIP_VER_DIS_BT_S 1 -/* EFUSE_CHIP_VER_DIS_APP_CPU : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_CHIP_VER_DIS_APP_CPU (BIT(0)) -#define EFUSE_CHIP_VER_DIS_APP_CPU_M (BIT(0)) -#define EFUSE_CHIP_VER_DIS_APP_CPU_V 0x1 -#define EFUSE_CHIP_VER_DIS_APP_CPU_S 0 - -#define EFUSE_BLK0_WDATA4_REG (DR_REG_EFUSE_BASE + 0x02c) -/* EFUSE_SDIO_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: program for sdio_force*/ -#define EFUSE_SDIO_FORCE (BIT(16)) -#define EFUSE_SDIO_FORCE_M (BIT(16)) -#define EFUSE_SDIO_FORCE_V 0x1 -#define EFUSE_SDIO_FORCE_S 16 -/* EFUSE_SDIO_TIEH : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: program for SDIO_TIEH*/ -#define EFUSE_SDIO_TIEH (BIT(15)) -#define EFUSE_SDIO_TIEH_M (BIT(15)) -#define EFUSE_SDIO_TIEH_V 0x1 -#define EFUSE_SDIO_TIEH_S 15 -/* EFUSE_XPD_SDIO_REG : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: program for XPD_SDIO_REG*/ -#define EFUSE_XPD_SDIO_REG (BIT(14)) -#define EFUSE_XPD_SDIO_REG_M (BIT(14)) -#define EFUSE_XPD_SDIO_REG_V 0x1 -#define EFUSE_XPD_SDIO_REG_S 14 -/* EFUSE_ADC_VREF : R/W ;bitpos:[12:8] ;default: 5'b0 ; */ -/*description: True ADC reference voltage */ -#define EFUSE_ADC_VREF 0x0000001F -#define EFUSE_ADC_VREF_M ((EFUSE_ADC_VREF_V)<<(EFUSE_ADC_VREF_S)) -#define EFUSE_ADC_VREF_V 0x1F +/** EFUSE_CHIP_PACKAGE : RW; bitpos: [11:9]; default: 0; + * Chip package identifier + */ +#define EFUSE_CHIP_PACKAGE 0x00000007U +#define EFUSE_CHIP_PACKAGE_M (EFUSE_CHIP_PACKAGE_V << EFUSE_CHIP_PACKAGE_S) +#define EFUSE_CHIP_PACKAGE_V 0x00000007U +#define EFUSE_CHIP_PACKAGE_S 9 +/** EFUSE_CHIP_CPU_FREQ_LOW : RW; bitpos: [12]; default: 0; + * If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is + * rated for 160MHz. 240MHz otherwise + */ +#define EFUSE_CHIP_CPU_FREQ_LOW (BIT(12)) +#define EFUSE_CHIP_CPU_FREQ_LOW_M (EFUSE_CHIP_CPU_FREQ_LOW_V << EFUSE_CHIP_CPU_FREQ_LOW_S) +#define EFUSE_CHIP_CPU_FREQ_LOW_V 0x00000001U +#define EFUSE_CHIP_CPU_FREQ_LOW_S 12 +/** EFUSE_CHIP_CPU_FREQ_RATED : RW; bitpos: [13]; default: 0; + * If set, the ESP32's maximum CPU frequency has been rated + */ +#define EFUSE_CHIP_CPU_FREQ_RATED (BIT(13)) +#define EFUSE_CHIP_CPU_FREQ_RATED_M (EFUSE_CHIP_CPU_FREQ_RATED_V << EFUSE_CHIP_CPU_FREQ_RATED_S) +#define EFUSE_CHIP_CPU_FREQ_RATED_V 0x00000001U +#define EFUSE_CHIP_CPU_FREQ_RATED_S 13 +/** EFUSE_BLK3_PART_RESERVE : RW; bitpos: [14]; default: 0; + * If set, this bit indicates that BLOCK3[143:96] is reserved for internal use + */ +#define EFUSE_BLK3_PART_RESERVE (BIT(14)) +#define EFUSE_BLK3_PART_RESERVE_M (EFUSE_BLK3_PART_RESERVE_V << EFUSE_BLK3_PART_RESERVE_S) +#define EFUSE_BLK3_PART_RESERVE_V 0x00000001U +#define EFUSE_BLK3_PART_RESERVE_S 14 +/** EFUSE_CHIP_VER_REV1 : RW; bitpos: [15]; default: 0; + * bit is set to 1 for rev1 silicon + */ +#define EFUSE_CHIP_VER_REV1 (BIT(15)) +#define EFUSE_CHIP_VER_REV1_M (EFUSE_CHIP_VER_REV1_V << EFUSE_CHIP_VER_REV1_S) +#define EFUSE_CHIP_VER_REV1_V 0x00000001U +#define EFUSE_CHIP_VER_REV1_S 15 +/** EFUSE_RESERVE_0_112 : RW; bitpos: [31:16]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RESERVE_0_112 0x0000FFFFU +#define EFUSE_RESERVE_0_112_M (EFUSE_RESERVE_0_112_V << EFUSE_RESERVE_0_112_S) +#define EFUSE_RESERVE_0_112_V 0x0000FFFFU +#define EFUSE_RESERVE_0_112_S 16 + +/** EFUSE_BLK0_WDATA4_REG register */ +#define EFUSE_BLK0_WDATA4_REG (DR_REG_EFUSE_BASE + 0x2c) +/** EFUSE_CLK8M_FREQ : R; bitpos: [7:0]; default: 0; + * 8MHz clock freq override + */ +#define EFUSE_CLK8M_FREQ 0x000000FFU +#define EFUSE_CLK8M_FREQ_M (EFUSE_CLK8M_FREQ_V << EFUSE_CLK8M_FREQ_S) +#define EFUSE_CLK8M_FREQ_V 0x000000FFU +#define EFUSE_CLK8M_FREQ_S 0 +/** EFUSE_ADC_VREF : RW; bitpos: [12:8]; default: 0; + * True ADC reference voltage + */ +#define EFUSE_ADC_VREF 0x0000001FU +#define EFUSE_ADC_VREF_M (EFUSE_ADC_VREF_V << EFUSE_ADC_VREF_S) +#define EFUSE_ADC_VREF_V 0x0000001FU #define EFUSE_ADC_VREF_S 8 -/* Note: EFUSE_ADC_VREF and SDIO_DREFH/M/L share the same address space. Newer - * versions of ESP32 come with EFUSE_ADC_VREF already burned, therefore - * SDIO_DREFH/M/L is only available in older versions of ESP32 */ -/* EFUSE_SDIO_DREFL : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_SDIO_DREFL 0x00000003 -#define EFUSE_SDIO_DREFL_M ((EFUSE_SDIO_DREFL_V)<<(EFUSE_SDIO_DREFL_S)) -#define EFUSE_SDIO_DREFL_V 0x3 -#define EFUSE_SDIO_DREFL_S 12 -/* EFUSE_SDIO_DREFM : R/W ;bitpos:[11:10] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_SDIO_DREFM 0x00000003 -#define EFUSE_SDIO_DREFM_M ((EFUSE_SDIO_DREFM_V)<<(EFUSE_SDIO_DREFM_S)) -#define EFUSE_SDIO_DREFM_V 0x3 -#define EFUSE_SDIO_DREFM_S 10 -/* EFUSE_SDIO_DREFH : R/W ;bitpos:[9:8] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_SDIO_DREFH 0x00000003 -#define EFUSE_SDIO_DREFH_M ((EFUSE_SDIO_DREFH_V)<<(EFUSE_SDIO_DREFH_S)) -#define EFUSE_SDIO_DREFH_V 0x3 -#define EFUSE_SDIO_DREFH_S 8 -/* EFUSE_CK8M_FREQ : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ -/*description: */ -#define EFUSE_CK8M_FREQ 0x000000FF -#define EFUSE_CK8M_FREQ_M ((EFUSE_CK8M_FREQ_V)<<(EFUSE_CK8M_FREQ_S)) -#define EFUSE_CK8M_FREQ_V 0xFF -#define EFUSE_CK8M_FREQ_S 0 - -#define EFUSE_BLK0_WDATA5_REG (DR_REG_EFUSE_BASE + 0x030) -/* EFUSE_FLASH_CRYPT_CONFIG : R/W ;bitpos:[31:28] ;default: 4'b0 ; */ -/*description: program for flash_crypt_config*/ -#define EFUSE_FLASH_CRYPT_CONFIG 0x0000000F -#define EFUSE_FLASH_CRYPT_CONFIG_M ((EFUSE_FLASH_CRYPT_CONFIG_V)<<(EFUSE_FLASH_CRYPT_CONFIG_S)) -#define EFUSE_FLASH_CRYPT_CONFIG_V 0xF -#define EFUSE_FLASH_CRYPT_CONFIG_S 28 -/* EFUSE_DIG_VOL_L6: R/W; bitpos:[27:24]; */ -/*descritpion: This field stores the difference between the digital regulator voltage at level6 and 1.2 V. (R/W) - BIT[27] is the sign bit, 0: + , 1: - - BIT[26:24] is the difference value, unit: 0.017V - volt_lv6 = BIT[27] ? 1.2 - BIT[26:24] * 0.017 : 1.2 + BIT[26:24] * 0.017 */ -#define EFUSE_DIG_VOL_L6 0x0F -#define EFUSE_DIG_VOL_L6_M ((EFUSE_RD_DIG_VOL_L6_V)<<(EFUSE_RD_DIG_VOL_L6_S)) -#define EFUSE_DIG_VOL_L6_V 0x0F -#define EFUSE_DIG_VOL_L6_S 24 -/* EFUSE_VOL_LEVEL_HP_INV: R/W; bitpos:[23:22] */ -/*description: This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz. -0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (R/W)*/ -#define EFUSE_VOL_LEVEL_HP_INV 0x03 -#define EFUSE_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V)<<(EFUSE_RD_VOL_LEVEL_HP_INV_S)) -#define EFUSE_VOL_LEVEL_HP_INV_V 0x03 -#define EFUSE_VOL_LEVEL_HP_INV_S 22 -/* EFUSE_INST_CONFIG : R/W ;bitpos:[27:20] ;default: 8'b0 ; */ -/* Deprecated */ -#define EFUSE_INST_CONFIG 0x000000FF /** Deprecated **/ -#define EFUSE_INST_CONFIG_M ((EFUSE_INST_CONFIG_V)<<(EFUSE_INST_CONFIG_S)) /** Deprecated **/ -#define EFUSE_INST_CONFIG_V 0xFF /** Deprecated **/ -#define EFUSE_INST_CONFIG_S 20 /** Deprecated **/ -/* EFUSE_SPI_PAD_CONFIG_CS0 : R/W ;bitpos:[19:15] ;default: 5'b0 ; */ -/*description: program for SPI_pad_config_cs0*/ -#define EFUSE_SPI_PAD_CONFIG_CS0 0x0000001F -#define EFUSE_SPI_PAD_CONFIG_CS0_M ((EFUSE_SPI_PAD_CONFIG_CS0_V)<<(EFUSE_SPI_PAD_CONFIG_CS0_S)) -#define EFUSE_SPI_PAD_CONFIG_CS0_V 0x1F -#define EFUSE_SPI_PAD_CONFIG_CS0_S 15 -/* EFUSE_SPI_PAD_CONFIG_D : R/W ;bitpos:[14:10] ;default: 5'b0 ; */ -/*description: program for SPI_pad_config_d*/ -#define EFUSE_SPI_PAD_CONFIG_D 0x0000001F -#define EFUSE_SPI_PAD_CONFIG_D_M ((EFUSE_SPI_PAD_CONFIG_D_V)<<(EFUSE_SPI_PAD_CONFIG_D_S)) -#define EFUSE_SPI_PAD_CONFIG_D_V 0x1F -#define EFUSE_SPI_PAD_CONFIG_D_S 10 -/* EFUSE_SPI_PAD_CONFIG_Q : R/W ;bitpos:[9:5] ;default: 5'b0 ; */ -/*description: program for SPI_pad_config_q*/ -#define EFUSE_SPI_PAD_CONFIG_Q 0x0000001F -#define EFUSE_SPI_PAD_CONFIG_Q_M ((EFUSE_SPI_PAD_CONFIG_Q_V)<<(EFUSE_SPI_PAD_CONFIG_Q_S)) -#define EFUSE_SPI_PAD_CONFIG_Q_V 0x1F -#define EFUSE_SPI_PAD_CONFIG_Q_S 5 -/* EFUSE_SPI_PAD_CONFIG_CLK : R/W ;bitpos:[4:0] ;default: 5'b0 ; */ -/*description: program for SPI_pad_config_clk*/ -#define EFUSE_SPI_PAD_CONFIG_CLK 0x0000001F -#define EFUSE_SPI_PAD_CONFIG_CLK_M ((EFUSE_SPI_PAD_CONFIG_CLK_V)<<(EFUSE_SPI_PAD_CONFIG_CLK_S)) -#define EFUSE_SPI_PAD_CONFIG_CLK_V 0x1F +/** EFUSE_RESERVE_0_141 : RW; bitpos: [13]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RESERVE_0_141 (BIT(13)) +#define EFUSE_RESERVE_0_141_M (EFUSE_RESERVE_0_141_V << EFUSE_RESERVE_0_141_S) +#define EFUSE_RESERVE_0_141_V 0x00000001U +#define EFUSE_RESERVE_0_141_S 13 +/** EFUSE_XPD_SDIO_REG : R; bitpos: [14]; default: 0; + * program for XPD_SDIO_REG + */ +#define EFUSE_XPD_SDIO_REG (BIT(14)) +#define EFUSE_XPD_SDIO_REG_M (EFUSE_XPD_SDIO_REG_V << EFUSE_XPD_SDIO_REG_S) +#define EFUSE_XPD_SDIO_REG_V 0x00000001U +#define EFUSE_XPD_SDIO_REG_S 14 +/** EFUSE_XPD_SDIO_TIEH : R; bitpos: [15]; default: 0; + * If XPD_SDIO_FORCE & XPD_SDIO_REG + */ +#define EFUSE_XPD_SDIO_TIEH (BIT(15)) +#define EFUSE_XPD_SDIO_TIEH_M (EFUSE_XPD_SDIO_TIEH_V << EFUSE_XPD_SDIO_TIEH_S) +#define EFUSE_XPD_SDIO_TIEH_V 0x00000001U +#define EFUSE_XPD_SDIO_TIEH_S 15 +/** EFUSE_XPD_SDIO_FORCE : R; bitpos: [16]; default: 0; + * Ignore MTDI pin (GPIO12) for VDD_SDIO on reset + */ +#define EFUSE_XPD_SDIO_FORCE (BIT(16)) +#define EFUSE_XPD_SDIO_FORCE_M (EFUSE_XPD_SDIO_FORCE_V << EFUSE_XPD_SDIO_FORCE_S) +#define EFUSE_XPD_SDIO_FORCE_V 0x00000001U +#define EFUSE_XPD_SDIO_FORCE_S 16 +/** EFUSE_RESERVE_0_145 : RW; bitpos: [31:17]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RESERVE_0_145 0x00007FFFU +#define EFUSE_RESERVE_0_145_M (EFUSE_RESERVE_0_145_V << EFUSE_RESERVE_0_145_S) +#define EFUSE_RESERVE_0_145_V 0x00007FFFU +#define EFUSE_RESERVE_0_145_S 17 + +/** EFUSE_BLK0_WDATA5_REG register */ +#define EFUSE_BLK0_WDATA5_REG (DR_REG_EFUSE_BASE + 0x30) +/** EFUSE_SPI_PAD_CONFIG_CLK : R; bitpos: [4:0]; default: 0; + * program for SPI_pad_config_clk + */ +#define EFUSE_SPI_PAD_CONFIG_CLK 0x0000001FU +#define EFUSE_SPI_PAD_CONFIG_CLK_M (EFUSE_SPI_PAD_CONFIG_CLK_V << EFUSE_SPI_PAD_CONFIG_CLK_S) +#define EFUSE_SPI_PAD_CONFIG_CLK_V 0x0000001FU #define EFUSE_SPI_PAD_CONFIG_CLK_S 0 +/** EFUSE_SPI_PAD_CONFIG_Q : R; bitpos: [9:5]; default: 0; + * program for SPI_pad_config_q + */ +#define EFUSE_SPI_PAD_CONFIG_Q 0x0000001FU +#define EFUSE_SPI_PAD_CONFIG_Q_M (EFUSE_SPI_PAD_CONFIG_Q_V << EFUSE_SPI_PAD_CONFIG_Q_S) +#define EFUSE_SPI_PAD_CONFIG_Q_V 0x0000001FU +#define EFUSE_SPI_PAD_CONFIG_Q_S 5 +/** EFUSE_SPI_PAD_CONFIG_D : R; bitpos: [14:10]; default: 0; + * program for SPI_pad_config_d + */ +#define EFUSE_SPI_PAD_CONFIG_D 0x0000001FU +#define EFUSE_SPI_PAD_CONFIG_D_M (EFUSE_SPI_PAD_CONFIG_D_V << EFUSE_SPI_PAD_CONFIG_D_S) +#define EFUSE_SPI_PAD_CONFIG_D_V 0x0000001FU +#define EFUSE_SPI_PAD_CONFIG_D_S 10 +/** EFUSE_SPI_PAD_CONFIG_CS0 : R; bitpos: [19:15]; default: 0; + * program for SPI_pad_config_cs0 + */ +#define EFUSE_SPI_PAD_CONFIG_CS0 0x0000001FU +#define EFUSE_SPI_PAD_CONFIG_CS0_M (EFUSE_SPI_PAD_CONFIG_CS0_V << EFUSE_SPI_PAD_CONFIG_CS0_S) +#define EFUSE_SPI_PAD_CONFIG_CS0_V 0x0000001FU +#define EFUSE_SPI_PAD_CONFIG_CS0_S 15 +/** EFUSE_CHIP_VER_REV2 : R; bitpos: [20]; default: 0; */ +#define EFUSE_CHIP_VER_REV2 (BIT(20)) +#define EFUSE_CHIP_VER_REV2_M (EFUSE_CHIP_VER_REV2_V << EFUSE_CHIP_VER_REV2_S) +#define EFUSE_CHIP_VER_REV2_V 0x00000001U +#define EFUSE_CHIP_VER_REV2_S 20 +/** EFUSE_RESERVE_0_181 : RW; bitpos: [21]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RESERVE_0_181 (BIT(21)) +#define EFUSE_RESERVE_0_181_M (EFUSE_RESERVE_0_181_V << EFUSE_RESERVE_0_181_S) +#define EFUSE_RESERVE_0_181_V 0x00000001U +#define EFUSE_RESERVE_0_181_S 21 +/** EFUSE_VOL_LEVEL_HP_INV : R; bitpos: [23:22]; default: 0; + * This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM + * to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO) + */ +#define EFUSE_VOL_LEVEL_HP_INV 0x00000003U +#define EFUSE_VOL_LEVEL_HP_INV_M (EFUSE_VOL_LEVEL_HP_INV_V << EFUSE_VOL_LEVEL_HP_INV_S) +#define EFUSE_VOL_LEVEL_HP_INV_V 0x00000003U +#define EFUSE_VOL_LEVEL_HP_INV_S 22 +/** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [25:24]; default: 0; */ +#define EFUSE_WAFER_VERSION_MINOR 0x00000003U +#define EFUSE_WAFER_VERSION_MINOR_M (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S) +#define EFUSE_WAFER_VERSION_MINOR_V 0x00000003U +#define EFUSE_WAFER_VERSION_MINOR_S 24 +/** EFUSE_RESERVE_0_186 : RW; bitpos: [27:26]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RESERVE_0_186 0x00000003U +#define EFUSE_RESERVE_0_186_M (EFUSE_RESERVE_0_186_V << EFUSE_RESERVE_0_186_S) +#define EFUSE_RESERVE_0_186_V 0x00000003U +#define EFUSE_RESERVE_0_186_S 26 +/** EFUSE_FLASH_CRYPT_CONFIG : R; bitpos: [31:28]; default: 0; + * program for flash_crypt_config + */ +#define EFUSE_FLASH_CRYPT_CONFIG 0x0000000FU +#define EFUSE_FLASH_CRYPT_CONFIG_M (EFUSE_FLASH_CRYPT_CONFIG_V << EFUSE_FLASH_CRYPT_CONFIG_S) +#define EFUSE_FLASH_CRYPT_CONFIG_V 0x0000000FU +#define EFUSE_FLASH_CRYPT_CONFIG_S 28 -#define EFUSE_BLK0_WDATA6_REG (DR_REG_EFUSE_BASE + 0x034) -/* EFUSE_KEY_STATUS : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: program for key_status*/ -#define EFUSE_KEY_STATUS (BIT(10)) -#define EFUSE_KEY_STATUS_M (BIT(10)) -#define EFUSE_KEY_STATUS_V 0x1 -#define EFUSE_KEY_STATUS_S 10 -/* EFUSE_DISABLE_DL_CACHE : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: program for download_dis_cache*/ -#define EFUSE_DISABLE_DL_CACHE (BIT(9)) -#define EFUSE_DISABLE_DL_CACHE_M (BIT(9)) -#define EFUSE_DISABLE_DL_CACHE_V 0x1 -#define EFUSE_DISABLE_DL_CACHE_S 9 -/* EFUSE_DISABLE_DL_DECRYPT : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: program for download_dis_decrypt*/ -#define EFUSE_DISABLE_DL_DECRYPT (BIT(8)) -#define EFUSE_DISABLE_DL_DECRYPT_M (BIT(8)) -#define EFUSE_DISABLE_DL_DECRYPT_V 0x1 -#define EFUSE_DISABLE_DL_DECRYPT_S 8 -/* EFUSE_DISABLE_DL_ENCRYPT : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: program for download_dis_encrypt*/ -#define EFUSE_DISABLE_DL_ENCRYPT (BIT(7)) -#define EFUSE_DISABLE_DL_ENCRYPT_M (BIT(7)) -#define EFUSE_DISABLE_DL_ENCRYPT_V 0x1 -#define EFUSE_DISABLE_DL_ENCRYPT_S 7 -/* EFUSE_DISABLE_JTAG : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: program for JTAG_disable*/ -#define EFUSE_DISABLE_JTAG (BIT(6)) -#define EFUSE_DISABLE_JTAG_M (BIT(6)) -#define EFUSE_DISABLE_JTAG_V 0x1 -#define EFUSE_DISABLE_JTAG_S 6 -/* EFUSE_ABS_DONE_1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: program for abstract_done_1*/ -#define EFUSE_ABS_DONE_1 (BIT(5)) -#define EFUSE_ABS_DONE_1_M (BIT(5)) -#define EFUSE_ABS_DONE_1_V 0x1 -#define EFUSE_ABS_DONE_1_S 5 -/* EFUSE_ABS_DONE_0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: program for abstract_done_0*/ -#define EFUSE_ABS_DONE_0 (BIT(4)) -#define EFUSE_ABS_DONE_0_M (BIT(4)) -#define EFUSE_ABS_DONE_0_V 0x1 -#define EFUSE_ABS_DONE_0_S 4 -/* EFUSE_DISABLE_SDIO_HOST : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_DISABLE_SDIO_HOST (BIT(3)) -#define EFUSE_DISABLE_SDIO_HOST_M (BIT(3)) -#define EFUSE_DISABLE_SDIO_HOST_V 0x1 -#define EFUSE_DISABLE_SDIO_HOST_S 3 -/* EFUSE_CONSOLE_DEBUG_DISABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: program for console_debug_disable*/ -#define EFUSE_CONSOLE_DEBUG_DISABLE (BIT(2)) -#define EFUSE_CONSOLE_DEBUG_DISABLE_M (BIT(2)) -#define EFUSE_CONSOLE_DEBUG_DISABLE_V 0x1 -#define EFUSE_CONSOLE_DEBUG_DISABLE_S 2 -/* EFUSE_CODING_SCHEME : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: program for coding_scheme*/ -#define EFUSE_CODING_SCHEME 0x00000003 -#define EFUSE_CODING_SCHEME_M ((EFUSE_CODING_SCHEME_V)<<(EFUSE_CODING_SCHEME_S)) -#define EFUSE_CODING_SCHEME_V 0x3 +/** EFUSE_BLK0_WDATA6_REG register */ +#define EFUSE_BLK0_WDATA6_REG (DR_REG_EFUSE_BASE + 0x34) +/** EFUSE_CODING_SCHEME : RW; bitpos: [1:0]; default: 0; + * program for coding_scheme + */ +#define EFUSE_CODING_SCHEME 0x00000003U +#define EFUSE_CODING_SCHEME_M (EFUSE_CODING_SCHEME_V << EFUSE_CODING_SCHEME_S) +#define EFUSE_CODING_SCHEME_V 0x00000003U #define EFUSE_CODING_SCHEME_S 0 +/** EFUSE_CONSOLE_DEBUG_DISABLE : RW; bitpos: [2]; default: 0; + * program for console_debug_disable + */ +#define EFUSE_CONSOLE_DEBUG_DISABLE (BIT(2)) +#define EFUSE_CONSOLE_DEBUG_DISABLE_M (EFUSE_CONSOLE_DEBUG_DISABLE_V << EFUSE_CONSOLE_DEBUG_DISABLE_S) +#define EFUSE_CONSOLE_DEBUG_DISABLE_V 0x00000001U +#define EFUSE_CONSOLE_DEBUG_DISABLE_S 2 +/** EFUSE_DISABLE_SDIO_HOST : RW; bitpos: [3]; default: 0; */ +#define EFUSE_DISABLE_SDIO_HOST (BIT(3)) +#define EFUSE_DISABLE_SDIO_HOST_M (EFUSE_DISABLE_SDIO_HOST_V << EFUSE_DISABLE_SDIO_HOST_S) +#define EFUSE_DISABLE_SDIO_HOST_V 0x00000001U +#define EFUSE_DISABLE_SDIO_HOST_S 3 +/** EFUSE_ABS_DONE_0 : RW; bitpos: [4]; default: 0; + * program for abstract_done_0 + */ +#define EFUSE_ABS_DONE_0 (BIT(4)) +#define EFUSE_ABS_DONE_0_M (EFUSE_ABS_DONE_0_V << EFUSE_ABS_DONE_0_S) +#define EFUSE_ABS_DONE_0_V 0x00000001U +#define EFUSE_ABS_DONE_0_S 4 +/** EFUSE_ABS_DONE_1 : RW; bitpos: [5]; default: 0; + * program for abstract_done_1 + */ +#define EFUSE_ABS_DONE_1 (BIT(5)) +#define EFUSE_ABS_DONE_1_M (EFUSE_ABS_DONE_1_V << EFUSE_ABS_DONE_1_S) +#define EFUSE_ABS_DONE_1_V 0x00000001U +#define EFUSE_ABS_DONE_1_S 5 +/** EFUSE_DISABLE_JTAG : RW; bitpos: [6]; default: 0; + * program for JTAG_disable + */ +#define EFUSE_DISABLE_JTAG (BIT(6)) +#define EFUSE_DISABLE_JTAG_M (EFUSE_DISABLE_JTAG_V << EFUSE_DISABLE_JTAG_S) +#define EFUSE_DISABLE_JTAG_V 0x00000001U +#define EFUSE_DISABLE_JTAG_S 6 +/** EFUSE_DISABLE_DL_ENCRYPT : RW; bitpos: [7]; default: 0; + * program for download_dis_encrypt + */ +#define EFUSE_DISABLE_DL_ENCRYPT (BIT(7)) +#define EFUSE_DISABLE_DL_ENCRYPT_M (EFUSE_DISABLE_DL_ENCRYPT_V << EFUSE_DISABLE_DL_ENCRYPT_S) +#define EFUSE_DISABLE_DL_ENCRYPT_V 0x00000001U +#define EFUSE_DISABLE_DL_ENCRYPT_S 7 +/** EFUSE_DISABLE_DL_DECRYPT : RW; bitpos: [8]; default: 0; + * program for download_dis_decrypt + */ +#define EFUSE_DISABLE_DL_DECRYPT (BIT(8)) +#define EFUSE_DISABLE_DL_DECRYPT_M (EFUSE_DISABLE_DL_DECRYPT_V << EFUSE_DISABLE_DL_DECRYPT_S) +#define EFUSE_DISABLE_DL_DECRYPT_V 0x00000001U +#define EFUSE_DISABLE_DL_DECRYPT_S 8 +/** EFUSE_DISABLE_DL_CACHE : RW; bitpos: [9]; default: 0; + * program for download_dis_cache + */ +#define EFUSE_DISABLE_DL_CACHE (BIT(9)) +#define EFUSE_DISABLE_DL_CACHE_M (EFUSE_DISABLE_DL_CACHE_V << EFUSE_DISABLE_DL_CACHE_S) +#define EFUSE_DISABLE_DL_CACHE_V 0x00000001U +#define EFUSE_DISABLE_DL_CACHE_S 9 +/** EFUSE_KEY_STATUS : RW; bitpos: [10]; default: 0; + * program for key_status + */ +#define EFUSE_KEY_STATUS (BIT(10)) +#define EFUSE_KEY_STATUS_M (EFUSE_KEY_STATUS_V << EFUSE_KEY_STATUS_S) +#define EFUSE_KEY_STATUS_V 0x00000001U +#define EFUSE_KEY_STATUS_S 10 -#define EFUSE_BLK1_RDATA0_REG (DR_REG_EFUSE_BASE + 0x038) -/* EFUSE_BLK1_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK1*/ -#define EFUSE_BLK1_DOUT0 0xFFFFFFFF -#define EFUSE_BLK1_DOUT0_M ((EFUSE_BLK1_DOUT0_V)<<(EFUSE_BLK1_DOUT0_S)) -#define EFUSE_BLK1_DOUT0_V 0xFFFFFFFF -#define EFUSE_BLK1_DOUT0_S 0 - -#define EFUSE_BLK1_RDATA1_REG (DR_REG_EFUSE_BASE + 0x03c) -/* EFUSE_BLK1_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK1*/ -#define EFUSE_BLK1_DOUT1 0xFFFFFFFF -#define EFUSE_BLK1_DOUT1_M ((EFUSE_BLK1_DOUT1_V)<<(EFUSE_BLK1_DOUT1_S)) -#define EFUSE_BLK1_DOUT1_V 0xFFFFFFFF -#define EFUSE_BLK1_DOUT1_S 0 - -#define EFUSE_BLK1_RDATA2_REG (DR_REG_EFUSE_BASE + 0x040) -/* EFUSE_BLK1_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK1*/ -#define EFUSE_BLK1_DOUT2 0xFFFFFFFF -#define EFUSE_BLK1_DOUT2_M ((EFUSE_BLK1_DOUT2_V)<<(EFUSE_BLK1_DOUT2_S)) -#define EFUSE_BLK1_DOUT2_V 0xFFFFFFFF -#define EFUSE_BLK1_DOUT2_S 0 - -#define EFUSE_BLK1_RDATA3_REG (DR_REG_EFUSE_BASE + 0x044) -/* EFUSE_BLK1_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK1*/ -#define EFUSE_BLK1_DOUT3 0xFFFFFFFF -#define EFUSE_BLK1_DOUT3_M ((EFUSE_BLK1_DOUT3_V)<<(EFUSE_BLK1_DOUT3_S)) -#define EFUSE_BLK1_DOUT3_V 0xFFFFFFFF -#define EFUSE_BLK1_DOUT3_S 0 - -#define EFUSE_BLK1_RDATA4_REG (DR_REG_EFUSE_BASE + 0x048) -/* EFUSE_BLK1_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK1*/ -#define EFUSE_BLK1_DOUT4 0xFFFFFFFF -#define EFUSE_BLK1_DOUT4_M ((EFUSE_BLK1_DOUT4_V)<<(EFUSE_BLK1_DOUT4_S)) -#define EFUSE_BLK1_DOUT4_V 0xFFFFFFFF -#define EFUSE_BLK1_DOUT4_S 0 - -#define EFUSE_BLK1_RDATA5_REG (DR_REG_EFUSE_BASE + 0x04c) -/* EFUSE_BLK1_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK1*/ -#define EFUSE_BLK1_DOUT5 0xFFFFFFFF -#define EFUSE_BLK1_DOUT5_M ((EFUSE_BLK1_DOUT5_V)<<(EFUSE_BLK1_DOUT5_S)) -#define EFUSE_BLK1_DOUT5_V 0xFFFFFFFF -#define EFUSE_BLK1_DOUT5_S 0 - -#define EFUSE_BLK1_RDATA6_REG (DR_REG_EFUSE_BASE + 0x050) -/* EFUSE_BLK1_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK1*/ -#define EFUSE_BLK1_DOUT6 0xFFFFFFFF -#define EFUSE_BLK1_DOUT6_M ((EFUSE_BLK1_DOUT6_V)<<(EFUSE_BLK1_DOUT6_S)) -#define EFUSE_BLK1_DOUT6_V 0xFFFFFFFF -#define EFUSE_BLK1_DOUT6_S 0 - -#define EFUSE_BLK1_RDATA7_REG (DR_REG_EFUSE_BASE + 0x054) -/* EFUSE_BLK1_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK1*/ -#define EFUSE_BLK1_DOUT7 0xFFFFFFFF -#define EFUSE_BLK1_DOUT7_M ((EFUSE_BLK1_DOUT7_V)<<(EFUSE_BLK1_DOUT7_S)) -#define EFUSE_BLK1_DOUT7_V 0xFFFFFFFF -#define EFUSE_BLK1_DOUT7_S 0 - -#define EFUSE_BLK2_RDATA0_REG (DR_REG_EFUSE_BASE + 0x058) -/* EFUSE_BLK2_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK2*/ -#define EFUSE_BLK2_DOUT0 0xFFFFFFFF -#define EFUSE_BLK2_DOUT0_M ((EFUSE_BLK2_DOUT0_V)<<(EFUSE_BLK2_DOUT0_S)) -#define EFUSE_BLK2_DOUT0_V 0xFFFFFFFF -#define EFUSE_BLK2_DOUT0_S 0 - -#define EFUSE_BLK2_RDATA1_REG (DR_REG_EFUSE_BASE + 0x05c) -/* EFUSE_BLK2_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK2*/ -#define EFUSE_BLK2_DOUT1 0xFFFFFFFF -#define EFUSE_BLK2_DOUT1_M ((EFUSE_BLK2_DOUT1_V)<<(EFUSE_BLK2_DOUT1_S)) -#define EFUSE_BLK2_DOUT1_V 0xFFFFFFFF -#define EFUSE_BLK2_DOUT1_S 0 - -#define EFUSE_BLK2_RDATA2_REG (DR_REG_EFUSE_BASE + 0x060) -/* EFUSE_BLK2_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK2*/ -#define EFUSE_BLK2_DOUT2 0xFFFFFFFF -#define EFUSE_BLK2_DOUT2_M ((EFUSE_BLK2_DOUT2_V)<<(EFUSE_BLK2_DOUT2_S)) -#define EFUSE_BLK2_DOUT2_V 0xFFFFFFFF -#define EFUSE_BLK2_DOUT2_S 0 - -#define EFUSE_BLK2_RDATA3_REG (DR_REG_EFUSE_BASE + 0x064) -/* EFUSE_BLK2_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK2*/ -#define EFUSE_BLK2_DOUT3 0xFFFFFFFF -#define EFUSE_BLK2_DOUT3_M ((EFUSE_BLK2_DOUT3_V)<<(EFUSE_BLK2_DOUT3_S)) -#define EFUSE_BLK2_DOUT3_V 0xFFFFFFFF -#define EFUSE_BLK2_DOUT3_S 0 - -#define EFUSE_BLK2_RDATA4_REG (DR_REG_EFUSE_BASE + 0x068) -/* EFUSE_BLK2_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK2*/ -#define EFUSE_BLK2_DOUT4 0xFFFFFFFF -#define EFUSE_BLK2_DOUT4_M ((EFUSE_BLK2_DOUT4_V)<<(EFUSE_BLK2_DOUT4_S)) -#define EFUSE_BLK2_DOUT4_V 0xFFFFFFFF -#define EFUSE_BLK2_DOUT4_S 0 - -#define EFUSE_BLK2_RDATA5_REG (DR_REG_EFUSE_BASE + 0x06c) -/* EFUSE_BLK2_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK2*/ -#define EFUSE_BLK2_DOUT5 0xFFFFFFFF -#define EFUSE_BLK2_DOUT5_M ((EFUSE_BLK2_DOUT5_V)<<(EFUSE_BLK2_DOUT5_S)) -#define EFUSE_BLK2_DOUT5_V 0xFFFFFFFF -#define EFUSE_BLK2_DOUT5_S 0 - -#define EFUSE_BLK2_RDATA6_REG (DR_REG_EFUSE_BASE + 0x070) -/* EFUSE_BLK2_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK2*/ -#define EFUSE_BLK2_DOUT6 0xFFFFFFFF -#define EFUSE_BLK2_DOUT6_M ((EFUSE_BLK2_DOUT6_V)<<(EFUSE_BLK2_DOUT6_S)) -#define EFUSE_BLK2_DOUT6_V 0xFFFFFFFF -#define EFUSE_BLK2_DOUT6_S 0 - -#define EFUSE_BLK2_RDATA7_REG (DR_REG_EFUSE_BASE + 0x074) -/* EFUSE_BLK2_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK2*/ -#define EFUSE_BLK2_DOUT7 0xFFFFFFFF -#define EFUSE_BLK2_DOUT7_M ((EFUSE_BLK2_DOUT7_V)<<(EFUSE_BLK2_DOUT7_S)) -#define EFUSE_BLK2_DOUT7_V 0xFFFFFFFF -#define EFUSE_BLK2_DOUT7_S 0 - -#define EFUSE_BLK3_RDATA0_REG (DR_REG_EFUSE_BASE + 0x078) -/* EFUSE_BLK3_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK3*/ -#define EFUSE_BLK3_DOUT0 0xFFFFFFFF -#define EFUSE_BLK3_DOUT0_M ((EFUSE_BLK3_DOUT0_V)<<(EFUSE_BLK3_DOUT0_S)) -#define EFUSE_BLK3_DOUT0_V 0xFFFFFFFF -#define EFUSE_BLK3_DOUT0_S 0 - -#define EFUSE_BLK3_RDATA1_REG (DR_REG_EFUSE_BASE + 0x07c) -/* EFUSE_BLK3_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK3*/ -#define EFUSE_BLK3_DOUT1 0xFFFFFFFF -#define EFUSE_BLK3_DOUT1_M ((EFUSE_BLK3_DOUT1_V)<<(EFUSE_BLK3_DOUT1_S)) -#define EFUSE_BLK3_DOUT1_V 0xFFFFFFFF -#define EFUSE_BLK3_DOUT1_S 0 - -#define EFUSE_BLK3_RDATA2_REG (DR_REG_EFUSE_BASE + 0x080) -/* EFUSE_BLK3_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK3*/ -#define EFUSE_BLK3_DOUT2 0xFFFFFFFF -#define EFUSE_BLK3_DOUT2_M ((EFUSE_BLK3_DOUT2_V)<<(EFUSE_BLK3_DOUT2_S)) -#define EFUSE_BLK3_DOUT2_V 0xFFFFFFFF -#define EFUSE_BLK3_DOUT2_S 0 - -/* Note: Newer ESP32s utilize BLK3_DATA3 and parts of BLK3_DATA4 for calibration - * purposes. This usage is indicated by the EFUSE_RD_BLK3_PART_RESERVE bit.*/ -#define EFUSE_BLK3_RDATA3_REG (DR_REG_EFUSE_BASE + 0x084) -/* EFUSE_BLK3_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK3*/ -#define EFUSE_BLK3_DOUT3 0xFFFFFFFF -#define EFUSE_BLK3_DOUT3_M ((EFUSE_BLK3_DOUT3_V)<<(EFUSE_BLK3_DOUT3_S)) -#define EFUSE_BLK3_DOUT3_V 0xFFFFFFFF -#define EFUSE_BLK3_DOUT3_S 0 -/* EFUSE_RD_ADC2_TP_HIGH : R/W ;bitpos:[31:23] ;default: 9'b0 ; */ -/*description: ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ -#define EFUSE_RD_ADC2_TP_HIGH 0x1FF -#define EFUSE_RD_ADC2_TP_HIGH_M ((EFUSE_RD_ADC2_TP_HIGH_V)<<(EFUSE_RD_ADC2_TP_HIGH_S)) -#define EFUSE_RD_ADC2_TP_HIGH_V 0x1FF -#define EFUSE_RD_ADC2_TP_HIGH_S 23 -/* EFUSE_RD_ADC2_TP_LOW : R/W ;bitpos:[22:16] ;default: 7'b0 ; */ -/*description: ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ -#define EFUSE_RD_ADC2_TP_LOW 0x7F -#define EFUSE_RD_ADC2_TP_LOW_M ((EFUSE_RD_ADC2_TP_LOW_V)<<(EFUSE_RD_ADC2_TP_LOW_S)) -#define EFUSE_RD_ADC2_TP_LOW_V 0x7F -#define EFUSE_RD_ADC2_TP_LOW_S 16 -/* EFUSE_RD_ADC1_TP_HIGH : R/W ;bitpos:[15:7] ;default: 9'b0 ; */ -/*description: ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ -#define EFUSE_RD_ADC1_TP_HIGH 0x1FF -#define EFUSE_RD_ADC1_TP_HIGH_M ((EFUSE_RD_ADC1_TP_HIGH_V)<<(EFUSE_RD_ADC1_TP_HIGH_S)) -#define EFUSE_RD_ADC1_TP_HIGH_V 0x1FF -#define EFUSE_RD_ADC1_TP_HIGH_S 7 -/* EFUSE_RD_ADC1_TP_LOW : R/W ;bitpos:[6:0] ;default: 7'b0 ; */ -/*description: ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ -#define EFUSE_RD_ADC1_TP_LOW 0x7F -#define EFUSE_RD_ADC1_TP_LOW_M ((EFUSE_RD_ADC1_TP_LOW_V)<<(EFUSE_RD_ADC1_TP_LOW_S)) -#define EFUSE_RD_ADC1_TP_LOW_V 0x7F +/** EFUSE_BLK1_RDATA0_REG register */ +#define EFUSE_BLK1_RDATA0_REG (DR_REG_EFUSE_BASE + 0x38) +/** EFUSE_RD_BLOCK1 : R; bitpos: [31:0]; default: 0; + * Flash encryption key + */ +#define EFUSE_RD_BLOCK1 0xFFFFFFFFU +#define EFUSE_RD_BLOCK1_M (EFUSE_RD_BLOCK1_V << EFUSE_RD_BLOCK1_S) +#define EFUSE_RD_BLOCK1_V 0xFFFFFFFFU +#define EFUSE_RD_BLOCK1_S 0 + +/** EFUSE_BLK1_RDATA1_REG register */ +#define EFUSE_BLK1_RDATA1_REG (DR_REG_EFUSE_BASE + 0x3c) +/** EFUSE_RD_BLOCK1_1 : R; bitpos: [31:0]; default: 0; + * Flash encryption key + */ +#define EFUSE_RD_BLOCK1_1 0xFFFFFFFFU +#define EFUSE_RD_BLOCK1_1_M (EFUSE_RD_BLOCK1_1_V << EFUSE_RD_BLOCK1_1_S) +#define EFUSE_RD_BLOCK1_1_V 0xFFFFFFFFU +#define EFUSE_RD_BLOCK1_1_S 0 + +/** EFUSE_BLK1_RDATA2_REG register */ +#define EFUSE_BLK1_RDATA2_REG (DR_REG_EFUSE_BASE + 0x40) +/** EFUSE_RD_BLOCK1_2 : R; bitpos: [31:0]; default: 0; + * Flash encryption key + */ +#define EFUSE_RD_BLOCK1_2 0xFFFFFFFFU +#define EFUSE_RD_BLOCK1_2_M (EFUSE_RD_BLOCK1_2_V << EFUSE_RD_BLOCK1_2_S) +#define EFUSE_RD_BLOCK1_2_V 0xFFFFFFFFU +#define EFUSE_RD_BLOCK1_2_S 0 + +/** EFUSE_BLK1_RDATA3_REG register */ +#define EFUSE_BLK1_RDATA3_REG (DR_REG_EFUSE_BASE + 0x44) +/** EFUSE_RD_BLOCK1_3 : R; bitpos: [31:0]; default: 0; + * Flash encryption key + */ +#define EFUSE_RD_BLOCK1_3 0xFFFFFFFFU +#define EFUSE_RD_BLOCK1_3_M (EFUSE_RD_BLOCK1_3_V << EFUSE_RD_BLOCK1_3_S) +#define EFUSE_RD_BLOCK1_3_V 0xFFFFFFFFU +#define EFUSE_RD_BLOCK1_3_S 0 + +/** EFUSE_BLK1_RDATA4_REG register */ +#define EFUSE_BLK1_RDATA4_REG (DR_REG_EFUSE_BASE + 0x48) +/** EFUSE_RD_BLOCK1_4 : R; bitpos: [31:0]; default: 0; + * Flash encryption key + */ +#define EFUSE_RD_BLOCK1_4 0xFFFFFFFFU +#define EFUSE_RD_BLOCK1_4_M (EFUSE_RD_BLOCK1_4_V << EFUSE_RD_BLOCK1_4_S) +#define EFUSE_RD_BLOCK1_4_V 0xFFFFFFFFU +#define EFUSE_RD_BLOCK1_4_S 0 + +/** EFUSE_BLK1_RDATA5_REG register */ +#define EFUSE_BLK1_RDATA5_REG (DR_REG_EFUSE_BASE + 0x4c) +/** EFUSE_RD_BLOCK1_5 : R; bitpos: [31:0]; default: 0; + * Flash encryption key + */ +#define EFUSE_RD_BLOCK1_5 0xFFFFFFFFU +#define EFUSE_RD_BLOCK1_5_M (EFUSE_RD_BLOCK1_5_V << EFUSE_RD_BLOCK1_5_S) +#define EFUSE_RD_BLOCK1_5_V 0xFFFFFFFFU +#define EFUSE_RD_BLOCK1_5_S 0 + +/** EFUSE_BLK1_RDATA6_REG register */ +#define EFUSE_BLK1_RDATA6_REG (DR_REG_EFUSE_BASE + 0x50) +/** EFUSE_RD_BLOCK1_6 : R; bitpos: [31:0]; default: 0; + * Flash encryption key + */ +#define EFUSE_RD_BLOCK1_6 0xFFFFFFFFU +#define EFUSE_RD_BLOCK1_6_M (EFUSE_RD_BLOCK1_6_V << EFUSE_RD_BLOCK1_6_S) +#define EFUSE_RD_BLOCK1_6_V 0xFFFFFFFFU +#define EFUSE_RD_BLOCK1_6_S 0 + +/** EFUSE_BLK1_RDATA7_REG register */ +#define EFUSE_BLK1_RDATA7_REG (DR_REG_EFUSE_BASE + 0x54) +/** EFUSE_RD_BLOCK1_7 : R; bitpos: [31:0]; default: 0; + * Flash encryption key + */ +#define EFUSE_RD_BLOCK1_7 0xFFFFFFFFU +#define EFUSE_RD_BLOCK1_7_M (EFUSE_RD_BLOCK1_7_V << EFUSE_RD_BLOCK1_7_S) +#define EFUSE_RD_BLOCK1_7_V 0xFFFFFFFFU +#define EFUSE_RD_BLOCK1_7_S 0 + +/** EFUSE_BLK2_RDATA0_REG register */ +#define EFUSE_BLK2_RDATA0_REG (DR_REG_EFUSE_BASE + 0x58) +/** EFUSE_RD_BLOCK2 : R; bitpos: [31:0]; default: 0; + * Security boot key + */ +#define EFUSE_RD_BLOCK2 0xFFFFFFFFU +#define EFUSE_RD_BLOCK2_M (EFUSE_RD_BLOCK2_V << EFUSE_RD_BLOCK2_S) +#define EFUSE_RD_BLOCK2_V 0xFFFFFFFFU +#define EFUSE_RD_BLOCK2_S 0 + +/** EFUSE_BLK2_RDATA1_REG register */ +#define EFUSE_BLK2_RDATA1_REG (DR_REG_EFUSE_BASE + 0x5c) +/** EFUSE_RD_BLOCK2_1 : R; bitpos: [31:0]; default: 0; + * Security boot key + */ +#define EFUSE_RD_BLOCK2_1 0xFFFFFFFFU +#define EFUSE_RD_BLOCK2_1_M (EFUSE_RD_BLOCK2_1_V << EFUSE_RD_BLOCK2_1_S) +#define EFUSE_RD_BLOCK2_1_V 0xFFFFFFFFU +#define EFUSE_RD_BLOCK2_1_S 0 + +/** EFUSE_BLK2_RDATA2_REG register */ +#define EFUSE_BLK2_RDATA2_REG (DR_REG_EFUSE_BASE + 0x60) +/** EFUSE_RD_BLOCK2_2 : R; bitpos: [31:0]; default: 0; + * Security boot key + */ +#define EFUSE_RD_BLOCK2_2 0xFFFFFFFFU +#define EFUSE_RD_BLOCK2_2_M (EFUSE_RD_BLOCK2_2_V << EFUSE_RD_BLOCK2_2_S) +#define EFUSE_RD_BLOCK2_2_V 0xFFFFFFFFU +#define EFUSE_RD_BLOCK2_2_S 0 + +/** EFUSE_BLK2_RDATA3_REG register */ +#define EFUSE_BLK2_RDATA3_REG (DR_REG_EFUSE_BASE + 0x64) +/** EFUSE_RD_BLOCK2_3 : R; bitpos: [31:0]; default: 0; + * Security boot key + */ +#define EFUSE_RD_BLOCK2_3 0xFFFFFFFFU +#define EFUSE_RD_BLOCK2_3_M (EFUSE_RD_BLOCK2_3_V << EFUSE_RD_BLOCK2_3_S) +#define EFUSE_RD_BLOCK2_3_V 0xFFFFFFFFU +#define EFUSE_RD_BLOCK2_3_S 0 + +/** EFUSE_BLK2_RDATA4_REG register */ +#define EFUSE_BLK2_RDATA4_REG (DR_REG_EFUSE_BASE + 0x68) +/** EFUSE_RD_BLOCK2_4 : R; bitpos: [31:0]; default: 0; + * Security boot key + */ +#define EFUSE_RD_BLOCK2_4 0xFFFFFFFFU +#define EFUSE_RD_BLOCK2_4_M (EFUSE_RD_BLOCK2_4_V << EFUSE_RD_BLOCK2_4_S) +#define EFUSE_RD_BLOCK2_4_V 0xFFFFFFFFU +#define EFUSE_RD_BLOCK2_4_S 0 + +/** EFUSE_BLK2_RDATA5_REG register */ +#define EFUSE_BLK2_RDATA5_REG (DR_REG_EFUSE_BASE + 0x6c) +/** EFUSE_RD_BLOCK2_5 : R; bitpos: [31:0]; default: 0; + * Security boot key + */ +#define EFUSE_RD_BLOCK2_5 0xFFFFFFFFU +#define EFUSE_RD_BLOCK2_5_M (EFUSE_RD_BLOCK2_5_V << EFUSE_RD_BLOCK2_5_S) +#define EFUSE_RD_BLOCK2_5_V 0xFFFFFFFFU +#define EFUSE_RD_BLOCK2_5_S 0 + +/** EFUSE_BLK2_RDATA6_REG register */ +#define EFUSE_BLK2_RDATA6_REG (DR_REG_EFUSE_BASE + 0x70) +/** EFUSE_RD_BLOCK2_6 : R; bitpos: [31:0]; default: 0; + * Security boot key + */ +#define EFUSE_RD_BLOCK2_6 0xFFFFFFFFU +#define EFUSE_RD_BLOCK2_6_M (EFUSE_RD_BLOCK2_6_V << EFUSE_RD_BLOCK2_6_S) +#define EFUSE_RD_BLOCK2_6_V 0xFFFFFFFFU +#define EFUSE_RD_BLOCK2_6_S 0 + +/** EFUSE_BLK2_RDATA7_REG register */ +#define EFUSE_BLK2_RDATA7_REG (DR_REG_EFUSE_BASE + 0x74) +/** EFUSE_RD_BLOCK2_7 : R; bitpos: [31:0]; default: 0; + * Security boot key + */ +#define EFUSE_RD_BLOCK2_7 0xFFFFFFFFU +#define EFUSE_RD_BLOCK2_7_M (EFUSE_RD_BLOCK2_7_V << EFUSE_RD_BLOCK2_7_S) +#define EFUSE_RD_BLOCK2_7_V 0xFFFFFFFFU +#define EFUSE_RD_BLOCK2_7_S 0 + +/** EFUSE_BLK3_RDATA0_REG register */ +#define EFUSE_BLK3_RDATA0_REG (DR_REG_EFUSE_BASE + 0x78) +/** EFUSE_RD_CUSTOM_MAC_CRC : R; bitpos: [7:0]; default: 0; + * CRC8 for custom MAC address + */ +#define EFUSE_RD_CUSTOM_MAC_CRC 0x000000FFU +#define EFUSE_RD_CUSTOM_MAC_CRC_M (EFUSE_RD_CUSTOM_MAC_CRC_V << EFUSE_RD_CUSTOM_MAC_CRC_S) +#define EFUSE_RD_CUSTOM_MAC_CRC_V 0x000000FFU +#define EFUSE_RD_CUSTOM_MAC_CRC_S 0 +/** EFUSE_RD_CUSTOM_MAC : R; bitpos: [31:8]; default: 0; + * Custom MAC address + */ +#define EFUSE_RD_CUSTOM_MAC 0x00FFFFFFU +#define EFUSE_RD_CUSTOM_MAC_M (EFUSE_RD_CUSTOM_MAC_V << EFUSE_RD_CUSTOM_MAC_S) +#define EFUSE_RD_CUSTOM_MAC_V 0x00FFFFFFU +#define EFUSE_RD_CUSTOM_MAC_S 8 + +/** EFUSE_BLK3_RDATA1_REG register */ +#define EFUSE_BLK3_RDATA1_REG (DR_REG_EFUSE_BASE + 0x7c) +/** EFUSE_RD_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0; + * Custom MAC address + */ +#define EFUSE_RD_CUSTOM_MAC_1 0x00FFFFFFU +#define EFUSE_RD_CUSTOM_MAC_1_M (EFUSE_RD_CUSTOM_MAC_1_V << EFUSE_RD_CUSTOM_MAC_1_S) +#define EFUSE_RD_CUSTOM_MAC_1_V 0x00FFFFFFU +#define EFUSE_RD_CUSTOM_MAC_1_S 0 +/** EFUSE_RESERVED_3_56 : R; bitpos: [31:24]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_3_56 0x000000FFU +#define EFUSE_RESERVED_3_56_M (EFUSE_RESERVED_3_56_V << EFUSE_RESERVED_3_56_S) +#define EFUSE_RESERVED_3_56_V 0x000000FFU +#define EFUSE_RESERVED_3_56_S 24 + +/** EFUSE_BLK3_RDATA2_REG register */ +#define EFUSE_BLK3_RDATA2_REG (DR_REG_EFUSE_BASE + 0x80) +/** EFUSE_RD_BLK3_RESERVED_2 : R; bitpos: [31:0]; default: 0; + * read for BLOCK3 + */ +#define EFUSE_RD_BLK3_RESERVED_2 0xFFFFFFFFU +#define EFUSE_RD_BLK3_RESERVED_2_M (EFUSE_RD_BLK3_RESERVED_2_V << EFUSE_RD_BLK3_RESERVED_2_S) +#define EFUSE_RD_BLK3_RESERVED_2_V 0xFFFFFFFFU +#define EFUSE_RD_BLK3_RESERVED_2_S 0 + +/** EFUSE_BLK3_RDATA3_REG register */ +#define EFUSE_BLK3_RDATA3_REG (DR_REG_EFUSE_BASE + 0x84) +/** EFUSE_RD_ADC1_TP_LOW : RW; bitpos: [6:0]; default: 0; + * ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + */ +#define EFUSE_RD_ADC1_TP_LOW 0x0000007FU +#define EFUSE_RD_ADC1_TP_LOW_M (EFUSE_RD_ADC1_TP_LOW_V << EFUSE_RD_ADC1_TP_LOW_S) +#define EFUSE_RD_ADC1_TP_LOW_V 0x0000007FU #define EFUSE_RD_ADC1_TP_LOW_S 0 +/** EFUSE_RD_ADC1_TP_HIGH : RW; bitpos: [15:7]; default: 0; + * ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + */ +#define EFUSE_RD_ADC1_TP_HIGH 0x000001FFU +#define EFUSE_RD_ADC1_TP_HIGH_M (EFUSE_RD_ADC1_TP_HIGH_V << EFUSE_RD_ADC1_TP_HIGH_S) +#define EFUSE_RD_ADC1_TP_HIGH_V 0x000001FFU +#define EFUSE_RD_ADC1_TP_HIGH_S 7 +/** EFUSE_RD_ADC2_TP_LOW : RW; bitpos: [22:16]; default: 0; + * ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + */ +#define EFUSE_RD_ADC2_TP_LOW 0x0000007FU +#define EFUSE_RD_ADC2_TP_LOW_M (EFUSE_RD_ADC2_TP_LOW_V << EFUSE_RD_ADC2_TP_LOW_S) +#define EFUSE_RD_ADC2_TP_LOW_V 0x0000007FU +#define EFUSE_RD_ADC2_TP_LOW_S 16 +/** EFUSE_RD_ADC2_TP_HIGH : RW; bitpos: [31:23]; default: 0; + * ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + */ +#define EFUSE_RD_ADC2_TP_HIGH 0x000001FFU +#define EFUSE_RD_ADC2_TP_HIGH_M (EFUSE_RD_ADC2_TP_HIGH_V << EFUSE_RD_ADC2_TP_HIGH_S) +#define EFUSE_RD_ADC2_TP_HIGH_V 0x000001FFU +#define EFUSE_RD_ADC2_TP_HIGH_S 23 -#define EFUSE_BLK3_RDATA4_REG (DR_REG_EFUSE_BASE + 0x088) -/* EFUSE_BLK3_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK3*/ -#define EFUSE_BLK3_DOUT4 0xFFFFFFFF -#define EFUSE_BLK3_DOUT4_M ((EFUSE_BLK3_DOUT4_V)<<(EFUSE_BLK3_DOUT4_S)) -#define EFUSE_BLK3_DOUT4_V 0xFFFFFFFF -#define EFUSE_BLK3_DOUT4_S 0 -/* EFUSE_RD_CAL_RESERVED: R/W ; bitpos:[0:15] ; default : 16'h0 ; */ -/*description: Reserved for future calibration use. Indicated by EFUSE_RD_BLK3_PART_RESERVE */ -#define EFUSE_RD_CAL_RESERVED 0x0000FFFF -#define EFUSE_RD_CAL_RESERVED_M ((EFUSE_RD_CAL_RESERVED_V)<<(EFUSE_RD_CAL_RESERVED_S)) -#define EFUSE_RD_CAL_RESERVED_V 0xFFFF -#define EFUSE_RD_CAL_RESERVED_S 0 - -#define EFUSE_BLK3_RDATA5_REG (DR_REG_EFUSE_BASE + 0x08c) -/* EFUSE_BLK3_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK3*/ -#define EFUSE_BLK3_DOUT5 0xFFFFFFFF -#define EFUSE_BLK3_DOUT5_M ((EFUSE_BLK3_DOUT5_V)<<(EFUSE_BLK3_DOUT5_S)) -#define EFUSE_BLK3_DOUT5_V 0xFFFFFFFF -#define EFUSE_BLK3_DOUT5_S 0 - -#define EFUSE_BLK3_RDATA6_REG (DR_REG_EFUSE_BASE + 0x090) -/* EFUSE_BLK3_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK3*/ -#define EFUSE_BLK3_DOUT6 0xFFFFFFFF -#define EFUSE_BLK3_DOUT6_M ((EFUSE_BLK3_DOUT6_V)<<(EFUSE_BLK3_DOUT6_S)) -#define EFUSE_BLK3_DOUT6_V 0xFFFFFFFF -#define EFUSE_BLK3_DOUT6_S 0 - -#define EFUSE_BLK3_RDATA7_REG (DR_REG_EFUSE_BASE + 0x094) -/* EFUSE_BLK3_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK3*/ -#define EFUSE_BLK3_DOUT7 0xFFFFFFFF -#define EFUSE_BLK3_DOUT7_M ((EFUSE_BLK3_DOUT7_V)<<(EFUSE_BLK3_DOUT7_S)) -#define EFUSE_BLK3_DOUT7_V 0xFFFFFFFF -#define EFUSE_BLK3_DOUT7_S 0 - -#define EFUSE_BLK1_WDATA0_REG (DR_REG_EFUSE_BASE + 0x098) -/* EFUSE_BLK1_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK1*/ -#define EFUSE_BLK1_DIN0 0xFFFFFFFF -#define EFUSE_BLK1_DIN0_M ((EFUSE_BLK1_DIN0_V)<<(EFUSE_BLK1_DIN0_S)) -#define EFUSE_BLK1_DIN0_V 0xFFFFFFFF +/** EFUSE_BLK3_RDATA4_REG register */ +#define EFUSE_BLK3_RDATA4_REG (DR_REG_EFUSE_BASE + 0x88) +/** EFUSE_RD_SECURE_VERSION : R; bitpos: [31:0]; default: 0; + * Secure version for anti-rollback + */ +#define EFUSE_RD_SECURE_VERSION 0xFFFFFFFFU +#define EFUSE_RD_SECURE_VERSION_M (EFUSE_RD_SECURE_VERSION_V << EFUSE_RD_SECURE_VERSION_S) +#define EFUSE_RD_SECURE_VERSION_V 0xFFFFFFFFU +#define EFUSE_RD_SECURE_VERSION_S 0 + +/** EFUSE_BLK3_RDATA5_REG register */ +#define EFUSE_BLK3_RDATA5_REG (DR_REG_EFUSE_BASE + 0x8c) +/** EFUSE_RESERVED_3_160 : R; bitpos: [23:0]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_3_160 0x00FFFFFFU +#define EFUSE_RESERVED_3_160_M (EFUSE_RESERVED_3_160_V << EFUSE_RESERVED_3_160_S) +#define EFUSE_RESERVED_3_160_V 0x00FFFFFFU +#define EFUSE_RESERVED_3_160_S 0 +/** EFUSE_RD_MAC_VERSION : R; bitpos: [31:24]; default: 0; + * Custom MAC version + */ +#define EFUSE_RD_MAC_VERSION 0x000000FFU +#define EFUSE_RD_MAC_VERSION_M (EFUSE_RD_MAC_VERSION_V << EFUSE_RD_MAC_VERSION_S) +#define EFUSE_RD_MAC_VERSION_V 0x000000FFU +#define EFUSE_RD_MAC_VERSION_S 24 + +/** EFUSE_BLK3_RDATA6_REG register */ +#define EFUSE_BLK3_RDATA6_REG (DR_REG_EFUSE_BASE + 0x90) +/** EFUSE_RD_BLK3_RESERVED_6 : R; bitpos: [31:0]; default: 0; + * read for BLOCK3 + */ +#define EFUSE_RD_BLK3_RESERVED_6 0xFFFFFFFFU +#define EFUSE_RD_BLK3_RESERVED_6_M (EFUSE_RD_BLK3_RESERVED_6_V << EFUSE_RD_BLK3_RESERVED_6_S) +#define EFUSE_RD_BLK3_RESERVED_6_V 0xFFFFFFFFU +#define EFUSE_RD_BLK3_RESERVED_6_S 0 + +/** EFUSE_BLK3_RDATA7_REG register */ +#define EFUSE_BLK3_RDATA7_REG (DR_REG_EFUSE_BASE + 0x94) +/** EFUSE_RD_BLK3_RESERVED_7 : R; bitpos: [31:0]; default: 0; + * read for BLOCK3 + */ +#define EFUSE_RD_BLK3_RESERVED_7 0xFFFFFFFFU +#define EFUSE_RD_BLK3_RESERVED_7_M (EFUSE_RD_BLK3_RESERVED_7_V << EFUSE_RD_BLK3_RESERVED_7_S) +#define EFUSE_RD_BLK3_RESERVED_7_V 0xFFFFFFFFU +#define EFUSE_RD_BLK3_RESERVED_7_S 0 + +/** EFUSE_BLK1_WDATA0_REG register */ +#define EFUSE_BLK1_WDATA0_REG (DR_REG_EFUSE_BASE + 0x98) +/** EFUSE_BLK1_DIN0 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK1 + */ +#define EFUSE_BLK1_DIN0 0xFFFFFFFFU +#define EFUSE_BLK1_DIN0_M (EFUSE_BLK1_DIN0_V << EFUSE_BLK1_DIN0_S) +#define EFUSE_BLK1_DIN0_V 0xFFFFFFFFU #define EFUSE_BLK1_DIN0_S 0 -#define EFUSE_BLK1_WDATA1_REG (DR_REG_EFUSE_BASE + 0x09c) -/* EFUSE_BLK1_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK1*/ -#define EFUSE_BLK1_DIN1 0xFFFFFFFF -#define EFUSE_BLK1_DIN1_M ((EFUSE_BLK1_DIN1_V)<<(EFUSE_BLK1_DIN1_S)) -#define EFUSE_BLK1_DIN1_V 0xFFFFFFFF +/** EFUSE_BLK1_WDATA1_REG register */ +#define EFUSE_BLK1_WDATA1_REG (DR_REG_EFUSE_BASE + 0x9c) +/** EFUSE_BLK1_DIN1 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK1 + */ +#define EFUSE_BLK1_DIN1 0xFFFFFFFFU +#define EFUSE_BLK1_DIN1_M (EFUSE_BLK1_DIN1_V << EFUSE_BLK1_DIN1_S) +#define EFUSE_BLK1_DIN1_V 0xFFFFFFFFU #define EFUSE_BLK1_DIN1_S 0 -#define EFUSE_BLK1_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0a0) -/* EFUSE_BLK1_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK1*/ -#define EFUSE_BLK1_DIN2 0xFFFFFFFF -#define EFUSE_BLK1_DIN2_M ((EFUSE_BLK1_DIN2_V)<<(EFUSE_BLK1_DIN2_S)) -#define EFUSE_BLK1_DIN2_V 0xFFFFFFFF +/** EFUSE_BLK1_WDATA2_REG register */ +#define EFUSE_BLK1_WDATA2_REG (DR_REG_EFUSE_BASE + 0xa0) +/** EFUSE_BLK1_DIN2 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK1 + */ +#define EFUSE_BLK1_DIN2 0xFFFFFFFFU +#define EFUSE_BLK1_DIN2_M (EFUSE_BLK1_DIN2_V << EFUSE_BLK1_DIN2_S) +#define EFUSE_BLK1_DIN2_V 0xFFFFFFFFU #define EFUSE_BLK1_DIN2_S 0 -#define EFUSE_BLK1_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0a4) -/* EFUSE_BLK1_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK1*/ -#define EFUSE_BLK1_DIN3 0xFFFFFFFF -#define EFUSE_BLK1_DIN3_M ((EFUSE_BLK1_DIN3_V)<<(EFUSE_BLK1_DIN3_S)) -#define EFUSE_BLK1_DIN3_V 0xFFFFFFFF +/** EFUSE_BLK1_WDATA3_REG register */ +#define EFUSE_BLK1_WDATA3_REG (DR_REG_EFUSE_BASE + 0xa4) +/** EFUSE_BLK1_DIN3 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK1 + */ +#define EFUSE_BLK1_DIN3 0xFFFFFFFFU +#define EFUSE_BLK1_DIN3_M (EFUSE_BLK1_DIN3_V << EFUSE_BLK1_DIN3_S) +#define EFUSE_BLK1_DIN3_V 0xFFFFFFFFU #define EFUSE_BLK1_DIN3_S 0 -#define EFUSE_BLK1_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0a8) -/* EFUSE_BLK1_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK1*/ -#define EFUSE_BLK1_DIN4 0xFFFFFFFF -#define EFUSE_BLK1_DIN4_M ((EFUSE_BLK1_DIN4_V)<<(EFUSE_BLK1_DIN4_S)) -#define EFUSE_BLK1_DIN4_V 0xFFFFFFFF +/** EFUSE_BLK1_WDATA4_REG register */ +#define EFUSE_BLK1_WDATA4_REG (DR_REG_EFUSE_BASE + 0xa8) +/** EFUSE_BLK1_DIN4 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK1 + */ +#define EFUSE_BLK1_DIN4 0xFFFFFFFFU +#define EFUSE_BLK1_DIN4_M (EFUSE_BLK1_DIN4_V << EFUSE_BLK1_DIN4_S) +#define EFUSE_BLK1_DIN4_V 0xFFFFFFFFU #define EFUSE_BLK1_DIN4_S 0 -#define EFUSE_BLK1_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0ac) -/* EFUSE_BLK1_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK1*/ -#define EFUSE_BLK1_DIN5 0xFFFFFFFF -#define EFUSE_BLK1_DIN5_M ((EFUSE_BLK1_DIN5_V)<<(EFUSE_BLK1_DIN5_S)) -#define EFUSE_BLK1_DIN5_V 0xFFFFFFFF +/** EFUSE_BLK1_WDATA5_REG register */ +#define EFUSE_BLK1_WDATA5_REG (DR_REG_EFUSE_BASE + 0xac) +/** EFUSE_BLK1_DIN5 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK1 + */ +#define EFUSE_BLK1_DIN5 0xFFFFFFFFU +#define EFUSE_BLK1_DIN5_M (EFUSE_BLK1_DIN5_V << EFUSE_BLK1_DIN5_S) +#define EFUSE_BLK1_DIN5_V 0xFFFFFFFFU #define EFUSE_BLK1_DIN5_S 0 -#define EFUSE_BLK1_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0b0) -/* EFUSE_BLK1_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK1*/ -#define EFUSE_BLK1_DIN6 0xFFFFFFFF -#define EFUSE_BLK1_DIN6_M ((EFUSE_BLK1_DIN6_V)<<(EFUSE_BLK1_DIN6_S)) -#define EFUSE_BLK1_DIN6_V 0xFFFFFFFF +/** EFUSE_BLK1_WDATA6_REG register */ +#define EFUSE_BLK1_WDATA6_REG (DR_REG_EFUSE_BASE + 0xb0) +/** EFUSE_BLK1_DIN6 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK1 + */ +#define EFUSE_BLK1_DIN6 0xFFFFFFFFU +#define EFUSE_BLK1_DIN6_M (EFUSE_BLK1_DIN6_V << EFUSE_BLK1_DIN6_S) +#define EFUSE_BLK1_DIN6_V 0xFFFFFFFFU #define EFUSE_BLK1_DIN6_S 0 -#define EFUSE_BLK1_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0b4) -/* EFUSE_BLK1_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK1*/ -#define EFUSE_BLK1_DIN7 0xFFFFFFFF -#define EFUSE_BLK1_DIN7_M ((EFUSE_BLK1_DIN7_V)<<(EFUSE_BLK1_DIN7_S)) -#define EFUSE_BLK1_DIN7_V 0xFFFFFFFF +/** EFUSE_BLK1_WDATA7_REG register */ +#define EFUSE_BLK1_WDATA7_REG (DR_REG_EFUSE_BASE + 0xb4) +/** EFUSE_BLK1_DIN7 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK1 + */ +#define EFUSE_BLK1_DIN7 0xFFFFFFFFU +#define EFUSE_BLK1_DIN7_M (EFUSE_BLK1_DIN7_V << EFUSE_BLK1_DIN7_S) +#define EFUSE_BLK1_DIN7_V 0xFFFFFFFFU #define EFUSE_BLK1_DIN7_S 0 -#define EFUSE_BLK2_WDATA0_REG (DR_REG_EFUSE_BASE + 0x0b8) -/* EFUSE_BLK2_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK2*/ -#define EFUSE_BLK2_DIN0 0xFFFFFFFF -#define EFUSE_BLK2_DIN0_M ((EFUSE_BLK2_DIN0_V)<<(EFUSE_BLK2_DIN0_S)) -#define EFUSE_BLK2_DIN0_V 0xFFFFFFFF +/** EFUSE_BLK2_WDATA0_REG register */ +#define EFUSE_BLK2_WDATA0_REG (DR_REG_EFUSE_BASE + 0xb8) +/** EFUSE_BLK2_DIN0 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK2 + */ +#define EFUSE_BLK2_DIN0 0xFFFFFFFFU +#define EFUSE_BLK2_DIN0_M (EFUSE_BLK2_DIN0_V << EFUSE_BLK2_DIN0_S) +#define EFUSE_BLK2_DIN0_V 0xFFFFFFFFU #define EFUSE_BLK2_DIN0_S 0 -#define EFUSE_BLK2_WDATA1_REG (DR_REG_EFUSE_BASE + 0x0bc) -/* EFUSE_BLK2_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK2*/ -#define EFUSE_BLK2_DIN1 0xFFFFFFFF -#define EFUSE_BLK2_DIN1_M ((EFUSE_BLK2_DIN1_V)<<(EFUSE_BLK2_DIN1_S)) -#define EFUSE_BLK2_DIN1_V 0xFFFFFFFF +/** EFUSE_BLK2_WDATA1_REG register */ +#define EFUSE_BLK2_WDATA1_REG (DR_REG_EFUSE_BASE + 0xbc) +/** EFUSE_BLK2_DIN1 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK2 + */ +#define EFUSE_BLK2_DIN1 0xFFFFFFFFU +#define EFUSE_BLK2_DIN1_M (EFUSE_BLK2_DIN1_V << EFUSE_BLK2_DIN1_S) +#define EFUSE_BLK2_DIN1_V 0xFFFFFFFFU #define EFUSE_BLK2_DIN1_S 0 -#define EFUSE_BLK2_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0c0) -/* EFUSE_BLK2_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK2*/ -#define EFUSE_BLK2_DIN2 0xFFFFFFFF -#define EFUSE_BLK2_DIN2_M ((EFUSE_BLK2_DIN2_V)<<(EFUSE_BLK2_DIN2_S)) -#define EFUSE_BLK2_DIN2_V 0xFFFFFFFF +/** EFUSE_BLK2_WDATA2_REG register */ +#define EFUSE_BLK2_WDATA2_REG (DR_REG_EFUSE_BASE + 0xc0) +/** EFUSE_BLK2_DIN2 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK2 + */ +#define EFUSE_BLK2_DIN2 0xFFFFFFFFU +#define EFUSE_BLK2_DIN2_M (EFUSE_BLK2_DIN2_V << EFUSE_BLK2_DIN2_S) +#define EFUSE_BLK2_DIN2_V 0xFFFFFFFFU #define EFUSE_BLK2_DIN2_S 0 -#define EFUSE_BLK2_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0c4) -/* EFUSE_BLK2_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK2*/ -#define EFUSE_BLK2_DIN3 0xFFFFFFFF -#define EFUSE_BLK2_DIN3_M ((EFUSE_BLK2_DIN3_V)<<(EFUSE_BLK2_DIN3_S)) -#define EFUSE_BLK2_DIN3_V 0xFFFFFFFF +/** EFUSE_BLK2_WDATA3_REG register */ +#define EFUSE_BLK2_WDATA3_REG (DR_REG_EFUSE_BASE + 0xc4) +/** EFUSE_BLK2_DIN3 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK2 + */ +#define EFUSE_BLK2_DIN3 0xFFFFFFFFU +#define EFUSE_BLK2_DIN3_M (EFUSE_BLK2_DIN3_V << EFUSE_BLK2_DIN3_S) +#define EFUSE_BLK2_DIN3_V 0xFFFFFFFFU #define EFUSE_BLK2_DIN3_S 0 -#define EFUSE_BLK2_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0c8) -/* EFUSE_BLK2_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK2*/ -#define EFUSE_BLK2_DIN4 0xFFFFFFFF -#define EFUSE_BLK2_DIN4_M ((EFUSE_BLK2_DIN4_V)<<(EFUSE_BLK2_DIN4_S)) -#define EFUSE_BLK2_DIN4_V 0xFFFFFFFF +/** EFUSE_BLK2_WDATA4_REG register */ +#define EFUSE_BLK2_WDATA4_REG (DR_REG_EFUSE_BASE + 0xc8) +/** EFUSE_BLK2_DIN4 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK2 + */ +#define EFUSE_BLK2_DIN4 0xFFFFFFFFU +#define EFUSE_BLK2_DIN4_M (EFUSE_BLK2_DIN4_V << EFUSE_BLK2_DIN4_S) +#define EFUSE_BLK2_DIN4_V 0xFFFFFFFFU #define EFUSE_BLK2_DIN4_S 0 -#define EFUSE_BLK2_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0cc) -/* EFUSE_BLK2_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK2*/ -#define EFUSE_BLK2_DIN5 0xFFFFFFFF -#define EFUSE_BLK2_DIN5_M ((EFUSE_BLK2_DIN5_V)<<(EFUSE_BLK2_DIN5_S)) -#define EFUSE_BLK2_DIN5_V 0xFFFFFFFF +/** EFUSE_BLK2_WDATA5_REG register */ +#define EFUSE_BLK2_WDATA5_REG (DR_REG_EFUSE_BASE + 0xcc) +/** EFUSE_BLK2_DIN5 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK2 + */ +#define EFUSE_BLK2_DIN5 0xFFFFFFFFU +#define EFUSE_BLK2_DIN5_M (EFUSE_BLK2_DIN5_V << EFUSE_BLK2_DIN5_S) +#define EFUSE_BLK2_DIN5_V 0xFFFFFFFFU #define EFUSE_BLK2_DIN5_S 0 -#define EFUSE_BLK2_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0d0) -/* EFUSE_BLK2_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK2*/ -#define EFUSE_BLK2_DIN6 0xFFFFFFFF -#define EFUSE_BLK2_DIN6_M ((EFUSE_BLK2_DIN6_V)<<(EFUSE_BLK2_DIN6_S)) -#define EFUSE_BLK2_DIN6_V 0xFFFFFFFF +/** EFUSE_BLK2_WDATA6_REG register */ +#define EFUSE_BLK2_WDATA6_REG (DR_REG_EFUSE_BASE + 0xd0) +/** EFUSE_BLK2_DIN6 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK2 + */ +#define EFUSE_BLK2_DIN6 0xFFFFFFFFU +#define EFUSE_BLK2_DIN6_M (EFUSE_BLK2_DIN6_V << EFUSE_BLK2_DIN6_S) +#define EFUSE_BLK2_DIN6_V 0xFFFFFFFFU #define EFUSE_BLK2_DIN6_S 0 -#define EFUSE_BLK2_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0d4) -/* EFUSE_BLK2_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK2*/ -#define EFUSE_BLK2_DIN7 0xFFFFFFFF -#define EFUSE_BLK2_DIN7_M ((EFUSE_BLK2_DIN7_V)<<(EFUSE_BLK2_DIN7_S)) -#define EFUSE_BLK2_DIN7_V 0xFFFFFFFF +/** EFUSE_BLK2_WDATA7_REG register */ +#define EFUSE_BLK2_WDATA7_REG (DR_REG_EFUSE_BASE + 0xd4) +/** EFUSE_BLK2_DIN7 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK2 + */ +#define EFUSE_BLK2_DIN7 0xFFFFFFFFU +#define EFUSE_BLK2_DIN7_M (EFUSE_BLK2_DIN7_V << EFUSE_BLK2_DIN7_S) +#define EFUSE_BLK2_DIN7_V 0xFFFFFFFFU #define EFUSE_BLK2_DIN7_S 0 -#define EFUSE_BLK3_WDATA0_REG (DR_REG_EFUSE_BASE + 0x0d8) -/* EFUSE_BLK3_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK3*/ -#define EFUSE_BLK3_DIN0 0xFFFFFFFF -#define EFUSE_BLK3_DIN0_M ((EFUSE_BLK3_DIN0_V)<<(EFUSE_BLK3_DIN0_S)) -#define EFUSE_BLK3_DIN0_V 0xFFFFFFFF +/** EFUSE_BLK3_WDATA0_REG register */ +#define EFUSE_BLK3_WDATA0_REG (DR_REG_EFUSE_BASE + 0xd8) +/** EFUSE_BLK3_DIN0 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK3 + */ +#define EFUSE_BLK3_DIN0 0xFFFFFFFFU +#define EFUSE_BLK3_DIN0_M (EFUSE_BLK3_DIN0_V << EFUSE_BLK3_DIN0_S) +#define EFUSE_BLK3_DIN0_V 0xFFFFFFFFU #define EFUSE_BLK3_DIN0_S 0 -#define EFUSE_BLK3_WDATA1_REG (DR_REG_EFUSE_BASE + 0x0dc) -/* EFUSE_BLK3_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK3*/ -#define EFUSE_BLK3_DIN1 0xFFFFFFFF -#define EFUSE_BLK3_DIN1_M ((EFUSE_BLK3_DIN1_V)<<(EFUSE_BLK3_DIN1_S)) -#define EFUSE_BLK3_DIN1_V 0xFFFFFFFF +/** EFUSE_BLK3_WDATA1_REG register */ +#define EFUSE_BLK3_WDATA1_REG (DR_REG_EFUSE_BASE + 0xdc) +/** EFUSE_BLK3_DIN1 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK3 + */ +#define EFUSE_BLK3_DIN1 0xFFFFFFFFU +#define EFUSE_BLK3_DIN1_M (EFUSE_BLK3_DIN1_V << EFUSE_BLK3_DIN1_S) +#define EFUSE_BLK3_DIN1_V 0xFFFFFFFFU #define EFUSE_BLK3_DIN1_S 0 -#define EFUSE_BLK3_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0e0) -/* EFUSE_BLK3_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK3*/ -#define EFUSE_BLK3_DIN2 0xFFFFFFFF -#define EFUSE_BLK3_DIN2_M ((EFUSE_BLK3_DIN2_V)<<(EFUSE_BLK3_DIN2_S)) -#define EFUSE_BLK3_DIN2_V 0xFFFFFFFF +/** EFUSE_BLK3_WDATA2_REG register */ +#define EFUSE_BLK3_WDATA2_REG (DR_REG_EFUSE_BASE + 0xe0) +/** EFUSE_BLK3_DIN2 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK3 + */ +#define EFUSE_BLK3_DIN2 0xFFFFFFFFU +#define EFUSE_BLK3_DIN2_M (EFUSE_BLK3_DIN2_V << EFUSE_BLK3_DIN2_S) +#define EFUSE_BLK3_DIN2_V 0xFFFFFFFFU #define EFUSE_BLK3_DIN2_S 0 -/* Note: Newer ESP32s utilize BLK3_DATA3 and parts of BLK3_DATA4 for calibration - * purposes. This usage is indicated by the EFUSE_RD_BLK3_PART_RESERVE bit.*/ -#define EFUSE_BLK3_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0e4) -/* EFUSE_BLK3_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK3*/ -#define EFUSE_BLK3_DIN3 0xFFFFFFFF -#define EFUSE_BLK3_DIN3_M ((EFUSE_BLK3_DIN3_V)<<(EFUSE_BLK3_DIN3_S)) -#define EFUSE_BLK3_DIN3_V 0xFFFFFFFF -#define EFUSE_BLK3_DIN3_S 0 -/* EFUSE_ADC2_TP_HIGH : R/W ;bitpos:[31:23] ;default: 9'b0 ; */ -/*description: ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ -#define EFUSE_ADC2_TP_HIGH 0x1FF -#define EFUSE_ADC2_TP_HIGH_M ((EFUSE_ADC2_TP_HIGH_V)<<(EFUSE_ADC2_TP_HIGH_S)) -#define EFUSE_ADC2_TP_HIGH_V 0x1FF -#define EFUSE_ADC2_TP_HIGH_S 23 -/* EFUSE_ADC2_TP_LOW : R/W ;bitpos:[22:16] ;default: 7'b0 ; */ -/*description: ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ -#define EFUSE_ADC2_TP_LOW 0x7F -#define EFUSE_ADC2_TP_LOW_M ((EFUSE_ADC2_TP_LOW_V)<<(EFUSE_ADC2_TP_LOW_S)) -#define EFUSE_ADC2_TP_LOW_V 0x7F -#define EFUSE_ADC2_TP_LOW_S 16 -/* EFUSE_ADC1_TP_HIGH : R/W ;bitpos:[15:7] ;default: 9'b0 ; */ -/*description: ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ -#define EFUSE_ADC1_TP_HIGH 0x1FF -#define EFUSE_ADC1_TP_HIGH_M ((EFUSE_ADC1_TP_HIGH_V)<<(EFUSE_ADC1_TP_HIGH_S)) -#define EFUSE_ADC1_TP_HIGH_V 0x1FF -#define EFUSE_ADC1_TP_HIGH_S 7 -/* EFUSE_ADC1_TP_LOW : R/W ;bitpos:[6:0] ;default: 7'b0 ; */ -/*description: ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ -#define EFUSE_ADC1_TP_LOW 0x7F -#define EFUSE_ADC1_TP_LOW_M ((EFUSE_ADC1_TP_LOW_V)<<(EFUSE_ADC1_TP_LOW_S)) -#define EFUSE_ADC1_TP_LOW_V 0x7F +/** EFUSE_BLK3_WDATA3_REG register */ +#define EFUSE_BLK3_WDATA3_REG (DR_REG_EFUSE_BASE + 0xe4) +/** EFUSE_ADC1_TP_LOW : RW; bitpos: [6:0]; default: 0; + * ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + */ +#define EFUSE_ADC1_TP_LOW 0x0000007FU +#define EFUSE_ADC1_TP_LOW_M (EFUSE_ADC1_TP_LOW_V << EFUSE_ADC1_TP_LOW_S) +#define EFUSE_ADC1_TP_LOW_V 0x0000007FU #define EFUSE_ADC1_TP_LOW_S 0 +/** EFUSE_ADC1_TP_HIGH : RW; bitpos: [15:7]; default: 0; + * ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + */ +#define EFUSE_ADC1_TP_HIGH 0x000001FFU +#define EFUSE_ADC1_TP_HIGH_M (EFUSE_ADC1_TP_HIGH_V << EFUSE_ADC1_TP_HIGH_S) +#define EFUSE_ADC1_TP_HIGH_V 0x000001FFU +#define EFUSE_ADC1_TP_HIGH_S 7 +/** EFUSE_ADC2_TP_LOW : RW; bitpos: [22:16]; default: 0; + * ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + */ +#define EFUSE_ADC2_TP_LOW 0x0000007FU +#define EFUSE_ADC2_TP_LOW_M (EFUSE_ADC2_TP_LOW_V << EFUSE_ADC2_TP_LOW_S) +#define EFUSE_ADC2_TP_LOW_V 0x0000007FU +#define EFUSE_ADC2_TP_LOW_S 16 +/** EFUSE_ADC2_TP_HIGH : RW; bitpos: [31:23]; default: 0; + * ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + */ +#define EFUSE_ADC2_TP_HIGH 0x000001FFU +#define EFUSE_ADC2_TP_HIGH_M (EFUSE_ADC2_TP_HIGH_V << EFUSE_ADC2_TP_HIGH_S) +#define EFUSE_ADC2_TP_HIGH_V 0x000001FFU +#define EFUSE_ADC2_TP_HIGH_S 23 -#define EFUSE_BLK3_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0e8) -/* EFUSE_BLK3_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK3*/ -#define EFUSE_BLK3_DIN4 0xFFFFFFFF -#define EFUSE_BLK3_DIN4_M ((EFUSE_BLK3_DIN4_V)<<(EFUSE_BLK3_DIN4_S)) -#define EFUSE_BLK3_DIN4_V 0xFFFFFFFF -#define EFUSE_BLK3_DIN4_S 0 -/* EFUSE_CAL_RESERVED: R/W ; bitpos:[0:15] ; default : 16'h0 ; */ -/*description: Reserved for future calibration use. Indicated by EFUSE_BLK3_PART_RESERVE */ -#define EFUSE_CAL_RESERVED 0x0000FFFF -#define EFUSE_CAL_RESERVED_M ((EFUSE_CAL_RESERVED_V)<<(EFUSE_CAL_RESERVED_S)) -#define EFUSE_CAL_RESERVED_V 0xFFFF -#define EFUSE_CAL_RESERVED_S 0 - -#define EFUSE_BLK3_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0ec) -/* EFUSE_BLK3_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK3*/ -#define EFUSE_BLK3_DIN5 0xFFFFFFFF -#define EFUSE_BLK3_DIN5_M ((EFUSE_BLK3_DIN5_V)<<(EFUSE_BLK3_DIN5_S)) -#define EFUSE_BLK3_DIN5_V 0xFFFFFFFF +/** EFUSE_BLK3_WDATA4_REG register */ +#define EFUSE_BLK3_WDATA4_REG (DR_REG_EFUSE_BASE + 0xe8) +/** EFUSE_SECURE_VERSION : R; bitpos: [31:0]; default: 0; + * Secure version for anti-rollback + */ +#define EFUSE_SECURE_VERSION 0xFFFFFFFFU +#define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) +#define EFUSE_SECURE_VERSION_V 0xFFFFFFFFU +#define EFUSE_SECURE_VERSION_S 0 + +/** EFUSE_BLK3_WDATA5_REG register */ +#define EFUSE_BLK3_WDATA5_REG (DR_REG_EFUSE_BASE + 0xec) +/** EFUSE_BLK3_DIN5 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK3 + */ +#define EFUSE_BLK3_DIN5 0xFFFFFFFFU +#define EFUSE_BLK3_DIN5_M (EFUSE_BLK3_DIN5_V << EFUSE_BLK3_DIN5_S) +#define EFUSE_BLK3_DIN5_V 0xFFFFFFFFU #define EFUSE_BLK3_DIN5_S 0 -#define EFUSE_BLK3_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0f0) -/* EFUSE_BLK3_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK3*/ -#define EFUSE_BLK3_DIN6 0xFFFFFFFF -#define EFUSE_BLK3_DIN6_M ((EFUSE_BLK3_DIN6_V)<<(EFUSE_BLK3_DIN6_S)) -#define EFUSE_BLK3_DIN6_V 0xFFFFFFFF +/** EFUSE_BLK3_WDATA6_REG register */ +#define EFUSE_BLK3_WDATA6_REG (DR_REG_EFUSE_BASE + 0xf0) +/** EFUSE_BLK3_DIN6 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK3 + */ +#define EFUSE_BLK3_DIN6 0xFFFFFFFFU +#define EFUSE_BLK3_DIN6_M (EFUSE_BLK3_DIN6_V << EFUSE_BLK3_DIN6_S) +#define EFUSE_BLK3_DIN6_V 0xFFFFFFFFU #define EFUSE_BLK3_DIN6_S 0 -#define EFUSE_BLK3_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0f4) -/* EFUSE_BLK3_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK3*/ -#define EFUSE_BLK3_DIN7 0xFFFFFFFF -#define EFUSE_BLK3_DIN7_M ((EFUSE_BLK3_DIN7_V)<<(EFUSE_BLK3_DIN7_S)) -#define EFUSE_BLK3_DIN7_V 0xFFFFFFFF +/** EFUSE_BLK3_WDATA7_REG register */ +#define EFUSE_BLK3_WDATA7_REG (DR_REG_EFUSE_BASE + 0xf4) +/** EFUSE_BLK3_DIN7 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK3 + */ +#define EFUSE_BLK3_DIN7 0xFFFFFFFFU +#define EFUSE_BLK3_DIN7_M (EFUSE_BLK3_DIN7_V << EFUSE_BLK3_DIN7_S) +#define EFUSE_BLK3_DIN7_V 0xFFFFFFFFU #define EFUSE_BLK3_DIN7_S 0 -#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x0f8) -/* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_CLK_EN (BIT(16)) -#define EFUSE_CLK_EN_M (BIT(16)) -#define EFUSE_CLK_EN_V 0x1 -#define EFUSE_CLK_EN_S 16 -/* EFUSE_CLK_SEL1 : R/W ;bitpos:[15:8] ;default: 8'h40 ; */ -/*description: efuse timing configure*/ -#define EFUSE_CLK_SEL1 0x000000FF -#define EFUSE_CLK_SEL1_M ((EFUSE_CLK_SEL1_V)<<(EFUSE_CLK_SEL1_S)) -#define EFUSE_CLK_SEL1_V 0xFF -#define EFUSE_CLK_SEL1_S 8 -/* EFUSE_CLK_SEL0 : R/W ;bitpos:[7:0] ;default: 8'h52 ; */ -/*description: efuse timing configure*/ -#define EFUSE_CLK_SEL0 0x000000FF -#define EFUSE_CLK_SEL0_M ((EFUSE_CLK_SEL0_V)<<(EFUSE_CLK_SEL0_S)) -#define EFUSE_CLK_SEL0_V 0xFF +/** EFUSE_CLK_REG register */ +#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0xf8) +/** EFUSE_CLK_SEL0 : RW; bitpos: [7:0]; default: 82; + * efuse timing configure + */ +#define EFUSE_CLK_SEL0 0x000000FFU +#define EFUSE_CLK_SEL0_M (EFUSE_CLK_SEL0_V << EFUSE_CLK_SEL0_S) +#define EFUSE_CLK_SEL0_V 0x000000FFU #define EFUSE_CLK_SEL0_S 0 +/** EFUSE_CLK_SEL1 : RW; bitpos: [15:8]; default: 64; + * efuse timing configure + */ +#define EFUSE_CLK_SEL1 0x000000FFU +#define EFUSE_CLK_SEL1_M (EFUSE_CLK_SEL1_V << EFUSE_CLK_SEL1_S) +#define EFUSE_CLK_SEL1_V 0x000000FFU +#define EFUSE_CLK_SEL1_S 8 +/** EFUSE_CLK_EN : RW; bitpos: [16]; default: 0; */ +#define EFUSE_CLK_EN (BIT(16)) +#define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) +#define EFUSE_CLK_EN_V 0x00000001U +#define EFUSE_CLK_EN_S 16 -#define EFUSE_WRITE_OP_CODE 0x5a5a -#define EFUSE_READ_OP_CODE 0x5aa5 - -#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x0fc) -/* EFUSE_FORCE_NO_WR_RD_DIS : R/W ;bitpos:[16] ;default: 1'h1 ; */ -/*description: */ -#define EFUSE_FORCE_NO_WR_RD_DIS (BIT(16)) -#define EFUSE_FORCE_NO_WR_RD_DIS_M (BIT(16)) -#define EFUSE_FORCE_NO_WR_RD_DIS_V 0x1 -#define EFUSE_FORCE_NO_WR_RD_DIS_S 16 -/* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: efuse operation code*/ -#define EFUSE_OP_CODE 0x0000FFFF -#define EFUSE_OP_CODE_M ((EFUSE_OP_CODE_V)<<(EFUSE_OP_CODE_S)) -#define EFUSE_OP_CODE_V 0xFFFF +/** EFUSE_CONF_REG register */ +#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0xfc) +/** EFUSE_OP_CODE : RW; bitpos: [15:0]; default: 0; + * efuse operation code + */ +#define EFUSE_OP_CODE 0x0000FFFFU +#define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) +#define EFUSE_OP_CODE_V 0x0000FFFFU #define EFUSE_OP_CODE_S 0 +/** EFUSE_FORCE_NO_WR_RD_DIS : RW; bitpos: [16]; default: 1; */ +#define EFUSE_FORCE_NO_WR_RD_DIS (BIT(16)) +#define EFUSE_FORCE_NO_WR_RD_DIS_M (EFUSE_FORCE_NO_WR_RD_DIS_V << EFUSE_FORCE_NO_WR_RD_DIS_S) +#define EFUSE_FORCE_NO_WR_RD_DIS_V 0x00000001U +#define EFUSE_FORCE_NO_WR_RD_DIS_S 16 -#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x100) -/* EFUSE_DEBUG : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define EFUSE_DEBUG 0xFFFFFFFF -#define EFUSE_DEBUG_M ((EFUSE_DEBUG_V)<<(EFUSE_DEBUG_S)) -#define EFUSE_DEBUG_V 0xFFFFFFFF +/** EFUSE_STATUS_REG register */ +#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x100) +/** EFUSE_DEBUG : R; bitpos: [31:0]; default: 0; */ +#define EFUSE_DEBUG 0xFFFFFFFFU +#define EFUSE_DEBUG_M (EFUSE_DEBUG_V << EFUSE_DEBUG_S) +#define EFUSE_DEBUG_V 0xFFFFFFFFU #define EFUSE_DEBUG_S 0 -#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x104) -/* EFUSE_PGM_CMD : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: command for program*/ -#define EFUSE_PGM_CMD (BIT(1)) -#define EFUSE_PGM_CMD_M (BIT(1)) -#define EFUSE_PGM_CMD_V 0x1 -#define EFUSE_PGM_CMD_S 1 -/* EFUSE_READ_CMD : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: command for read*/ -#define EFUSE_READ_CMD (BIT(0)) -#define EFUSE_READ_CMD_M (BIT(0)) -#define EFUSE_READ_CMD_V 0x1 +/** EFUSE_CMD_REG register */ +#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x104) +/** EFUSE_READ_CMD : RW; bitpos: [0]; default: 0; + * command for read + */ +#define EFUSE_READ_CMD (BIT(0)) +#define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) +#define EFUSE_READ_CMD_V 0x00000001U #define EFUSE_READ_CMD_S 0 +/** EFUSE_PGM_CMD : RW; bitpos: [1]; default: 0; + * command for program + */ +#define EFUSE_PGM_CMD (BIT(1)) +#define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) +#define EFUSE_PGM_CMD_V 0x00000001U +#define EFUSE_PGM_CMD_S 1 -#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x108) -/* EFUSE_PGM_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: program done interrupt raw status*/ -#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) -#define EFUSE_PGM_DONE_INT_RAW_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_RAW_V 0x1 -#define EFUSE_PGM_DONE_INT_RAW_S 1 -/* EFUSE_READ_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: read done interrupt raw status*/ -#define EFUSE_READ_DONE_INT_RAW (BIT(0)) -#define EFUSE_READ_DONE_INT_RAW_M (BIT(0)) -#define EFUSE_READ_DONE_INT_RAW_V 0x1 +/** EFUSE_INT_RAW_REG register */ +#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x108) +/** EFUSE_READ_DONE_INT_RAW : R; bitpos: [0]; default: 0; + * read done interrupt raw status + */ +#define EFUSE_READ_DONE_INT_RAW (BIT(0)) +#define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) +#define EFUSE_READ_DONE_INT_RAW_V 0x00000001U #define EFUSE_READ_DONE_INT_RAW_S 0 +/** EFUSE_PGM_DONE_INT_RAW : R; bitpos: [1]; default: 0; + * program done interrupt raw status + */ +#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) +#define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) +#define EFUSE_PGM_DONE_INT_RAW_V 0x00000001U +#define EFUSE_PGM_DONE_INT_RAW_S 1 -#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x10c) -/* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: program done interrupt status*/ -#define EFUSE_PGM_DONE_INT_ST (BIT(1)) -#define EFUSE_PGM_DONE_INT_ST_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_ST_V 0x1 -#define EFUSE_PGM_DONE_INT_ST_S 1 -/* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: read done interrupt status*/ -#define EFUSE_READ_DONE_INT_ST (BIT(0)) -#define EFUSE_READ_DONE_INT_ST_M (BIT(0)) -#define EFUSE_READ_DONE_INT_ST_V 0x1 +/** EFUSE_INT_ST_REG register */ +#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x10c) +/** EFUSE_READ_DONE_INT_ST : R; bitpos: [0]; default: 0; + * read done interrupt status + */ +#define EFUSE_READ_DONE_INT_ST (BIT(0)) +#define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) +#define EFUSE_READ_DONE_INT_ST_V 0x00000001U #define EFUSE_READ_DONE_INT_ST_S 0 +/** EFUSE_PGM_DONE_INT_ST : R; bitpos: [1]; default: 0; + * program done interrupt status + */ +#define EFUSE_PGM_DONE_INT_ST (BIT(1)) +#define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) +#define EFUSE_PGM_DONE_INT_ST_V 0x00000001U +#define EFUSE_PGM_DONE_INT_ST_S 1 -#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x110) -/* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: program done interrupt enable*/ -#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) -#define EFUSE_PGM_DONE_INT_ENA_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_ENA_V 0x1 -#define EFUSE_PGM_DONE_INT_ENA_S 1 -/* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: read done interrupt enable*/ -#define EFUSE_READ_DONE_INT_ENA (BIT(0)) -#define EFUSE_READ_DONE_INT_ENA_M (BIT(0)) -#define EFUSE_READ_DONE_INT_ENA_V 0x1 +/** EFUSE_INT_ENA_REG register */ +#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x110) +/** EFUSE_READ_DONE_INT_ENA : RW; bitpos: [0]; default: 0; + * read done interrupt enable + */ +#define EFUSE_READ_DONE_INT_ENA (BIT(0)) +#define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) +#define EFUSE_READ_DONE_INT_ENA_V 0x00000001U #define EFUSE_READ_DONE_INT_ENA_S 0 +/** EFUSE_PGM_DONE_INT_ENA : RW; bitpos: [1]; default: 0; + * program done interrupt enable + */ +#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) +#define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) +#define EFUSE_PGM_DONE_INT_ENA_V 0x00000001U +#define EFUSE_PGM_DONE_INT_ENA_S 1 -#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x114) -/* EFUSE_PGM_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: program done interrupt clear*/ -#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) -#define EFUSE_PGM_DONE_INT_CLR_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_CLR_V 0x1 -#define EFUSE_PGM_DONE_INT_CLR_S 1 -/* EFUSE_READ_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: read done interrupt clear*/ -#define EFUSE_READ_DONE_INT_CLR (BIT(0)) -#define EFUSE_READ_DONE_INT_CLR_M (BIT(0)) -#define EFUSE_READ_DONE_INT_CLR_V 0x1 +/** EFUSE_INT_CLR_REG register */ +#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x114) +/** EFUSE_READ_DONE_INT_CLR : W; bitpos: [0]; default: 0; + * read done interrupt clear + */ +#define EFUSE_READ_DONE_INT_CLR (BIT(0)) +#define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) +#define EFUSE_READ_DONE_INT_CLR_V 0x00000001U #define EFUSE_READ_DONE_INT_CLR_S 0 +/** EFUSE_PGM_DONE_INT_CLR : W; bitpos: [1]; default: 0; + * program done interrupt clear + */ +#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) +#define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) +#define EFUSE_PGM_DONE_INT_CLR_V 0x00000001U +#define EFUSE_PGM_DONE_INT_CLR_S 1 -#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x118) -/* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) -#define EFUSE_DAC_CLK_PAD_SEL_M (BIT(8)) -#define EFUSE_DAC_CLK_PAD_SEL_V 0x1 -#define EFUSE_DAC_CLK_PAD_SEL_S 8 -/* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd40 ; */ -/*description: efuse timing configure*/ -#define EFUSE_DAC_CLK_DIV 0x000000FF -#define EFUSE_DAC_CLK_DIV_M ((EFUSE_DAC_CLK_DIV_V)<<(EFUSE_DAC_CLK_DIV_S)) -#define EFUSE_DAC_CLK_DIV_V 0xFF +/** EFUSE_DAC_CONF_REG register */ +#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x118) +/** EFUSE_DAC_CLK_DIV : RW; bitpos: [7:0]; default: 40; + * efuse timing configure + */ +#define EFUSE_DAC_CLK_DIV 0x000000FFU +#define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) +#define EFUSE_DAC_CLK_DIV_V 0x000000FFU #define EFUSE_DAC_CLK_DIV_S 0 +/** EFUSE_DAC_CLK_PAD_SEL : RW; bitpos: [8]; default: 0; */ +#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) +#define EFUSE_DAC_CLK_PAD_SEL_M (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S) +#define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001U +#define EFUSE_DAC_CLK_PAD_SEL_S 8 -#define EFUSE_DEC_STATUS_REG (DR_REG_EFUSE_BASE + 0x11c) -/* EFUSE_DEC_WARNINGS : RO ;bitpos:[11:0] ;default: 12'b0 ; */ -/*description: the decode result of 3/4 coding scheme has warning*/ -#define EFUSE_DEC_WARNINGS 0x00000FFF -#define EFUSE_DEC_WARNINGS_M ((EFUSE_DEC_WARNINGS_V)<<(EFUSE_DEC_WARNINGS_S)) -#define EFUSE_DEC_WARNINGS_V 0xFFF +/** EFUSE_DEC_STATUS_REG register */ +#define EFUSE_DEC_STATUS_REG (DR_REG_EFUSE_BASE + 0x11c) +/** EFUSE_DEC_WARNINGS : R; bitpos: [11:0]; default: 0; + * the decode result of 3/4 coding scheme has warning + */ +#define EFUSE_DEC_WARNINGS 0x00000FFFU +#define EFUSE_DEC_WARNINGS_M (EFUSE_DEC_WARNINGS_V << EFUSE_DEC_WARNINGS_S) +#define EFUSE_DEC_WARNINGS_V 0x00000FFFU #define EFUSE_DEC_WARNINGS_S 0 -#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1FC) -/* EFUSE_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042600 ; */ -/*description: */ -#define EFUSE_DATE 0xFFFFFFFF -#define EFUSE_DATE_M ((EFUSE_DATE_V)<<(EFUSE_DATE_S)) -#define EFUSE_DATE_V 0xFFFFFFFF +/** EFUSE_DATE_REG register */ +#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) +/** EFUSE_DATE : RW; bitpos: [31:0]; default: 369370624; */ +#define EFUSE_DATE 0xFFFFFFFFU +#define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S) +#define EFUSE_DATE_V 0xFFFFFFFFU #define EFUSE_DATE_S 0 - - - -#endif /*_SOC_EFUSE_REG_H_ */ +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/soc/esp32/include/soc/efuse_struct.h b/tools/sdk/esp32/include/soc/esp32/include/soc/efuse_struct.h index 246572e40f3..f8d78500a3a 100644 --- a/tools/sdk/esp32/include/soc/esp32/include/soc/efuse_struct.h +++ b/tools/sdk/esp32/include/soc/esp32/include/soc/efuse_struct.h @@ -1,106 +1,1276 @@ -/* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ +#pragma once -#ifndef _SOC_EFUSE_STRUCT_H_ -#define _SOC_EFUSE_STRUCT_H_ #include - #ifdef __cplusplus extern "C" { #endif -typedef volatile struct efuse_dev_s { - uint32_t blk0_rdata0; - uint32_t blk0_rdata1; - uint32_t blk0_rdata2; - uint32_t blk0_rdata3; - uint32_t blk0_rdata4; - uint32_t blk0_rdata5; - uint32_t blk0_rdata6; - - uint32_t blk0_wdata0; - uint32_t blk0_wdata1; - uint32_t blk0_wdata2; - uint32_t blk0_wdata3; - uint32_t blk0_wdata4; - uint32_t blk0_wdata5; - uint32_t blk0_wdata6; - - uint32_t blk1_rdata0; - uint32_t blk1_rdata1; - uint32_t blk1_rdata2; - uint32_t blk1_rdata3; - uint32_t blk1_rdata4; - uint32_t blk1_rdata5; - uint32_t blk1_rdata6; - uint32_t blk1_rdata7; - - uint32_t blk2_rdata0; - uint32_t blk2_rdata1; - uint32_t blk2_rdata2; - uint32_t blk2_rdata3; - uint32_t blk2_rdata4; - uint32_t blk2_rdata5; - uint32_t blk2_rdata6; - uint32_t blk2_rdata7; - - uint32_t blk3_rdata0; - uint32_t blk3_rdata1; - uint32_t blk3_rdata2; - uint32_t blk3_rdata3; - uint32_t blk3_rdata4; - uint32_t blk3_rdata5; - uint32_t blk3_rdata6; - uint32_t blk3_rdata7; - - uint32_t blk1_wdata0; - uint32_t blk1_wdata1; - uint32_t blk1_wdata2; - uint32_t blk1_wdata3; - uint32_t blk1_wdata4; - uint32_t blk1_wdata5; - uint32_t blk1_wdata6; - uint32_t blk1_wdata7; - - uint32_t blk2_wdata0; - uint32_t blk2_wdata1; - uint32_t blk2_wdata2; - uint32_t blk2_wdata3; - uint32_t blk2_wdata4; - uint32_t blk2_wdata5; - uint32_t blk2_wdata6; - uint32_t blk2_wdata7; - - uint32_t blk3_wdata0; - uint32_t blk3_wdata1; - uint32_t blk3_wdata2; - uint32_t blk3_wdata3; - uint32_t blk3_wdata4; - uint32_t blk3_wdata5; - uint32_t blk3_wdata6; - uint32_t blk3_wdata7; - - uint32_t clk; - uint32_t conf; - uint32_t status; - uint32_t cmd; - uint32_t int_raw; - uint32_t int_st; - uint32_t int_ena; - uint32_t int_clr; - uint32_t dac_conf; - uint32_t dec_status; - uint32_t reserve[55]; - uint32_t date; +/** Type of blk0_rdata0 register */ +typedef union { + struct { + /** rd_efuse_wr_dis : R; bitpos: [15:0]; default: 0; + * read for efuse_wr_disable + */ + uint32_t rd_efuse_wr_dis:16; + /** rd_efuse_rd_dis : R; bitpos: [19:16]; default: 0; + * read for efuse_rd_disable + */ + uint32_t rd_efuse_rd_dis:4; + /** rd_flash_crypt_cnt : R; bitpos: [26:20]; default: 0; + * read for flash_crypt_cnt + */ + uint32_t rd_flash_crypt_cnt:7; + /** rd_uart_download_dis : R; bitpos: [27]; default: 0; + * Disable UART download mode. Valid for ESP32 V3 and newer, only + */ + uint32_t rd_uart_download_dis:1; + /** reserved_0_28 : R; bitpos: [31:28]; default: 0; + * reserved + */ + uint32_t reserved_0_28:4; + }; + uint32_t val; +} efuse_blk0_rdata0_reg_t; + +/** Type of blk0_rdata1 register */ +typedef union { + struct { + /** rd_mac : R; bitpos: [31:0]; default: 0; + * MAC address + */ + uint32_t rd_mac:32; + }; + uint32_t val; +} efuse_blk0_rdata1_reg_t; + +/** Type of blk0_rdata2 register */ +typedef union { + struct { + /** rd_mac_1 : R; bitpos: [15:0]; default: 0; + * MAC address + */ + uint32_t rd_mac_1:16; + /** rd_mac_crc : R; bitpos: [23:16]; default: 0; + * CRC8 for MAC address + */ + uint32_t rd_mac_crc:8; + /** rd_reserve_0_88 : RW; bitpos: [31:24]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_88:8; + }; + uint32_t val; +} efuse_blk0_rdata2_reg_t; + +/** Type of blk0_rdata3 register */ +typedef union { + struct { + /** rd_disable_app_cpu : R; bitpos: [0]; default: 0; + * Disables APP CPU + */ + uint32_t rd_disable_app_cpu:1; + /** rd_disable_bt : R; bitpos: [1]; default: 0; + * Disables Bluetooth + */ + uint32_t rd_disable_bt:1; + /** rd_chip_package_4bit : R; bitpos: [2]; default: 0; + * Chip package identifier #4bit + */ + uint32_t rd_chip_package_4bit:1; + /** rd_dis_cache : R; bitpos: [3]; default: 0; + * Disables cache + */ + uint32_t rd_dis_cache:1; + /** rd_spi_pad_config_hd : R; bitpos: [8:4]; default: 0; + * read for SPI_pad_config_hd + */ + uint32_t rd_spi_pad_config_hd:5; + /** rd_chip_package : RW; bitpos: [11:9]; default: 0; + * Chip package identifier + */ + uint32_t rd_chip_package:3; + /** rd_chip_cpu_freq_low : RW; bitpos: [12]; default: 0; + * If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is + * rated for 160MHz. 240MHz otherwise + */ + uint32_t rd_chip_cpu_freq_low:1; + /** rd_chip_cpu_freq_rated : RW; bitpos: [13]; default: 0; + * If set, the ESP32's maximum CPU frequency has been rated + */ + uint32_t rd_chip_cpu_freq_rated:1; + /** rd_blk3_part_reserve : RW; bitpos: [14]; default: 0; + * If set, this bit indicates that BLOCK3[143:96] is reserved for internal use + */ + uint32_t rd_blk3_part_reserve:1; + /** rd_chip_ver_rev1 : RW; bitpos: [15]; default: 0; + * bit is set to 1 for rev1 silicon + */ + uint32_t rd_chip_ver_rev1:1; + /** rd_reserve_0_112 : RW; bitpos: [31:16]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_112:16; + }; + uint32_t val; +} efuse_blk0_rdata3_reg_t; + +/** Type of blk0_rdata4 register */ +typedef union { + struct { + /** rd_clk8m_freq : R; bitpos: [7:0]; default: 0; + * 8MHz clock freq override + */ + uint32_t rd_clk8m_freq:8; + /** rd_adc_vref : RW; bitpos: [12:8]; default: 0; + * True ADC reference voltage + */ + uint32_t rd_adc_vref:5; + /** rd_reserve_0_141 : RW; bitpos: [13]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_141:1; + /** rd_xpd_sdio_reg : R; bitpos: [14]; default: 0; + * read for XPD_SDIO_REG + */ + uint32_t rd_xpd_sdio_reg:1; + /** rd_xpd_sdio_tieh : R; bitpos: [15]; default: 0; + * If XPD_SDIO_FORCE & XPD_SDIO_REG + */ + uint32_t rd_xpd_sdio_tieh:1; + /** rd_xpd_sdio_force : R; bitpos: [16]; default: 0; + * Ignore MTDI pin (GPIO12) for VDD_SDIO on reset + */ + uint32_t rd_xpd_sdio_force:1; + /** rd_reserve_0_145 : RW; bitpos: [31:17]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_145:15; + }; + uint32_t val; +} efuse_blk0_rdata4_reg_t; + +/** Type of blk0_rdata5 register */ +typedef union { + struct { + /** rd_spi_pad_config_clk : R; bitpos: [4:0]; default: 0; + * read for SPI_pad_config_clk + */ + uint32_t rd_spi_pad_config_clk:5; + /** rd_spi_pad_config_q : R; bitpos: [9:5]; default: 0; + * read for SPI_pad_config_q + */ + uint32_t rd_spi_pad_config_q:5; + /** rd_spi_pad_config_d : R; bitpos: [14:10]; default: 0; + * read for SPI_pad_config_d + */ + uint32_t rd_spi_pad_config_d:5; + /** rd_spi_pad_config_cs0 : R; bitpos: [19:15]; default: 0; + * read for SPI_pad_config_cs0 + */ + uint32_t rd_spi_pad_config_cs0:5; + /** rd_chip_ver_rev2 : R; bitpos: [20]; default: 0; */ + uint32_t rd_chip_ver_rev2:1; + /** rd_reserve_0_181 : RW; bitpos: [21]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_181:1; + /** rd_vol_level_hp_inv : R; bitpos: [23:22]; default: 0; + * This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM + * to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO) + */ + uint32_t rd_vol_level_hp_inv:2; + /** rd_wafer_version_minor : R; bitpos: [25:24]; default: 0; */ + uint32_t rd_wafer_version_minor:2; + /** rd_reserve_0_186 : RW; bitpos: [27:26]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_186:2; + /** rd_flash_crypt_config : R; bitpos: [31:28]; default: 0; + * read for flash_crypt_config + */ + uint32_t rd_flash_crypt_config:4; + }; + uint32_t val; +} efuse_blk0_rdata5_reg_t; + +/** Type of blk0_rdata6 register */ +typedef union { + struct { + /** rd_coding_scheme : R; bitpos: [1:0]; default: 0; + * read for coding_scheme + */ + uint32_t rd_coding_scheme:2; + /** rd_console_debug_disable : R; bitpos: [2]; default: 0; + * read for console_debug_disable + */ + uint32_t rd_console_debug_disable:1; + /** rd_disable_sdio_host : R; bitpos: [3]; default: 0; */ + uint32_t rd_disable_sdio_host:1; + /** rd_abs_done_0 : R; bitpos: [4]; default: 0; + * read for abstract_done_0 + */ + uint32_t rd_abs_done_0:1; + /** rd_abs_done_1 : R; bitpos: [5]; default: 0; + * read for abstract_done_1 + */ + uint32_t rd_abs_done_1:1; + /** rd_jtag_disable : R; bitpos: [6]; default: 0; + * Disable JTAG + */ + uint32_t rd_jtag_disable:1; + /** rd_disable_dl_encrypt : R; bitpos: [7]; default: 0; + * read for download_dis_encrypt + */ + uint32_t rd_disable_dl_encrypt:1; + /** rd_disable_dl_decrypt : R; bitpos: [8]; default: 0; + * read for download_dis_decrypt + */ + uint32_t rd_disable_dl_decrypt:1; + /** rd_disable_dl_cache : R; bitpos: [9]; default: 0; + * read for download_dis_cache + */ + uint32_t rd_disable_dl_cache:1; + /** rd_key_status : R; bitpos: [10]; default: 0; + * read for key_status + */ + uint32_t rd_key_status:1; + /** rd_reserve_0_203 : RW; bitpos: [31:11]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_203:21; + }; + uint32_t val; +} efuse_blk0_rdata6_reg_t; + +/** Type of blk0_wdata0 register */ +typedef union { + struct { + /** wr_dis : RW; bitpos: [15:0]; default: 0; + * program for efuse_wr_disable + */ + uint32_t wr_dis:16; + /** rd_dis : RW; bitpos: [19:16]; default: 0; + * program for efuse_rd_disable + */ + uint32_t rd_dis:4; + /** flash_crypt_cnt : RW; bitpos: [26:20]; default: 0; + * program for flash_crypt_cnt + */ + uint32_t flash_crypt_cnt:7; + uint32_t reserved_27:5; + }; + uint32_t val; +} efuse_blk0_wdata0_reg_t; + +/** Type of blk0_wdata1 register */ +typedef union { + struct { + /** wifi_mac_crc_low : RW; bitpos: [31:0]; default: 0; + * program for low 32bit WIFI_MAC_Address + */ + uint32_t wifi_mac_crc_low:32; + }; + uint32_t val; +} efuse_blk0_wdata1_reg_t; + +/** Type of blk0_wdata2 register */ +typedef union { + struct { + /** wifi_mac_crc_high : RW; bitpos: [23:0]; default: 0; + * program for high 24bit WIFI_MAC_Address + */ + uint32_t wifi_mac_crc_high:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} efuse_blk0_wdata2_reg_t; + +/** Type of blk0_wdata3 register */ +typedef union { + struct { + /** disable_app_cpu : R; bitpos: [0]; default: 0; + * Disables APP CPU + */ + uint32_t disable_app_cpu:1; + /** disable_bt : R; bitpos: [1]; default: 0; + * Disables Bluetooth + */ + uint32_t disable_bt:1; + /** chip_package_4bit : R; bitpos: [2]; default: 0; + * Chip package identifier #4bit + */ + uint32_t chip_package_4bit:1; + /** dis_cache : R; bitpos: [3]; default: 0; + * Disables cache + */ + uint32_t dis_cache:1; + /** spi_pad_config_hd : R; bitpos: [8:4]; default: 0; + * program for SPI_pad_config_hd + */ + uint32_t spi_pad_config_hd:5; + /** chip_package : RW; bitpos: [11:9]; default: 0; + * Chip package identifier + */ + uint32_t chip_package:3; + /** chip_cpu_freq_low : RW; bitpos: [12]; default: 0; + * If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is + * rated for 160MHz. 240MHz otherwise + */ + uint32_t chip_cpu_freq_low:1; + /** chip_cpu_freq_rated : RW; bitpos: [13]; default: 0; + * If set, the ESP32's maximum CPU frequency has been rated + */ + uint32_t chip_cpu_freq_rated:1; + /** blk3_part_reserve : RW; bitpos: [14]; default: 0; + * If set, this bit indicates that BLOCK3[143:96] is reserved for internal use + */ + uint32_t blk3_part_reserve:1; + /** chip_ver_rev1 : RW; bitpos: [15]; default: 0; + * bit is set to 1 for rev1 silicon + */ + uint32_t chip_ver_rev1:1; + /** reserve_0_112 : RW; bitpos: [31:16]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t reserve_0_112:16; + }; + uint32_t val; +} efuse_blk0_wdata3_reg_t; + +/** Type of blk0_wdata4 register */ +typedef union { + struct { + /** clk8m_freq : R; bitpos: [7:0]; default: 0; + * 8MHz clock freq override + */ + uint32_t clk8m_freq:8; + /** adc_vref : RW; bitpos: [12:8]; default: 0; + * True ADC reference voltage + */ + uint32_t adc_vref:5; + /** reserve_0_141 : RW; bitpos: [13]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t reserve_0_141:1; + /** xpd_sdio_reg : R; bitpos: [14]; default: 0; + * program for XPD_SDIO_REG + */ + uint32_t xpd_sdio_reg:1; + /** xpd_sdio_tieh : R; bitpos: [15]; default: 0; + * If XPD_SDIO_FORCE & XPD_SDIO_REG + */ + uint32_t xpd_sdio_tieh:1; + /** xpd_sdio_force : R; bitpos: [16]; default: 0; + * Ignore MTDI pin (GPIO12) for VDD_SDIO on reset + */ + uint32_t xpd_sdio_force:1; + /** reserve_0_145 : RW; bitpos: [31:17]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t reserve_0_145:15; + }; + uint32_t val; +} efuse_blk0_wdata4_reg_t; + +/** Type of blk0_wdata5 register */ +typedef union { + struct { + /** spi_pad_config_clk : R; bitpos: [4:0]; default: 0; + * program for SPI_pad_config_clk + */ + uint32_t spi_pad_config_clk:5; + /** spi_pad_config_q : R; bitpos: [9:5]; default: 0; + * program for SPI_pad_config_q + */ + uint32_t spi_pad_config_q:5; + /** spi_pad_config_d : R; bitpos: [14:10]; default: 0; + * program for SPI_pad_config_d + */ + uint32_t spi_pad_config_d:5; + /** spi_pad_config_cs0 : R; bitpos: [19:15]; default: 0; + * program for SPI_pad_config_cs0 + */ + uint32_t spi_pad_config_cs0:5; + /** chip_ver_rev2 : R; bitpos: [20]; default: 0; */ + uint32_t chip_ver_rev2:1; + /** reserve_0_181 : RW; bitpos: [21]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t reserve_0_181:1; + /** vol_level_hp_inv : R; bitpos: [23:22]; default: 0; + * This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM + * to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO) + */ + uint32_t vol_level_hp_inv:2; + /** wafer_version_minor : R; bitpos: [25:24]; default: 0; */ + uint32_t wafer_version_minor:2; + /** reserve_0_186 : RW; bitpos: [27:26]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t reserve_0_186:2; + /** flash_crypt_config : R; bitpos: [31:28]; default: 0; + * program for flash_crypt_config + */ + uint32_t flash_crypt_config:4; + }; + uint32_t val; +} efuse_blk0_wdata5_reg_t; + +/** Type of blk0_wdata6 register */ +typedef union { + struct { + /** coding_scheme : RW; bitpos: [1:0]; default: 0; + * program for coding_scheme + */ + uint32_t coding_scheme:2; + /** console_debug_disable : RW; bitpos: [2]; default: 0; + * program for console_debug_disable + */ + uint32_t console_debug_disable:1; + /** disable_sdio_host : RW; bitpos: [3]; default: 0; */ + uint32_t disable_sdio_host:1; + /** abs_done_0 : RW; bitpos: [4]; default: 0; + * program for abstract_done_0 + */ + uint32_t abs_done_0:1; + /** abs_done_1 : RW; bitpos: [5]; default: 0; + * program for abstract_done_1 + */ + uint32_t abs_done_1:1; + /** disable_jtag : RW; bitpos: [6]; default: 0; + * program for JTAG_disable + */ + uint32_t disable_jtag:1; + /** disable_dl_encrypt : RW; bitpos: [7]; default: 0; + * program for download_dis_encrypt + */ + uint32_t disable_dl_encrypt:1; + /** disable_dl_decrypt : RW; bitpos: [8]; default: 0; + * program for download_dis_decrypt + */ + uint32_t disable_dl_decrypt:1; + /** disable_dl_cache : RW; bitpos: [9]; default: 0; + * program for download_dis_cache + */ + uint32_t disable_dl_cache:1; + /** key_status : RW; bitpos: [10]; default: 0; + * program for key_status + */ + uint32_t key_status:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} efuse_blk0_wdata6_reg_t; + +/** Type of blk1_rdata0 register */ +typedef union { + struct { + /** rd_block1 : R; bitpos: [31:0]; default: 0; + * Flash encryption key + */ + uint32_t rd_block1:32; + }; + uint32_t val; +} efuse_blk1_rdata0_reg_t; + +/** Type of blk1_rdata1 register */ +typedef union { + struct { + /** rd_block1_1 : R; bitpos: [31:0]; default: 0; + * Flash encryption key + */ + uint32_t rd_block1_1:32; + }; + uint32_t val; +} efuse_blk1_rdata1_reg_t; + +/** Type of blk1_rdata2 register */ +typedef union { + struct { + /** rd_block1_2 : R; bitpos: [31:0]; default: 0; + * Flash encryption key + */ + uint32_t rd_block1_2:32; + }; + uint32_t val; +} efuse_blk1_rdata2_reg_t; + +/** Type of blk1_rdata3 register */ +typedef union { + struct { + /** rd_block1_3 : R; bitpos: [31:0]; default: 0; + * Flash encryption key + */ + uint32_t rd_block1_3:32; + }; + uint32_t val; +} efuse_blk1_rdata3_reg_t; + +/** Type of blk1_rdata4 register */ +typedef union { + struct { + /** rd_block1_4 : R; bitpos: [31:0]; default: 0; + * Flash encryption key + */ + uint32_t rd_block1_4:32; + }; + uint32_t val; +} efuse_blk1_rdata4_reg_t; + +/** Type of blk1_rdata5 register */ +typedef union { + struct { + /** rd_block1_5 : R; bitpos: [31:0]; default: 0; + * Flash encryption key + */ + uint32_t rd_block1_5:32; + }; + uint32_t val; +} efuse_blk1_rdata5_reg_t; + +/** Type of blk1_rdata6 register */ +typedef union { + struct { + /** rd_block1_6 : R; bitpos: [31:0]; default: 0; + * Flash encryption key + */ + uint32_t rd_block1_6:32; + }; + uint32_t val; +} efuse_blk1_rdata6_reg_t; + +/** Type of blk1_rdata7 register */ +typedef union { + struct { + /** rd_block1_7 : R; bitpos: [31:0]; default: 0; + * Flash encryption key + */ + uint32_t rd_block1_7:32; + }; + uint32_t val; +} efuse_blk1_rdata7_reg_t; + +/** Type of blk2_rdata0 register */ +typedef union { + struct { + /** rd_block2 : R; bitpos: [31:0]; default: 0; + * Security boot key + */ + uint32_t rd_block2:32; + }; + uint32_t val; +} efuse_blk2_rdata0_reg_t; + +/** Type of blk2_rdata1 register */ +typedef union { + struct { + /** rd_block2_1 : R; bitpos: [31:0]; default: 0; + * Security boot key + */ + uint32_t rd_block2_1:32; + }; + uint32_t val; +} efuse_blk2_rdata1_reg_t; + +/** Type of blk2_rdata2 register */ +typedef union { + struct { + /** rd_block2_2 : R; bitpos: [31:0]; default: 0; + * Security boot key + */ + uint32_t rd_block2_2:32; + }; + uint32_t val; +} efuse_blk2_rdata2_reg_t; + +/** Type of blk2_rdata3 register */ +typedef union { + struct { + /** rd_block2_3 : R; bitpos: [31:0]; default: 0; + * Security boot key + */ + uint32_t rd_block2_3:32; + }; + uint32_t val; +} efuse_blk2_rdata3_reg_t; + +/** Type of blk2_rdata4 register */ +typedef union { + struct { + /** rd_block2_4 : R; bitpos: [31:0]; default: 0; + * Security boot key + */ + uint32_t rd_block2_4:32; + }; + uint32_t val; +} efuse_blk2_rdata4_reg_t; + +/** Type of blk2_rdata5 register */ +typedef union { + struct { + /** rd_block2_5 : R; bitpos: [31:0]; default: 0; + * Security boot key + */ + uint32_t rd_block2_5:32; + }; + uint32_t val; +} efuse_blk2_rdata5_reg_t; + +/** Type of blk2_rdata6 register */ +typedef union { + struct { + /** rd_block2_6 : R; bitpos: [31:0]; default: 0; + * Security boot key + */ + uint32_t rd_block2_6:32; + }; + uint32_t val; +} efuse_blk2_rdata6_reg_t; + +/** Type of blk2_rdata7 register */ +typedef union { + struct { + /** rd_block2_7 : R; bitpos: [31:0]; default: 0; + * Security boot key + */ + uint32_t rd_block2_7:32; + }; + uint32_t val; +} efuse_blk2_rdata7_reg_t; + +/** Type of blk3_rdata0 register */ +typedef union { + struct { + /** rd_custom_mac_crc : R; bitpos: [7:0]; default: 0; + * CRC8 for custom MAC address + */ + uint32_t rd_custom_mac_crc:8; + /** rd_custom_mac : R; bitpos: [31:8]; default: 0; + * Custom MAC address + */ + uint32_t rd_custom_mac:24; + }; + uint32_t val; +} efuse_blk3_rdata0_reg_t; + +/** Type of blk3_rdata1 register */ +typedef union { + struct { + /** rd_custom_mac_1 : R; bitpos: [23:0]; default: 0; + * Custom MAC address + */ + uint32_t rd_custom_mac_1:24; + /** reserved_3_56 : R; bitpos: [31:24]; default: 0; + * reserved + */ + uint32_t reserved_3_56:8; + }; + uint32_t val; +} efuse_blk3_rdata1_reg_t; + +/** Type of blk3_rdata2 register */ +typedef union { + struct { + /** rd_blk3_reserved_2 : R; bitpos: [31:0]; default: 0; + * read for BLOCK3 + */ + uint32_t rd_blk3_reserved_2:32; + }; + uint32_t val; +} efuse_blk3_rdata2_reg_t; + +/** Type of blk3_rdata3 register */ +typedef union { + struct { + /** rd_adc1_tp_low : RW; bitpos: [6:0]; default: 0; + * ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + */ + uint32_t rd_adc1_tp_low:7; + /** rd_adc1_tp_high : RW; bitpos: [15:7]; default: 0; + * ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + */ + uint32_t rd_adc1_tp_high:9; + /** rd_adc2_tp_low : RW; bitpos: [22:16]; default: 0; + * ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + */ + uint32_t rd_adc2_tp_low:7; + /** rd_adc2_tp_high : RW; bitpos: [31:23]; default: 0; + * ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + */ + uint32_t rd_adc2_tp_high:9; + }; + uint32_t val; +} efuse_blk3_rdata3_reg_t; + +/** Type of blk3_rdata4 register */ +typedef union { + struct { + /** rd_secure_version : R; bitpos: [31:0]; default: 0; + * Secure version for anti-rollback + */ + uint32_t rd_secure_version:32; + }; + uint32_t val; +} efuse_blk3_rdata4_reg_t; + +/** Type of blk3_rdata5 register */ +typedef union { + struct { + /** reserved_3_160 : R; bitpos: [23:0]; default: 0; + * reserved + */ + uint32_t reserved_3_160:24; + /** rd_mac_version : R; bitpos: [31:24]; default: 0; + * Custom MAC version + */ + uint32_t rd_mac_version:8; + }; + uint32_t val; +} efuse_blk3_rdata5_reg_t; + +/** Type of blk3_rdata6 register */ +typedef union { + struct { + /** rd_blk3_reserved_6 : R; bitpos: [31:0]; default: 0; + * read for BLOCK3 + */ + uint32_t rd_blk3_reserved_6:32; + }; + uint32_t val; +} efuse_blk3_rdata6_reg_t; + +/** Type of blk3_rdata7 register */ +typedef union { + struct { + /** rd_blk3_reserved_7 : R; bitpos: [31:0]; default: 0; + * read for BLOCK3 + */ + uint32_t rd_blk3_reserved_7:32; + }; + uint32_t val; +} efuse_blk3_rdata7_reg_t; + +/** Type of blk1_wdata0 register */ +typedef union { + struct { + /** blk1_din0 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK1 + */ + uint32_t blk1_din0:32; + }; + uint32_t val; +} efuse_blk1_wdata0_reg_t; + +/** Type of blk1_wdata1 register */ +typedef union { + struct { + /** blk1_din1 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK1 + */ + uint32_t blk1_din1:32; + }; + uint32_t val; +} efuse_blk1_wdata1_reg_t; + +/** Type of blk1_wdata2 register */ +typedef union { + struct { + /** blk1_din2 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK1 + */ + uint32_t blk1_din2:32; + }; + uint32_t val; +} efuse_blk1_wdata2_reg_t; + +/** Type of blk1_wdata3 register */ +typedef union { + struct { + /** blk1_din3 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK1 + */ + uint32_t blk1_din3:32; + }; + uint32_t val; +} efuse_blk1_wdata3_reg_t; + +/** Type of blk1_wdata4 register */ +typedef union { + struct { + /** blk1_din4 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK1 + */ + uint32_t blk1_din4:32; + }; + uint32_t val; +} efuse_blk1_wdata4_reg_t; + +/** Type of blk1_wdata5 register */ +typedef union { + struct { + /** blk1_din5 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK1 + */ + uint32_t blk1_din5:32; + }; + uint32_t val; +} efuse_blk1_wdata5_reg_t; + +/** Type of blk1_wdata6 register */ +typedef union { + struct { + /** blk1_din6 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK1 + */ + uint32_t blk1_din6:32; + }; + uint32_t val; +} efuse_blk1_wdata6_reg_t; + +/** Type of blk1_wdata7 register */ +typedef union { + struct { + /** blk1_din7 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK1 + */ + uint32_t blk1_din7:32; + }; + uint32_t val; +} efuse_blk1_wdata7_reg_t; + +/** Type of blk2_wdata0 register */ +typedef union { + struct { + /** blk2_din0 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK2 + */ + uint32_t blk2_din0:32; + }; + uint32_t val; +} efuse_blk2_wdata0_reg_t; + +/** Type of blk2_wdata1 register */ +typedef union { + struct { + /** blk2_din1 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK2 + */ + uint32_t blk2_din1:32; + }; + uint32_t val; +} efuse_blk2_wdata1_reg_t; + +/** Type of blk2_wdata2 register */ +typedef union { + struct { + /** blk2_din2 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK2 + */ + uint32_t blk2_din2:32; + }; + uint32_t val; +} efuse_blk2_wdata2_reg_t; + +/** Type of blk2_wdata3 register */ +typedef union { + struct { + /** blk2_din3 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK2 + */ + uint32_t blk2_din3:32; + }; + uint32_t val; +} efuse_blk2_wdata3_reg_t; + +/** Type of blk2_wdata4 register */ +typedef union { + struct { + /** blk2_din4 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK2 + */ + uint32_t blk2_din4:32; + }; + uint32_t val; +} efuse_blk2_wdata4_reg_t; + +/** Type of blk2_wdata5 register */ +typedef union { + struct { + /** blk2_din5 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK2 + */ + uint32_t blk2_din5:32; + }; + uint32_t val; +} efuse_blk2_wdata5_reg_t; + +/** Type of blk2_wdata6 register */ +typedef union { + struct { + /** blk2_din6 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK2 + */ + uint32_t blk2_din6:32; + }; + uint32_t val; +} efuse_blk2_wdata6_reg_t; + +/** Type of blk2_wdata7 register */ +typedef union { + struct { + /** blk2_din7 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK2 + */ + uint32_t blk2_din7:32; + }; + uint32_t val; +} efuse_blk2_wdata7_reg_t; + +/** Type of blk3_wdata0 register */ +typedef union { + struct { + /** blk3_din0 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK3 + */ + uint32_t blk3_din0:32; + }; + uint32_t val; +} efuse_blk3_wdata0_reg_t; + +/** Type of blk3_wdata1 register */ +typedef union { + struct { + /** blk3_din1 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK3 + */ + uint32_t blk3_din1:32; + }; + uint32_t val; +} efuse_blk3_wdata1_reg_t; + +/** Type of blk3_wdata2 register */ +typedef union { + struct { + /** blk3_din2 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK3 + */ + uint32_t blk3_din2:32; + }; + uint32_t val; +} efuse_blk3_wdata2_reg_t; + +/** Type of blk3_wdata3 register */ +typedef union { + struct { + /** adc1_tp_low : RW; bitpos: [6:0]; default: 0; + * ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + */ + uint32_t adc1_tp_low:7; + /** adc1_tp_high : RW; bitpos: [15:7]; default: 0; + * ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + */ + uint32_t adc1_tp_high:9; + /** adc2_tp_low : RW; bitpos: [22:16]; default: 0; + * ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + */ + uint32_t adc2_tp_low:7; + /** adc2_tp_high : RW; bitpos: [31:23]; default: 0; + * ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + */ + uint32_t adc2_tp_high:9; + }; + uint32_t val; +} efuse_blk3_wdata3_reg_t; + +/** Type of blk3_wdata4 register */ +typedef union { + struct { + /** secure_version : R; bitpos: [31:0]; default: 0; + * Secure version for anti-rollback + */ + uint32_t secure_version:32; + }; + uint32_t val; +} efuse_blk3_wdata4_reg_t; + +/** Type of blk3_wdata5 register */ +typedef union { + struct { + /** blk3_din5 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK3 + */ + uint32_t blk3_din5:32; + }; + uint32_t val; +} efuse_blk3_wdata5_reg_t; + +/** Type of blk3_wdata6 register */ +typedef union { + struct { + /** blk3_din6 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK3 + */ + uint32_t blk3_din6:32; + }; + uint32_t val; +} efuse_blk3_wdata6_reg_t; + +/** Type of blk3_wdata7 register */ +typedef union { + struct { + /** blk3_din7 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK3 + */ + uint32_t blk3_din7:32; + }; + uint32_t val; +} efuse_blk3_wdata7_reg_t; + +/** Type of clk register */ +typedef union { + struct { + /** clk_sel0 : RW; bitpos: [7:0]; default: 82; + * efuse timing configure + */ + uint32_t clk_sel0:8; + /** clk_sel1 : RW; bitpos: [15:8]; default: 64; + * efuse timing configure + */ + uint32_t clk_sel1:8; + /** clk_en : RW; bitpos: [16]; default: 0; */ + uint32_t clk_en:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} efuse_clk_reg_t; + +/** Type of conf register */ +typedef union { + struct { + /** op_code : RW; bitpos: [15:0]; default: 0; + * efuse operation code + */ + uint32_t op_code:16; + /** force_no_wr_rd_dis : RW; bitpos: [16]; default: 1; */ + uint32_t force_no_wr_rd_dis:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} efuse_conf_reg_t; + +/** Type of status register */ +typedef union { + struct { + /** debug : R; bitpos: [31:0]; default: 0; */ + uint32_t debug:32; + }; + uint32_t val; +} efuse_status_reg_t; + +/** Type of cmd register */ +typedef union { + struct { + /** read_cmd : RW; bitpos: [0]; default: 0; + * command for read + */ + uint32_t read_cmd:1; + /** pgm_cmd : RW; bitpos: [1]; default: 0; + * command for program + */ + uint32_t pgm_cmd:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_cmd_reg_t; + +/** Type of int_raw register */ +typedef union { + struct { + /** read_done_int_raw : R; bitpos: [0]; default: 0; + * read done interrupt raw status + */ + uint32_t read_done_int_raw:1; + /** pgm_done_int_raw : R; bitpos: [1]; default: 0; + * program done interrupt raw status + */ + uint32_t pgm_done_int_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_raw_reg_t; + +/** Type of int_st register */ +typedef union { + struct { + /** read_done_int_st : R; bitpos: [0]; default: 0; + * read done interrupt status + */ + uint32_t read_done_int_st:1; + /** pgm_done_int_st : R; bitpos: [1]; default: 0; + * program done interrupt status + */ + uint32_t pgm_done_int_st:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_st_reg_t; + +/** Type of int_ena register */ +typedef union { + struct { + /** read_done_int_ena : RW; bitpos: [0]; default: 0; + * read done interrupt enable + */ + uint32_t read_done_int_ena:1; + /** pgm_done_int_ena : RW; bitpos: [1]; default: 0; + * program done interrupt enable + */ + uint32_t pgm_done_int_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_ena_reg_t; + +/** Type of int_clr register */ +typedef union { + struct { + /** read_done_int_clr : W; bitpos: [0]; default: 0; + * read done interrupt clear + */ + uint32_t read_done_int_clr:1; + /** pgm_done_int_clr : W; bitpos: [1]; default: 0; + * program done interrupt clear + */ + uint32_t pgm_done_int_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_clr_reg_t; + +/** Type of dac_conf register */ +typedef union { + struct { + /** dac_clk_div : RW; bitpos: [7:0]; default: 40; + * efuse timing configure + */ + uint32_t dac_clk_div:8; + /** dac_clk_pad_sel : RW; bitpos: [8]; default: 0; */ + uint32_t dac_clk_pad_sel:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} efuse_dac_conf_reg_t; + +/** Type of dec_status register */ +typedef union { + struct { + /** dec_warnings : R; bitpos: [11:0]; default: 0; + * the decode result of 3/4 coding scheme has warning + */ + uint32_t dec_warnings:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} efuse_dec_status_reg_t; + +/** Type of date register */ +typedef union { + struct { + /** date : RW; bitpos: [31:0]; default: 369370624; */ + uint32_t date:32; + }; + uint32_t val; +} efuse_date_reg_t; + + +typedef struct { + volatile efuse_blk0_rdata0_reg_t blk0_rdata0; + volatile efuse_blk0_rdata1_reg_t blk0_rdata1; + volatile efuse_blk0_rdata2_reg_t blk0_rdata2; + volatile efuse_blk0_rdata3_reg_t blk0_rdata3; + volatile efuse_blk0_rdata4_reg_t blk0_rdata4; + volatile efuse_blk0_rdata5_reg_t blk0_rdata5; + volatile efuse_blk0_rdata6_reg_t blk0_rdata6; + volatile efuse_blk0_wdata0_reg_t blk0_wdata0; + volatile efuse_blk0_wdata1_reg_t blk0_wdata1; + volatile efuse_blk0_wdata2_reg_t blk0_wdata2; + volatile efuse_blk0_wdata3_reg_t blk0_wdata3; + volatile efuse_blk0_wdata4_reg_t blk0_wdata4; + volatile efuse_blk0_wdata5_reg_t blk0_wdata5; + volatile efuse_blk0_wdata6_reg_t blk0_wdata6; + volatile efuse_blk1_rdata0_reg_t blk1_rdata0; + volatile efuse_blk1_rdata1_reg_t blk1_rdata1; + volatile efuse_blk1_rdata2_reg_t blk1_rdata2; + volatile efuse_blk1_rdata3_reg_t blk1_rdata3; + volatile efuse_blk1_rdata4_reg_t blk1_rdata4; + volatile efuse_blk1_rdata5_reg_t blk1_rdata5; + volatile efuse_blk1_rdata6_reg_t blk1_rdata6; + volatile efuse_blk1_rdata7_reg_t blk1_rdata7; + volatile efuse_blk2_rdata0_reg_t blk2_rdata0; + volatile efuse_blk2_rdata1_reg_t blk2_rdata1; + volatile efuse_blk2_rdata2_reg_t blk2_rdata2; + volatile efuse_blk2_rdata3_reg_t blk2_rdata3; + volatile efuse_blk2_rdata4_reg_t blk2_rdata4; + volatile efuse_blk2_rdata5_reg_t blk2_rdata5; + volatile efuse_blk2_rdata6_reg_t blk2_rdata6; + volatile efuse_blk2_rdata7_reg_t blk2_rdata7; + volatile efuse_blk3_rdata0_reg_t blk3_rdata0; + volatile efuse_blk3_rdata1_reg_t blk3_rdata1; + volatile efuse_blk3_rdata2_reg_t blk3_rdata2; + volatile efuse_blk3_rdata3_reg_t blk3_rdata3; + volatile efuse_blk3_rdata4_reg_t blk3_rdata4; + volatile efuse_blk3_rdata5_reg_t blk3_rdata5; + volatile efuse_blk3_rdata6_reg_t blk3_rdata6; + volatile efuse_blk3_rdata7_reg_t blk3_rdata7; + volatile efuse_blk1_wdata0_reg_t blk1_wdata0; + volatile efuse_blk1_wdata1_reg_t blk1_wdata1; + volatile efuse_blk1_wdata2_reg_t blk1_wdata2; + volatile efuse_blk1_wdata3_reg_t blk1_wdata3; + volatile efuse_blk1_wdata4_reg_t blk1_wdata4; + volatile efuse_blk1_wdata5_reg_t blk1_wdata5; + volatile efuse_blk1_wdata6_reg_t blk1_wdata6; + volatile efuse_blk1_wdata7_reg_t blk1_wdata7; + volatile efuse_blk2_wdata0_reg_t blk2_wdata0; + volatile efuse_blk2_wdata1_reg_t blk2_wdata1; + volatile efuse_blk2_wdata2_reg_t blk2_wdata2; + volatile efuse_blk2_wdata3_reg_t blk2_wdata3; + volatile efuse_blk2_wdata4_reg_t blk2_wdata4; + volatile efuse_blk2_wdata5_reg_t blk2_wdata5; + volatile efuse_blk2_wdata6_reg_t blk2_wdata6; + volatile efuse_blk2_wdata7_reg_t blk2_wdata7; + volatile efuse_blk3_wdata0_reg_t blk3_wdata0; + volatile efuse_blk3_wdata1_reg_t blk3_wdata1; + volatile efuse_blk3_wdata2_reg_t blk3_wdata2; + volatile efuse_blk3_wdata3_reg_t blk3_wdata3; + volatile efuse_blk3_wdata4_reg_t blk3_wdata4; + volatile efuse_blk3_wdata5_reg_t blk3_wdata5; + volatile efuse_blk3_wdata6_reg_t blk3_wdata6; + volatile efuse_blk3_wdata7_reg_t blk3_wdata7; + volatile efuse_clk_reg_t clk; + volatile efuse_conf_reg_t conf; + volatile efuse_status_reg_t status; + volatile efuse_cmd_reg_t cmd; + volatile efuse_int_raw_reg_t int_raw; + volatile efuse_int_st_reg_t int_st; + volatile efuse_int_ena_reg_t int_ena; + volatile efuse_int_clr_reg_t int_clr; + volatile efuse_dac_conf_reg_t dac_conf; + volatile efuse_dec_status_reg_t dec_status; + uint32_t reserved_120[55]; + volatile efuse_date_reg_t date; } efuse_dev_t; extern efuse_dev_t EFUSE; +#ifndef __cplusplus +_Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure"); +#endif + #ifdef __cplusplus } #endif - -#endif /* _SOC_EFUSE_STRUCT_H_ */ diff --git a/tools/sdk/esp32/include/soc/esp32/include/soc/soc_caps.h b/tools/sdk/esp32/include/soc/esp32/include/soc/soc_caps.h index a43ecf424ef..61bfb4c17ea 100644 --- a/tools/sdk/esp32/include/soc/esp32/include/soc/soc_caps.h +++ b/tools/sdk/esp32/include/soc/esp32/include/soc/soc_caps.h @@ -412,3 +412,4 @@ #define SOC_BLE_SUPPORTED (1) /*!< Support Bluetooth Low Energy hardware */ #define SOC_BLE_MESH_SUPPORTED (1) /*!< Support BLE MESH */ #define SOC_BT_CLASSIC_SUPPORTED (1) /*!< Support Bluetooth Classic hardware */ +#define SOC_BLE_DEVICE_PRIVACY_SUPPORTED (0) /*!< Support BLE device privacy mode */ diff --git a/tools/sdk/esp32/include/spi_flash/include/esp_spi_flash_counters.h b/tools/sdk/esp32/include/spi_flash/include/esp_spi_flash_counters.h index ab8157c256d..3355ee16bc2 100644 --- a/tools/sdk/esp32/include/spi_flash/include/esp_spi_flash_counters.h +++ b/tools/sdk/esp32/include/spi_flash/include/esp_spi_flash_counters.h @@ -1,16 +1,8 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -32,31 +24,38 @@ typedef struct { uint32_t count; // number of times operation was executed uint32_t time; // total time taken, in microseconds uint32_t bytes; // total number of bytes -} spi_flash_counter_t; +} esp_flash_counter_t; typedef struct { - spi_flash_counter_t read; - spi_flash_counter_t write; - spi_flash_counter_t erase; -} spi_flash_counters_t; + esp_flash_counter_t read; + esp_flash_counter_t write; + esp_flash_counter_t erase; +} esp_flash_counters_t; + +// for deprecate old api +typedef esp_flash_counter_t spi_flash_counter_t; +typedef esp_flash_counters_t spi_flash_counters_t; /** * @brief Reset SPI flash operation counters */ -void spi_flash_reset_counters(void); +void esp_flash_reset_counters(void); +void spi_flash_reset_counters(void) __attribute__((deprecated("Please use 'esp_flash_reset_counters' instead"))); /** * @brief Print SPI flash operation counters */ -void spi_flash_dump_counters(void); +void esp_flash_dump_counters(FILE* stream); +void spi_flash_dump_counters(void) __attribute__((deprecated("Please use 'esp_flash_dump_counters' instead"))); /** * @brief Return current SPI flash operation counters * - * @return pointer to the spi_flash_counters_t structure holding values + * @return pointer to the esp_flash_counters_t structure holding values * of the operation counters */ -const spi_flash_counters_t* spi_flash_get_counters(void); +const esp_flash_counters_t* esp_flash_get_counters(void); +const spi_flash_counters_t* spi_flash_get_counters(void) __attribute__((deprecated("Please use 'esp_flash_get_counters' instead"))); #ifdef __cplusplus } diff --git a/tools/sdk/esp32/include/tcp_transport/include/esp_transport_socks_proxy.h b/tools/sdk/esp32/include/tcp_transport/include/esp_transport_socks_proxy.h new file mode 100644 index 00000000000..566ed9a6de6 --- /dev/null +++ b/tools/sdk/esp32/include/tcp_transport/include/esp_transport_socks_proxy.h @@ -0,0 +1,61 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "esp_transport.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum socks_version_t {SOCKS4 = 4} socks_version_t; + +typedef enum socks_transport_response_t { + // The following values correspond to transport operation + SOCKS_RESPONSE_TARGET_NOT_FOUND = 0xF0, + SOCKS_RESPONSE_PROXY_UNREACHABLE = 0xF1, + SOCKS_TIMEOUT = 0xF2, + // The following values are defined by the SOCKS4 protocol + SOCKS_RESPONSE_SUCCESS = 0x5a, + SOCKS_RESPONSE_REQUEST_REJECTED = 0x5B, + SOCKS_RESPONSE_NOT_RUNNING_IDENTD = 0x5c, + SOCKS_RESPONSE_COULD_NOT_CONFIRM_ID = 0x5d, +} socks_transport_error_t; + +/* + * Socks configuration structure + */ +typedef struct esp_transport_socks_proxy_config_t { + const socks_version_t version; /*!< Socks protocol version.*/ + const char *address;/*!< Proxy address*/ + const int port; /*< Proxy port*/ +} esp_transport_socks_proxy_config_t; + +/** +* @brief Create a proxy transport +* @param parent_handle Handle for the parent transport +* @param config Pointer to the configuration structure to use +* +* @return +* - transport Handler for the created transport. +* - NULL in case of failure +*/ +esp_transport_handle_t esp_transport_socks_proxy_init(esp_transport_handle_t parent_handle, const esp_transport_socks_proxy_config_t *config); + +/** +* @brief Changes the configuration of the proxy +* @param socks_transport Handle for the transport +* @param config Pointer to the configuration structure to use +* +* @return +* - ESP_OK on success +*/ +esp_err_t esp_transport_socks_proxy_set_config(esp_transport_handle_t socks_transport, const esp_transport_socks_proxy_config_t *config); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/ld/libbtdm_app.a b/tools/sdk/esp32/ld/libbtdm_app.a index 7297f243ffe..d3ef78691a7 100644 Binary files a/tools/sdk/esp32/ld/libbtdm_app.a and b/tools/sdk/esp32/ld/libbtdm_app.a differ diff --git a/tools/sdk/esp32/ld/sections.ld b/tools/sdk/esp32/ld/sections.ld index ab4bccbbacd..10c0d907722 100644 --- a/tools/sdk/esp32/ld/sections.ld +++ b/tools/sdk/esp32/ld/sections.ld @@ -1,6 +1,6 @@ /* Automatically generated file; DO NOT EDIT */ /* Espressif IoT Development Framework Linker Script */ -/* Generated from: /Users/ficeto/Desktop/ESP32/ESP-IDF-5/esp32-arduino-lib-builder/esp-idf/components/esp_system/ld/esp32/sections.ld.in */ +/* Generated from: /home/runner/work/esp32-arduino-lib-builder/esp32-arduino-lib-builder/esp-idf/components/esp_system/ld/esp32/sections.ld.in */ /* * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD @@ -824,7 +824,7 @@ SECTIONS *libesp_system.a:esp_system_chip.*(.literal.esp_get_free_heap_size .literal.esp_get_free_internal_heap_size .literal.esp_get_idf_version .literal.esp_get_minimum_free_heap_size .text .text.esp_get_free_heap_size .text.esp_get_free_internal_heap_size .text.esp_get_idf_version .text.esp_get_minimum_free_heap_size) *libfreertos.a:app_startup.*(.literal .literal.* .text .text.*) *libheap.a:multi_heap.*(.literal.multi_heap_check .literal.multi_heap_dump .literal.multi_heap_dump_tlsf .literal.multi_heap_get_info_impl .literal.multi_heap_register_impl .literal.tlsf_check_hook .text .text.multi_heap_check .text.multi_heap_dump .text.multi_heap_dump_tlsf .text.multi_heap_free_size_impl .text.multi_heap_get_info_impl .text.multi_heap_get_info_tlsf .text.multi_heap_minimum_free_size_impl .text.multi_heap_register_impl .text.tlsf_check_hook) - *libheap.a:multi_heap_poisoning.*(.literal.multi_heap_free_size .literal.multi_heap_get_info .literal.multi_heap_minimum_free_size .literal.multi_heap_register .text .text.multi_heap_free_size .text.multi_heap_get_info .text.multi_heap_minimum_free_size .text.multi_heap_register .text.subtract_poison_overhead) + *libheap.a:multi_heap_poisoning.*(.literal.multi_heap_free_size .literal.multi_heap_get_info .literal.multi_heap_minimum_free_size .literal.multi_heap_register .text .text.multi_heap_free_size .text.multi_heap_get_info .text.multi_heap_minimum_free_size .text.multi_heap_register) *libheap.a:tlsf.*(.literal.default_walker .literal.tlsf_add_pool .literal.tlsf_check .literal.tlsf_check_pool .literal.tlsf_create .literal.tlsf_create_with_pool .literal.tlsf_remove_pool .literal.tlsf_walk_pool .text .text.default_walker .text.integrity_walker .text.tlsf_add_pool .text.tlsf_check .text.tlsf_check_pool .text.tlsf_create .text.tlsf_create_with_pool .text.tlsf_destroy .text.tlsf_fit_size .text.tlsf_pool_overhead .text.tlsf_remove_pool .text.tlsf_walk_pool) *liblog.a:log.*(.literal.esp_log_level_get .literal.esp_log_level_set .literal.esp_log_set_vprintf .literal.esp_log_writev .literal.heap_bubble_down .literal.s_log_level_get_and_unlock .text .text.esp_log_level_get .text.esp_log_level_set .text.esp_log_set_vprintf .text.esp_log_writev .text.heap_bubble_down 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2635ea5049b..6fc3211870b 100644 Binary files a/tools/sdk/esp32/lib/libwear_levelling.a and b/tools/sdk/esp32/lib/libwear_levelling.a differ diff --git a/tools/sdk/esp32/lib/libwifi_provisioning.a b/tools/sdk/esp32/lib/libwifi_provisioning.a index 25d2da02ec8..258c246b05a 100644 Binary files a/tools/sdk/esp32/lib/libwifi_provisioning.a and b/tools/sdk/esp32/lib/libwifi_provisioning.a differ diff --git a/tools/sdk/esp32/lib/libwpa_supplicant.a b/tools/sdk/esp32/lib/libwpa_supplicant.a index 8f6fbc8b08f..4c9db43f65d 100644 Binary files a/tools/sdk/esp32/lib/libwpa_supplicant.a and b/tools/sdk/esp32/lib/libwpa_supplicant.a differ diff --git a/tools/sdk/esp32/lib/libws2812_led.a b/tools/sdk/esp32/lib/libws2812_led.a index 166108b00d4..2be90295a1c 100644 Binary files a/tools/sdk/esp32/lib/libws2812_led.a and b/tools/sdk/esp32/lib/libws2812_led.a differ diff --git a/tools/sdk/esp32/lib/libxtensa.a b/tools/sdk/esp32/lib/libxtensa.a index fef649ff23b..70be615515c 100644 Binary files a/tools/sdk/esp32/lib/libxtensa.a and b/tools/sdk/esp32/lib/libxtensa.a differ diff --git a/tools/sdk/esp32/platformio-build.py b/tools/sdk/esp32/platformio-build.py index 0824e99c67f..2b2411df194 100644 --- a/tools/sdk/esp32/platformio-build.py +++ b/tools/sdk/esp32/platformio-build.py @@ -110,6 +110,7 @@ "-u", "pthread_include_pthread_cond_impl", "-u", "pthread_include_pthread_local_storage_impl", "-u", "pthread_include_pthread_rwlock_impl", + "-u", "pthread_include_pthread_semaphore_impl", "-u", "ld_include_highint_hdl", "-u", "start_app", "-u", "start_app_other_cores", @@ -133,6 +134,7 @@ join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "freertos", "FreeRTOS-Kernel", "portable", "xtensa", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "freertos", "esp_additions", "include", "freertos"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "freertos", "esp_additions", "include"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "freertos", "esp_additions", "arch", "xtensa", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "esp_hw_support", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "esp_hw_support", "include", "soc"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "esp_hw_support", "include", "soc", "esp32"), @@ -256,6 +258,7 @@ join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "esp_http_server", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "esp_https_ota", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "esp_https_server", "include"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "esp_psram", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "esp_lcd", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "esp_lcd", "interface"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "protobuf-c", "protobuf-c"), @@ -263,7 +266,6 @@ join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "protocomm", "include", "security"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "protocomm", "include", "transports"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "esp_local_ctrl", "include"), - join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "esp_psram", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "espcoredump", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "espcoredump", "include", "port", "xtensa"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "wear_levelling", "include"), @@ -307,11 +309,6 @@ join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "esp-dl", "include", "layer"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "esp-dl", "include", "detect"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "esp-dl", "include", "model_zoo"), - join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "esp-sr", "src", "include"), - join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "esp-sr", "esp-tts", "esp_tts_chinese", "include"), - join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "esp-sr", "include", "esp32"), - join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "esp32-camera", "driver", "include"), - join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "esp32-camera", "conversions", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "espressif__esp-dsp", "modules", "dotprod", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "espressif__esp-dsp", "modules", "support", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "espressif__esp-dsp", "modules", "windows", "include"), @@ -337,6 +334,11 @@ join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "espressif__esp-dsp", "modules", "common", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "espressif__esp-dsp", "modules", "kalman", "ekf", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "espressif__esp-dsp", "modules", "kalman", "ekf_imu13states", "include"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "esp-sr", "src", "include"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "esp-sr", "esp-tts", "esp_tts_chinese", "include"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "esp-sr", "include", "esp32"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "esp32-camera", "driver", "include"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "esp32-camera", "conversions", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "fb_gfx", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", env.BoardConfig().get("build.arduino.memory_type", (env.BoardConfig().get("build.flash_mode", "dio") + "_qspi")), "include"), join(FRAMEWORK_DIR, "cores", env.BoardConfig().get("build.core")) @@ -349,12 +351,12 @@ ], LIBS=[ - "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lapp_trace", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lbt", "-lunity", "-lcmock", "-lconsole", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-lesp_hid", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_https_server", "-lesp_lcd", "-lprotobuf-c", "-lprotocomm", "-lesp_local_ctrl", "-lesp_psram", "-lespcoredump", "-lwear_levelling", "-lsdmmc", "-lfatfs", "-ljson", "-lmqtt", "-lperfmon", "-lspiffs", "-lulp", "-lwifi_provisioning", "-lespressif__mdns", "-lcbor", "-lrmaker_common", "-lesp_diagnostics", "-lrtc_store", "-lesp_insights", "-ljson_parser", "-ljson_generator", "-lesp_schedule", "-lespressif__esp_secure_cert_mgr", "-lesp_rainmaker", "-lgpio_button", "-lqrcode", "-lws2812_led", "-lesp-sr", "-lesp32-camera", "-lesp_littlefs", "-lespressif__esp-dsp", "-lfb_gfx", "-lapp_trace", "-lapp_trace", "-lcmock", "-lunity", "-lesp_lcd", "-lperfmon", "-lesp_hid", "-lfatfs", "-lwear_levelling", "-lsdmmc", "-lesp_insights", "-lcbor", "-lesp_diagnostics", "-lrtc_store", "-lesp_rainmaker", "-lesp_local_ctrl", "-lesp_https_server", "-lwifi_provisioning", "-lprotocomm", "-lbt", "-lbtdm_app", "-lprotobuf-c", "-lespressif__mdns", "-ljson_parser", "-ljson_generator", "-lesp_schedule", "-lespressif__esp_secure_cert_mgr", "-lqrcode", "-lrmaker_common", "-lconsole", "-lmqtt", "-lcat_face_detect", "-lhuman_face_detect", "-lcolor_detect", "-lmfn", "-ldl", "-lmultinet", "-lesp_audio_processor", "-lesp_audio_front_end", "-lwakenet", "-lesp-sr", "-lmultinet", "-lesp_audio_processor", "-lesp_audio_front_end", "-lwakenet", "-ljson", "-lspiffs", "-ldl_lib", "-lc_speech_features", "-lwakeword_model", "-lmultinet2_ch", "-lesp_tts_chinese", "-lvoice_set_xiaole", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxt_hal", "-lc", "-lm", "-lnewlib", "-lstdc++", "-lpthread", "-lgcc", "-lcxx", "-lphy", "-lrtc", "-lesp_phy", "-lphy", "-lrtc", "-lesp_phy", "-lphy", "-lrtc" + "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lapp_trace", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lbt", "-lunity", "-lcmock", "-lconsole", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-lesp_hid", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_https_server", "-lesp_psram", "-lesp_lcd", "-lprotobuf-c", "-lprotocomm", "-lesp_local_ctrl", "-lespcoredump", "-lwear_levelling", "-lsdmmc", "-lfatfs", "-ljson", "-lmqtt", "-lperfmon", "-lspiffs", "-lulp", "-lwifi_provisioning", "-lespressif__mdns", "-lcbor", "-lrmaker_common", "-lesp_diagnostics", "-lrtc_store", "-lesp_insights", "-ljson_parser", "-ljson_generator", "-lesp_schedule", "-lespressif__esp_secure_cert_mgr", "-lesp_rainmaker", "-lgpio_button", "-lqrcode", "-lws2812_led", "-lespressif__esp-dsp", "-lesp-sr", "-lesp32-camera", "-lesp_littlefs", "-lfb_gfx", "-lapp_trace", "-lapp_trace", "-lcmock", "-lunity", "-lesp_lcd", "-lperfmon", "-lesp_hid", "-lfatfs", "-lwear_levelling", "-lsdmmc", "-lesp_insights", "-lcbor", "-lesp_diagnostics", "-lrtc_store", "-lesp_rainmaker", "-lesp_local_ctrl", "-lesp_https_server", "-lwifi_provisioning", "-lprotocomm", "-lbt", "-lbtdm_app", "-lprotobuf-c", "-lespressif__mdns", "-ljson_parser", "-ljson_generator", "-lesp_schedule", "-lespressif__esp_secure_cert_mgr", "-lqrcode", "-lrmaker_common", "-lconsole", "-lmqtt", "-lcat_face_detect", "-lhuman_face_detect", "-lcolor_detect", "-lmfn", "-ldl", "-lmultinet", "-lesp_audio_processor", "-lesp_audio_front_end", "-lwakenet", "-lesp-sr", "-lmultinet", "-lesp_audio_processor", "-lesp_audio_front_end", "-lwakenet", "-ljson", "-lspiffs", "-lespressif__esp-dsp", "-ldl_lib", "-lc_speech_features", "-lwakeword_model", "-lmultinet2_ch", "-lesp_tts_chinese", "-lvoice_set_xiaole", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxt_hal", "-lc", "-lm", "-lnewlib", "-lstdc++", "-lpthread", "-lgcc", "-lcxx", "-lphy", "-lrtc", "-lesp_phy", "-lphy", "-lrtc", "-lesp_phy", "-lphy", "-lrtc" ], CPPDEFINES=[ "ESP_PLATFORM", - ("IDF_VER", '\\"v5.1-dev-4124-gbb9200acec\\"'), + ("IDF_VER", '\\"v5.1-dev-4528-g420ebd208a\\"'), ("MBEDTLS_CONFIG_FILE", '\\"mbedtls/esp_config.h\\"'), ("SOC_MMU_PAGE_SIZE", 'CONFIG_MMU_PAGE_SIZE'), "UNITY_INCLUDE_CONFIG_H", diff --git a/tools/sdk/esp32/qio_qspi/include/sdkconfig.h b/tools/sdk/esp32/qio_qspi/include/sdkconfig.h index f459417a212..eed9d752f7f 100644 --- a/tools/sdk/esp32/qio_qspi/include/sdkconfig.h +++ b/tools/sdk/esp32/qio_qspi/include/sdkconfig.h @@ -230,6 +230,7 @@ #define CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE 1 #define CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP 1 #define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x10 +#define CONFIG_BOOTLOADER_RESERVE_RTC_MEM 1 #define CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT 1 #define CONFIG_SECURE_BOOT_V1_SUPPORTED 1 #define CONFIG_APP_COMPILE_TIME_DATE 1 @@ -1078,5 +1079,5 @@ #define CONFIG_WARN_WRITE_STRINGS CONFIG_COMPILER_WARN_WRITE_STRINGS #define CONFIG_WPA_MBEDTLS_CRYPTO CONFIG_ESP_WIFI_MBEDTLS_CRYPTO #define CONFIG_WPA_MBEDTLS_TLS_CLIENT CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT -#define CONFIG_ARDUINO_IDF_COMMIT "" +#define CONFIG_ARDUINO_IDF_COMMIT "420ebd208a" #define CONFIG_ARDUINO_IDF_BRANCH "release/v5.1" diff --git a/tools/sdk/esp32/qio_qspi/libspi_flash.a b/tools/sdk/esp32/qio_qspi/libspi_flash.a index 6bcbc369d2f..7e5d121bb31 100644 Binary files a/tools/sdk/esp32/qio_qspi/libspi_flash.a and b/tools/sdk/esp32/qio_qspi/libspi_flash.a differ diff --git a/tools/sdk/esp32/qout_qspi/include/sdkconfig.h b/tools/sdk/esp32/qout_qspi/include/sdkconfig.h index 8d7b0e8831a..a48f2ca4050 100644 --- a/tools/sdk/esp32/qout_qspi/include/sdkconfig.h +++ b/tools/sdk/esp32/qout_qspi/include/sdkconfig.h @@ -230,6 +230,7 @@ #define CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE 1 #define CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP 1 #define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x10 +#define CONFIG_BOOTLOADER_RESERVE_RTC_MEM 1 #define CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT 1 #define CONFIG_SECURE_BOOT_V1_SUPPORTED 1 #define CONFIG_APP_COMPILE_TIME_DATE 1 @@ -1078,5 +1079,5 @@ #define CONFIG_WARN_WRITE_STRINGS CONFIG_COMPILER_WARN_WRITE_STRINGS #define CONFIG_WPA_MBEDTLS_CRYPTO CONFIG_ESP_WIFI_MBEDTLS_CRYPTO #define CONFIG_WPA_MBEDTLS_TLS_CLIENT CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT -#define CONFIG_ARDUINO_IDF_COMMIT "" +#define CONFIG_ARDUINO_IDF_COMMIT "420ebd208a" #define CONFIG_ARDUINO_IDF_BRANCH "release/v5.1" diff --git a/tools/sdk/esp32/qout_qspi/libspi_flash.a b/tools/sdk/esp32/qout_qspi/libspi_flash.a index bcb745481c5..6438e30a779 100644 Binary files a/tools/sdk/esp32/qout_qspi/libspi_flash.a and b/tools/sdk/esp32/qout_qspi/libspi_flash.a differ diff --git a/tools/sdk/esp32/sdkconfig b/tools/sdk/esp32/sdkconfig index 9012cc8192b..ebbb8628f4a 100644 --- a/tools/sdk/esp32/sdkconfig +++ b/tools/sdk/esp32/sdkconfig @@ -259,6 +259,7 @@ CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP=y # CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS is not set CONFIG_BOOTLOADER_RESERVE_RTC_SIZE=0x10 # CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC is not set +CONFIG_BOOTLOADER_RESERVE_RTC_MEM=y CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT=y # end of Bootloader config @@ -742,6 +743,7 @@ CONFIG_BLE_MESH_DISCARD_OLD_SEQ_AUTH=y # BLE Mesh specific test option # # CONFIG_BLE_MESH_SELF_TEST is not set +# CONFIG_BLE_MESH_BQB_TEST is not set # CONFIG_BLE_MESH_SHELL is not set # CONFIG_BLE_MESH_DEBUG is not set # end of BLE Mesh specific test option @@ -1204,7 +1206,6 @@ CONFIG_PICO_PSRAM_CS_IO=10 # ESP Ringbuf # # CONFIG_RINGBUF_PLACE_FUNCTIONS_INTO_FLASH is not set -# CONFIG_RINGBUF_PLACE_ISR_FUNCTIONS_INTO_FLASH is not set # end of ESP Ringbuf # @@ -1352,12 +1353,19 @@ CONFIG_ESP_WIFI_MBEDTLS_CRYPTO=y CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT=y # CONFIG_ESP_WIFI_WAPI_PSK is not set # CONFIG_ESP_WIFI_SUITE_B_192 is not set -# CONFIG_ESP_WIFI_WPS_STRICT is not set # CONFIG_ESP_WIFI_11KV_SUPPORT is not set # CONFIG_ESP_WIFI_MBO_SUPPORT is not set # CONFIG_ESP_WIFI_DPP_SUPPORT is not set # CONFIG_ESP_WIFI_11R_SUPPORT is not set # CONFIG_ESP_WIFI_WPS_SOFTAP_REGISTRAR is not set + +# +# WPS Configuration Options +# +# CONFIG_ESP_WIFI_WPS_STRICT is not set +# CONFIG_ESP_WIFI_WPS_PASSPHRASE is not set +# end of WPS Configuration Options + # CONFIG_ESP_WIFI_DEBUG_PRINT is not set # CONFIG_ESP_WIFI_TESTING_OPTIONS is not set # end of Wi-Fi @@ -1494,6 +1502,7 @@ CONFIG_HEAP_POISONING_LIGHT=y CONFIG_HEAP_TRACING_OFF=y # CONFIG_HEAP_TRACING_STANDALONE is not set # CONFIG_HEAP_TRACING_TOHOST is not set +# CONFIG_HEAP_USE_HOOKS is not set # CONFIG_HEAP_TASK_TRACKING is not set # CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS is not set # end of Heap memory debugging @@ -2212,6 +2221,8 @@ CONFIG_MDNS_PREDEF_NETIF_ETH=y # end of mDNS # end of Component config +# CONFIG_IDF_EXPERIMENTAL_FEATURES is not set + # Deprecated options for backward compatibility # CONFIG_APP_BUILD_TYPE_ELF_RAM is not set # CONFIG_NO_BLOBS is not set @@ -2421,12 +2432,12 @@ CONFIG_WPA_MBEDTLS_CRYPTO=y CONFIG_WPA_MBEDTLS_TLS_CLIENT=y # CONFIG_WPA_WAPI_PSK is not set # CONFIG_WPA_SUITE_B_192 is not set -# CONFIG_WPA_WPS_STRICT is not set # CONFIG_WPA_11KV_SUPPORT is not set # CONFIG_WPA_MBO_SUPPORT is not set # CONFIG_WPA_DPP_SUPPORT is not set # CONFIG_WPA_11R_SUPPORT is not set # CONFIG_WPA_WPS_SOFTAP_REGISTRAR is not set +# CONFIG_WPA_WPS_STRICT is not set # CONFIG_WPA_DEBUG_PRINT is not set # CONFIG_WPA_TESTING_OPTIONS is not set CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH=y diff --git a/tools/sdk/esp32c3/bin/bootloader_dio_40m.elf b/tools/sdk/esp32c3/bin/bootloader_dio_40m.elf index b2bf118a68e..ffa4cc6909d 100755 Binary files a/tools/sdk/esp32c3/bin/bootloader_dio_40m.elf and b/tools/sdk/esp32c3/bin/bootloader_dio_40m.elf differ diff --git a/tools/sdk/esp32c3/bin/bootloader_dio_80m.elf b/tools/sdk/esp32c3/bin/bootloader_dio_80m.elf index b2bf118a68e..ffa4cc6909d 100755 Binary files a/tools/sdk/esp32c3/bin/bootloader_dio_80m.elf and b/tools/sdk/esp32c3/bin/bootloader_dio_80m.elf differ diff --git a/tools/sdk/esp32c3/bin/bootloader_dout_40m.elf b/tools/sdk/esp32c3/bin/bootloader_dout_40m.elf index b2bf118a68e..ffa4cc6909d 100755 Binary files a/tools/sdk/esp32c3/bin/bootloader_dout_40m.elf and b/tools/sdk/esp32c3/bin/bootloader_dout_40m.elf differ diff --git a/tools/sdk/esp32c3/bin/bootloader_dout_80m.elf b/tools/sdk/esp32c3/bin/bootloader_dout_80m.elf index b2bf118a68e..ffa4cc6909d 100755 Binary files a/tools/sdk/esp32c3/bin/bootloader_dout_80m.elf and b/tools/sdk/esp32c3/bin/bootloader_dout_80m.elf differ diff --git a/tools/sdk/esp32c3/bin/bootloader_qio_40m.elf b/tools/sdk/esp32c3/bin/bootloader_qio_40m.elf index 3f04f777c98..79e67400718 100755 Binary files a/tools/sdk/esp32c3/bin/bootloader_qio_40m.elf and b/tools/sdk/esp32c3/bin/bootloader_qio_40m.elf differ diff --git a/tools/sdk/esp32c3/bin/bootloader_qio_80m.elf b/tools/sdk/esp32c3/bin/bootloader_qio_80m.elf index 3f04f777c98..79e67400718 100755 Binary files a/tools/sdk/esp32c3/bin/bootloader_qio_80m.elf and b/tools/sdk/esp32c3/bin/bootloader_qio_80m.elf differ diff --git a/tools/sdk/esp32c3/bin/bootloader_qout_40m.elf b/tools/sdk/esp32c3/bin/bootloader_qout_40m.elf index 6f7833fb21b..bdb5ed06687 100755 Binary files a/tools/sdk/esp32c3/bin/bootloader_qout_40m.elf and b/tools/sdk/esp32c3/bin/bootloader_qout_40m.elf differ diff --git a/tools/sdk/esp32c3/bin/bootloader_qout_80m.elf b/tools/sdk/esp32c3/bin/bootloader_qout_80m.elf index 6f7833fb21b..bdb5ed06687 100755 Binary files a/tools/sdk/esp32c3/bin/bootloader_qout_80m.elf and b/tools/sdk/esp32c3/bin/bootloader_qout_80m.elf differ diff --git a/tools/sdk/esp32c3/dio_qspi/include/sdkconfig.h b/tools/sdk/esp32c3/dio_qspi/include/sdkconfig.h index cb32f065278..d0c58f64a27 100644 --- a/tools/sdk/esp32c3/dio_qspi/include/sdkconfig.h +++ b/tools/sdk/esp32c3/dio_qspi/include/sdkconfig.h @@ -191,6 +191,8 @@ #define CONFIG_SOC_EFUSE_DIS_USB_JTAG 1 #define CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT 1 #define CONFIG_SOC_EFUSE_SOFT_DIS_JTAG 1 +#define CONFIG_SOC_EFUSE_DIS_ICACHE 1 +#define CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 #define CONFIG_SOC_SECURE_BOOT_V2_RSA 1 #define CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 #define CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 @@ -239,6 +241,7 @@ #define CONFIG_SOC_BLE_SUPPORTED 1 #define CONFIG_SOC_BLE_MESH_SUPPORTED 1 #define CONFIG_SOC_BLE_50_SUPPORTED 1 +#define CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED 1 #define CONFIG_IDF_CMAKE 1 #define CONFIG_IDF_TARGET_ARCH_RISCV 1 #define CONFIG_IDF_TARGET_ARCH "riscv" @@ -259,6 +262,7 @@ #define CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE 1 #define CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP 1 #define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x10 +#define CONFIG_BOOTLOADER_RESERVE_RTC_MEM 1 #define CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT 1 #define CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED 1 #define CONFIG_SECURE_BOOT_V2_PREFERRED 1 @@ -432,13 +436,12 @@ #define CONFIG_BT_SMP_ENABLE 1 #define CONFIG_BT_BLE_ESTAB_LINK_CONN_TOUT 30 #define CONFIG_BT_MAX_DEVICE_NAME_LEN 32 -#define CONFIG_BT_BLE_RPA_SUPPORTED 1 #define CONFIG_BT_BLE_RPA_TIMEOUT 900 #define CONFIG_BT_BLE_50_FEATURES_SUPPORTED 1 #define CONFIG_BT_BLE_42_FEATURES_SUPPORTED 1 #define CONFIG_BT_CTRL_MODE_EFF 1 -#define CONFIG_BT_CTRL_BLE_MAX_ACT 10 -#define CONFIG_BT_CTRL_BLE_MAX_ACT_EFF 10 +#define CONFIG_BT_CTRL_BLE_MAX_ACT 6 +#define CONFIG_BT_CTRL_BLE_MAX_ACT_EFF 6 #define CONFIG_BT_CTRL_BLE_STATIC_ACL_TX_BUF_NB 0 #define CONFIG_BT_CTRL_PINNED_TO_CORE 0 #define CONFIG_BT_CTRL_HCI_MODE_VHCI 1 @@ -1110,5 +1113,5 @@ #define CONFIG_WARN_WRITE_STRINGS CONFIG_COMPILER_WARN_WRITE_STRINGS #define CONFIG_WPA_MBEDTLS_CRYPTO CONFIG_ESP_WIFI_MBEDTLS_CRYPTO #define CONFIG_WPA_MBEDTLS_TLS_CLIENT CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT -#define CONFIG_ARDUINO_IDF_COMMIT "" +#define CONFIG_ARDUINO_IDF_COMMIT "420ebd208a" #define CONFIG_ARDUINO_IDF_BRANCH "release/v5.1" diff --git a/tools/sdk/esp32c3/dio_qspi/libspi_flash.a b/tools/sdk/esp32c3/dio_qspi/libspi_flash.a index 94efb1c011e..1b2afafcd74 100644 Binary files a/tools/sdk/esp32c3/dio_qspi/libspi_flash.a and b/tools/sdk/esp32c3/dio_qspi/libspi_flash.a differ diff --git a/tools/sdk/esp32c3/dout_qspi/include/sdkconfig.h b/tools/sdk/esp32c3/dout_qspi/include/sdkconfig.h index 3c13af65ae0..e2ba7c22457 100644 --- a/tools/sdk/esp32c3/dout_qspi/include/sdkconfig.h +++ b/tools/sdk/esp32c3/dout_qspi/include/sdkconfig.h @@ -191,6 +191,8 @@ #define CONFIG_SOC_EFUSE_DIS_USB_JTAG 1 #define CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT 1 #define CONFIG_SOC_EFUSE_SOFT_DIS_JTAG 1 +#define CONFIG_SOC_EFUSE_DIS_ICACHE 1 +#define CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 #define CONFIG_SOC_SECURE_BOOT_V2_RSA 1 #define CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 #define CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 @@ -239,6 +241,7 @@ #define CONFIG_SOC_BLE_SUPPORTED 1 #define CONFIG_SOC_BLE_MESH_SUPPORTED 1 #define CONFIG_SOC_BLE_50_SUPPORTED 1 +#define CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED 1 #define CONFIG_IDF_CMAKE 1 #define CONFIG_IDF_TARGET_ARCH_RISCV 1 #define CONFIG_IDF_TARGET_ARCH "riscv" @@ -259,6 +262,7 @@ #define CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE 1 #define CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP 1 #define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x10 +#define CONFIG_BOOTLOADER_RESERVE_RTC_MEM 1 #define CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT 1 #define CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED 1 #define CONFIG_SECURE_BOOT_V2_PREFERRED 1 @@ -432,13 +436,12 @@ #define CONFIG_BT_SMP_ENABLE 1 #define CONFIG_BT_BLE_ESTAB_LINK_CONN_TOUT 30 #define CONFIG_BT_MAX_DEVICE_NAME_LEN 32 -#define CONFIG_BT_BLE_RPA_SUPPORTED 1 #define CONFIG_BT_BLE_RPA_TIMEOUT 900 #define CONFIG_BT_BLE_50_FEATURES_SUPPORTED 1 #define CONFIG_BT_BLE_42_FEATURES_SUPPORTED 1 #define CONFIG_BT_CTRL_MODE_EFF 1 -#define CONFIG_BT_CTRL_BLE_MAX_ACT 10 -#define CONFIG_BT_CTRL_BLE_MAX_ACT_EFF 10 +#define CONFIG_BT_CTRL_BLE_MAX_ACT 6 +#define CONFIG_BT_CTRL_BLE_MAX_ACT_EFF 6 #define CONFIG_BT_CTRL_BLE_STATIC_ACL_TX_BUF_NB 0 #define CONFIG_BT_CTRL_PINNED_TO_CORE 0 #define CONFIG_BT_CTRL_HCI_MODE_VHCI 1 @@ -1110,5 +1113,5 @@ #define CONFIG_WARN_WRITE_STRINGS CONFIG_COMPILER_WARN_WRITE_STRINGS #define CONFIG_WPA_MBEDTLS_CRYPTO CONFIG_ESP_WIFI_MBEDTLS_CRYPTO #define CONFIG_WPA_MBEDTLS_TLS_CLIENT CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT -#define CONFIG_ARDUINO_IDF_COMMIT "" +#define CONFIG_ARDUINO_IDF_COMMIT "420ebd208a" #define CONFIG_ARDUINO_IDF_BRANCH "release/v5.1" diff --git a/tools/sdk/esp32c3/dout_qspi/libspi_flash.a b/tools/sdk/esp32c3/dout_qspi/libspi_flash.a index 06435c1cfa5..9342e90480a 100644 Binary files a/tools/sdk/esp32c3/dout_qspi/libspi_flash.a and b/tools/sdk/esp32c3/dout_qspi/libspi_flash.a differ diff --git a/tools/sdk/esp32c3/flags/defines b/tools/sdk/esp32c3/flags/defines index 5847d2162fb..2c8b36ae704 100644 --- a/tools/sdk/esp32c3/flags/defines +++ b/tools/sdk/esp32c3/flags/defines @@ -1 +1 @@ --DESP_PLATFORM -DIDF_VER=\"v5.1-dev-4124-gbb9200acec\" -DMBEDTLS_CONFIG_FILE=\"mbedtls/esp_config.h\" -DSOC_MMU_PAGE_SIZE=CONFIG_MMU_PAGE_SIZE -DUNITY_INCLUDE_CONFIG_H -D_GNU_SOURCE -D_POSIX_READER_WRITER_LOCKS -DconfigENABLE_FREERTOS_DEBUG_OCDAWARE=1 \ No newline at end of file +-DESP_PLATFORM -DIDF_VER=\"v5.1-dev-4528-g420ebd208a\" -DMBEDTLS_CONFIG_FILE=\"mbedtls/esp_config.h\" -DSOC_MMU_PAGE_SIZE=CONFIG_MMU_PAGE_SIZE -DUNITY_INCLUDE_CONFIG_H -D_GNU_SOURCE -D_POSIX_READER_WRITER_LOCKS -DconfigENABLE_FREERTOS_DEBUG_OCDAWARE=1 \ No newline at end of file diff --git a/tools/sdk/esp32c3/flags/includes b/tools/sdk/esp32c3/flags/includes index 169367e8fa1..8805e1b382d 100644 --- a/tools/sdk/esp32c3/flags/includes +++ b/tools/sdk/esp32c3/flags/includes @@ -1 +1 @@ --iwithprefixbefore newlib/platform_include -iwithprefixbefore freertos/FreeRTOS-Kernel/include -iwithprefixbefore freertos/FreeRTOS-Kernel/portable/riscv/include -iwithprefixbefore freertos/esp_additions/include/freertos -iwithprefixbefore freertos/esp_additions/include -iwithprefixbefore esp_hw_support/include -iwithprefixbefore esp_hw_support/include/soc -iwithprefixbefore esp_hw_support/include/soc/esp32c3 -iwithprefixbefore esp_hw_support/port/esp32c3 -iwithprefixbefore heap/include -iwithprefixbefore log/include -iwithprefixbefore soc/include -iwithprefixbefore soc/esp32c3 -iwithprefixbefore soc/esp32c3/include -iwithprefixbefore hal/esp32c3/include -iwithprefixbefore hal/include -iwithprefixbefore hal/platform_port/include -iwithprefixbefore esp_rom/include -iwithprefixbefore esp_rom/include/esp32c3 -iwithprefixbefore esp_rom/esp32c3 -iwithprefixbefore esp_common/include -iwithprefixbefore esp_system/include -iwithprefixbefore esp_system/port/soc -iwithprefixbefore esp_system/port/include/riscv -iwithprefixbefore esp_system/port/include/private -iwithprefixbefore riscv/include -iwithprefixbefore lwip/include -iwithprefixbefore lwip/include/apps -iwithprefixbefore lwip/include/apps/sntp -iwithprefixbefore lwip/lwip/src/include -iwithprefixbefore lwip/port/include -iwithprefixbefore lwip/port/freertos/include -iwithprefixbefore lwip/port/esp32xx/include -iwithprefixbefore lwip/port/esp32xx/include/arch -iwithprefixbefore espressif__mdns/include -iwithprefixbefore console -iwithprefixbefore vfs/include -iwithprefixbefore esp_netif/include -iwithprefixbefore esp_event/include -iwithprefixbefore esp_ringbuf/include -iwithprefixbefore efuse/include -iwithprefixbefore efuse/esp32c3/include -iwithprefixbefore driver/include -iwithprefixbefore driver/deprecated -iwithprefixbefore driver/analog_comparator/include -iwithprefixbefore driver/dac/include -iwithprefixbefore driver/gpio/include -iwithprefixbefore driver/gptimer/include -iwithprefixbefore driver/i2c/include -iwithprefixbefore driver/i2s/include -iwithprefixbefore driver/ledc/include -iwithprefixbefore driver/mcpwm/include -iwithprefixbefore driver/parlio/include -iwithprefixbefore driver/pcnt/include -iwithprefixbefore driver/rmt/include -iwithprefixbefore driver/sdio_slave/include -iwithprefixbefore driver/sdmmc/include -iwithprefixbefore driver/sigma_delta/include -iwithprefixbefore driver/spi/include -iwithprefixbefore driver/temperature_sensor/include -iwithprefixbefore driver/touch_sensor/include -iwithprefixbefore driver/twai/include -iwithprefixbefore driver/uart/include -iwithprefixbefore driver/usb_serial_jtag/include -iwithprefixbefore esp_pm/include -iwithprefixbefore mbedtls/port/include -iwithprefixbefore mbedtls/mbedtls/include -iwithprefixbefore mbedtls/mbedtls/library -iwithprefixbefore mbedtls/esp_crt_bundle/include -iwithprefixbefore esp_app_format/include -iwithprefixbefore bootloader_support/include -iwithprefixbefore bootloader_support/bootloader_flash/include -iwithprefixbefore esp_partition/include -iwithprefixbefore app_update/include -iwithprefixbefore esp_mm/include -iwithprefixbefore spi_flash/include -iwithprefixbefore pthread/include -iwithprefixbefore esp_timer/include -iwithprefixbefore app_trace/include -iwithprefixbefore nvs_flash/include -iwithprefixbefore esp_phy/include -iwithprefixbefore esp_phy/esp32c3/include -iwithprefixbefore wpa_supplicant/include -iwithprefixbefore wpa_supplicant/port/include -iwithprefixbefore wpa_supplicant/esp_supplicant/include -iwithprefixbefore esp_coex/include -iwithprefixbefore esp_wifi/include -iwithprefixbefore esp_wifi/wifi_apps/include -iwithprefixbefore bt/include/esp32c3/include -iwithprefixbefore bt/common/osi/include -iwithprefixbefore bt/common/api/include/api -iwithprefixbefore bt/common/btc/profile/esp/blufi/include -iwithprefixbefore bt/common/btc/profile/esp/include -iwithprefixbefore bt/host/bluedroid/api/include/api -iwithprefixbefore bt/esp_ble_mesh/mesh_common/include -iwithprefixbefore bt/esp_ble_mesh/mesh_common/tinycrypt/include -iwithprefixbefore bt/esp_ble_mesh/mesh_core -iwithprefixbefore bt/esp_ble_mesh/mesh_core/include -iwithprefixbefore bt/esp_ble_mesh/mesh_core/storage -iwithprefixbefore bt/esp_ble_mesh/btc/include -iwithprefixbefore bt/esp_ble_mesh/mesh_models/common/include -iwithprefixbefore bt/esp_ble_mesh/mesh_models/client/include -iwithprefixbefore bt/esp_ble_mesh/mesh_models/server/include -iwithprefixbefore bt/esp_ble_mesh/api/core/include -iwithprefixbefore bt/esp_ble_mesh/api/models/include -iwithprefixbefore bt/esp_ble_mesh/api -iwithprefixbefore bt/porting/ext/tinycrypt/include -iwithprefixbefore unity/include -iwithprefixbefore unity/unity/src -iwithprefixbefore cmock/CMock/src -iwithprefixbefore http_parser -iwithprefixbefore esp-tls -iwithprefixbefore esp-tls/esp-tls-crypto -iwithprefixbefore esp_adc/include -iwithprefixbefore esp_adc/interface -iwithprefixbefore esp_adc/esp32c3/include -iwithprefixbefore esp_adc/deprecated/include -iwithprefixbefore esp_eth/include -iwithprefixbefore esp_gdbstub/include -iwithprefixbefore esp_gdbstub/riscv -iwithprefixbefore esp_gdbstub/esp32c3 -iwithprefixbefore esp_hid/include -iwithprefixbefore tcp_transport/include -iwithprefixbefore esp_http_client/include -iwithprefixbefore esp_http_server/include -iwithprefixbefore esp_https_ota/include -iwithprefixbefore esp_https_server/include -iwithprefixbefore esp_lcd/include -iwithprefixbefore esp_lcd/interface -iwithprefixbefore protobuf-c/protobuf-c -iwithprefixbefore protocomm/include/common -iwithprefixbefore protocomm/include/security -iwithprefixbefore protocomm/include/transports -iwithprefixbefore esp_local_ctrl/include -iwithprefixbefore esp_psram/include -iwithprefixbefore espcoredump/include -iwithprefixbefore espcoredump/include/port/riscv -iwithprefixbefore wear_levelling/include -iwithprefixbefore sdmmc/include -iwithprefixbefore fatfs/diskio -iwithprefixbefore fatfs/vfs -iwithprefixbefore fatfs/src -iwithprefixbefore idf_test/include -iwithprefixbefore idf_test/include/esp32c3 -iwithprefixbefore ieee802154/include -iwithprefixbefore json/cJSON -iwithprefixbefore mqtt/esp-mqtt/include -iwithprefixbefore spiffs/include -iwithprefixbefore wifi_provisioning/include -iwithprefixbefore cbor/port/include -iwithprefixbefore rmaker_common/include -iwithprefixbefore esp_diagnostics/include -iwithprefixbefore rtc_store/include -iwithprefixbefore esp_insights/include -iwithprefixbefore json_parser/upstream/include -iwithprefixbefore json_parser/upstream -iwithprefixbefore json_generator/upstream -iwithprefixbefore esp_schedule/include -iwithprefixbefore espressif__esp_secure_cert_mgr/include -iwithprefixbefore esp_rainmaker/include -iwithprefixbefore gpio_button/button/include -iwithprefixbefore qrcode/include -iwithprefixbefore ws2812_led -iwithprefixbefore esp_littlefs/include -iwithprefixbefore esp-dl/include -iwithprefixbefore esp-dl/include/tool -iwithprefixbefore esp-dl/include/typedef -iwithprefixbefore esp-dl/include/image -iwithprefixbefore esp-dl/include/math -iwithprefixbefore esp-dl/include/nn -iwithprefixbefore esp-dl/include/layer -iwithprefixbefore esp-dl/include/detect -iwithprefixbefore esp-dl/include/model_zoo -iwithprefixbefore esp-sr/esp-tts/esp_tts_chinese/include -iwithprefixbefore esp32-camera/driver/include -iwithprefixbefore esp32-camera/conversions/include -iwithprefixbefore espressif__esp-dsp/modules/dotprod/include -iwithprefixbefore espressif__esp-dsp/modules/support/include -iwithprefixbefore espressif__esp-dsp/modules/windows/include -iwithprefixbefore espressif__esp-dsp/modules/windows/hann/include -iwithprefixbefore espressif__esp-dsp/modules/windows/blackman/include -iwithprefixbefore espressif__esp-dsp/modules/windows/blackman_harris/include -iwithprefixbefore espressif__esp-dsp/modules/windows/blackman_nuttall/include -iwithprefixbefore espressif__esp-dsp/modules/windows/nuttall/include -iwithprefixbefore espressif__esp-dsp/modules/windows/flat_top/include -iwithprefixbefore espressif__esp-dsp/modules/iir/include -iwithprefixbefore espressif__esp-dsp/modules/fir/include -iwithprefixbefore espressif__esp-dsp/modules/math/include -iwithprefixbefore espressif__esp-dsp/modules/math/add/include -iwithprefixbefore espressif__esp-dsp/modules/math/sub/include -iwithprefixbefore espressif__esp-dsp/modules/math/mul/include -iwithprefixbefore espressif__esp-dsp/modules/math/addc/include -iwithprefixbefore espressif__esp-dsp/modules/math/mulc/include -iwithprefixbefore espressif__esp-dsp/modules/math/sqrt/include -iwithprefixbefore espressif__esp-dsp/modules/matrix/include -iwithprefixbefore espressif__esp-dsp/modules/fft/include -iwithprefixbefore espressif__esp-dsp/modules/dct/include -iwithprefixbefore espressif__esp-dsp/modules/conv/include -iwithprefixbefore espressif__esp-dsp/modules/common/include -iwithprefixbefore espressif__esp-dsp/modules/kalman/ekf/include -iwithprefixbefore espressif__esp-dsp/modules/kalman/ekf_imu13states/include -iwithprefixbefore fb_gfx/include \ No newline at end of file +-iwithprefixbefore newlib/platform_include -iwithprefixbefore freertos/FreeRTOS-Kernel/include -iwithprefixbefore freertos/FreeRTOS-Kernel/portable/riscv/include -iwithprefixbefore freertos/esp_additions/include/freertos -iwithprefixbefore freertos/esp_additions/include -iwithprefixbefore freertos/esp_additions/arch/riscv/include -iwithprefixbefore esp_hw_support/include -iwithprefixbefore esp_hw_support/include/soc -iwithprefixbefore esp_hw_support/include/soc/esp32c3 -iwithprefixbefore esp_hw_support/port/esp32c3 -iwithprefixbefore heap/include -iwithprefixbefore log/include -iwithprefixbefore soc/include -iwithprefixbefore soc/esp32c3 -iwithprefixbefore soc/esp32c3/include -iwithprefixbefore hal/esp32c3/include -iwithprefixbefore hal/include -iwithprefixbefore hal/platform_port/include -iwithprefixbefore esp_rom/include -iwithprefixbefore esp_rom/include/esp32c3 -iwithprefixbefore esp_rom/esp32c3 -iwithprefixbefore esp_common/include -iwithprefixbefore esp_system/include -iwithprefixbefore esp_system/port/soc -iwithprefixbefore esp_system/port/include/riscv -iwithprefixbefore esp_system/port/include/private -iwithprefixbefore riscv/include -iwithprefixbefore lwip/include -iwithprefixbefore lwip/include/apps -iwithprefixbefore lwip/include/apps/sntp -iwithprefixbefore lwip/lwip/src/include -iwithprefixbefore lwip/port/include -iwithprefixbefore lwip/port/freertos/include -iwithprefixbefore lwip/port/esp32xx/include -iwithprefixbefore lwip/port/esp32xx/include/arch -iwithprefixbefore espressif__mdns/include -iwithprefixbefore console -iwithprefixbefore vfs/include -iwithprefixbefore esp_netif/include -iwithprefixbefore esp_event/include -iwithprefixbefore esp_ringbuf/include -iwithprefixbefore efuse/include -iwithprefixbefore efuse/esp32c3/include -iwithprefixbefore driver/include -iwithprefixbefore driver/deprecated -iwithprefixbefore driver/analog_comparator/include -iwithprefixbefore driver/dac/include -iwithprefixbefore driver/gpio/include -iwithprefixbefore driver/gptimer/include -iwithprefixbefore driver/i2c/include -iwithprefixbefore driver/i2s/include -iwithprefixbefore driver/ledc/include -iwithprefixbefore driver/mcpwm/include -iwithprefixbefore driver/parlio/include -iwithprefixbefore driver/pcnt/include -iwithprefixbefore driver/rmt/include -iwithprefixbefore driver/sdio_slave/include -iwithprefixbefore driver/sdmmc/include -iwithprefixbefore driver/sigma_delta/include -iwithprefixbefore driver/spi/include -iwithprefixbefore driver/temperature_sensor/include -iwithprefixbefore driver/touch_sensor/include -iwithprefixbefore driver/twai/include -iwithprefixbefore driver/uart/include -iwithprefixbefore driver/usb_serial_jtag/include -iwithprefixbefore esp_pm/include -iwithprefixbefore mbedtls/port/include -iwithprefixbefore mbedtls/mbedtls/include -iwithprefixbefore mbedtls/mbedtls/library -iwithprefixbefore mbedtls/esp_crt_bundle/include -iwithprefixbefore esp_app_format/include -iwithprefixbefore bootloader_support/include -iwithprefixbefore bootloader_support/bootloader_flash/include -iwithprefixbefore esp_partition/include -iwithprefixbefore app_update/include -iwithprefixbefore esp_mm/include -iwithprefixbefore spi_flash/include -iwithprefixbefore pthread/include -iwithprefixbefore esp_timer/include -iwithprefixbefore app_trace/include -iwithprefixbefore nvs_flash/include -iwithprefixbefore esp_phy/include -iwithprefixbefore esp_phy/esp32c3/include -iwithprefixbefore wpa_supplicant/include -iwithprefixbefore wpa_supplicant/port/include -iwithprefixbefore wpa_supplicant/esp_supplicant/include -iwithprefixbefore esp_coex/include -iwithprefixbefore esp_wifi/include -iwithprefixbefore esp_wifi/wifi_apps/include -iwithprefixbefore bt/include/esp32c3/include -iwithprefixbefore bt/common/osi/include -iwithprefixbefore bt/common/api/include/api -iwithprefixbefore bt/common/btc/profile/esp/blufi/include -iwithprefixbefore bt/common/btc/profile/esp/include -iwithprefixbefore bt/host/bluedroid/api/include/api -iwithprefixbefore bt/esp_ble_mesh/mesh_common/include -iwithprefixbefore bt/esp_ble_mesh/mesh_common/tinycrypt/include -iwithprefixbefore bt/esp_ble_mesh/mesh_core -iwithprefixbefore bt/esp_ble_mesh/mesh_core/include -iwithprefixbefore bt/esp_ble_mesh/mesh_core/storage -iwithprefixbefore bt/esp_ble_mesh/btc/include -iwithprefixbefore bt/esp_ble_mesh/mesh_models/common/include -iwithprefixbefore bt/esp_ble_mesh/mesh_models/client/include -iwithprefixbefore bt/esp_ble_mesh/mesh_models/server/include -iwithprefixbefore bt/esp_ble_mesh/api/core/include -iwithprefixbefore bt/esp_ble_mesh/api/models/include -iwithprefixbefore bt/esp_ble_mesh/api -iwithprefixbefore bt/porting/ext/tinycrypt/include -iwithprefixbefore unity/include -iwithprefixbefore unity/unity/src -iwithprefixbefore cmock/CMock/src -iwithprefixbefore http_parser -iwithprefixbefore esp-tls -iwithprefixbefore esp-tls/esp-tls-crypto -iwithprefixbefore esp_adc/include -iwithprefixbefore esp_adc/interface -iwithprefixbefore esp_adc/esp32c3/include -iwithprefixbefore esp_adc/deprecated/include -iwithprefixbefore esp_eth/include -iwithprefixbefore esp_gdbstub/include -iwithprefixbefore esp_gdbstub/riscv -iwithprefixbefore esp_gdbstub/esp32c3 -iwithprefixbefore esp_hid/include -iwithprefixbefore tcp_transport/include -iwithprefixbefore esp_http_client/include -iwithprefixbefore esp_http_server/include -iwithprefixbefore esp_https_ota/include -iwithprefixbefore esp_https_server/include -iwithprefixbefore esp_psram/include -iwithprefixbefore esp_lcd/include -iwithprefixbefore esp_lcd/interface -iwithprefixbefore protobuf-c/protobuf-c -iwithprefixbefore protocomm/include/common -iwithprefixbefore protocomm/include/security -iwithprefixbefore protocomm/include/transports -iwithprefixbefore esp_local_ctrl/include -iwithprefixbefore espcoredump/include -iwithprefixbefore espcoredump/include/port/riscv -iwithprefixbefore wear_levelling/include -iwithprefixbefore sdmmc/include -iwithprefixbefore fatfs/diskio -iwithprefixbefore fatfs/vfs -iwithprefixbefore fatfs/src -iwithprefixbefore idf_test/include -iwithprefixbefore idf_test/include/esp32c3 -iwithprefixbefore ieee802154/include -iwithprefixbefore json/cJSON -iwithprefixbefore mqtt/esp-mqtt/include -iwithprefixbefore spiffs/include -iwithprefixbefore wifi_provisioning/include -iwithprefixbefore cbor/port/include -iwithprefixbefore rmaker_common/include -iwithprefixbefore esp_diagnostics/include -iwithprefixbefore rtc_store/include -iwithprefixbefore esp_insights/include -iwithprefixbefore json_parser/upstream/include -iwithprefixbefore json_parser/upstream -iwithprefixbefore json_generator/upstream -iwithprefixbefore esp_schedule/include -iwithprefixbefore espressif__esp_secure_cert_mgr/include -iwithprefixbefore esp_rainmaker/include -iwithprefixbefore gpio_button/button/include -iwithprefixbefore qrcode/include -iwithprefixbefore ws2812_led -iwithprefixbefore esp_littlefs/include -iwithprefixbefore esp-dl/include -iwithprefixbefore esp-dl/include/tool -iwithprefixbefore esp-dl/include/typedef -iwithprefixbefore esp-dl/include/image -iwithprefixbefore esp-dl/include/math -iwithprefixbefore esp-dl/include/nn -iwithprefixbefore esp-dl/include/layer -iwithprefixbefore esp-dl/include/detect -iwithprefixbefore esp-dl/include/model_zoo -iwithprefixbefore espressif__esp-dsp/modules/dotprod/include -iwithprefixbefore espressif__esp-dsp/modules/support/include -iwithprefixbefore espressif__esp-dsp/modules/windows/include -iwithprefixbefore espressif__esp-dsp/modules/windows/hann/include -iwithprefixbefore espressif__esp-dsp/modules/windows/blackman/include -iwithprefixbefore espressif__esp-dsp/modules/windows/blackman_harris/include -iwithprefixbefore espressif__esp-dsp/modules/windows/blackman_nuttall/include -iwithprefixbefore espressif__esp-dsp/modules/windows/nuttall/include -iwithprefixbefore espressif__esp-dsp/modules/windows/flat_top/include -iwithprefixbefore espressif__esp-dsp/modules/iir/include -iwithprefixbefore espressif__esp-dsp/modules/fir/include -iwithprefixbefore espressif__esp-dsp/modules/math/include -iwithprefixbefore espressif__esp-dsp/modules/math/add/include -iwithprefixbefore espressif__esp-dsp/modules/math/sub/include -iwithprefixbefore espressif__esp-dsp/modules/math/mul/include -iwithprefixbefore espressif__esp-dsp/modules/math/addc/include -iwithprefixbefore espressif__esp-dsp/modules/math/mulc/include -iwithprefixbefore espressif__esp-dsp/modules/math/sqrt/include -iwithprefixbefore espressif__esp-dsp/modules/matrix/include -iwithprefixbefore espressif__esp-dsp/modules/fft/include -iwithprefixbefore espressif__esp-dsp/modules/dct/include -iwithprefixbefore espressif__esp-dsp/modules/conv/include -iwithprefixbefore espressif__esp-dsp/modules/common/include -iwithprefixbefore espressif__esp-dsp/modules/kalman/ekf/include -iwithprefixbefore espressif__esp-dsp/modules/kalman/ekf_imu13states/include -iwithprefixbefore esp-sr/esp-tts/esp_tts_chinese/include -iwithprefixbefore esp32-camera/driver/include -iwithprefixbefore esp32-camera/conversions/include -iwithprefixbefore fb_gfx/include \ No newline at end of file diff --git a/tools/sdk/esp32c3/flags/ld_flags b/tools/sdk/esp32c3/flags/ld_flags index 94a3ff59c60..5c20080e823 100644 --- a/tools/sdk/esp32c3/flags/ld_flags +++ b/tools/sdk/esp32c3/flags/ld_flags @@ -1 +1 @@ --nostartfiles -march=rv32imc_zicsr_zifencei --specs=nosys.specs -Wl,--cref -Wl,--defsym=IDF_TARGET_ESP32C3=0 -Wl,--no-warn-rwx-segments -fno-rtti -fno-lto -Wl,--gc-sections -Wl,--warn-common -Wl,--wrap=esp_log_write -Wl,--wrap=esp_log_writev -Wl,--wrap=log_printf -u _Z5setupv -u _Z4loopv -u esp_app_desc -u pthread_include_pthread_impl -u pthread_include_pthread_cond_impl -u pthread_include_pthread_local_storage_impl -u pthread_include_pthread_rwlock_impl -u start_app -u __ubsan_include -u __assert_func -Wl,--undefined=uxTopUsedPriority -Wl,--undefined=FreeRTOS_openocd_params -u app_main -u newlib_include_heap_impl -u newlib_include_syscalls_impl -u newlib_include_pthread_impl -u newlib_include_assert_impl -u __cxa_guard_dummy -u include_esp_phy_override -u vfs_include_syscalls_impl \ No newline at end of file +-nostartfiles -march=rv32imc_zicsr_zifencei --specs=nosys.specs -Wl,--cref -Wl,--defsym=IDF_TARGET_ESP32C3=0 -Wl,--no-warn-rwx-segments -fno-rtti -fno-lto -Wl,--gc-sections -Wl,--warn-common -Wl,--wrap=esp_log_write -Wl,--wrap=esp_log_writev -Wl,--wrap=log_printf -u _Z5setupv -u _Z4loopv -u esp_app_desc -u pthread_include_pthread_impl -u pthread_include_pthread_cond_impl -u pthread_include_pthread_local_storage_impl -u pthread_include_pthread_rwlock_impl -u pthread_include_pthread_semaphore_impl -u start_app -u __ubsan_include -u __assert_func -Wl,--undefined=uxTopUsedPriority -Wl,--undefined=FreeRTOS_openocd_params -u app_main -u newlib_include_heap_impl -u newlib_include_syscalls_impl -u newlib_include_pthread_impl -u newlib_include_assert_impl -u __cxa_guard_dummy -u include_esp_phy_override -u vfs_include_syscalls_impl \ No newline at end of file diff --git a/tools/sdk/esp32c3/flags/ld_libs b/tools/sdk/esp32c3/flags/ld_libs index 59dabfaf39c..e4cafe01ec0 100644 --- a/tools/sdk/esp32c3/flags/ld_libs +++ b/tools/sdk/esp32c3/flags/ld_libs @@ -1 +1 @@ --lriscv -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lapp_trace -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lbt -lunity -lcmock -lconsole -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -lesp_hid -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_https_server -lesp_lcd -lprotobuf-c -lprotocomm -lesp_local_ctrl -lespcoredump -lwear_levelling -lsdmmc -lfatfs -ljson -lmqtt -lspiffs -lwifi_provisioning -lespressif__mdns -lcbor -lrmaker_common -lesp_diagnostics -lrtc_store -lesp_insights -ljson_parser -ljson_generator -lesp_schedule -lespressif__esp_secure_cert_mgr -lesp_rainmaker -lgpio_button -lqrcode -lws2812_led -lesp32-camera -lesp_littlefs -lespressif__esp-dsp -lfb_gfx -lapp_trace -lapp_trace -lcmock -lunity -lesp_lcd -lesp_hid -lfatfs -lwear_levelling -lsdmmc -lesp_insights -lcbor -lesp_diagnostics -lrtc_store -lesp_rainmaker -lesp_local_ctrl -lesp_https_server -lwifi_provisioning -lprotocomm -lbt -lbtdm_app -lprotobuf-c -ljson -lespressif__mdns -ljson_parser -ljson_generator -lesp_schedule -lespressif__esp_secure_cert_mgr -lqrcode -lrmaker_common -lconsole -lmqtt -lcat_face_detect -lhuman_face_detect -lcolor_detect -lmfn -ldl -lspiffs -lesp_tts_chinese -lvoice_set_xiaole -lriscv -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lespcoredump -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lriscv -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lespcoredump -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lriscv -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lespcoredump -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lriscv -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lespcoredump -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lriscv -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lespcoredump -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lriscv -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lespcoredump -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lc -lm -lnewlib -lstdc++ -lpthread -lgcc -lcxx -lphy -lbtbb -lesp_phy -lphy -lbtbb -lesp_phy -lphy -lbtbb \ No newline at end of file +-lriscv -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lapp_trace -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lbt -lunity -lcmock -lconsole -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -lesp_hid -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_https_server -lesp_lcd -lprotobuf-c -lprotocomm -lesp_local_ctrl -lespcoredump -lwear_levelling -lsdmmc -lfatfs -ljson -lmqtt -lspiffs -lwifi_provisioning -lespressif__mdns -lcbor -lrmaker_common -lesp_diagnostics -lrtc_store -lesp_insights -ljson_parser -ljson_generator -lesp_schedule -lespressif__esp_secure_cert_mgr -lesp_rainmaker -lgpio_button -lqrcode -lws2812_led -lespressif__esp-dsp -lesp32-camera -lesp_littlefs -lfb_gfx -lapp_trace -lapp_trace -lcmock -lunity -lesp_lcd -lesp_hid -lfatfs -lwear_levelling -lsdmmc -lesp_insights -lcbor -lesp_diagnostics -lrtc_store -lesp_rainmaker -lesp_local_ctrl -lesp_https_server -lwifi_provisioning -lprotocomm -lbt -lbtdm_app -lprotobuf-c -ljson -lespressif__mdns -ljson_parser -ljson_generator -lesp_schedule -lespressif__esp_secure_cert_mgr -lqrcode -lrmaker_common -lconsole -lmqtt -lcat_face_detect -lhuman_face_detect -lcolor_detect -lmfn -ldl -lspiffs -lespressif__esp-dsp -lesp_tts_chinese -lvoice_set_xiaole -lriscv -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lespcoredump -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lriscv -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lespcoredump -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lriscv -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lespcoredump -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lriscv -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lespcoredump -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lriscv -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lespcoredump -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lriscv -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lespcoredump -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lc -lm -lnewlib -lstdc++ -lpthread -lgcc -lcxx -lphy -lbtbb -lesp_phy -lphy -lbtbb -lesp_phy -lphy -lbtbb \ No newline at end of file diff --git a/tools/sdk/esp32c3/include/bootloader_support/include/bootloader_common.h b/tools/sdk/esp32c3/include/bootloader_support/include/bootloader_common.h index 6145a72ef8e..b74acf560c7 100644 --- a/tools/sdk/esp32c3/include/bootloader_support/include/bootloader_common.h +++ b/tools/sdk/esp32c3/include/bootloader_support/include/bootloader_common.h @@ -173,7 +173,7 @@ esp_err_t bootloader_common_check_chip_validity(const esp_image_header_t* img_hd */ void bootloader_common_vddsdio_configure(void); -#if defined( CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP ) || defined( CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC ) +#if CONFIG_BOOTLOADER_RESERVE_RTC_MEM /** * @brief Returns partition from rtc_retain_mem * @@ -223,6 +223,21 @@ void bootloader_common_reset_rtc_retain_mem(void); */ uint16_t bootloader_common_get_rtc_retain_mem_reboot_counter(void); +/** + * @brief Returns True if Factory reset has happened + * + * Reset the status after reading it. + * + * @return True: Factory reset has happened + * False: No Factory reset + */ +bool bootloader_common_get_rtc_retain_mem_factory_reset_state(void); + +/** + * @brief Sets Factory reset status + */ +void bootloader_common_set_rtc_retain_mem_factory_reset_state(void); + /** * @brief Returns rtc_retain_mem * @@ -233,7 +248,7 @@ uint16_t bootloader_common_get_rtc_retain_mem_reboot_counter(void); */ rtc_retain_mem_t* bootloader_common_get_rtc_retain_mem(void); -#endif +#endif // CONFIG_BOOTLOADER_RESERVE_RTC_MEM #ifdef __cplusplus } diff --git a/tools/sdk/esp32c3/include/bootloader_support/include/esp_image_format.h b/tools/sdk/esp32c3/include/bootloader_support/include/esp_image_format.h index 20545f5d7f6..5ec2ff0282f 100644 --- a/tools/sdk/esp32c3/include/bootloader_support/include/esp_image_format.h +++ b/tools/sdk/esp32c3/include/bootloader_support/include/esp_image_format.h @@ -47,7 +47,14 @@ typedef enum { typedef struct { esp_partition_pos_t partition; /*!< Partition of application which worked before goes to the deep sleep. */ uint16_t reboot_counter; /*!< Reboot counter. Reset only when power is off. */ - uint16_t reserve; /*!< Reserve */ + union { + struct { + uint8_t factory_reset_state : 1; /* True when Factory reset has occurred */ + uint8_t reserve : 7; /* Reserve */ + }; + uint8_t val; + } flags; + uint8_t reserve; /*!< Reserve */ #ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC uint8_t custom[CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE]; /*!< Reserve for custom propose */ #endif @@ -57,6 +64,8 @@ typedef struct { ESP_STATIC_ASSERT(offsetof(rtc_retain_mem_t, crc) == sizeof(rtc_retain_mem_t) - sizeof(uint32_t), "CRC field must be the last field of rtc_retain_mem_t structure"); +#ifdef CONFIG_BOOTLOADER_RESERVE_RTC_MEM + #ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC ESP_STATIC_ASSERT(CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE % 4 == 0, "CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE must be a multiple of 4 bytes"); /* The custom field must be the penultimate field */ @@ -64,19 +73,16 @@ ESP_STATIC_ASSERT(offsetof(rtc_retain_mem_t, custom) == sizeof(rtc_retain_mem_t) "custom field in rtc_retain_mem_t structure must be the field before the CRC one"); #endif -#if defined(CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP) || defined(CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC) ESP_STATIC_ASSERT(CONFIG_BOOTLOADER_RESERVE_RTC_SIZE % 4 == 0, "CONFIG_BOOTLOADER_RESERVE_RTC_SIZE must be a multiple of 4 bytes"); -#endif #ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC #define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE + CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE) -#elif defined(CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP) +#else #define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE) #endif -#if defined(CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP) || defined(CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC) ESP_STATIC_ASSERT(sizeof(rtc_retain_mem_t) <= ESP_BOOTLOADER_RESERVE_RTC, "Reserved RTC area must exceed size of rtc_retain_mem_t"); -#endif +#endif // CONFIG_BOOTLOADER_RESERVE_RTC_MEM /** * @brief Verify an app image. diff --git a/tools/sdk/esp32c3/include/bt/host/bluedroid/api/include/api/esp_gap_bt_api.h b/tools/sdk/esp32c3/include/bt/host/bluedroid/api/include/api/esp_gap_bt_api.h index 76197f81a3e..78d31125ce8 100644 --- a/tools/sdk/esp32c3/include/bt/host/bluedroid/api/include/api/esp_gap_bt_api.h +++ b/tools/sdk/esp32c3/include/bt/host/bluedroid/api/include/api/esp_gap_bt_api.h @@ -576,7 +576,9 @@ esp_err_t esp_bt_gap_config_eir_data(esp_bt_eir_data_t *eir_data); /** * @brief This function is called to set class of device. * The structure esp_bt_gap_cb_t will be called with ESP_BT_GAP_SET_COD_EVT after set COD ends. - * Some profile have special restrictions on class of device, changes may cause these profile do not work. + * This function should be called after Bluetooth profiles are initialized, otherwise the user configured + * class of device can be overwritten. + * Some profiles have special restrictions on class of device, and changes may make these profiles unable to work. * * @param[in] cod - class of device * @param[in] mode - setting mode diff --git a/tools/sdk/esp32c3/include/driver/include/esp_private/spi_common_internal.h b/tools/sdk/esp32c3/include/driver/include/esp_private/spi_common_internal.h index 83b9c1ad6b3..6cc711b5224 100644 --- a/tools/sdk/esp32c3/include/driver/include/esp_private/spi_common_internal.h +++ b/tools/sdk/esp32c3/include/driver/include/esp_private/spi_common_internal.h @@ -13,6 +13,10 @@ #include "freertos/FreeRTOS.h" #include "hal/spi_types.h" #include "esp_pm.h" +#if SOC_GDMA_SUPPORTED +#include "esp_private/gdma.h" +#endif + #ifdef __cplusplus extern "C" @@ -130,6 +134,22 @@ esp_err_t spicommon_dma_chan_alloc(spi_host_device_t host_id, spi_dma_chan_t dma */ esp_err_t spicommon_dma_chan_free(spi_host_device_t host_id); +#if SOC_GDMA_SUPPORTED +/** + * @brief Get SPI GDMA Handle for GMDA Supported Chip + * + * @param host_id SPI host ID + * @param gdma_handle GDMA Handle to Return + * @param gdma_direction GDMA Channel Direction in Enum + * - GDMA_CHANNEL_DIRECTION_TX + * - GDMA_CHANNEL_DIRECTION_RX + * + * @return + * - ESP_OK: On success + */ +esp_err_t spicommon_gdma_get_handle(spi_host_device_t host_id, gdma_channel_handle_t *gdma_handle, gdma_channel_direction_t gdma_direction); +#endif + /** * @brief Connect a SPI peripheral to GPIO pins * diff --git a/tools/sdk/esp32c3/include/driver/ledc/include/driver/ledc.h b/tools/sdk/esp32c3/include/driver/ledc/include/driver/ledc.h index 509b81634d3..c0e2f14530f 100644 --- a/tools/sdk/esp32c3/include/driver/ledc/include/driver/ledc.h +++ b/tools/sdk/esp32c3/include/driver/ledc/include/driver/ledc.h @@ -450,10 +450,10 @@ esp_err_t ledc_fade_start(ledc_mode_t speed_mode, ledc_channel_t channel, ledc_f #if SOC_LEDC_SUPPORT_FADE_STOP /** - * @brief Stop LEDC fading. Duty of the channel will stay at its present vlaue. + * @brief Stop LEDC fading. The duty of the channel is garanteed to be fixed at most one PWM cycle after the function returns. * @note This API can be called if a new fixed duty or a new fade want to be set while the last fade operation is still running in progress. * @note Call this API will abort the fading operation only if it was started by calling ledc_fade_start with LEDC_FADE_NO_WAIT mode. - * @note If a fade was started with LEDC_FADE_WAIT_DONE mode, calling this API afterwards is no use in stopping the fade. Fade will continue until it reachs the target duty. + * @note If a fade was started with LEDC_FADE_WAIT_DONE mode, calling this API afterwards HAS no use in stopping the fade. Fade will continue until it reachs the target duty. * @param speed_mode Select the LEDC channel group with specified speed mode. Note that not all targets support high speed mode. * @param channel LEDC channel number * diff --git a/tools/sdk/esp32c3/include/driver/rmt/include/driver/rmt_rx.h b/tools/sdk/esp32c3/include/driver/rmt/include/driver/rmt_rx.h index c750a59a734..ddb409d94a7 100644 --- a/tools/sdk/esp32c3/include/driver/rmt/include/driver/rmt_rx.h +++ b/tools/sdk/esp32c3/include/driver/rmt/include/driver/rmt_rx.h @@ -29,10 +29,12 @@ typedef struct { * @brief RMT RX channel specific configuration */ typedef struct { - int gpio_num; /*!< GPIO number used by RMT RX channel. Set to -1 if unused */ + gpio_num_t gpio_num; /*!< GPIO number used by RMT RX channel. Set to -1 if unused */ rmt_clock_source_t clk_src; /*!< Clock source of RMT RX channel, channels in the same group must use the same clock source */ uint32_t resolution_hz; /*!< Channel clock resolution, in Hz */ - size_t mem_block_symbols; /*!< Size of memory block, in number of `rmt_symbol_word_t`, must be an even */ + size_t mem_block_symbols; /*!< Size of memory block, in number of `rmt_symbol_word_t`, must be an even. + In the DMA mode, this field controls the DMA buffer size, it can be set to a large value (e.g. 1024); + In the normal mode, this field controls the number of RMT memory block that will be used by the channel. */ struct { uint32_t invert_in: 1; /*!< Whether to invert the incoming RMT channel signal */ uint32_t with_dma: 1; /*!< If set, the driver will allocate an RMT channel with DMA capability */ diff --git a/tools/sdk/esp32c3/include/driver/rmt/include/driver/rmt_tx.h b/tools/sdk/esp32c3/include/driver/rmt/include/driver/rmt_tx.h index 83b1cef392e..9444ae3aabc 100644 --- a/tools/sdk/esp32c3/include/driver/rmt/include/driver/rmt_tx.h +++ b/tools/sdk/esp32c3/include/driver/rmt/include/driver/rmt_tx.h @@ -30,10 +30,12 @@ typedef struct { * @brief RMT TX channel specific configuration */ typedef struct { - int gpio_num; /*!< GPIO number used by RMT TX channel. Set to -1 if unused */ + gpio_num_t gpio_num; /*!< GPIO number used by RMT TX channel. Set to -1 if unused */ rmt_clock_source_t clk_src; /*!< Clock source of RMT TX channel, channels in the same group must use the same clock source */ uint32_t resolution_hz; /*!< Channel clock resolution, in Hz */ - size_t mem_block_symbols; /*!< Size of memory block, in number of `rmt_symbol_word_t`, must be an even */ + size_t mem_block_symbols; /*!< Size of memory block, in number of `rmt_symbol_word_t`, must be an even. + In the DMA mode, this field controls the DMA buffer size, it can be set to a large value; + In the normal mode, this field controls the number of RMT memory block that will be used by the channel. */ size_t trans_queue_depth; /*!< Depth of internal transfer queue, increase this value can support more transfers pending in the background */ struct { uint32_t invert_out: 1; /*!< Whether to invert the RMT channel signal before output to GPIO pad */ diff --git a/tools/sdk/esp32c3/include/driver/rmt/include/driver/rmt_types.h b/tools/sdk/esp32c3/include/driver/rmt/include/driver/rmt_types.h index 2dea896ea67..63032d4d994 100644 --- a/tools/sdk/esp32c3/include/driver/rmt/include/driver/rmt_types.h +++ b/tools/sdk/esp32c3/include/driver/rmt/include/driver/rmt_types.h @@ -10,6 +10,7 @@ #include #include #include "hal/rmt_types.h" +#include "hal/gpio_types.h" // for gpio_num_t #ifdef __cplusplus extern "C" { diff --git a/tools/sdk/esp32c3/include/driver/sdmmc/include/driver/sdmmc_host.h b/tools/sdk/esp32c3/include/driver/sdmmc/include/driver/sdmmc_host.h index 1a4beb892a4..46b6f6af366 100644 --- a/tools/sdk/esp32c3/include/driver/sdmmc/include/driver/sdmmc_host.h +++ b/tools/sdk/esp32c3/include/driver/sdmmc/include/driver/sdmmc_host.h @@ -40,6 +40,7 @@ extern "C" { .get_bus_width = &sdmmc_host_get_slot_width, \ .set_bus_ddr_mode = &sdmmc_host_set_bus_ddr_mode, \ .set_card_clk = &sdmmc_host_set_card_clk, \ + .set_cclk_always_on = &sdmmc_host_set_cclk_always_on, \ .do_transaction = &sdmmc_host_do_transaction, \ .deinit = &sdmmc_host_deinit, \ .io_int_enable = sdmmc_host_io_int_enable, \ @@ -204,6 +205,19 @@ esp_err_t sdmmc_host_set_card_clk(int slot, uint32_t freq_khz); */ esp_err_t sdmmc_host_set_bus_ddr_mode(int slot, bool ddr_enabled); +/** + * @brief Enable or disable always-on card clock + * When cclk_always_on is false, the host controller is allowed to shut down + * the card clock between the commands. When cclk_always_on is true, the clock + * is generated even if no command is in progress. + * @param slot slot number + * @param cclk_always_on enable or disable always-on clock + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_ARG if the slot number is invalid + */ +esp_err_t sdmmc_host_set_cclk_always_on(int slot, bool cclk_always_on); + /** * @brief Send command to the card and get response * diff --git a/tools/sdk/esp32c3/include/driver/sdmmc/include/driver/sdmmc_types.h b/tools/sdk/esp32c3/include/driver/sdmmc/include/driver/sdmmc_types.h index 8a38d792e3a..bc74a38c1d5 100644 --- a/tools/sdk/esp32c3/include/driver/sdmmc/include/driver/sdmmc_types.h +++ b/tools/sdk/esp32c3/include/driver/sdmmc/include/driver/sdmmc_types.h @@ -175,6 +175,7 @@ typedef struct { size_t (*get_bus_width)(int slot); /*!< host function to get bus width */ esp_err_t (*set_bus_ddr_mode)(int slot, bool ddr_enable); /*!< host function to set DDR mode */ esp_err_t (*set_card_clk)(int slot, uint32_t freq_khz); /*!< host function to set card clock frequency */ + esp_err_t (*set_cclk_always_on)(int slot, bool cclk_always_on); /*!< host function to set whether the clock is always enabled */ esp_err_t (*do_transaction)(int slot, sdmmc_command_t* cmdinfo); /*!< host function to do a transaction */ union { esp_err_t (*deinit)(void); /*!< host function to deinitialize the driver */ diff --git a/tools/sdk/esp32c3/include/driver/spi/include/driver/sdspi_host.h b/tools/sdk/esp32c3/include/driver/spi/include/driver/sdspi_host.h index 3b127fbfefb..146cff69cd3 100644 --- a/tools/sdk/esp32c3/include/driver/spi/include/driver/sdspi_host.h +++ b/tools/sdk/esp32c3/include/driver/spi/include/driver/sdspi_host.h @@ -45,6 +45,7 @@ typedef int sdspi_dev_handle_t; .get_bus_width = NULL, \ .set_bus_ddr_mode = NULL, \ .set_card_clk = &sdspi_host_set_card_clk, \ + .set_cclk_always_on = NULL, \ .do_transaction = &sdspi_host_do_transaction, \ .deinit_p = &sdspi_host_remove_device, \ .io_int_enable = &sdspi_host_io_int_enable, \ diff --git a/tools/sdk/esp32c3/include/driver/uart/include/driver/uart.h b/tools/sdk/esp32c3/include/driver/uart/include/driver/uart.h index ba5f49306ea..314adf172dd 100644 --- a/tools/sdk/esp32c3/include/driver/uart/include/driver/uart.h +++ b/tools/sdk/esp32c3/include/driver/uart/include/driver/uart.h @@ -766,8 +766,10 @@ esp_err_t uart_get_collision_flag(uart_port_t uart_num, bool* collision_flag); * The character that triggers wakeup is not received by UART (i.e. it can not * be obtained from UART FIFO). Depending on the baud rate, a few characters * after that will also not be received. Note that when the chip enters and exits - * light sleep mode, APB frequency will be changing. To make sure that UART has - * correct baud rate all the time, select UART_SCLK_REF_TICK or UART_SCLK_XTAL as UART clock source in uart_config_t::source_clk. + * light sleep mode, APB frequency will be changing. To ensure that UART has + * correct Baud rate all the time, it is necessary to select a source clock which has + * a fixed frequency and remains active during sleep. For the supported clock sources + * of the chips, please refer to `uart_sclk_t` or `soc_periph_uart_clk_src_legacy_t` * * @note in ESP32, the wakeup signal can only be input via IO_MUX (i.e. * GPIO3 should be configured as function_1 to wake up UART0, diff --git a/tools/sdk/esp32c3/include/efuse/esp32c3/include/esp_efuse_table.h b/tools/sdk/esp32c3/include/efuse/esp32c3/include/esp_efuse_table.h index 05afdbc155d..ecee5f3c1d6 100644 --- a/tools/sdk/esp32c3/include/efuse/esp32c3/include/esp_efuse_table.h +++ b/tools/sdk/esp32c3/include/efuse/esp32c3/include/esp_efuse_table.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,7 +10,7 @@ extern "C" { #include "esp_efuse.h" -// md5_digest_table d006c80095638b5dbdc8649bf7e04dce +// md5_digest_table 661eec06c4c442af5baa0c947029db74 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -19,74 +19,167 @@ extern "C" { extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_ICACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG[]; +#define ESP_EFUSE_WR_DIS_DIS_USB_DEVICE ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[]; +#define ESP_EFUSE_WR_DIS_DIS_CAN ESP_EFUSE_WR_DIS_DIS_TWAI +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[]; +#define ESP_EFUSE_WR_DIS_KEY0_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_0 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[]; +#define ESP_EFUSE_WR_DIS_KEY1_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_1 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[]; +#define ESP_EFUSE_WR_DIS_KEY2_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_2 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[]; +#define ESP_EFUSE_WR_DIS_KEY3_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_3 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[]; +#define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[]; +#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[]; +#define ESP_EFUSE_WR_DIS_DIS_LEGACY_SPI_BOOT ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[]; +#define ESP_EFUSE_WR_DIS_UART_PRINT_CHANNEL ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[]; +#define ESP_EFUSE_WR_DIS_DIS_USB_DOWNLOAD_MODE ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ERR_RST_ENABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[]; +#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CLK[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_Q[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_HD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_WP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_DQS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D4[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D5[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D6[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D7[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_LO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_K_RTC_LDO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_K_DIG_LDO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_V_RTC_DBIAS20[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_V_DIG_DBIAS20[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIG_DBIAS_HVT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_THRES_HVT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_HI[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[]; +#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[]; +#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC +#define ESP_EFUSE_WR_DIS_USER_DATA_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[]; +#define ESP_EFUSE_WR_DIS_KEY0 ESP_EFUSE_WR_DIS_BLOCK_KEY0 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[]; +#define ESP_EFUSE_WR_DIS_KEY1 ESP_EFUSE_WR_DIS_BLOCK_KEY1 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[]; +#define ESP_EFUSE_WR_DIS_KEY2 ESP_EFUSE_WR_DIS_BLOCK_KEY2 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[]; +#define ESP_EFUSE_WR_DIS_KEY3 ESP_EFUSE_WR_DIS_BLOCK_KEY3 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[]; +#define ESP_EFUSE_WR_DIS_KEY4 ESP_EFUSE_WR_DIS_BLOCK_KEY4 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[]; +#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[]; +#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_AS_GPIO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[]; +#define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[]; +#define ESP_EFUSE_RD_DIS_KEY1 ESP_EFUSE_RD_DIS_BLOCK_KEY1 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[]; +#define ESP_EFUSE_RD_DIS_KEY2 ESP_EFUSE_RD_DIS_BLOCK_KEY2 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[]; +#define ESP_EFUSE_RD_DIS_KEY3 ESP_EFUSE_RD_DIS_BLOCK_KEY3 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[]; +#define ESP_EFUSE_RD_DIS_KEY4 ESP_EFUSE_RD_DIS_BLOCK_KEY4 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[]; +#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[]; +#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DEVICE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[]; +#define ESP_EFUSE_DIS_USB_DEVICE ESP_EFUSE_DIS_USB_SERIAL_JTAG extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[]; +#define ESP_EFUSE_DIS_CAN ESP_EFUSE_DIS_TWAI extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[]; extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[]; -extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[]; extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[]; extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[]; -extern const esp_efuse_desc_t* ESP_EFUSE_BTLC_GPIO_ENABLE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[]; -extern const esp_efuse_desc_t* ESP_EFUSE_POWER_GLITCH_DSENSE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[]; extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[]; +#define ESP_EFUSE_KEY0_PURPOSE ESP_EFUSE_KEY_PURPOSE_0 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[]; +#define ESP_EFUSE_KEY1_PURPOSE ESP_EFUSE_KEY_PURPOSE_1 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[]; +#define ESP_EFUSE_KEY2_PURPOSE ESP_EFUSE_KEY_PURPOSE_2 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[]; +#define ESP_EFUSE_KEY3_PURPOSE ESP_EFUSE_KEY_PURPOSE_3 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[]; +#define ESP_EFUSE_KEY4_PURPOSE ESP_EFUSE_KEY_PURPOSE_4 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[]; +#define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5 extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[]; extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[]; +#define ESP_EFUSE_DIS_LEGACY_SPI_BOOT ESP_EFUSE_DIS_DIRECT_BOOT extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[]; +#define ESP_EFUSE_UART_PRINT_CHANNEL ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[]; +#define ESP_EFUSE_DIS_USB_DOWNLOAD_MODE ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[]; extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[]; extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[]; @@ -94,21 +187,29 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_ERR_RST_ENABLE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[]; +extern const esp_efuse_desc_t* ESP_EFUSE_MAC[]; +#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_LO[]; extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[]; +extern const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_THRES_HVT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_HI[]; extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[]; @@ -123,20 +224,24 @@ extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[]; extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[]; extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[]; extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[]; +#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[]; +#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_USER_DATA_MAC_CUSTOM +#define ESP_EFUSE_CUSTOM_MAC ESP_EFUSE_USER_DATA_MAC_CUSTOM extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[]; +#define ESP_EFUSE_BLOCK_KEY0 ESP_EFUSE_KEY0 extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[]; +#define ESP_EFUSE_BLOCK_KEY1 ESP_EFUSE_KEY1 extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[]; +#define ESP_EFUSE_BLOCK_KEY2 ESP_EFUSE_KEY2 extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[]; +#define ESP_EFUSE_BLOCK_KEY3 ESP_EFUSE_KEY3 extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[]; +#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4 extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[]; +#define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5 extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[]; -extern const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[]; -extern const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[]; -extern const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_THRES_HVT[]; +#define ESP_EFUSE_BLOCK_SYS_DATA2 ESP_EFUSE_SYS_DATA_PART2 #ifdef __cplusplus } diff --git a/tools/sdk/esp32c3/include/esp-tls/esp_tls.h b/tools/sdk/esp32c3/include/esp-tls/esp_tls.h index 3ada350379e..0efe587b53b 100644 --- a/tools/sdk/esp32c3/include/esp-tls/esp_tls.h +++ b/tools/sdk/esp32c3/include/esp-tls/esp_tls.h @@ -71,6 +71,15 @@ typedef struct tls_keep_alive_cfg { int keep_alive_count; /*!< Keep-alive packet retry send count */ } tls_keep_alive_cfg_t; +/* +* @brief ESP-TLS Address families +*/ +typedef enum esp_tls_addr_family { + ESP_TLS_AF_UNSPEC = 0, /**< Unspecified address family. */ + ESP_TLS_AF_INET, /**< IPv4 address family. */ + ESP_TLS_AF_INET6, /**< IPv6 address family. */ +} esp_tls_addr_family_t; + /** * @brief ESP-TLS configuration parameters * @@ -182,6 +191,8 @@ typedef struct esp_tls_cfg { #ifdef CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS esp_tls_client_session_t *client_session; /*! Pointer for the client session ticket context. */ #endif /* CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS */ + + esp_tls_addr_family_t addr_family; /*!< The address family to use when connecting to a host. */ } esp_tls_cfg_t; #ifdef CONFIG_ESP_TLS_SERVER diff --git a/tools/sdk/esp32c3/include/esp_coex/include/esp_coexist.h b/tools/sdk/esp32c3/include/esp_coex/include/esp_coexist.h index e3fb019d420..9ed897c28a7 100644 --- a/tools/sdk/esp32c3/include/esp_coex/include/esp_coexist.h +++ b/tools/sdk/esp32c3/include/esp_coex/include/esp_coexist.h @@ -201,6 +201,14 @@ esp_err_t esp_external_coex_set_validate_high(bool is_high_valid); #endif #endif +#if CONFIG_ESP_COEX_SW_COEXIST_ENABLE && CONFIG_SOC_IEEE802154_SUPPORTED +/** + * @brief Enable Wi-Fi and 802.15.4 coexistence. + * @return : ESP_OK - success, other - failed + */ +esp_err_t esp_coex_wifi_i154_enable(void); +#endif + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32c3/include/esp_coex/include/esp_coexist_adapter.h b/tools/sdk/esp32c3/include/esp_coex/include/esp_coexist_adapter.h index 11bf54d9b5e..fde83d1111d 100644 --- a/tools/sdk/esp32c3/include/esp_coex/include/esp_coexist_adapter.h +++ b/tools/sdk/esp32c3/include/esp_coex/include/esp_coexist_adapter.h @@ -38,7 +38,10 @@ typedef struct { void (* _free)(void *p); int64_t (* _esp_timer_get_time)(void); bool (* _env_is_chip)(void); +#if CONFIG_IDF_TARGET_ESP32C2 + // this function is only used on esp32c2 uint32_t (* _slowclk_cal_get)(void); +#endif void (* _timer_disarm)(void *timer); void (* _timer_done)(void *ptimer); void (* _timer_setfn)(void *ptimer, void *pfunction, void *parg); diff --git a/tools/sdk/esp32c3/include/esp_http_client/include/esp_http_client.h b/tools/sdk/esp32c3/include/esp_http_client/include/esp_http_client.h index 5638b7c6817..e1dbd5c8f1c 100644 --- a/tools/sdk/esp32c3/include/esp_http_client/include/esp_http_client.h +++ b/tools/sdk/esp32c3/include/esp_http_client/include/esp_http_client.h @@ -382,6 +382,34 @@ esp_err_t esp_http_client_set_password(esp_http_client_handle_t client, const ch */ esp_err_t esp_http_client_set_authtype(esp_http_client_handle_t client, esp_http_client_auth_type_t auth_type); +/** + * @brief Get http request user_data. + * The value stored from the esp_http_client_config_t will be written + * to the address passed into data. + * + * @param[in] client The esp_http_client handle + * @param[out] data A pointer to the pointer that will be set to user_data. + * + * @return + * - ESP_OK + * - ESP_ERR_INVALID_ARG + */ +esp_err_t esp_http_client_get_user_data(esp_http_client_handle_t client, void **data); + +/** + * @brief Set http request user_data. + * The value passed in +data+ will be available during event callbacks. + * No memory management will be performed on the user's behalf. + * + * @param[in] client The esp_http_client handle + * @param[in] data The pointer to the user data + * + * @return + * - ESP_OK + * - ESP_ERR_INVALID_ARG + */ +esp_err_t esp_http_client_set_user_data(esp_http_client_handle_t client, void *data); + /** * @brief Get HTTP client session errno * diff --git a/tools/sdk/esp32c3/include/esp_http_server/include/esp_http_server.h b/tools/sdk/esp32c3/include/esp_http_server/include/esp_http_server.h index 3826a40c9a3..39c2a82a31f 100644 --- a/tools/sdk/esp32c3/include/esp_http_server/include/esp_http_server.h +++ b/tools/sdk/esp32c3/include/esp_http_server/include/esp_http_server.h @@ -15,6 +15,7 @@ #include #include #include +#include #ifdef __cplusplus extern "C" { diff --git a/tools/sdk/esp32c3/include/esp_hw_support/include/esp_private/esp_modem_clock.h b/tools/sdk/esp32c3/include/esp_hw_support/include/esp_private/esp_modem_clock.h index 8b406550c66..bc678e039c3 100644 --- a/tools/sdk/esp32c3/include/esp_hw_support/include/esp_private/esp_modem_clock.h +++ b/tools/sdk/esp32c3/include/esp_hw_support/include/esp_private/esp_modem_clock.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,6 +10,7 @@ #include #include +#include "soc/soc_caps.h" #include "soc/periph_defs.h" #include "hal/modem_clock_types.h" diff --git a/tools/sdk/esp32c3/include/esp_hw_support/include/esp_private/gdma.h b/tools/sdk/esp32c3/include/esp_hw_support/include/esp_private/gdma.h index d71f3c6fc8a..bf5d97dd324 100644 --- a/tools/sdk/esp32c3/include/esp_hw_support/include/esp_private/gdma.h +++ b/tools/sdk/esp32c3/include/esp_hw_support/include/esp_private/gdma.h @@ -177,14 +177,28 @@ esp_err_t gdma_set_transfer_ability(gdma_channel_handle_t dma_chan, const gdma_t /** * @brief Apply channel strategy for GDMA channel * - * @param dma_chan GDMA channel handle, allocated by `gdma_new_channel` - * @param config Configuration of GDMA channel strategy + * @param[in] dma_chan GDMA channel handle, allocated by `gdma_new_channel` + * @param[in] config Configuration of GDMA channel strategy * - ESP_OK: Apply channel strategy successfully * - ESP_ERR_INVALID_ARG: Apply channel strategy failed because of invalid argument * - ESP_FAIL: Apply channel strategy failed because of other error */ esp_err_t gdma_apply_strategy(gdma_channel_handle_t dma_chan, const gdma_strategy_config_t *config); +/** + * @brief Set GDMA channel priority + * + * @note By default, all GDMA channels are with the same priority: 0. Channels with the same priority are served in round-robin manner. + * + * @param[in] dma_chan GDMA channel handle, allocated by `gdma_new_channel` + * @param[in] priority Priority of GDMA channel, higher value means higher priority + * @return + * - ESP_OK: Set GDMA channel priority successfully + * - ESP_ERR_INVALID_ARG: Set GDMA channel priority failed because of invalid argument, e.g. priority out of range [0,GDMA_LL_CHANNEL_MAX_PRIORITY] + * - ESP_FAIL: Set GDMA channel priority failed because of other error + */ +esp_err_t gdma_set_priority(gdma_channel_handle_t dma_chan, uint32_t priority); + /** * @brief Delete GDMA channel * @note If you call `gdma_new_channel` several times for a same peripheral, make sure you call this API the same times. @@ -251,6 +265,7 @@ esp_err_t gdma_register_rx_event_callbacks(gdma_channel_handle_t dma_chan, gdma_ * @return * - ESP_OK: Start DMA engine successfully * - ESP_ERR_INVALID_ARG: Start DMA engine failed because of invalid argument + * - ESP_ERR_INVALID_STATE: Start DMA engine failed because of invalid state, e.g. the channel is controlled by ETM, so can't start it manually * - ESP_FAIL: Start DMA engine failed because of other error */ esp_err_t gdma_start(gdma_channel_handle_t dma_chan, intptr_t desc_base_addr); @@ -265,6 +280,7 @@ esp_err_t gdma_start(gdma_channel_handle_t dma_chan, intptr_t desc_base_addr); * @return * - ESP_OK: Stop DMA engine successfully * - ESP_ERR_INVALID_ARG: Stop DMA engine failed because of invalid argument + * - ESP_ERR_INVALID_STATE: Stop DMA engine failed because of invalid state, e.g. the channel is controlled by ETM, so can't stop it manually * - ESP_FAIL: Stop DMA engine failed because of other error */ esp_err_t gdma_stop(gdma_channel_handle_t dma_chan); @@ -333,6 +349,7 @@ typedef struct { * @brief Get the ETM task for GDMA channel * * @note The created ETM task object can be deleted later by calling `esp_etm_del_task` + * @note If the GDMA task (e.g. start/stop) is controlled by ETM, then you can't use `gdma_start`/`gdma_stop` to control it. * * @param[in] dma_chan GDMA channel handle, allocated by `gdma_new_channel` * @param[in] config GDMA ETM task configuration diff --git a/tools/sdk/esp32c3/include/esp_hw_support/include/esp_private/sleep_modem.h b/tools/sdk/esp32c3/include/esp_hw_support/include/esp_private/sleep_modem.h index 7e11d88a9e6..7601aeebd82 100644 --- a/tools/sdk/esp32c3/include/esp_hw_support/include/esp_private/sleep_modem.h +++ b/tools/sdk/esp32c3/include/esp_hw_support/include/esp_private/sleep_modem.h @@ -42,6 +42,13 @@ void mac_bb_power_up_cb_execute(void); #if SOC_PM_SUPPORT_PMU_MODEM_STATE +/** + * @brief The retention action in the modem state of WiFi PHY module + * + * @param restore true for restore the PHY context, false for backup the PHY context + */ +void sleep_modem_wifi_do_phy_retention(bool restore); + /** * @brief Get WiFi modem state * diff --git a/tools/sdk/esp32c3/include/esp_hw_support/include/soc/esp32c2/memprot.h b/tools/sdk/esp32c3/include/esp_hw_support/include/soc/esp32c2/memprot.h deleted file mode 100644 index c7b1ad461e8..00000000000 --- a/tools/sdk/esp32c3/include/esp_hw_support/include/soc/esp32c2/memprot.h +++ /dev/null @@ -1,440 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - - -/* INTERNAL API - * generic interface to PMS memory protection features - */ - -#pragma once - -#include -#include -#include "esp_attr.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef IRAM_SRAM_START -#define IRAM_SRAM_START 0x4037C000 -#endif - -#ifndef DRAM_SRAM_START -#define DRAM_SRAM_START 0x3FC7C000 -#endif - -typedef enum { - MEMPROT_NONE = 0x00000000, - MEMPROT_IRAM0_SRAM = 0x00000001, - MEMPROT_DRAM0_SRAM = 0x00000002, - MEMPROT_ALL = 0xFFFFFFFF -} mem_type_prot_t; - -typedef enum { - MEMPROT_SPLITLINE_NONE = 0, - MEMPROT_IRAM0_DRAM0_SPLITLINE, - MEMPROT_IRAM0_LINE_0_SPLITLINE, - MEMPROT_IRAM0_LINE_1_SPLITLINE, - MEMPROT_DRAM0_DMA_LINE_0_SPLITLINE, - MEMPROT_DRAM0_DMA_LINE_1_SPLITLINE -} split_line_t; - -typedef enum { - MEMPROT_PMS_AREA_NONE = 0, - MEMPROT_IRAM0_PMS_AREA_0, - MEMPROT_IRAM0_PMS_AREA_1, - MEMPROT_IRAM0_PMS_AREA_2, - MEMPROT_IRAM0_PMS_AREA_3, - MEMPROT_DRAM0_PMS_AREA_0, - MEMPROT_DRAM0_PMS_AREA_1, - MEMPROT_DRAM0_PMS_AREA_2, - MEMPROT_DRAM0_PMS_AREA_3 -} pms_area_t; - -typedef enum -{ - MEMPROT_PMS_WORLD_0 = 0, - MEMPROT_PMS_WORLD_1, - MEMPROT_PMS_WORLD_2, - MEMPROT_PMS_WORLD_INVALID = 0xFFFFFFFF -} pms_world_t; - -typedef enum -{ - MEMPROT_PMS_OP_READ = 0, - MEMPROT_PMS_OP_WRITE, - MEMPROT_PMS_OP_FETCH, - MEMPROT_PMS_OP_INVALID = 0xFFFFFFFF -} pms_operation_type_t; - -/** - * @brief Converts Memory protection type to string - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - */ -const char *esp_memprot_mem_type_to_str(mem_type_prot_t mem_type); - -/** - * @brief Converts Split line type to string - * - * @param line_type Split line type (see split_line_t enum) - */ -const char *esp_memprot_split_line_to_str(split_line_t line_type); - -/** - * @brief Converts PMS Area type to string - * - * @param area_type PMS Area type (see pms_area_t enum) - */ -const char *esp_memprot_pms_to_str(pms_area_t area_type); - -/** - * @brief Returns PMS splitting address for given Split line type - * - * The value is taken from PMS configuration registers (IRam0 range) - * For details on split lines see 'esp_memprot_set_prot_int' function description - * - * @param line_type Split line type (see split_line_t enum) - * - * @return appropriate split line address - */ -uint32_t *esp_memprot_get_split_addr(split_line_t line_type); - -/** - * @brief Returns default main IRAM/DRAM splitting address - * - * The address value is given by _iram_text_end global (IRam0 range) - - * @return Main I/D split line (IRam0_DRam0_Split_Addr) - */ -void *esp_memprot_get_default_main_split_addr(void); - -/** - * @brief Sets a lock for the main IRAM/DRAM splitting address - * - * Locks can be unlocked only by digital system reset - */ -void esp_memprot_set_split_line_lock(void); - -/** - * @brief Gets a lock status for the main IRAM/DRAM splitting address - * - * @return true/false (locked/unlocked) - */ -bool esp_memprot_get_split_line_lock(void); - -/** - * @brief Sets required split line address - * - * @param line_type Split line type (see split_line_t enum) - * @param line_addr target address from a memory range relevant to given line_type (IRAM/DRAM) - */ -void esp_memprot_set_split_line(split_line_t line_type, const void *line_addr); - -/** - * @brief Sets a lock for PMS Area settings of required Memory type - * - * Locks can be unlocked only by digital system reset - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - */ -void esp_memprot_set_pms_lock(mem_type_prot_t mem_type); - -/** - * @brief Gets a lock status for PMS Area settings of required Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return true/false (locked/unlocked) - */ -bool esp_memprot_get_pms_lock(mem_type_prot_t mem_type); - -/** - * @brief Sets permissions for given PMS Area in IRam0 memory range (MEMPROT_IRAM0_SRAM) - * - * @param area_type IRam0 PMS Area type (see pms_area_t enum) - * @param r Read permission flag - * @param w Write permission flag - * @param x Execute permission flag - */ -void esp_memprot_iram_set_pms_area(pms_area_t area_type, bool r, bool w, bool x); - -/** - * @brief Gets current permissions for given PMS Area in IRam0 memory range (MEMPROT_IRAM0_SRAM) - * - * @param area_type IRam0 PMS Area type (see pms_area_t enum) - * @param r Read permission flag holder - * @param w Write permission flag holder - * @param x Execute permission flag holder - */ -void esp_memprot_iram_get_pms_area(pms_area_t area_type, bool *r, bool *w, bool *x); - -/** - * @brief Sets permissions for given PMS Area in DRam0 memory range (MEMPROT_DRAM0_SRAM) - * - * @param area_type DRam0 PMS Area type (see pms_area_t enum) - * @param r Read permission flag - * @param w Write permission flag - */ -void esp_memprot_dram_set_pms_area(pms_area_t area_type, bool r, bool w); - -/** - * @brief Gets current permissions for given PMS Area in DRam0 memory range (MEMPROT_DRAM0_SRAM) - * - * @param area_type DRam0 PMS Area type (see pms_area_t enum) - * @param r Read permission flag holder - * @param w Write permission flag holder - */ -void esp_memprot_dram_get_pms_area(pms_area_t area_type, bool *r, bool *w); - -/** - * @brief Sets a lock for PMS interrupt monitor settings of required Memory type - * - * Locks can be unlocked only by digital system reset - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - */ -void esp_memprot_set_monitor_lock(mem_type_prot_t mem_type); - -/** - * @brief Gets a lock status for PMS interrupt monitor settings of required Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return true/false (locked/unlocked) - */ -bool esp_memprot_get_monitor_lock(mem_type_prot_t mem_type); - -/** - * @brief Enable PMS violation interrupt monitoring of required Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * @param enable/disable - */ -void esp_memprot_set_monitor_en(mem_type_prot_t mem_type, bool enable); - -/** - * @brief Gets enable/disable status for PMS interrupt monitor settings of required Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return true/false (enabled/disabled) - */ -bool esp_memprot_get_monitor_en(mem_type_prot_t mem_type); - -/** - * @brief Gets CPU ID for currently active PMS violation interrupt - * - * @return CPU ID (CPU_PRO for ESP32-C2) - */ -int IRAM_ATTR esp_memprot_intr_get_cpuid(void); - -/** - * @brief Clears current interrupt ON flag for given Memory type - * - * Interrupt clearing happens in two steps: - * 1. Interrupt CLR flag is set (to clear the interrupt ON status) - * 2. Interrupt CLR flag is reset (to allow further monitoring) - * This operation is non-atomic by PMS module design - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - */ -void IRAM_ATTR esp_memprot_monitor_clear_intr(mem_type_prot_t mem_type); - -/** - * @brief Returns active PMS violation interrupt (if any) - * - * This function iterates through supported Memory type status registers - * and returns the first interrupt-on flag. If none is found active, - * MEMPROT_NONE is returned. - * Order of checking (in current version): - * 1. MEMPROT_IRAM0_SRAM - * 2. MEMPROT_DRAM0_SRAM - * - * @return mem_type Memory protection type related to active interrupt found (see mem_type_prot_t enum) - */ -mem_type_prot_t IRAM_ATTR esp_memprot_get_active_intr_memtype(void); - -/** - * @brief Checks whether any violation interrupt is active - * - * @return true/false (yes/no) - */ -bool IRAM_ATTR esp_memprot_is_locked_any(void); - -/** - * @brief Checks whether any violation interrupt is enabled - * - * @return true/false (yes/no) - */ -bool IRAM_ATTR esp_memprot_is_intr_ena_any(void); - -/** - * @brief Checks whether any violation interrupt is enabled - * - * @return true/false (yes/no) - */ -bool IRAM_ATTR esp_memprot_get_violate_intr_on(mem_type_prot_t mem_type); - -/** - * @brief Returns the address which caused the violation interrupt (if any) - * - * The address is taken from appropriate PMS violation status register, based given Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return faulting address - */ -uint32_t IRAM_ATTR esp_memprot_get_violate_addr(mem_type_prot_t mem_type); - -/** - * @brief Returns the World identifier of the code causing the violation interrupt (if any) - * - * The value is taken from appropriate PMS violation status register, based given Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return World identifier (see pms_world_t enum) - */ -pms_world_t IRAM_ATTR esp_memprot_get_violate_world(mem_type_prot_t mem_type); - -/** - * @brief Returns Read or Write operation type which caused the violation interrupt (if any) - * - * The value (bit) is taken from appropriate PMS violation status register, based given Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return PMS operation type relevant to mem_type parameter (se pms_operation_type_t) - */ -pms_operation_type_t IRAM_ATTR esp_memprot_get_violate_wr(mem_type_prot_t mem_type); - -/** - * @brief Returns LoadStore flag of the operation type which caused the violation interrupt (if any) - * - * The value (bit) is taken from appropriate PMS violation status register, based given Memory type - * Effective only on IRam0 access - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return true/false (LoadStore bit on/off) - */ -bool IRAM_ATTR esp_memprot_get_violate_loadstore(mem_type_prot_t mem_type); - -/** - * @brief Returns byte-enables for the address which caused the violation interrupt (if any) - * - * The value is taken from appropriate PMS violation status register, based given Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return byte-enables - */ -uint32_t IRAM_ATTR esp_memprot_get_violate_byte_en(mem_type_prot_t mem_type); - -/** - * @brief Returns raw contents of DRam0 status register 1 - * - * @return 32-bit register value - */ -uint32_t IRAM_ATTR esp_memprot_get_dram_status_reg_1(void); - -/** - * @brief Returns raw contents of DRam0 status register 2 - * - * @return 32-bit register value - */ -uint32_t IRAM_ATTR esp_memprot_get_dram_status_reg_2(void); - -/** - * @brief Returns raw contents of IRam0 status register - * - * @return 32-bit register value - */ -uint32_t IRAM_ATTR esp_memprot_get_iram_status_reg(void); - -/** - * @brief Register PMS violation interrupt in global interrupt matrix for given Memory type - * - * Memory protection components uses specific interrupt number, see ETS_MEMPROT_ERR_INUM - * The registration makes the panic-handler routine being called when the interrupt appears - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - */ -void esp_memprot_set_intr_matrix(mem_type_prot_t mem_type); - -/** - * @brief Convenient routine for setting the PMS defaults - * - * Called on application startup, depending on CONFIG_ESP_SYSTEM_MEMPROT_FEATURE Kconfig settings - * For implementation details see 'esp_memprot_set_prot_int' description - * - * @param invoke_panic_handler register all interrupts for panic handling (true/false) - * @param lock_feature lock the defaults to prevent further PMS settings changes (true/false) - * @param mem_type_mask 32-bit field of specific PMS parts to configure (see 'esp_memprot_set_prot_int') - */ -void esp_memprot_set_prot(bool invoke_panic_handler, bool lock_feature, uint32_t *mem_type_mask); - -/** - * @brief Internal routine for setting the PMS defaults - * - * Called on application startup from within 'esp_memprot_set_prot'. Allows setting a specific splitting address - * (main I/D split line) - see the parameter 'split_addr'. If the 'split_addr' equals to NULL, default I/D split line - * is used (&_iram_text_end) and all the remaining lines share the same address. - * The function sets all the split lines and PMS areas to the same space, - * ie there is a single instruction space and single data space at the end. - * The PMS split lines and permission areas scheme described below: - * - * DRam0/DMA IRam0 - * ----------------------------------------------- - * ... | IRam0_PMS_0 | - * DRam0_PMS_0 ----------------------------------------------- IRam0_line1_Split_addr - * ... | IRam0_PMS_1 | - * ... ----------------------------------------------- IRam0_line0_Split_addr - * | IRam0_PMS_2 | - * =============================================== IRam0_DRam0_Split_addr (main I/D) - * | DRam0_PMS_1 | - * DRam0_DMA_line0_Split_addr ----------------------------------------------- ... - * | DRam0_PMS_2 | ... - * DRam0_DMA_line1_Split_addr ----------------------------------------------- IRam0_PMS_3 - * | DRam0_PMS_3 | ... - * ----------------------------------------------- - * - * Default settings provided by 'esp_memprot_set_prot_int' are as follows: - * - * DRam0/DMA IRam0 - * ----------------------------------------------- - * | IRam0_PMS_0 = IRam0_PMS_1 = IRam0_PMS_2 | - * | DRam0_PMS_0 | IRam0_line1_Split_addr - * DRam0_DMA_line0_Split_addr | | = - * = =============================================== IRam0_line0_Split_addr - * DRam0_DMA_line1_Split_addr | | = - * | DRam0_PMS_1 = DRam0_PMS_2 = DRam0_PMS_3 | IRam0_DRam0_Split_addr (main I/D) - * | IRam0_PMS_3 | - * ----------------------------------------------- - * - * Once the memprot feature is locked, it can be unlocked only by digital system reset - * - * @param invoke_panic_handler register all the violation interrupts for panic handling (true/false) - * @param lock_feature lock the defaults to prevent further PMS settings changes (true/false) - * @param split_addr specific main I/D adrees or NULL to use default ($_iram_text_end) - * @param mem_type_mask 32-bit field of specific PMS parts to configure (members of mem_type_prot_t) - */ -void esp_memprot_set_prot_int(bool invoke_panic_handler, bool lock_feature, void *split_addr, uint32_t *mem_type_mask); - -/** - * @brief Returns raw contents of PMS interrupt monitor register for given Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return 32-bit register value - */ -uint32_t esp_memprot_get_monitor_enable_reg(mem_type_prot_t mem_type); - -#ifdef __cplusplus -} -#endif diff --git a/tools/sdk/esp32c3/include/esp_hw_support/include/soc/esp32s2/memprot.h b/tools/sdk/esp32c3/include/esp_hw_support/include/soc/esp32s2/memprot.h index 0ebd6474578..596633ac7f2 100644 --- a/tools/sdk/esp32c3/include/esp_hw_support/include/soc/esp32s2/memprot.h +++ b/tools/sdk/esp32c3/include/esp_hw_support/include/soc/esp32s2/memprot.h @@ -68,7 +68,7 @@ typedef enum { * The address is given by region-specific global symbol exported from linker script, * it is not read out from related configuration register. */ -uint32_t *IRAM_ATTR esp_memprot_get_split_addr(mem_type_prot_t mem_type); +uint32_t * esp_memprot_get_split_addr(mem_type_prot_t mem_type); /** * @brief Initializes illegal memory access control for required memory section. @@ -116,7 +116,7 @@ esp_err_t esp_memprot_clear_intr(mem_type_prot_t mem_type); * * @return Memory protection area type (see mem_type_prot_t enum) */ -mem_type_prot_t IRAM_ATTR esp_memprot_get_active_intr_memtype(void); +mem_type_prot_t esp_memprot_get_active_intr_memtype(void); /** * @brief Gets interrupt status register contents for specified memory region @@ -141,7 +141,7 @@ esp_err_t esp_memprot_get_fault_reg(mem_type_prot_t mem_type, uint32_t *fault_re * DRAM0: 0 - non-atomic operation, 1 - atomic operation * @return ESP_OK on success, ESP_ERR_INVALID_ARG on failure */ -esp_err_t IRAM_ATTR esp_memprot_get_fault_status(mem_type_prot_t mem_type, uint32_t **faulting_address, uint32_t *op_type, uint32_t *op_subtype); +esp_err_t esp_memprot_get_fault_status(mem_type_prot_t mem_type, uint32_t **faulting_address, uint32_t *op_type, uint32_t *op_subtype); /** * @brief Gets string representation of required memory region identifier @@ -150,7 +150,7 @@ esp_err_t IRAM_ATTR esp_memprot_get_fault_status(mem_type_prot_t mem_type, uint3 * * @return mem_type as string */ -const char *IRAM_ATTR esp_memprot_type_to_str(mem_type_prot_t mem_type); +const char * esp_memprot_type_to_str(mem_type_prot_t mem_type); /** * @brief Detects whether any of the interrupt locks is active (requires digital system reset to unlock) diff --git a/tools/sdk/esp32c3/include/esp_lcd/include/esp_lcd_panel_commands.h b/tools/sdk/esp32c3/include/esp_lcd/include/esp_lcd_panel_commands.h index 091ef1cffef..5917c3e8774 100644 --- a/tools/sdk/esp32c3/include/esp_lcd/include/esp_lcd_panel_commands.h +++ b/tools/sdk/esp32c3/include/esp_lcd/include/esp_lcd_panel_commands.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -31,7 +31,7 @@ #define LCD_CMD_RAMRD 0x2E // Read frame memory #define LCD_CMD_PTLAR 0x30 // Define the partial area #define LCD_CMD_VSCRDEF 0x33 // Vertical scrolling definition -#define LCD_CMD_TEOFF 0x34 // Turns of tearing effect +#define LCD_CMD_TEOFF 0x34 // Turns off tearing effect #define LCD_CMD_TEON 0x35 // Turns on tearing effect #define LCD_CMD_MADCTL 0x36 // Memory data access control @@ -48,7 +48,7 @@ #define LCD_CMD_COLMOD 0x3A // Defines the format of RGB picture data #define LCD_CMD_RAMWRC 0x3C // Memory write continue #define LCD_CMD_RAMRDC 0x3E // Memory read continue -#define LCD_CMD_STE 0x44 // Set tear scanline, tearing effect output signal when display module reaches line N -#define LCD_CMD_GDCAN 0x45 // Get scanline +#define LCD_CMD_STE 0x44 // Set tear scan line, tearing effect output signal when display module reaches line N +#define LCD_CMD_GDCAN 0x45 // Get scan line #define LCD_CMD_WRDISBV 0x51 // Write display brightness #define LCD_CMD_RDDISBV 0x52 // Read display brightness value diff --git a/tools/sdk/esp32c3/include/esp_lcd/include/esp_lcd_panel_io.h b/tools/sdk/esp32c3/include/esp_lcd/include/esp_lcd_panel_io.h index c01fe3e441f..de7b434b5f8 100644 --- a/tools/sdk/esp32c3/include/esp_lcd/include/esp_lcd_panel_io.h +++ b/tools/sdk/esp32c3/include/esp_lcd/include/esp_lcd_panel_io.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -71,7 +71,7 @@ esp_err_t esp_lcd_panel_io_rx_param(esp_lcd_panel_io_handle_t io, int lcd_cmd, v * this function will wait until they are finished and the queue is empty before sending the command(s). * * @param[in] io LCD panel IO handle, which is created by other factory API like `esp_lcd_new_panel_io_spi()` - * @param[in] lcd_cmd The specific LCD command (set to -1 if no command needed - only in SPI and I2C) + * @param[in] lcd_cmd The specific LCD command, set to -1 if no command needed * @param[in] param Buffer that holds the command specific parameters, set to NULL if no parameter is needed for the command * @param[in] param_size Size of `param` in memory, in bytes, set to zero if no parameter is needed for the command * @return diff --git a/tools/sdk/esp32c3/include/esp_mm/include/esp_cache.h b/tools/sdk/esp32c3/include/esp_mm/include/esp_cache.h index 800e8865695..af51a18ed72 100644 --- a/tools/sdk/esp32c3/include/esp_mm/include/esp_cache.h +++ b/tools/sdk/esp32c3/include/esp_mm/include/esp_cache.h @@ -41,9 +41,9 @@ extern "C" { * @note You should not call this during any Flash operations (e.g. esp_flash APIs, nvs and some other APIs that are based on esp_flash APIs) * @note If XIP_From_PSRAM is enabled (by enabling both CONFIG_SPIRAM_FETCH_INSTRUCTIONS and CONFIG_SPIRAM_RODATA), you can call this API during Flash operations * - * @param[in] Starting address to do the msync - * @param[in] Size to do the msync - * @param[in] Flags, see `ESP_CACHE_MSYNC_FLAG_x` + * @param[in] addr Starting address to do the msync + * @param[in] size Size to do the msync + * @param[in] flags Flags, see `ESP_CACHE_MSYNC_FLAG_x` * * @return * - ESP_OK: diff --git a/tools/sdk/esp32c3/include/esp_mm/include/esp_mmu_map.h b/tools/sdk/esp32c3/include/esp_mm/include/esp_mmu_map.h index 33d3396441d..355b0c97501 100644 --- a/tools/sdk/esp32c3/include/esp_mm/include/esp_mmu_map.h +++ b/tools/sdk/esp32c3/include/esp_mm/include/esp_mmu_map.h @@ -47,7 +47,7 @@ extern "C" { * - the to-be-mapped paddr block is overlapped with an already mapped paddr block. * - the to-be-mapped paddr block encloses an already mapped paddr block. * 2. If the to-be-mapped paddr block is enclosed by an already mapped paddr block, no new mapping will happen, return ESP_ERR_INVALID_STATE. The out pointer will be the already mapped paddr corresponding vaddr. - * 3. If the to-be-mapped paddr block is totally the same as an already mapped paddr block, no new mapping will happen, return ESP_ERR_INVALID_STATE. The out pointer will be the corresponding vaddr. + * 3. If the to-be-mapped paddr block is identical with an already mapped paddr block, no new mapping will happen, return ESP_ERR_INVALID_STATE. The out pointer will be the corresponding vaddr. * * - If this flag isn't set, overlapped, enclosed or same to-be-mapped paddr block will lead to ESP_ERR_INVALID_ARG. */ @@ -77,7 +77,7 @@ typedef uint32_t esp_paddr_t; * - ESP_ERR_NOT_FOUND: No enough size free block to use * - ESP_ERR_NO_MEM: Out of memory, this API will allocate some heap memory for internal usage * - ESP_ERR_INVALID_STATE: Paddr is mapped already, this API will return corresponding vaddr_start of the previously mapped block. - * Only to-be-mapped paddr block is totally enclosed by a previously mapped block will lead to this error: + * Only to-be-mapped paddr block is totally enclosed by a previously mapped block will lead to this error. (Identical scenario will behave similarly) * new_block_start new_block_end * |-------- New Block --------| * |--------------- Block ---------------| @@ -156,6 +156,20 @@ esp_err_t esp_mmu_vaddr_to_paddr(void *vaddr, esp_paddr_t *out_paddr, mmu_target */ esp_err_t esp_mmu_paddr_to_vaddr(esp_paddr_t paddr, mmu_target_t target, mmu_vaddr_t type, void **out_vaddr); +/** + * @brief If the physical address is mapped, this API will provide the capabilities of the virtual address where the physical address is mapped to. + * + * @note: Only return value is ESP_OK(which means physically address is successfully mapped), then caps you get make sense. + * @note This API only check one page (see CONFIG_MMU_PAGE_SIZE), starting from the `paddr` + * + * @param[in] paddr Physical address + * @param[out] out_caps Bitwise OR of MMU_MEM_CAP_* flags indicating the capabilities of a virtual address where the physical address is mapped to. + * @return + * - ESP_OK: Physical address successfully mapped. + * - ESP_ERR_INVALID_ARG: Null pointer + * - ESP_ERR_NOT_FOUND: Physical address is not mapped successfully. + */ +esp_err_t esp_mmu_paddr_find_caps(const esp_paddr_t paddr, mmu_mem_caps_t *out_caps); #ifdef __cplusplus } diff --git a/tools/sdk/esp32c3/include/esp_netif/include/esp_netif.h b/tools/sdk/esp32c3/include/esp_netif/include/esp_netif.h index 9372b6d1506..2510a1eefee 100644 --- a/tools/sdk/esp32c3/include/esp_netif/include/esp_netif.h +++ b/tools/sdk/esp32c3/include/esp_netif/include/esp_netif.h @@ -523,6 +523,34 @@ int esp_netif_get_netif_impl_index(esp_netif_t *esp_netif); */ esp_err_t esp_netif_get_netif_impl_name(esp_netif_t *esp_netif, char* name); +/** + * @brief Enable NAPT on an interface + * + * @note Enable operation can be performed only on one interface at a time. + * NAPT cannot be enabled on multiple interfaces according to this implementation. + * + * @param[in] esp_netif Handle to esp-netif instance + * + * @return + * - ESP_OK + * - ESP_FAIL + * - ESP_ERR_NOT_SUPPORTED +*/ + +esp_err_t esp_netif_napt_enable(esp_netif_t *esp_netif); + +/** + * @brief Disable NAPT on an interface. + * + * @param[in] esp_netif Handle to esp-netif instance + * + * @return + * - ESP_OK + * - ESP_FAIL + * - ESP_ERR_NOT_SUPPORTED +*/ +esp_err_t esp_netif_napt_disable(esp_netif_t *esp_netif); + /** * @} */ diff --git a/tools/sdk/esp32c3/include/esp_phy/include/esp_phy_init.h b/tools/sdk/esp32c3/include/esp_phy/include/esp_phy_init.h index 4f30c7795fc..4813e5bdee6 100644 --- a/tools/sdk/esp32c3/include/esp_phy/include/esp_phy_init.h +++ b/tools/sdk/esp32c3/include/esp_phy/include/esp_phy_init.h @@ -180,6 +180,15 @@ void esp_phy_disable(void); */ void esp_btbb_enable(void); +/** + * @brief Disable BTBB module + * + * Dsiable BTBB module, used by IEEE802154 or Bluetooth. + * Users should not call this API in their application. + * + */ +void esp_btbb_disable(void); + /** * @brief Load calibration data from NVS and initialize PHY and RF module */ diff --git a/tools/sdk/esp32c3/include/esp_rom/include/esp32/rom/ets_sys.h b/tools/sdk/esp32c3/include/esp_rom/include/esp32/rom/ets_sys.h index 6f9688fcf18..549db8ffc63 100644 --- a/tools/sdk/esp32c3/include/esp_rom/include/esp32/rom/ets_sys.h +++ b/tools/sdk/esp32c3/include/esp_rom/include/esp32/rom/ets_sys.h @@ -48,7 +48,10 @@ extern "C" { typedef enum { ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1 /**< return failed in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, } ETS_STATUS; typedef uint32_t ETSSignal; @@ -621,13 +624,16 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); #define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) typedef enum { OK = 0, FAIL, PENDING, BUSY, CANCEL, -} STATUS; +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif /** * @} diff --git a/tools/sdk/esp32c3/include/esp_rom/include/esp32/rom/uart.h b/tools/sdk/esp32c3/include/esp_rom/include/esp32/rom/uart.h index 3eb59f30f96..3bd0d38f484 100644 --- a/tools/sdk/esp32c3/include/esp_rom/include/esp32/rom/uart.h +++ b/tools/sdk/esp32c3/include/esp_rom/include/esp32/rom/uart.h @@ -227,7 +227,7 @@ void uart_buff_switch(uint8_t uart_no); * * @return OK. */ -STATUS uart_tx_one_char(uint8_t TxChar); +ETS_STATUS uart_tx_one_char(uint8_t TxChar); /** * @brief Output a char to message exchange channel, wait until fifo not full. @@ -237,7 +237,7 @@ STATUS uart_tx_one_char(uint8_t TxChar); * * @return OK. */ -STATUS uart_tx_one_char2(uint8_t TxChar); +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); /** * @brief Wait until uart tx full empty. @@ -273,7 +273,7 @@ static inline void IRAM_ATTR uart_tx_wait_idle(uint8_t uart_no) { * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_one_char(uint8_t *pRxChar); +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); /** * @brief Get an input char from message channel, wait until successful. @@ -295,7 +295,7 @@ char uart_rx_one_char_block(void); * * @return OK. */ -STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); /** * @brief Process uart received information in the interrupt handler. @@ -318,7 +318,7 @@ void uart_rx_intr_handler(void *para); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); /** * @brief Get all chars from receive buffer. @@ -329,7 +329,7 @@ STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); * @return OK for successful. * FAIL for failed. */ -STATUS UartGetCmdLn(uint8_t *pCmdLn); +ETS_STATUS UartGetCmdLn(uint8_t *pCmdLn); /** * @brief Get uart configuration struct. @@ -379,7 +379,7 @@ int recv_packet(uint8_t *p, int len, uint8_t is_sync); * @return OK for successful. * FAIL for failed. */ -STATUS SendMsg(uint8_t *pData, uint16_t DataLen); +ETS_STATUS SendMsg(uint8_t *pData, uint16_t DataLen); /** * @brief Receive an packet from download tool, with SLIP escaping. @@ -395,7 +395,7 @@ STATUS SendMsg(uint8_t *pData, uint16_t DataLen); * @return OK for successful. * FAIL for failed. */ -STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync); +ETS_STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync); extern UartDevice UartDev; diff --git a/tools/sdk/esp32c3/include/esp_rom/include/esp32c2/rom/ets_sys.h b/tools/sdk/esp32c3/include/esp_rom/include/esp32c2/rom/ets_sys.h index 6d2e3a4ef4e..ad642fcc460 100644 --- a/tools/sdk/esp32c3/include/esp_rom/include/esp32c2/rom/ets_sys.h +++ b/tools/sdk/esp32c3/include/esp_rom/include/esp32c2/rom/ets_sys.h @@ -43,7 +43,10 @@ extern "C" { typedef enum { ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1 /**< return failed in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, } ETS_STATUS; typedef ETS_STATUS ets_status_t; @@ -438,13 +441,16 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); #define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) typedef enum { OK = 0, FAIL, PENDING, BUSY, CANCEL, -} STATUS; +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif /** * @} diff --git a/tools/sdk/esp32c3/include/esp_rom/include/esp32c2/rom/uart.h b/tools/sdk/esp32c3/include/esp_rom/include/esp32c2/rom/uart.h index 8a4507e8108..454e0d83a11 100644 --- a/tools/sdk/esp32c3/include/esp_rom/include/esp32c2/rom/uart.h +++ b/tools/sdk/esp32c3/include/esp_rom/include/esp32c2/rom/uart.h @@ -205,7 +205,7 @@ void uart_tx_switch(uint8_t uart_no); * * @return OK. */ -STATUS uart_tx_one_char(uint8_t TxChar); +ETS_STATUS uart_tx_one_char(uint8_t TxChar); /** * @brief Output a char to message exchange channel, wait until fifo not full. @@ -215,7 +215,7 @@ STATUS uart_tx_one_char(uint8_t TxChar); * * @return OK. */ -STATUS uart_tx_one_char2(uint8_t TxChar); +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); /** * @brief Wait until uart tx full empty. @@ -245,7 +245,7 @@ void uart_tx_wait_idle(uint8_t uart_no); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_one_char(uint8_t *pRxChar); +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); /** * @brief Get an input char from message channel, wait until successful. @@ -267,7 +267,7 @@ char uart_rx_one_char_block(void); * * @return OK. */ -STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); /** * @brief Get an char from receive buffer. @@ -280,7 +280,7 @@ STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); /** * @brief Get all chars from receive buffer. @@ -291,7 +291,7 @@ STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); * @return OK for successful. * FAIL for failed. */ -STATUS UartGetCmdLn(uint8_t *pCmdLn); +ETS_STATUS UartGetCmdLn(uint8_t *pCmdLn); /** * @brief Get uart configuration struct. diff --git a/tools/sdk/esp32c3/include/esp_rom/include/esp32c3/rom/ets_sys.h b/tools/sdk/esp32c3/include/esp_rom/include/esp32c3/rom/ets_sys.h index d5489bd835d..06b3b47d8c2 100644 --- a/tools/sdk/esp32c3/include/esp_rom/include/esp32c3/rom/ets_sys.h +++ b/tools/sdk/esp32c3/include/esp_rom/include/esp32c3/rom/ets_sys.h @@ -43,7 +43,10 @@ extern "C" { typedef enum { ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1 /**< return failed in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, } ETS_STATUS; typedef ETS_STATUS ets_status_t; @@ -430,13 +433,16 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); #define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) typedef enum { OK = 0, FAIL, PENDING, BUSY, CANCEL, -} STATUS; +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif /** * @} diff --git a/tools/sdk/esp32c3/include/esp_rom/include/esp32c3/rom/uart.h b/tools/sdk/esp32c3/include/esp_rom/include/esp32c3/rom/uart.h index 0cd91b06d57..a4fbd52077f 100644 --- a/tools/sdk/esp32c3/include/esp_rom/include/esp32c3/rom/uart.h +++ b/tools/sdk/esp32c3/include/esp_rom/include/esp32c3/rom/uart.h @@ -195,7 +195,7 @@ void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue); * * @return OK. */ -STATUS uart_tx_one_char(uint8_t TxChar); +ETS_STATUS uart_tx_one_char(uint8_t TxChar); /** * @brief Output a char to message exchange channel, wait until fifo not full. @@ -205,7 +205,7 @@ STATUS uart_tx_one_char(uint8_t TxChar); * * @return OK. */ -STATUS uart_tx_one_char2(uint8_t TxChar); +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); /** * @brief Wait until uart tx full empty. @@ -235,7 +235,7 @@ void uart_tx_wait_idle(uint8_t uart_no); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_one_char(uint8_t *pRxChar); +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); /** * @brief Get an input char from message channel, wait until successful. @@ -257,7 +257,7 @@ char uart_rx_one_char_block(void); * * @return OK. */ -STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); /** * @brief Get an char from receive buffer. @@ -270,7 +270,7 @@ STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); /** * @brief Get uart configuration struct. diff --git a/tools/sdk/esp32c3/include/esp_rom/include/esp32c6/rom/ets_sys.h b/tools/sdk/esp32c3/include/esp_rom/include/esp32c6/rom/ets_sys.h index 48a724d54b8..7c04af3a54c 100644 --- a/tools/sdk/esp32c3/include/esp_rom/include/esp32c6/rom/ets_sys.h +++ b/tools/sdk/esp32c3/include/esp_rom/include/esp32c6/rom/ets_sys.h @@ -43,7 +43,10 @@ extern "C" { typedef enum { ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1 /**< return failed in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, } ETS_STATUS; typedef ETS_STATUS ets_status_t; @@ -407,13 +410,16 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); #define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) typedef enum { OK = 0, FAIL, PENDING, BUSY, CANCEL, -} STATUS; +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif /** * @} diff --git a/tools/sdk/esp32c3/include/esp_rom/include/esp32c6/rom/uart.h b/tools/sdk/esp32c3/include/esp_rom/include/esp32c6/rom/uart.h index 380f19a4e56..9045c42f6f6 100644 --- a/tools/sdk/esp32c3/include/esp_rom/include/esp32c6/rom/uart.h +++ b/tools/sdk/esp32c3/include/esp_rom/include/esp32c6/rom/uart.h @@ -205,7 +205,7 @@ void uart_tx_switch(uint8_t uart_no); * * @return OK. */ -STATUS uart_tx_one_char(uint8_t TxChar); +ETS_STATUS uart_tx_one_char(uint8_t TxChar); /** * @brief Output a char to message exchange channel, wait until fifo not full. @@ -215,7 +215,7 @@ STATUS uart_tx_one_char(uint8_t TxChar); * * @return OK. */ -STATUS uart_tx_one_char2(uint8_t TxChar); +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); /** * @brief Wait until uart tx full empty. @@ -245,7 +245,7 @@ void uart_tx_wait_idle(uint8_t uart_no); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_one_char(uint8_t *pRxChar); +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); /** * @brief Get an input char from message channel, wait until successful. @@ -267,7 +267,7 @@ char uart_rx_one_char_block(void); * * @return OK. */ -STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); /** * @brief Process uart recevied information in the interrupt handler. @@ -290,7 +290,7 @@ void uart_rx_intr_handler(void *para); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); /** * @brief Get all chars from receive buffer. @@ -301,7 +301,7 @@ STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); * @return OK for successful. * FAIL for failed. */ -STATUS UartGetCmdLn(uint8_t *pCmdLn); +ETS_STATUS UartGetCmdLn(uint8_t *pCmdLn); /** * @brief Get uart configuration struct. diff --git a/tools/sdk/esp32c3/include/esp_rom/include/esp32h2/rom/efuse.h b/tools/sdk/esp32c3/include/esp_rom/include/esp32h2/rom/efuse.h index 6cd9f4b377e..dc612dff4b8 100644 --- a/tools/sdk/esp32c3/include/esp_rom/include/esp32h2/rom/efuse.h +++ b/tools/sdk/esp32c3/include/esp_rom/include/esp32h2/rom/efuse.h @@ -27,7 +27,8 @@ extern "C" { typedef enum { ETS_EFUSE_KEY_PURPOSE_USER = 0, - ETS_EFUSE_KEY_PURPOSE_RESERVED = 1, + ETS_EFUSE_KEY_PURPOSE_ECDSA_KEY = 1, + ETS_EFUSE_KEY_PURPOSE_RESERVED = 2, ETS_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, diff --git a/tools/sdk/esp32c3/include/esp_rom/include/esp32h2/rom/ets_sys.h b/tools/sdk/esp32c3/include/esp_rom/include/esp32h2/rom/ets_sys.h index b9ac5a13f41..b9247bc3bdf 100644 --- a/tools/sdk/esp32c3/include/esp_rom/include/esp32h2/rom/ets_sys.h +++ b/tools/sdk/esp32c3/include/esp_rom/include/esp32h2/rom/ets_sys.h @@ -43,7 +43,10 @@ extern "C" { typedef enum { ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1 /**< return failed in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, } ETS_STATUS; typedef ETS_STATUS ets_status_t; @@ -406,13 +409,16 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); #define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) typedef enum { OK = 0, FAIL, PENDING, BUSY, CANCEL, -} STATUS; +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif /** * @} diff --git a/tools/sdk/esp32c3/include/esp_rom/include/esp32h2/rom/uart.h b/tools/sdk/esp32c3/include/esp_rom/include/esp32h2/rom/uart.h index 380f19a4e56..9045c42f6f6 100644 --- a/tools/sdk/esp32c3/include/esp_rom/include/esp32h2/rom/uart.h +++ b/tools/sdk/esp32c3/include/esp_rom/include/esp32h2/rom/uart.h @@ -205,7 +205,7 @@ void uart_tx_switch(uint8_t uart_no); * * @return OK. */ -STATUS uart_tx_one_char(uint8_t TxChar); +ETS_STATUS uart_tx_one_char(uint8_t TxChar); /** * @brief Output a char to message exchange channel, wait until fifo not full. @@ -215,7 +215,7 @@ STATUS uart_tx_one_char(uint8_t TxChar); * * @return OK. */ -STATUS uart_tx_one_char2(uint8_t TxChar); +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); /** * @brief Wait until uart tx full empty. @@ -245,7 +245,7 @@ void uart_tx_wait_idle(uint8_t uart_no); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_one_char(uint8_t *pRxChar); +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); /** * @brief Get an input char from message channel, wait until successful. @@ -267,7 +267,7 @@ char uart_rx_one_char_block(void); * * @return OK. */ -STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); /** * @brief Process uart recevied information in the interrupt handler. @@ -290,7 +290,7 @@ void uart_rx_intr_handler(void *para); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); /** * @brief Get all chars from receive buffer. @@ -301,7 +301,7 @@ STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); * @return OK for successful. * FAIL for failed. */ -STATUS UartGetCmdLn(uint8_t *pCmdLn); +ETS_STATUS UartGetCmdLn(uint8_t *pCmdLn); /** * @brief Get uart configuration struct. diff --git a/tools/sdk/esp32c3/include/esp_rom/include/esp32h4/rom/ets_sys.h b/tools/sdk/esp32c3/include/esp_rom/include/esp32h4/rom/ets_sys.h index 902127abfbb..91544de628a 100644 --- a/tools/sdk/esp32c3/include/esp_rom/include/esp32h4/rom/ets_sys.h +++ b/tools/sdk/esp32c3/include/esp_rom/include/esp32h4/rom/ets_sys.h @@ -43,7 +43,10 @@ extern "C" { typedef enum { ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1 /**< return failed in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, } ETS_STATUS; typedef ETS_STATUS ets_status_t; @@ -441,13 +444,16 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); #define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) typedef enum { OK = 0, FAIL, PENDING, BUSY, CANCEL, -} STATUS; +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif /** * @} diff --git a/tools/sdk/esp32c3/include/esp_rom/include/esp32h4/rom/uart.h b/tools/sdk/esp32c3/include/esp_rom/include/esp32h4/rom/uart.h index d271893d761..28677ac4097 100644 --- a/tools/sdk/esp32c3/include/esp_rom/include/esp32h4/rom/uart.h +++ b/tools/sdk/esp32c3/include/esp_rom/include/esp32h4/rom/uart.h @@ -205,7 +205,7 @@ void uart_tx_switch(uint8_t uart_no); * * @return OK. */ -STATUS uart_tx_one_char(uint8_t TxChar); +ETS_STATUS uart_tx_one_char(uint8_t TxChar); /** * @brief Output a char to message exchange channel, wait until fifo not full. @@ -215,7 +215,7 @@ STATUS uart_tx_one_char(uint8_t TxChar); * * @return OK. */ -STATUS uart_tx_one_char2(uint8_t TxChar); +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); /** * @brief Wait until uart tx full empty. @@ -245,7 +245,7 @@ void uart_tx_wait_idle(uint8_t uart_no); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_one_char(uint8_t *pRxChar); +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); /** * @brief Get an input char from message channel, wait until successful. @@ -267,7 +267,7 @@ char uart_rx_one_char_block(void); * * @return OK. */ -STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); /** * @brief Get an char from receive buffer. @@ -280,7 +280,7 @@ STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); /** * @brief Get all chars from receive buffer. @@ -291,7 +291,7 @@ STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); * @return OK for successful. * FAIL for failed. */ -STATUS UartGetCmdLn(uint8_t *pCmdLn); +ETS_STATUS UartGetCmdLn(uint8_t *pCmdLn); /** * @brief Get uart configuration struct. diff --git a/tools/sdk/esp32c3/include/esp_rom/include/esp32s2/rom/ets_sys.h b/tools/sdk/esp32c3/include/esp_rom/include/esp32s2/rom/ets_sys.h index a2cf1adce34..19c1994de71 100644 --- a/tools/sdk/esp32c3/include/esp_rom/include/esp32s2/rom/ets_sys.h +++ b/tools/sdk/esp32c3/include/esp_rom/include/esp32s2/rom/ets_sys.h @@ -45,7 +45,10 @@ extern "C" { typedef enum { ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1 /**< return failed in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, } ETS_STATUS; typedef ETS_STATUS ets_status_t; @@ -556,13 +559,16 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); #define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) typedef enum { OK = 0, FAIL, PENDING, BUSY, CANCEL, -} STATUS; +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif /** * @} diff --git a/tools/sdk/esp32c3/include/esp_rom/include/esp32s2/rom/uart.h b/tools/sdk/esp32c3/include/esp_rom/include/esp32s2/rom/uart.h index 899413f3171..491d2c28fbe 100644 --- a/tools/sdk/esp32c3/include/esp_rom/include/esp32s2/rom/uart.h +++ b/tools/sdk/esp32c3/include/esp_rom/include/esp32s2/rom/uart.h @@ -1,16 +1,8 @@ -// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _ROM_UART_H_ #define _ROM_UART_H_ @@ -251,7 +243,7 @@ void uart_buff_switch(uint8_t uart_no); * * @return OK. */ -STATUS uart_tx_one_char(uint8_t TxChar); +ETS_STATUS uart_tx_one_char(uint8_t TxChar); /** * @brief Output a char to message exchange channel, wait until fifo not full. @@ -261,7 +253,7 @@ STATUS uart_tx_one_char(uint8_t TxChar); * * @return OK. */ -STATUS uart_tx_one_char2(uint8_t TxChar); +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); /** * @brief Wait until uart tx full empty. @@ -291,7 +283,7 @@ void uart_tx_wait_idle(uint8_t uart_no); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_one_char(uint8_t *pRxChar); +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); /** * @brief Get an input char from message channel, wait until successful. @@ -313,7 +305,7 @@ char uart_rx_one_char_block(void); * * @return OK. */ -STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); /** * @brief Process uart recevied information in the interrupt handler. @@ -336,7 +328,7 @@ void uart_rx_intr_handler(void *para); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); /** * @brief Get all chars from receive buffer. @@ -347,7 +339,7 @@ STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); * @return OK for successful. * FAIL for failed. */ -STATUS UartGetCmdLn(uint8_t *pCmdLn); +ETS_STATUS UartGetCmdLn(uint8_t *pCmdLn); /** * @brief Get uart configuration struct. @@ -397,7 +389,7 @@ int recv_packet(uint8_t *p, int len, uint8_t is_sync); * @return OK for successful. * FAIL for failed. */ -STATUS SendMsg(uint8_t *pData, uint16_t DataLen); +ETS_STATUS SendMsg(uint8_t *pData, uint16_t DataLen); /** * @brief Receive an packet from download tool, with SLIP escaping. @@ -413,7 +405,7 @@ STATUS SendMsg(uint8_t *pData, uint16_t DataLen); * @return OK for successful. * FAIL for failed. */ -STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync); +ETS_STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync); /** * @brief Check if this UART is in download connection. diff --git a/tools/sdk/esp32c3/include/esp_rom/include/esp32s3/rom/ets_sys.h b/tools/sdk/esp32c3/include/esp_rom/include/esp32s3/rom/ets_sys.h index 9047442c36e..83c93b2eb6a 100644 --- a/tools/sdk/esp32c3/include/esp_rom/include/esp32s3/rom/ets_sys.h +++ b/tools/sdk/esp32c3/include/esp_rom/include/esp32s3/rom/ets_sys.h @@ -43,7 +43,10 @@ extern "C" { typedef enum { ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1 /**< return failed in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, } ETS_STATUS; typedef ETS_STATUS ets_status_t; @@ -543,13 +546,16 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); #define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) typedef enum { OK = 0, FAIL, PENDING, BUSY, CANCEL, -} STATUS; +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif /** * @} diff --git a/tools/sdk/esp32c3/include/esp_rom/include/esp32s3/rom/uart.h b/tools/sdk/esp32c3/include/esp_rom/include/esp32s3/rom/uart.h index 3486886ad54..864563f7883 100644 --- a/tools/sdk/esp32c3/include/esp_rom/include/esp32s3/rom/uart.h +++ b/tools/sdk/esp32c3/include/esp_rom/include/esp32s3/rom/uart.h @@ -203,7 +203,7 @@ void uart_tx_switch(uint8_t uart_no); * * @return OK. */ -STATUS uart_tx_one_char(uint8_t TxChar); +ETS_STATUS uart_tx_one_char(uint8_t TxChar); /** * @brief Output a char to message exchange channel, wait until fifo not full. @@ -213,7 +213,7 @@ STATUS uart_tx_one_char(uint8_t TxChar); * * @return OK. */ -STATUS uart_tx_one_char2(uint8_t TxChar); +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); /** * @brief Wait until uart tx full empty. @@ -243,7 +243,7 @@ void uart_tx_wait_idle(uint8_t uart_no); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_one_char(uint8_t *pRxChar); +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); /** * @brief Get an input char from message channel, wait until successful. @@ -265,7 +265,7 @@ char uart_rx_one_char_block(void); * * @return OK. */ -STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); /** * @brief Get an char from receive buffer. @@ -278,7 +278,7 @@ STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); /** * @brief Get uart configuration struct. diff --git a/tools/sdk/esp32c3/include/esp_wifi/include/esp_mesh.h b/tools/sdk/esp32c3/include/esp_wifi/include/esp_mesh.h index 78f65945051..5ba707b527e 100644 --- a/tools/sdk/esp32c3/include/esp_wifi/include/esp_mesh.h +++ b/tools/sdk/esp32c3/include/esp_wifi/include/esp_mesh.h @@ -174,7 +174,8 @@ typedef enum { MESH_EVENT_PARENT_DISCONNECTED, /**< parent is disconnected on station interface */ MESH_EVENT_NO_PARENT_FOUND, /**< no parent found */ MESH_EVENT_LAYER_CHANGE, /**< layer changes over the mesh network */ - MESH_EVENT_TODS_STATE, /**< state represents whether the root is able to access external IP network */ + MESH_EVENT_TODS_STATE, /**< state represents whether the root is able to access external IP network. + This state is a manual event that needs to be triggered with esp_mesh_post_toDS_state(). */ MESH_EVENT_VOTE_STARTED, /**< the process of voting a new root is started either by children or by the root */ MESH_EVENT_VOTE_STOPPED, /**< the process of voting a new root is stopped */ MESH_EVENT_ROOT_ADDRESS, /**< the root address is obtained. It is posted by mesh stack automatically. */ @@ -1175,7 +1176,10 @@ esp_err_t esp_mesh_get_rx_pending(mesh_rx_pending_t *pending); int esp_mesh_available_txupQ_num(const mesh_addr_t *addr, uint32_t *xseqno_in); /** - * @brief Set the number of queue + * @brief Set the number of RX queue for the node, the average number of window allocated to one of + * its child node is: wnd = xon_qsize / (2 * max_connection + 1). + * However, the window of each child node is not strictly equal to the average value, + * it is affected by the traffic also. * * @attention This API shall be called before mesh is started. * diff --git a/tools/sdk/esp32c3/include/esp_wifi/include/esp_wifi.h b/tools/sdk/esp32c3/include/esp_wifi/include/esp_wifi.h index 863ebb7d702..3c0ade914b1 100644 --- a/tools/sdk/esp32c3/include/esp_wifi/include/esp_wifi.h +++ b/tools/sdk/esp32c3/include/esp_wifi/include/esp_wifi.h @@ -660,10 +660,10 @@ esp_err_t esp_wifi_get_country(wifi_country_t *country); /** - * @brief Set MAC address of WiFi station or the soft-AP interface. + * @brief Set MAC address of WiFi station, soft-AP or NAN interface. * * @attention 1. This API can only be called when the interface is disabled - * @attention 2. Soft-AP and station have different MAC addresses, do not set them to be the same. + * @attention 2. Above mentioned interfaces have different MAC addresses, do not set them to be the same. * @attention 3. The bit 0 of the first byte of MAC address can not be 1. For example, the MAC address * can set to be "1a:XX:XX:XX:XX:XX", but can not be "15:XX:XX:XX:XX:XX". * @@ -1151,6 +1151,7 @@ esp_err_t esp_wifi_set_inactive_time(wifi_interface_t ifx, uint16_t sec); * @return * - ESP_OK: succeed * - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init + * - ESP_ERR_WIFI_NOT_STARTED: WiFi is not started by esp_wifi_start * - ESP_ERR_WIFI_ARG: invalid argument */ esp_err_t esp_wifi_get_inactive_time(wifi_interface_t ifx, uint16_t *sec); @@ -1348,6 +1349,19 @@ esp_err_t esp_wifi_sta_get_aid(uint16_t *aid); */ esp_err_t esp_wifi_sta_get_negotiated_phymode(wifi_phy_mode_t *phymode); +/** + * @brief Config dynamic carrier sense + * + * @attention This API should be called after esp_wifi_start(). + * + * @param enabled Dynamic carrier sense is enabled or not. + * + * @return + * - ESP_OK: succeed + * - others: failed + */ +esp_err_t esp_wifi_set_dynamic_cs(bool enabled); + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32c3/include/esp_wifi/include/esp_wifi_types.h b/tools/sdk/esp32c3/include/esp_wifi/include/esp_wifi_types.h index ac12c34b497..614bcd2cb5b 100644 --- a/tools/sdk/esp32c3/include/esp_wifi/include/esp_wifi_types.h +++ b/tools/sdk/esp32c3/include/esp_wifi/include/esp_wifi_types.h @@ -129,6 +129,7 @@ typedef enum { WIFI_REASON_AP_TSF_RESET = 206, WIFI_REASON_ROAMING = 207, WIFI_REASON_ASSOC_COMEBACK_TIME_TOO_LONG = 208, + WIFI_REASON_SA_QUERY_TIMEOUT = 209, } wifi_err_reason_t; typedef enum { diff --git a/tools/sdk/esp32c3/include/esp_wifi/wifi_apps/include/esp_nan.h b/tools/sdk/esp32c3/include/esp_wifi/wifi_apps/include/esp_nan.h index 0fba2bf5f57..9be6bbb6659 100644 --- a/tools/sdk/esp32c3/include/esp_wifi/wifi_apps/include/esp_nan.h +++ b/tools/sdk/esp32c3/include/esp_wifi/wifi_apps/include/esp_nan.h @@ -120,8 +120,8 @@ esp_err_t esp_wifi_nan_cancel_service(uint8_t service_id); * @param req NAN Datapath Request parameters. * * @return - * - non-zero: NAN Datapath Identifier - * - zero: failed + * - non-zero NAN Datapath identifier: If NAN datapath req was accepted by publisher + * - zero: If NAN datapath req was rejected by publisher or a timeout occurs */ uint8_t esp_wifi_nan_datapath_req(wifi_nan_datapath_req_t *req); diff --git a/tools/sdk/esp32c3/include/freertos/FreeRTOS-Kernel/portable/riscv/include/freertos/FreeRTOSConfig_arch.h b/tools/sdk/esp32c3/include/freertos/FreeRTOS-Kernel/portable/riscv/include/freertos/FreeRTOSConfig_arch.h deleted file mode 100644 index f7a8110521d..00000000000 --- a/tools/sdk/esp32c3/include/freertos/FreeRTOS-Kernel/portable/riscv/include/freertos/FreeRTOSConfig_arch.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef FREERTOS_CONFIG_RISCV_H -#define FREERTOS_CONFIG_RISCV_H - -//RISC-V Archiecture specific configuration. This file is included in the common FreeRTOSConfig.h. - -#include "sdkconfig.h" - -/* ------------------------------------------------- FreeRTOS Config --------------------------------------------------- - * - All Vanilla FreeRTOS configuration goes into this section - * ------------------------------------------------------------------------------------------------------------------ */ - -// ------------------ Scheduler Related -------------------- - -#ifdef CONFIG_FREERTOS_OPTIMIZED_SCHEDULER -#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 -#else -#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 -#endif -#define configMAX_API_CALL_INTERRUPT_PRIORITY 0 - -/* ------------------------------------------------ ESP-IDF Additions -------------------------------------------------- - * - * ------------------------------------------------------------------------------------------------------------------ */ - -#ifndef configISR_STACK_SIZE -#define configISR_STACK_SIZE (CONFIG_FREERTOS_ISR_STACKSIZE) -#endif - -#endif // FREERTOS_CONFIG_RISCV_H diff --git a/tools/sdk/esp32c3/include/freertos/FreeRTOS-Kernel/portable/riscv/include/freertos/portmacro.h b/tools/sdk/esp32c3/include/freertos/FreeRTOS-Kernel/portable/riscv/include/freertos/portmacro.h index 055ee338816..b889f02bba7 100644 --- a/tools/sdk/esp32c3/include/freertos/FreeRTOS-Kernel/portable/riscv/include/freertos/portmacro.h +++ b/tools/sdk/esp32c3/include/freertos/FreeRTOS-Kernel/portable/riscv/include/freertos/portmacro.h @@ -385,6 +385,14 @@ FORCE_INLINE_ATTR BaseType_t xPortGetCoreID(void) #define portALT_GET_RUN_TIME_COUNTER_VALUE(x) do {x = (uint32_t)esp_timer_get_time();} while(0) #endif +// --------------------- TCB Cleanup ----------------------- + +#if CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP +/* If enabled, users must provide an implementation of vPortCleanUpTCB() */ +extern void vPortCleanUpTCB ( void *pxTCB ); +#define portCLEAN_UP_TCB( pxTCB ) vPortCleanUpTCB( pxTCB ) +#endif /* CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP */ + // -------------- Optimized Task Selection ----------------- #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 @@ -424,7 +432,7 @@ FORCE_INLINE_ATTR bool xPortCanYield(void) /* ------------------------------------------------------ Misc --------------------------------------------------------- * - Miscellaneous porting macros - * - These are not port of the FreeRTOS porting interface, but are used by other FreeRTOS dependent components + * - These are not part of the FreeRTOS porting interface, but are used by other FreeRTOS dependent components * ------------------------------------------------------------------------------------------------------------------ */ // -------------------- Heap Related ----------------------- diff --git a/tools/sdk/esp32c3/include/freertos/esp_additions/arch/riscv/include/freertos/FreeRTOSConfig_arch.h b/tools/sdk/esp32c3/include/freertos/esp_additions/arch/riscv/include/freertos/FreeRTOSConfig_arch.h new file mode 100644 index 00000000000..f4b4996d2f4 --- /dev/null +++ b/tools/sdk/esp32c3/include/freertos/esp_additions/arch/riscv/include/freertos/FreeRTOSConfig_arch.h @@ -0,0 +1,58 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/* RISC-V Architecture specific configuration. This file is included in the common FreeRTOSConfig.h. */ + +#include "sdkconfig.h" + +/* ------------------------------------------------- FreeRTOS Config --------------------------------------------------- + * - All Vanilla FreeRTOS configuration goes into this section + * ------------------------------------------------------------------------------------------------------------------ */ + +/* ------------------ Scheduler Related -------------------- */ + +#define configMAX_PRIORITIES ( 25 ) +#ifdef CONFIG_FREERTOS_OPTIMIZED_SCHEDULER + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#endif /* CONFIG_FREERTOS_OPTIMIZED_SCHEDULER */ +#define configMINIMAL_STACK_SIZE ( CONFIG_FREERTOS_IDLE_TASK_STACKSIZE + configSTACK_OVERHEAD_TOTAL ) +#define configMAX_API_CALL_INTERRUPT_PRIORITY 0 + +/* ----------------------- System -------------------------- */ + +#define configUSE_NEWLIB_REENTRANT 1 +#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1 + +/* ----------------------- Memory ------------------------- */ + +/* This isn't used as FreeRTOS will only allocate from internal memory (see + * heap_idf.c). We simply define this macro to span all non-statically-allocated + * shared RAM. */ +#define configTOTAL_HEAP_SIZE ( &_heap_end - &_heap_start ) + +/* ------------------- Run-time Stats ---------------------- */ + +#if CONFIG_FREERTOS_USE_TRACE_FACILITY + /* Used by uxTaskGetSystemState(), and other trace facility functions */ + #define configUSE_TRACE_FACILITY 1 +#endif /* CONFIG_FREERTOS_USE_TRACE_FACILITY */ + +/* -------------------- API Includes ----------------------- */ + +#define INCLUDE_xTaskDelayUntil 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 + +/* ------------------------------------------------ ESP-IDF Additions -------------------------------------------------- + * + * ------------------------------------------------------------------------------------------------------------------ */ + +#ifndef configISR_STACK_SIZE + #define configISR_STACK_SIZE ( CONFIG_FREERTOS_ISR_STACKSIZE ) +#endif diff --git a/tools/sdk/esp32c3/include/freertos/esp_additions/include/esp_private/freertos_idf_additions_priv.h b/tools/sdk/esp32c3/include/freertos/esp_additions/include/esp_private/freertos_idf_additions_priv.h new file mode 100644 index 00000000000..c6e6ba81c08 --- /dev/null +++ b/tools/sdk/esp32c3/include/freertos/esp_additions/include/esp_private/freertos_idf_additions_priv.h @@ -0,0 +1,99 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/* + * This file is like "idf_additions.h" but for private API (i.e., only meant to + * be called by other internally by other + * ESP-IDF components. + */ + +#include "sdkconfig.h" +#include "freertos/FreeRTOS.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/* ----------------------------------------------------------------------------- + * Priority Raise/Restore + * - Special functions to forcefully raise and restore a task's priority + * - Used by cache_utils.c when disabling/enabling the cache + * -------------------------------------------------------------------------- */ + +#if ( INCLUDE_vTaskPrioritySet == 1 ) + + typedef struct + { + UBaseType_t uxPriority; + #if ( configUSE_MUTEXES == 1 ) + UBaseType_t uxBasePriority; + #endif + } prvTaskSavedPriority_t; + +/** + * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be + * available. See the configuration section for more information. + * + * Saves the current priority and current base priority of a task, then + * raises the task's current and base priority to uxNewPriority if + * uxNewPriority is of a higher priority. + * + * Once a task's priority has been raised with this function, the priority + * can be restored by calling prvTaskPriorityRestore() + * + * - Note that this function differs from vTaskPrioritySet() as the task's + * current priority will be modified even if the task has already + * inherited a priority. + * - This function is intended for special circumstance where a task must be + * forced immediately to a higher priority. + * + * For configUSE_MUTEXES == 0: A context switch will occur before the + * function returns if the priority being set is higher than the currently + * executing task. + * + * @note This functions is private and should only be called internally + * within various IDF components. Users should never call this function from + * their application. + * + * @note vTaskPrioritySet() should not be called while a task's priority is + * already raised via this function + * + * @param pxSavedPriority returns base and current priorities + * + * @param uxNewPriority The priority to which the task's priority will be + * set. + */ + void prvTaskPriorityRaise( prvTaskSavedPriority_t * pxSavedPriority, + UBaseType_t uxNewPriority ); + +/** + * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be + * available. + * See the configuration section for more information. + * + * Restore a task's priority that was previously raised by + * prvTaskPriorityRaise(). + * + * For configUSE_MUTEXES == 0: A context switch will occur before the function + * returns if the priority + * being set is higher than the currently executing task. + * + * @note This functions is private and should only be called internally within + * various IDF components. Users should never call this function from their + * application. + * + * @param pxSavedPriority previously saved base and current priorities that need + * to be restored + */ + void prvTaskPriorityRestore( prvTaskSavedPriority_t * pxSavedPriority ); + +#endif // ( INCLUDE_vTaskPrioritySet == 1) + +#ifdef __cplusplus + } +#endif diff --git a/tools/sdk/esp32c3/include/freertos/esp_additions/include/freertos/FreeRTOSConfig.h b/tools/sdk/esp32c3/include/freertos/esp_additions/include/freertos/FreeRTOSConfig.h index 182ca817180..3a3c10ea253 100644 --- a/tools/sdk/esp32c3/include/freertos/esp_additions/include/freertos/FreeRTOSConfig.h +++ b/tools/sdk/esp32c3/include/freertos/esp_additions/include/freertos/FreeRTOSConfig.h @@ -1,293 +1,285 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H +#pragma once #include "sdkconfig.h" -/* -This file gets pulled into assembly sources. Therefore, some includes need to be wrapped in #ifndef __ASSEMBLER__ -*/ +/* This file gets pulled into assembly sources. Therefore, some includes need to + * be wrapped in #ifndef __ASSEMBLER__ */ #ifndef __ASSEMBLER__ -#include //For configASSERT() + /* For configASSERT() */ + #include #endif /* def __ASSEMBLER__ */ -#ifdef CONFIG_FREERTOS_SMP - -// Pull in the SMP configuration -#include "freertos/FreeRTOSConfig_smp.h" - -#else // CONFIG_FREERTOS_SMP - -// The arch-specific FreeRTOSConfig_arch.h in port//include. -#include "freertos/FreeRTOSConfig_arch.h" - -#if !(defined(FREERTOS_CONFIG_XTENSA_H) \ - || defined(FREERTOS_CONFIG_RISCV_H) \ - || defined(FREERTOS_CONFIG_LINUX_H)) -#error "Needs architecture-speific FreeRTOSConfig.h!" -#endif - /* ----------------------------------------------------- Helpers ------------------------------------------------------- * - Macros that the FreeRTOS configuration macros depend on * ------------------------------------------------------------------------------------------------------------------ */ /* Higher stack checker modes cause overhead on each function call */ #if CONFIG_STACK_CHECK_ALL || CONFIG_STACK_CHECK_STRONG -#define STACK_OVERHEAD_CHECKER 256 + #define STACK_OVERHEAD_CHECKER 256 #else -#define STACK_OVERHEAD_CHECKER 0 + #define STACK_OVERHEAD_CHECKER 0 #endif /* with optimizations disabled, scheduler uses additional stack */ #if CONFIG_COMPILER_OPTIMIZATION_NONE -#define STACK_OVERHEAD_OPTIMIZATION 320 + #define STACK_OVERHEAD_OPTIMIZATION 320 #else -#define STACK_OVERHEAD_OPTIMIZATION 0 + #define STACK_OVERHEAD_OPTIMIZATION 0 #endif /* apptrace mdule increases minimum stack usage */ #if CONFIG_APPTRACE_ENABLE -#define STACK_OVERHEAD_APPTRACE 1280 + #define STACK_OVERHEAD_APPTRACE 1280 #else -#define STACK_OVERHEAD_APPTRACE 0 + #define STACK_OVERHEAD_APPTRACE 0 #endif /* Stack watchpoint decreases minimum usable stack size by up to 60 bytes. - See FreeRTOS FREERTOS_WATCHPOINT_END_OF_STACK option in Kconfig. */ + * See FreeRTOS FREERTOS_WATCHPOINT_END_OF_STACK option in Kconfig. */ #if CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK -#define STACK_OVERHEAD_WATCHPOINT 60 + #define STACK_OVERHEAD_WATCHPOINT 60 #else -#define STACK_OVERHEAD_WATCHPOINT 0 + #define STACK_OVERHEAD_WATCHPOINT 0 #endif -#define configSTACK_OVERHEAD_TOTAL ( \ - STACK_OVERHEAD_CHECKER + \ - STACK_OVERHEAD_OPTIMIZATION + \ - STACK_OVERHEAD_APPTRACE + \ - STACK_OVERHEAD_WATCHPOINT \ - ) +#define configSTACK_OVERHEAD_TOTAL \ + ( \ + STACK_OVERHEAD_CHECKER + \ + STACK_OVERHEAD_OPTIMIZATION + \ + STACK_OVERHEAD_APPTRACE + \ + STACK_OVERHEAD_WATCHPOINT \ + ) + +/* The arch-specific FreeRTOSConfig_arch.h in esp_additions/arch_include/. + * Placed here due to configSTACK_OVERHEAD_TOTAL. Todo: IDF-5712. */ +#include "freertos/FreeRTOSConfig_arch.h" /* ------------------------------------------------- FreeRTOS Config --------------------------------------------------- * - All Vanilla FreeRTOS configuration goes into this section * - Keep this section in-sync with the corresponding version of single-core upstream version of FreeRTOS - * - Don't put any SMP or ESP-IDF exclusive FreeRTOS configurations here. Those go into the next section + * - Don't put any Amazon SMP FreeRTOS or IDF FreeRTOS configurations here. Those go into the next section * - Not all FreeRTOS configuration are listed. Some configurations have default values set in FreeRTOS.h thus don't * need to be explicitly defined. * ------------------------------------------------------------------------------------------------------------------ */ /*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - * - * See http://www.freertos.org/a00110.html - *----------------------------------------------------------*/ - -// ------------------ Scheduler Related -------------------- - -#define configUSE_PREEMPTION 1 -#define configUSE_TICKLESS_IDLE CONFIG_FREERTOS_USE_TICKLESS_IDLE +* Application specific definitions. +* +* These definitions should be adjusted for your particular hardware and +* application requirements. +* +* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE +* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. +* +* See http://www.freertos.org/a00110.html +*----------------------------------------------------------*/ + +/* ------------------ Scheduler Related -------------------- */ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE CONFIG_FREERTOS_USE_TICKLESS_IDLE #if configUSE_TICKLESS_IDLE -#define configEXPECTED_IDLE_TIME_BEFORE_SLEEP CONFIG_FREERTOS_IDLE_TIME_BEFORE_SLEEP -#endif //configUSE_TICKLESS_IDLE -#define configCPU_CLOCK_HZ (CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ * 1000000) -#define configTICK_RATE_HZ CONFIG_FREERTOS_HZ -#ifdef CONFIG_IDF_TARGET_LINUX -#define configMAX_PRIORITIES ( 7 ) // Default in upstream simulator -/* The stack allocated by FreeRTOS will be passed to a pthread. - pthread has a minimal stack size which currently is 16KB. - The rest is for additional structures of the POSIX/Linux port. - This is a magic number since PTHREAD_STACK_MIN seems to not be a constant. */ -#define configMINIMAL_STACK_SIZE ( ( unsigned short ) (0x4000 + 40) / sizeof(portSTACK_TYPE) ) -#else -#define configMAX_PRIORITIES ( 25 ) //This has impact on speed of search for highest priority -#define configMINIMAL_STACK_SIZE ( CONFIG_FREERTOS_IDLE_TASK_STACKSIZE + configSTACK_OVERHEAD_TOTAL ) -#endif -#define configUSE_TIME_SLICING 1 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 0 -#define configKERNEL_INTERRUPT_PRIORITY 1 //Todo: This currently isn't used anywhere - -// ------------- Synchronization Primitives ---------------- - -#define configUSE_MUTEXES 1 -#define configUSE_RECURSIVE_MUTEXES 1 -#define configUSE_COUNTING_SEMAPHORES 1 -#define configUSE_QUEUE_SETS 1 -#define configQUEUE_REGISTRY_SIZE CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE -#define configUSE_TASK_NOTIFICATIONS 1 -#define configTASK_NOTIFICATION_ARRAY_ENTRIES CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES - -// ----------------------- System -------------------------- - -#define configMAX_TASK_NAME_LEN CONFIG_FREERTOS_MAX_TASK_NAME_LEN -#define configNUM_THREAD_LOCAL_STORAGE_POINTERS CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS -#define configSTACK_DEPTH_TYPE uint32_t -#ifndef CONFIG_IDF_TARGET_LINUX -#define configUSE_NEWLIB_REENTRANT 1 -#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1 -#else -#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0 // Default in upstream simulator -#endif + #define configEXPECTED_IDLE_TIME_BEFORE_SLEEP CONFIG_FREERTOS_IDLE_TIME_BEFORE_SLEEP +#endif /* configUSE_TICKLESS_IDLE */ +#define configCPU_CLOCK_HZ ( CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ * 1000000 ) +#define configTICK_RATE_HZ CONFIG_FREERTOS_HZ +#define configUSE_TIME_SLICING 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configKERNEL_INTERRUPT_PRIORITY 1 /*Todo: This currently isn't used anywhere */ + +/* ------------- Synchronization Primitives ---------------- */ + +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_QUEUE_SETS 1 +#define configQUEUE_REGISTRY_SIZE CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE +#define configUSE_TASK_NOTIFICATIONS 1 +#define configTASK_NOTIFICATION_ARRAY_ENTRIES CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES + +/* ----------------------- System -------------------------- */ + +#define configMAX_TASK_NAME_LEN CONFIG_FREERTOS_MAX_TASK_NAME_LEN +#if CONFIG_FREERTOS_SMP +/* Number of TLSP is doubled to store TLSP deletion callbacks */ + #define configNUM_THREAD_LOCAL_STORAGE_POINTERS ( CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS * 2 ) +#else /* CONFIG_FREERTOS_SMP */ + #define configNUM_THREAD_LOCAL_STORAGE_POINTERS CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS +#endif /* CONFIG_FREERTOS_SMP */ +#define configSTACK_DEPTH_TYPE uint32_t #if CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY -#define configENABLE_BACKWARD_COMPATIBILITY 1 -#else -#define configENABLE_BACKWARD_COMPATIBILITY 0 -#endif -#define configASSERT(a) assert(a) - -// ----------------------- Memory ------------------------- - -#define configSUPPORT_STATIC_ALLOCATION 1 -#define configSUPPORT_DYNAMIC_ALLOCATION 1 -#ifdef CONFIG_IDF_TARGET_LINUX -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 65 * 1024 ) ) // Default in upstream simulator -#else -//We define the heap to span all of the non-statically-allocated shared RAM. ToDo: Make sure there -//is some space left for the app and main cpu when running outside of a thread. -#define configTOTAL_HEAP_SIZE (&_heap_end - &_heap_start)//( ( size_t ) (64 * 1024) ) -#endif -#define configAPPLICATION_ALLOCATED_HEAP 1 -#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 - -// ------------------------ Hooks -------------------------- - -#define configUSE_IDLE_HOOK CONFIG_FREERTOS_USE_IDLE_HOOK -#define configUSE_TICK_HOOK CONFIG_FREERTOS_USE_TICK_HOOK + #define configENABLE_BACKWARD_COMPATIBILITY 1 +#else /* CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY */ + #define configENABLE_BACKWARD_COMPATIBILITY 0 +#endif /* CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY */ +#define configASSERT( a ) assert( a ) + +/* ----------------------- Memory ------------------------- */ + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configAPPLICATION_ALLOCATED_HEAP 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +/* ------------------------ Hooks -------------------------- */ + +#if CONFIG_FREERTOS_USE_IDLE_HOOK + #define configUSE_IDLE_HOOK 1 +#else /* CONFIG_FREERTOS_USE_IDLE_HOOK */ + #define configUSE_IDLE_HOOK 0 +#endif /* CONFIG_FREERTOS_USE_IDLE_HOOK */ +#if CONFIG_FREERTOS_USE_TICK_HOOK + #define configUSE_TICK_HOOK 1 +#else /* CONFIG_FREERTOS_USE_TICK_HOOK */ + #define configUSE_TICK_HOOK 0 +#endif /* CONFIG_FREERTOS_USE_TICK_HOOK */ #if CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE -#define configCHECK_FOR_STACK_OVERFLOW 0 + #define configCHECK_FOR_STACK_OVERFLOW 0 #elif CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL -#define configCHECK_FOR_STACK_OVERFLOW 1 + #define configCHECK_FOR_STACK_OVERFLOW 1 #elif CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY -#define configCHECK_FOR_STACK_OVERFLOW 2 -#endif -#define configRECORD_STACK_HIGH_ADDRESS 1 // This must be set as the port requires TCB.pxEndOfStack + #define configCHECK_FOR_STACK_OVERFLOW 2 +#endif /* CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE */ +#define configRECORD_STACK_HIGH_ADDRESS 1 /* This must be set as the port requires TCB.pxEndOfStack */ -// ------------------- Run-time Stats ---------------------- +/* ------------------- Run-time Stats ---------------------- */ #ifdef CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS -#define configGENERATE_RUN_TIME_STATS 1 /* Used by vTaskGetRunTimeStats() */ -#endif -#ifdef CONFIG_IDF_TARGET_LINUX -#define configUSE_TRACE_FACILITY 1 -#else -#ifdef CONFIG_FREERTOS_USE_TRACE_FACILITY -#define configUSE_TRACE_FACILITY 1 /* Used by uxTaskGetSystemState(), and other trace facility functions */ -#endif -#endif + #define configGENERATE_RUN_TIME_STATS 1 /* Used by vTaskGetRunTimeStats() */ +#endif /* CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS */ #ifdef CONFIG_FREERTOS_USE_STATS_FORMATTING_FUNCTIONS -#define configUSE_STATS_FORMATTING_FUNCTIONS 1 /* Used by vTaskList() */ -#endif + #define configUSE_STATS_FORMATTING_FUNCTIONS 1 /* Used by vTaskList() */ +#endif /* CONFIG_FREERTOS_USE_STATS_FORMATTING_FUNCTIONS */ -// -------------------- Co-routines ----------------------- +/* -------------------- Co-routines ----------------------- */ -#define configUSE_CO_ROUTINES 0 // CO_ROUTINES are not supported in ESP-IDF -#define configMAX_CO_ROUTINE_PRIORITIES 2 +#define configUSE_CO_ROUTINES 0 /* CO_ROUTINES are not supported in ESP-IDF */ +#define configMAX_CO_ROUTINE_PRIORITIES 2 -// ------------------- Software Timer ---------------------- +/* ------------------- Software Timer ---------------------- */ -#define configUSE_TIMERS 1 -#define configTIMER_TASK_PRIORITY CONFIG_FREERTOS_TIMER_TASK_PRIORITY -#define configTIMER_QUEUE_LENGTH CONFIG_FREERTOS_TIMER_QUEUE_LENGTH -#define configTIMER_TASK_STACK_DEPTH CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY CONFIG_FREERTOS_TIMER_TASK_PRIORITY +#define configTIMER_QUEUE_LENGTH CONFIG_FREERTOS_TIMER_QUEUE_LENGTH +#define configTIMER_TASK_STACK_DEPTH CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH -// -------------------- API Includes ----------------------- +/* -------------------- API Includes ----------------------- */ #if CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY -#define configENABLE_BACKWARD_COMPATIBILITY 1 -#else -#define configENABLE_BACKWARD_COMPATIBILITY 0 -#endif - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelay 1 -#define INCLUDE_xTaskGetIdleTaskHandle 1 -#define INCLUDE_xTaskAbortDelay 1 -#define INCLUDE_xSemaphoreGetMutexHolder 1 -#define INCLUDE_xTaskGetHandle 1 -#define INCLUDE_uxTaskGetStackHighWaterMark 1 -#define INCLUDE_uxTaskGetStackHighWaterMark2 1 -#define INCLUDE_eTaskGetState 1 -#define INCLUDE_xTaskResumeFromISR 1 -#define INCLUDE_xTimerPendFunctionCall 1 -#define INCLUDE_xTaskGetSchedulerState 1 -#ifdef CONFIG_IDF_TARGET_LINUX -#define INCLUDE_xTaskGetCurrentTaskHandle 0 // not defined in POSIX simulator -#define INCLUDE_vTaskDelayUntil 1 -#else -#define INCLUDE_xTaskDelayUntil 1 -#define INCLUDE_xTaskGetCurrentTaskHandle 1 -#endif -//Unlisted -#define INCLUDE_pxTaskGetStackStart 1 - -// -------------------- Trace Macros ----------------------- + #define configENABLE_BACKWARD_COMPATIBILITY 1 +#else /* CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY */ + #define configENABLE_BACKWARD_COMPATIBILITY 0 +#endif /* CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetIdleTaskHandle 1 +#define INCLUDE_xTaskAbortDelay 1 +#define INCLUDE_xSemaphoreGetMutexHolder 1 +#define INCLUDE_xTaskGetHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_uxTaskGetStackHighWaterMark2 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTaskResumeFromISR 1 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskGetSchedulerState 1 +/* Unlisted */ +#define INCLUDE_pxTaskGetStackStart 1 + +/* -------------------- Trace Macros ----------------------- */ /* -For trace macros. -Note: Include trace macros here and not above as trace macros are dependent on some of the FreeRTOS configs -*/ + * For trace macros. + * Note: Include trace macros here and not above as trace macros are dependent on some of the FreeRTOS configs + */ #ifndef __ASSEMBLER__ -#if CONFIG_SYSVIEW_ENABLE -#include "SEGGER_SYSVIEW_FreeRTOS.h" -#undef INLINE // to avoid redefinition -#endif //CONFIG_SYSVIEW_ENABLE + #if CONFIG_SYSVIEW_ENABLE + #include "SEGGER_SYSVIEW_FreeRTOS.h" + #undef INLINE /* to avoid redefinition */ + #endif /* CONFIG_SYSVIEW_ENABLE */ + + #if CONFIG_FREERTOS_SMP + +/* Default values for trace macros added to ESP-IDF implementation of SYSVIEW + * that is not part of Amazon SMP FreeRTOS. */ + #ifndef traceISR_EXIT + #define traceISR_EXIT() + #endif + #ifndef traceISR_ENTER + #define traceISR_ENTER( _n_ ) + #endif + + #ifndef traceQUEUE_GIVE_FROM_ISR + #define traceQUEUE_GIVE_FROM_ISR( pxQueue ) + #endif + + #ifndef traceQUEUE_GIVE_FROM_ISR_FAILED + #define traceQUEUE_GIVE_FROM_ISR_FAILED( pxQueue ) + #endif + + #ifndef traceQUEUE_SEMAPHORE_RECEIVE + #define traceQUEUE_SEMAPHORE_RECEIVE( pxQueue ) + #endif + #endif /* CONFIG_FREERTOS_SMP */ #endif /* def __ASSEMBLER__ */ -/* ------------------------------------------------ ESP-IDF Additions -------------------------------------------------- - * - All FreeRTOS related configurations no part of Vanilla FreeRTOS goes into this section - * - FreeRTOS configurations related to SMP and ESP-IDF additions go into this section +/* ----------------------------------------------- Amazon SMP FreeRTOS ------------------------------------------------- + * - All Amazon SMP FreeRTOS specific configurations * ------------------------------------------------------------------------------------------------------------------ */ -// ------------------------- SMP --------------------------- - -#ifndef CONFIG_FREERTOS_UNICORE -#define portNUM_PROCESSORS 2 -#else -#define portNUM_PROCESSORS 1 -#endif -#define configNUM_CORES portNUM_PROCESSORS -#ifdef CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID -#define configTASKLIST_INCLUDE_COREID 1 -#endif - -// ---------------------- Features ------------------------- - -#ifdef CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS -#define configTHREAD_LOCAL_STORAGE_DELETE_CALLBACKS 1 -#endif - -#if CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER -#define configCHECK_MUTEX_GIVEN_BY_OWNER 1 -#else -#define configCHECK_MUTEX_GIVEN_BY_OWNER 0 -#endif - -#ifndef __ASSEMBLER__ -#if CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP -extern void vPortCleanUpTCB ( void *pxTCB ); -#define portCLEAN_UP_TCB( pxTCB ) vPortCleanUpTCB( pxTCB ) -#endif -#endif - -// -------------------- Compatibility ---------------------- +#if CONFIG_FREERTOS_SMP + #ifdef CONFIG_FREERTOS_UNICORE + #define configNUM_CORES 1 + #else + #define configNUM_CORES 2 + #endif /* CONFIG_FREERTOS_UNICORE */ + #define configUSE_CORE_AFFINITY 1 + #define configRUN_MULTIPLE_PRIORITIES 1 + #define configUSE_TASK_PREEMPTION_DISABLE 1 + +/* This is always enabled to call IDF style idle hooks, by can be "--Wl,--wrap" + * if users enable CONFIG_FREERTOS_USE_MINIMAL_IDLE_HOOK. */ + #define configUSE_MINIMAL_IDLE_HOOK 1 + +/* IDF Newlib supports dynamic reentrancy. We provide our own __getreent() + * function. */ + #define configNEWLIB_REENTRANT_IS_DYNAMIC 1 +#endif /* CONFIG_FREERTOS_SMP */ + +/* -------------------------------------------------- IDF FreeRTOS ----------------------------------------------------- + * - All IDF FreeRTOS specific configurations + * ------------------------------------------------------------------------------------------------------------------ */ -// backward compatibility for 4.4 -#define xTaskRemoveFromUnorderedEventList vTaskRemoveFromUnorderedEventList +#if !CONFIG_FREERTOS_SMP + #ifdef CONFIG_FREERTOS_UNICORE + #define configNUM_CORES 1 + #else + #define configNUM_CORES 2 + #endif /* CONFIG_FREERTOS_UNICORE */ + #ifdef CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID + #define configTASKLIST_INCLUDE_COREID 1 + #endif /* CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID */ + #ifdef CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS + #define configTHREAD_LOCAL_STORAGE_DELETE_CALLBACKS 1 + #endif /* CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS */ + #if CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER + #define configCHECK_MUTEX_GIVEN_BY_OWNER 1 + #endif /* CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER */ +#endif /* !CONFIG_FREERTOS_SMP */ -#endif // CONFIG_FREERTOS_SMP +/* ------------------------------------------------ ESP-IDF Additions -------------------------------------------------- + * - Any other macros required by the rest of ESP-IDF + * ------------------------------------------------------------------------------------------------------------------ */ -#endif /* FREERTOS_CONFIG_H */ +#define portNUM_PROCESSORS configNUM_CORES diff --git a/tools/sdk/esp32c3/include/freertos/esp_additions/include/freertos/idf_additions.h b/tools/sdk/esp32c3/include/freertos/esp_additions/include/freertos/idf_additions.h index 6523575c8da..22aac424b74 100644 --- a/tools/sdk/esp32c3/include/freertos/esp_additions/include/freertos/idf_additions.h +++ b/tools/sdk/esp32c3/include/freertos/esp_additions/include/freertos/idf_additions.h @@ -1,45 +1,65 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ +#pragma once + +/* + * This file contains the function prototypes of ESP-IDF specific API additions + * to the FreeRTOS kernel. These API additions are not part of Vanilla (i.e., + * upstream) FreeRTOS and include things such as.... + * - Various helper functions + * - API for ESP-IDF feature additions to FreeRTOS (such as TSLP deletion + * call backs) + */ + #include "sdkconfig.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" -#include "idf_additions_inc.h" -#if CONFIG_FREERTOS_SMP || __DOXYGEN__ +#ifdef __cplusplus + extern "C" { +#endif -/* ------------------------------------------------ Helper Functions --------------------------------------------------- +/* ----------------------------------------------------------------------------- + * SMP related API additions to FreeRTOS * - * ------------------------------------------------------------------------------------------------------------------ */ + * Todo: Move IDF FreeRTOS SMP related additions to this header as well (see + * IDF-7201) + * -------------------------------------------------------------------------- */ + +#if CONFIG_FREERTOS_SMP || __DOXYGEN__ /** * @brief Create a new task that is pinned to a particular core * - * Helper function to create a task that is pinned to a particular core, or has no affinity. In other wrods, the created - * task will have an affinity mask of: + * Helper function to create a task that is pinned to a particular core, or has + * no affinity. In other wrods, the created task will have an affinity mask of: * - (1 << xCoreID) if it is pinned to a particular core * - Set to tskNO_AFFINITY if it has no affinity * * @param pxTaskCode Pointer to the task entry function. * @param pcName A descriptive name for the task. * @param usStackDepth The size of the task stack. - * @param pvParameters Pointer that will be used as the parameter for the task being created. + * @param pvParameters Pointer that will be used as the parameter for the task + * being created. * @param uxPriority The priority at which the task should run. - * @param pxCreatedTask Used to pass back a handle by which the created task can be referenced. - * @param xCoreID The core to which the task is pinned to, or tskNO_AFFINITY if the task has no core affinity - * @return pdPASS if the task was successfully created and added to a ready list, otherwise an error code defined in the - * file projdefs.h + * @param pxCreatedTask Used to pass back a handle by which the created task can + * be referenced. + * @param xCoreID The core to which the task is pinned to, or tskNO_AFFINITY if + * the task has no core affinity + * @return pdPASS if the task was successfully created and added to a ready + * list, otherwise an error code defined in the file projdefs.h */ -BaseType_t xTaskCreatePinnedToCore( TaskFunction_t pxTaskCode, - const char * const pcName, - const uint32_t usStackDepth, - void * const pvParameters, - UBaseType_t uxPriority, - TaskHandle_t * const pxCreatedTask, - const BaseType_t xCoreID); + BaseType_t xTaskCreatePinnedToCore( TaskFunction_t pxTaskCode, + const char * const pcName, + const uint32_t usStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask, + const BaseType_t xCoreID ); /** @@ -50,142 +70,118 @@ BaseType_t xTaskCreatePinnedToCore( TaskFunction_t pxTaskCode, * @param pxTaskCode Pointer to the task entry function. * @param pcName A descriptive name for the task. * @param ulStackDepth The size of the task stack. - * @param pvParameters Pointer that will be used as the parameter for the task being created. + * @param pvParameters Pointer that will be used as the parameter for the task + * being created. * @param uxPriority The priority at which the task should run. - * @param puxStackBuffer Must point to a StackType_t array that has at least ulStackDepth indexes - * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will then be used to hold the task's data structures, - * @param xCoreID The core to which the task is pinned to, or tskNO_AFFINITY if the task has no core affinity + * @param puxStackBuffer Must point to a StackType_t array that has at least + * ulStackDepth indexes + * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will + * then be used to hold the task's data structures, + * @param xCoreID The core to which the task is pinned to, or tskNO_AFFINITY if + * the task has no core affinity * @return The task handle if the task was created, NULL otherwise. */ -#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) -TaskHandle_t xTaskCreateStaticPinnedToCore( TaskFunction_t pxTaskCode, - const char * const pcName, - const uint32_t ulStackDepth, - void * const pvParameters, - UBaseType_t uxPriority, - StackType_t * const puxStackBuffer, - StaticTask_t * const pxTaskBuffer, - const BaseType_t xCoreID ); -#endif /* configSUPPORT_STATIC_ALLOCATION */ + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + TaskHandle_t xTaskCreateStaticPinnedToCore( TaskFunction_t pxTaskCode, + const char * const pcName, + const uint32_t ulStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer, + const BaseType_t xCoreID ); + #endif /* configSUPPORT_STATIC_ALLOCATION */ /** * @brief Get the handle of the task running on a certain core * - * Because of the nature of SMP processing, there is no guarantee that this value will still be valid on return and - * should only be used for debugging purposes. + * Because of the nature of SMP processing, there is no guarantee that this + * value will still be valid on return and should only be used for debugging + * purposes. * - * [refactor-todo] Mark this function as deprecated, call xTaskGetCurrentTaskHandleCPU() instead + * [refactor-todo] Mark this function as deprecated, call + * xTaskGetCurrentTaskHandleCPU() instead * * @param xCoreID The core to query * @return Handle of the current task running on the queried core */ -TaskHandle_t xTaskGetCurrentTaskHandleForCPU( BaseType_t xCoreID ); + TaskHandle_t xTaskGetCurrentTaskHandleForCPU( BaseType_t xCoreID ); /** * @brief Get the handle of idle task for the given CPU. * - * [refactor-todo] Mark this function as deprecated, call xTaskGetIdleTaskHandle() instead + * [refactor-todo] Mark this function as deprecated, call + * xTaskGetIdleTaskHandle() instead * * @param xCoreID The core to query * @return Handle of the idle task for the queried core */ -TaskHandle_t xTaskGetIdleTaskHandleForCPU( BaseType_t xCoreID ); + TaskHandle_t xTaskGetIdleTaskHandleForCPU( BaseType_t xCoreID ); /** * @brief Get the current core affintiy of a particular task * - * Helper function to get the core affinity of a particular task. If the task is pinned to a particular core, the core - * ID is returned. If the task is not pinned to a particular core, tskNO_AFFINITY is returned. + * Helper function to get the core affinity of a particular task. If the task is + * pinned to a particular core, the core ID is returned. If the task is not + * pinned to a particular core, tskNO_AFFINITY is returned. * - * [refactor-todo] Mark this function as deprecated, call vTaskCoreAffinityGet() instead + * [refactor-todo] Mark this function as deprecated, call vTaskCoreAffinityGet() + * instead * * @param xTask The task to query * @return The tasks coreID or tskNO_AFFINITY */ -BaseType_t xTaskGetAffinity( TaskHandle_t xTask ); - -#if ( CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS ) - - /** - * Prototype of local storage pointer deletion callback. - */ - typedef void (*TlsDeleteCallbackFunction_t)( int, void * ); - - /** - * Set local storage pointer and deletion callback. - * - * Each task contains an array of pointers that is dimensioned by the - * configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h. - * The kernel does not use the pointers itself, so the application writer - * can use the pointers for any purpose they wish. - * - * Local storage pointers set for a task can reference dynamically - * allocated resources. This function is similar to - * vTaskSetThreadLocalStoragePointer, but provides a way to release - * these resources when the task gets deleted. For each pointer, - * a callback function can be set. This function will be called - * when task is deleted, with the local storage pointer index - * and value as arguments. - * - * @param xTaskToSet Task to set thread local storage pointer for - * @param xIndex The index of the pointer to set, from 0 to - * configNUM_THREAD_LOCAL_STORAGE_POINTERS - 1. - * @param pvValue Pointer value to set. - * @param pvDelCallback Function to call to dispose of the local - * storage pointer when the task is deleted. - */ - void vTaskSetThreadLocalStoragePointerAndDelCallback( - TaskHandle_t xTaskToSet, - BaseType_t xIndex, - void *pvValue, - TlsDeleteCallbackFunction_t pvDelCallback); -#endif // CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS + BaseType_t xTaskGetAffinity( TaskHandle_t xTask ); #endif // CONFIG_FREERTOS_SMP || __DOXYGEN__ -#if ( INCLUDE_vTaskPrioritySet == 1 ) +/* ----------------------------------------------------------------------------- + * TLSP Deletion Callback related API additions + * + * Todo: Move IDF FreeRTOS TLSP Deletion Callback related additions to this + * header as well (see IDF-7201) + * -------------------------------------------------------------------------- */ + +#if CONFIG_FREERTOS_SMP || __DOXYGEN__ + + #if ( CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS ) /** - * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Saves the current priority and current base priority of a task, then raises the tasks - * current and base priority to uxNewPriority if uxNewPriority is of a higher priority. - * Once a task's priority has been raised with this function, the priority can be restored - * by calling prvTaskPriorityRestore() - * - Note that this function differs from vTaskPrioritySet() as the task's current priority - * will be modified even if the task has already inherited a priority. - * - This function is intended for special circumstance where a task must be forced immediately - * to a higher priority. - * - * For configUSE_MUTEXES == 0: A context switch will occur before the function returns if the priority - * being set is higher than the currently executing task. - * - * @note This functions is private is only be called internally within various IDF components. - * Users should never call this function from their application. - * - * @note vTaskPrioritySet() should not be called while a task's priority is already raised via this function - * - * @param pxSavedPriority returns base and current priorities - * - * @param uxNewPriority The priority to which the task will be set. + * Prototype of local storage pointer deletion callback. */ -void prvTaskPriorityRaise( prvTaskSavedPriority_t * pxSavedPriority, UBaseType_t uxNewPriority ); + typedef void (* TlsDeleteCallbackFunction_t)( int, + void * ); /** - * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Restore a task's priority that was previously raised by prvTaskPriorityRaise(). - * - * For configUSE_MUTEXES == 0: A context switch will occur before the function returns if the priority - * being set is higher than the currently executing task. - * - * @note This functions is private is only be called internally within various IDF components. - * Users should never call this function from their application. - * - * @param pxSavedPriority previously saved base and current priorities that need to be restored + * Set local storage pointer and deletion callback. + * + * Each task contains an array of pointers that is dimensioned by the + * configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h. The + * kernel does not use the pointers itself, so the application writer can use + * the pointers for any purpose they wish. + * + * Local storage pointers set for a task can reference dynamically allocated + * resources. This function is similar to vTaskSetThreadLocalStoragePointer, but + * provides a way to release these resources when the task gets deleted. For + * each pointer, a callback function can be set. This function will be called + * when task is deleted, with the local storage pointer index and value as + * arguments. + * + * @param xTaskToSet Task to set thread local storage pointer for + * @param xIndex The index of the pointer to set, from 0 to + * configNUM_THREAD_LOCAL_STORAGE_POINTERS - 1. + * @param pvValue Pointer value to set. + * @param pvDelCallback Function to call to dispose of the local storage + * pointer when the task is deleted. */ -void prvTaskPriorityRestore( prvTaskSavedPriority_t * pxSavedPriority ); + void vTaskSetThreadLocalStoragePointerAndDelCallback( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue, + TlsDeleteCallbackFunction_t pvDelCallback ); + #endif // CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS + +#endif // CONFIG_FREERTOS_SMP || __DOXYGEN__ -#endif // ( INCLUDE_vTaskPrioritySet == 1) +#ifdef __cplusplus + } +#endif diff --git a/tools/sdk/esp32c3/include/freertos/esp_additions/include/freertos/idf_additions_inc.h b/tools/sdk/esp32c3/include/freertos/esp_additions/include/freertos/idf_additions_inc.h deleted file mode 100644 index 25b0b6d9a4d..00000000000 --- a/tools/sdk/esp32c3/include/freertos/esp_additions/include/freertos/idf_additions_inc.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - - -#ifndef FREERTOS_ADDITITIONS_INC_H_ -#define FREERTOS_ADDITITIONS_INC_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "sdkconfig.h" -#include "freertos/FreeRTOS.h" - -#if ( INCLUDE_vTaskPrioritySet == 1 ) - -typedef struct { - UBaseType_t uxPriority; -#if ( configUSE_MUTEXES == 1 ) - UBaseType_t uxBasePriority; -#endif -} prvTaskSavedPriority_t; - -#endif // ( INCLUDE_vTaskPrioritySet == 1) - -#ifdef __cplusplus -} -#endif - -#endif //FREERTOS_ADDITITIONS_INC_H_ diff --git a/tools/sdk/esp32c3/include/hal/esp32c3/include/hal/efuse_ll.h b/tools/sdk/esp32c3/include/hal/esp32c3/include/hal/efuse_ll.h index ee1deaf1ea2..b6fcf1bb6bf 100644 --- a/tools/sdk/esp32c3/include/hal/esp32c3/include/hal/efuse_ll.h +++ b/tools/sdk/esp32c3/include/hal/esp32c3/include/hal/efuse_ll.h @@ -32,7 +32,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void) { - return EFUSE.rd_mac_spi_sys_0; + return EFUSE.rd_mac_spi_sys_0.mac_0; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void) @@ -59,7 +59,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_ve // use efuse_hal_get_minor_chip_version() to get minor chip version __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void) { - return (EFUSE.rd_mac_spi_sys_5.wafer_version_minor_high << 3) + EFUSE.rd_mac_spi_sys_3.wafer_version_minor_low; + return (EFUSE.rd_mac_spi_sys_5.wafer_version_minor_hi << 3) + EFUSE.rd_mac_spi_sys_3.wafer_version_minor_lo; } __attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void) @@ -114,7 +114,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_v_rtc_dbias20 __attribute__((always_inline)) static inline uint32_t efuse_ll_get_v_dig_dbias20(void) { // EFUSE_BLK1, 157, 8, BLOCK1 voltage of digital dbias20 - return (EFUSE.rd_mac_spi_sys_5.v_dig_dbias20_hi << 3) + EFUSE.rd_mac_spi_sys_4.v_dig_dbias20_low; + return (EFUSE.rd_mac_spi_sys_5.v_dig_dbias20_1 << 3) + EFUSE.rd_mac_spi_sys_4.v_dig_dbias20; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_dig_dbias_hvt(void) diff --git a/tools/sdk/esp32c3/include/hal/esp32c3/include/hal/gdma_ll.h b/tools/sdk/esp32c3/include/hal/esp32c3/include/hal/gdma_ll.h index 617b118f21b..3ccb5a0fac9 100644 --- a/tools/sdk/esp32c3/include/hal/esp32c3/include/hal/gdma_ll.h +++ b/tools/sdk/esp32c3/include/hal/esp32c3/include/hal/gdma_ll.h @@ -18,6 +18,8 @@ extern "C" { #define GDMA_LL_GET_HW(id) (((id) == 0) ? (&GDMA) : NULL) +#define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5] + #define GDMA_LL_RX_EVENT_MASK (0x06A7) #define GDMA_LL_TX_EVENT_MASK (0x1958) diff --git a/tools/sdk/esp32c3/include/hal/esp32c3/include/hal/ledc_ll.h b/tools/sdk/esp32c3/include/hal/esp32c3/include/hal/ledc_ll.h index d2543733253..0edca338901 100644 --- a/tools/sdk/esp32c3/include/hal/esp32c3/include/hal/ledc_ll.h +++ b/tools/sdk/esp32c3/include/hal/esp32c3/include/hal/ledc_ll.h @@ -33,6 +33,8 @@ extern "C" { LEDC_SLOW_CLK_RC_FAST, \ } +#define LEDC_LL_GLOBAL_CLK_DEFAULT LEDC_SLOW_CLK_RC_FAST + /** * @brief Set LEDC low speed timer clock * diff --git a/tools/sdk/esp32c3/include/hal/include/hal/ecdsa_hal.h b/tools/sdk/esp32c3/include/hal/include/hal/ecdsa_hal.h new file mode 100644 index 00000000000..d7244b3dc05 --- /dev/null +++ b/tools/sdk/esp32c3/include/hal/include/hal/ecdsa_hal.h @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/******************************************************************************* + * NOTICE + * The HAL is not public api, don't use in application code. + * See readme.md in soc/README.md + ******************************************************************************/ + +#pragma once + +#include +#include "hal/ecdsa_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * ECDSA peripheral config structure + */ +typedef struct { + ecdsa_mode_t mode; /* Mode of operation */ + ecdsa_curve_t curve; /* Curve to use for operation */ + ecdsa_k_mode_t k_mode; /* Source of K */ + ecdsa_sha_mode_t sha_mode; /* Source of SHA that needs to be signed */ +} ecdsa_hal_config_t; + +/** + * @brief Generate ECDSA signature + * + * @param conf Configuration for ECDSA operation, see ``ecdsa_hal_config_t`` + * @param k Value of K used internally. Set this to NULL if K is generated by hardware + * @param hash Hash that is to be signed + * @param r_out Buffer that will contain `R` component of ECDSA signature + * @param s_out Buffer that will contain `S` component of ECDSA signature + * @param len Length of the r_out and s_out buffer (32 bytes for SECP256R1, 24 for SECP192R1) + */ +void ecdsa_hal_gen_signature(ecdsa_hal_config_t *conf, const uint8_t *k, const uint8_t *hash, + uint8_t *r_out, uint8_t *s_out, uint16_t len); + +/** + * @brief Verify given ECDSA signature + * + * @param conf Configuration for ECDSA operation, see ``ecdsa_hal_config_t`` + * @param hash Hash that was signed + * @param r `R` component of ECDSA signature + * @param s `S` component of ECDSA signature + * @param pub_x X coordinate of public key + * @param pub_y Y coordinate of public key + * @param len Length of r and s buffer (32 bytes for SECP256R1, 24 for SECP192R1) + * + * @return - 0, if the signature matches + * - -1, if verification fails + */ +int ecdsa_hal_verify_signature(ecdsa_hal_config_t *conf, const uint8_t *hash, const uint8_t *r, const uint8_t *s, + const uint8_t *pub_x, const uint8_t *pub_y, uint16_t len); +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32c3/include/hal/include/hal/ecdsa_types.h b/tools/sdk/esp32c3/include/hal/include/hal/ecdsa_types.h new file mode 100644 index 00000000000..fdb2f3d3cf0 --- /dev/null +++ b/tools/sdk/esp32c3/include/hal/include/hal/ecdsa_types.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief ECDSA peripheral work modes + */ +typedef enum { + ECDSA_MODE_SIGN_VERIFY, + ECDSA_MODE_SIGN_GEN, +} ecdsa_mode_t; + +/** + * @brief ECDSA curve options + */ +typedef enum { + ECDSA_CURVE_SECP192R1, + ECDSA_CURVE_SECP256R1, +} ecdsa_curve_t; + +/** + * @brief Source of 'K' used internally for generating signature + */ +typedef enum { + ECDSA_K_USE_TRNG, + ECDSA_K_USER_PROVIDED, +} ecdsa_k_mode_t; + +/** + * @brief Source of SHA message that is to be signed/verified + */ +typedef enum { + ECDSA_Z_USE_SHA_PERI, + ECDSA_Z_USER_PROVIDED, +} ecdsa_sha_mode_t; + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32c3/include/hal/include/hal/efuse_hal.h b/tools/sdk/esp32c3/include/hal/include/hal/efuse_hal.h index 2f141b74404..bb11c9ae7b3 100644 --- a/tools/sdk/esp32c3/include/hal/include/hal/efuse_hal.h +++ b/tools/sdk/esp32c3/include/hal/include/hal/efuse_hal.h @@ -26,6 +26,15 @@ void efuse_hal_get_mac(uint8_t *mac); */ uint32_t efuse_hal_chip_revision(void); +/** + * @brief Is flash encryption currently enabled in hardware? + * + * Flash encryption is enabled if the FLASH_CRYPT_CNT efuse has an odd number of bits set. + * + * @return true if flash encryption is enabled. + */ +bool efuse_hal_flash_encryption_enabled(void); + /** * @brief Returns major chip version */ diff --git a/tools/sdk/esp32c3/include/hal/include/hal/modem_clock_hal.h b/tools/sdk/esp32c3/include/hal/include/hal/modem_clock_hal.h new file mode 100644 index 00000000000..9912308f5eb --- /dev/null +++ b/tools/sdk/esp32c3/include/hal/include/hal/modem_clock_hal.h @@ -0,0 +1,48 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The HAL layer for MODEM CLOCK + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc/soc_caps.h" +#include "hal/modem_syscon_ll.h" +#include "hal/modem_lpcon_ll.h" +#include "hal/modem_clock_types.h" + +typedef struct { + modem_syscon_dev_t *syscon_dev; + modem_lpcon_dev_t *lpcon_dev; +} modem_clock_hal_context_t; + +#if MAC_SUPPORT_PMU_MODEM_STATE +void modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain, uint32_t bitmap); +#endif + +void modem_clock_hal_enable_fe_clock(modem_clock_hal_context_t *hal, bool enable); + +#if SOC_BT_SUPPORTED +void modem_clock_hal_set_ble_rtc_timer_divisor_value(modem_clock_hal_context_t *hal, uint32_t divider); +void modem_clock_hal_enable_ble_rtc_timer_clock(modem_clock_hal_context_t *hal, bool enable); +void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src); +void modem_clock_hal_deselect_all_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t *hal); +#endif + +void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src); +void modem_clock_hal_deselect_all_coex_lpclk_source(modem_clock_hal_context_t *hal); + +#if SOC_WIFI_SUPPORTED +void modem_clock_hal_select_wifi_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src); +void modem_clock_hal_deselect_all_wifi_lpclk_source(modem_clock_hal_context_t *hal); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32c3/include/hal/include/hal/rmt_types.h b/tools/sdk/esp32c3/include/hal/include/hal/rmt_types.h index 1082761d87a..7650c78bb70 100644 --- a/tools/sdk/esp32c3/include/hal/include/hal/rmt_types.h +++ b/tools/sdk/esp32c3/include/hal/include/hal/rmt_types.h @@ -1,11 +1,12 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once +#include #include "soc/clk_tree_defs.h" #include "soc/soc_caps.h" @@ -28,12 +29,12 @@ typedef int rmt_clock_source_t; */ typedef union { struct { - unsigned int duration0 : 15; /*!< Duration of level0 */ - unsigned int level0 : 1; /*!< Level of the first part */ - unsigned int duration1 : 15; /*!< Duration of level1 */ - unsigned int level1 : 1; /*!< Level of the second part */ + uint16_t duration0 : 15; /*!< Duration of level0 */ + uint16_t level0 : 1; /*!< Level of the first part */ + uint16_t duration1 : 15; /*!< Duration of level1 */ + uint16_t level1 : 1; /*!< Level of the second part */ }; - unsigned int val; /*!< Equivalent unsigned value for the RMT symbol */ + uint32_t val; /*!< Equivalent unsigned value for the RMT symbol */ } rmt_symbol_word_t; #ifdef __cplusplus diff --git a/tools/sdk/esp32c3/include/hal/include/hal/spi_slave_hd_hal.h b/tools/sdk/esp32c3/include/hal/include/hal/spi_slave_hd_hal.h index 099139cc015..d426f97e970 100644 --- a/tools/sdk/esp32c3/include/hal/include/hal/spi_slave_hd_hal.h +++ b/tools/sdk/esp32c3/include/hal/include/hal/spi_slave_hd_hal.h @@ -1,16 +1,8 @@ -// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ /******************************************************************************* * NOTICE @@ -258,8 +250,7 @@ int spi_slave_hd_hal_get_rxlen(spi_slave_hd_hal_context_t *hal); */ int spi_slave_hd_hal_get_last_addr(spi_slave_hd_hal_context_t *hal); -#if CONFIG_IDF_TARGET_ESP32S2 -//Append mode is only supported on ESP32S2 now + //////////////////////////////////////////////////////////////////////////////// // Append Mode //////////////////////////////////////////////////////////////////////////////// @@ -315,4 +306,3 @@ esp_err_t spi_slave_hd_hal_txdma_append(spi_slave_hd_hal_context_t *hal, uint8_t * - ESP_ERR_INVALID_STATE: Function called in invalid state. */ esp_err_t spi_slave_hd_hal_rxdma_append(spi_slave_hd_hal_context_t *hal, uint8_t *data, size_t len, void *arg); -#endif //#if CONFIG_IDF_TARGET_ESP32S2 diff --git a/tools/sdk/esp32c3/include/heap/include/esp_heap_caps.h b/tools/sdk/esp32c3/include/heap/include/esp_heap_caps.h index e5adf162b83..f3d1026c8b5 100644 --- a/tools/sdk/esp32c3/include/heap/include/esp_heap_caps.h +++ b/tools/sdk/esp32c3/include/heap/include/esp_heap_caps.h @@ -11,6 +11,7 @@ #include "multi_heap.h" #include #include "esp_err.h" +#include "esp_attr.h" #ifdef __cplusplus extern "C" { @@ -53,6 +54,26 @@ typedef void (*esp_alloc_failed_hook_t) (size_t size, uint32_t caps, const char */ esp_err_t heap_caps_register_failed_alloc_callback(esp_alloc_failed_hook_t callback); +#ifdef CONFIG_HEAP_USE_HOOKS +/** + * @brief callback called after every allocation + * @param ptr the allocated memory + * @param size in bytes of the allocation + * @param caps Bitwise OR of MALLOC_CAP_* flags indicating the type of memory allocated. + * @note this hook is called on the same thread as the allocation, which may be within a low level operation. + * You should refrain from doing heavy work, logging, flash writes, or any locking. + */ +__attribute__((weak)) IRAM_ATTR void esp_heap_trace_alloc_hook(void* ptr, size_t size, uint32_t caps); + +/** + * @brief callback called after every free + * @param ptr the memory that was freed + * @note this hook is called on the same thread as the allocation, which may be within a low level operation. + * You should refrain from doing heavy work, logging, flash writes, or any locking. + */ +__attribute__((weak)) IRAM_ATTR void esp_heap_trace_free_hook(void* ptr); +#endif + /** * @brief Allocate a chunk of memory which has the given capabilities * diff --git a/tools/sdk/esp32c3/include/heap/include/esp_heap_trace.h b/tools/sdk/esp32c3/include/heap/include/esp_heap_trace.h index b1c5d476e4c..2b0daa2e4c6 100644 --- a/tools/sdk/esp32c3/include/heap/include/esp_heap_trace.h +++ b/tools/sdk/esp32c3/include/heap/include/esp_heap_trace.h @@ -36,8 +36,11 @@ typedef struct heap_trace_record_t { size_t size; ///< Size of the allocation void *alloced_by[CONFIG_HEAP_TRACING_STACK_DEPTH]; ///< Call stack of the caller which allocated the memory. void *freed_by[CONFIG_HEAP_TRACING_STACK_DEPTH]; ///< Call stack of the caller which freed the memory (all zero if not freed.) -#ifdef CONFIG_HEAP_TRACING_STANDALONE - TAILQ_ENTRY(heap_trace_record_t) tailq; ///< Linked list: prev & next records +#if CONFIG_HEAP_TRACING_STANDALONE + TAILQ_ENTRY(heap_trace_record_t) tailq_list; ///< Linked list: prev & next records +#if CONFIG_HEAP_TRACE_HASH_MAP + TAILQ_ENTRY(heap_trace_record_t) tailq_hashmap; ///< Linked list: prev & next in hashmap entry list +#endif // CONFIG_HEAP_TRACE_HASH_MAP #endif // CONFIG_HEAP_TRACING_STANDALONE } heap_trace_record_t; @@ -52,6 +55,10 @@ typedef struct { size_t capacity; ///< The capacity of the internal buffer size_t high_water_mark; ///< The maximum value that 'count' got to size_t has_overflowed; ///< True if the internal buffer overflowed at some point +#if CONFIG_HEAP_TRACE_HASH_MAP + size_t total_hashmap_hits; ///< If hashmap is used, the total number of hits + size_t total_hashmap_miss; ///< If hashmap is used, the total number of misses (possibly due to overflow) +#endif } heap_trace_summary_t; /** diff --git a/tools/sdk/esp32c3/include/mbedtls/port/include/ecdsa/ecdsa_alt.h b/tools/sdk/esp32c3/include/mbedtls/port/include/ecdsa/ecdsa_alt.h new file mode 100644 index 00000000000..9e2620b3126 --- /dev/null +++ b/tools/sdk/esp32c3/include/mbedtls/port/include/ecdsa/ecdsa_alt.h @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "sdkconfig.h" +#include "mbedtls/pk.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef CONFIG_MBEDTLS_HARDWARE_ECDSA_SIGN + +/** + * @brief Initialize MPI to notify mbedtls_ecdsa_sign to use the private key in efuse + * We break the MPI struct of the private key in order to + * differentiate between hardware key and software key + * + * @note Currently, `efuse_blk` is not used internally. + * Hardware will choose the efuse block that has purpose set to ECDSA_KEY. + * In case of multiple ECDSA_KEY burnt in efuse, hardware will choose the + * greater efuse block number as the private key. + * + * @param key The MPI in which this functions stores the hardware context. + * This must be uninitialized + * @param efuse_blk The efuse key block that should be used as the private key. + * The key purpose of this block must be ECDSA_KEY + * + * @return - 0 if successful + * - -1 otherwise + * + */ +int esp_ecdsa_privkey_load_mpi(mbedtls_mpi *key, int efuse_blk); + +/** + * @brief Initialize PK context to notify mbedtls_ecdsa_sign to use the private key in efuse + * We break the MPI struct used to represent the private key `d` in ECP keypair + * in order to differentiate between hardware key and software key + * + * @note Currently, `efuse_blk` is not used internally. + * Hardware will choose the efuse block that has purpose set to ECDSA_KEY. + * In case of multiple ECDSA_KEY burnt in efuse, hardware will choose the + * greater efuse block number as the private key. + * + * @param key_ctx The context in which this functions stores the hardware context. + * This must be uninitialized + * @param efuse_blk The efuse key block that should be used as the private key. + * The key purpose of this block must be ECDSA_KEY + * + * @return - 0 if successful + * - -1 otherwise + */ +int esp_ecdsa_privkey_load_pk_context(mbedtls_pk_context *key_ctx, int efuse_blk); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32c3/include/mbedtls/port/include/mbedtls/esp_config.h b/tools/sdk/esp32c3/include/mbedtls/port/include/mbedtls/esp_config.h index 71905d8cb3c..ea2efa243ad 100644 --- a/tools/sdk/esp32c3/include/mbedtls/port/include/mbedtls/esp_config.h +++ b/tools/sdk/esp32c3/include/mbedtls/port/include/mbedtls/esp_config.h @@ -224,6 +224,7 @@ #undef MBEDTLS_ECP_VERIFY_ALT #undef MBEDTLS_ECP_VERIFY_ALT_SOFT_FALLBACK #endif + /** * \def MBEDTLS_ENTROPY_HARDWARE_ALT * diff --git a/tools/sdk/esp32c3/include/pthread/include/semaphore.h b/tools/sdk/esp32c3/include/pthread/include/semaphore.h new file mode 100644 index 00000000000..5a7ef56b971 --- /dev/null +++ b/tools/sdk/esp32c3/include/pthread/include/semaphore.h @@ -0,0 +1,73 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef unsigned int sem_t; + +/** + * This is the maximum value to which any POSIX semaphore can count on ESP chips. + */ +#define SEM_VALUE_MAX 0x7FFF + +/** + * This is a POSIX function, please refer to the POSIX specification for a detailed description. + * + * Must NOT be called if threads are still blocked on semaphore! + */ +int sem_destroy(sem_t *sem); + +/** + * This is a POSIX function, please refer to the POSIX specification for a detailed description. + * + * Note that on ESP chips, pshared is ignored. Semaphores can always be shared between FreeRTOS tasks. + */ +int sem_init(sem_t *sem, int pshared, unsigned value); + +/** + * This is a POSIX function, please refer to the POSIX specification for a detailed description. + * + * Note that, unlike specified in POSIX, this implementation returns -1 and sets errno to + * EAGAIN if the semaphore can not be unlocked (posted) due to its value being SEM_VALUE_MAX. + */ +int sem_post(sem_t *sem); + +/** + * This is a POSIX function, please refer to the POSIX specification for a detailed description. + * + * Note the following three deviations/issues originating from the underlying FreeRTOS implementation: + * * The time value passed by abstime will be rounded up to the next FreeRTOS tick. + * * The actual timeout will happen after the tick the time was rounded to + * and before the following tick. + * * It is possible, though unlikely, that the task is preempted directly after the timeout calculation, + * delaying timeout of the following blocking operating system call by the duration of the preemption. + */ +int sem_timedwait(sem_t * restrict semaphore, const struct timespec *restrict abstime); + +/** + * This is a POSIX function, please refer to the POSIX specification for a detailed description. + */ +int sem_trywait(sem_t *sem); + +/** + * This is a POSIX function, please refer to the POSIX specification for a detailed description. + */ +int sem_wait(sem_t *sem); + +/** + * This is a POSIX function, please refer to the POSIX specification for a detailed description. + */ +int sem_getvalue(sem_t *restrict sem, int *restrict sval); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32c3/include/soc/esp32c3/include/soc/efuse_defs.h b/tools/sdk/esp32c3/include/soc/esp32c3/include/soc/efuse_defs.h new file mode 100644 index 00000000000..55f3abff560 --- /dev/null +++ b/tools/sdk/esp32c3/include/soc/esp32c3/include/soc/efuse_defs.h @@ -0,0 +1,17 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define EFUSE_WRITE_OP_CODE 0x5a5a +#define EFUSE_READ_OP_CODE 0x5aa5 + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32c3/include/soc/esp32c3/include/soc/efuse_reg.h b/tools/sdk/esp32c3/include/soc/esp32c3/include/soc/efuse_reg.h index 0b612fd64fb..29dafb6df5a 100644 --- a/tools/sdk/esp32c3/include/soc/esp32c3/include/soc/efuse_reg.h +++ b/tools/sdk/esp32c3/include/soc/esp32c3/include/soc/efuse_reg.h @@ -1,2015 +1,2623 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_EFUSE_REG_H_ -#define _SOC_EFUSE_REG_H_ - +#pragma once +#include +#include "soc/soc.h" +#include "efuse_defs.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" -#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x000) -/* EFUSE_WR_DIS : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Disable programming of individual eFuses.*/ -#define EFUSE_WR_DIS 0xFFFFFFFF -#define EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S)) -#define EFUSE_WR_DIS_V 0xFFFFFFFF -#define EFUSE_WR_DIS_S 0 -#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x004) -/* EFUSE_POWER_GLITCH_DSENSE : R/W ;bitpos:[31:30] ;default: 2'h0 ; */ -/*description: Sample delay configuration of power glitch.*/ -#define EFUSE_POWER_GLITCH_DSENSE 0x00000003 -#define EFUSE_POWER_GLITCH_DSENSE_M ((EFUSE_POWER_GLITCH_DSENSE_V)<<(EFUSE_POWER_GLITCH_DSENSE_S)) -#define EFUSE_POWER_GLITCH_DSENSE_V 0x3 -#define EFUSE_POWER_GLITCH_DSENSE_S 30 -/* EFUSE_POWERGLITCH_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Set this bit to enable power glitch function.*/ -#define EFUSE_POWERGLITCH_EN (BIT(29)) -#define EFUSE_POWERGLITCH_EN_M (BIT(29)) -#define EFUSE_POWERGLITCH_EN_V 0x1 -#define EFUSE_POWERGLITCH_EN_S 29 -/* EFUSE_BTLC_GPIO_ENABLE : R/W ;bitpos:[28:27] ;default: 2'h0 ; */ -/*description: Enable btlc gpio.*/ -#define EFUSE_BTLC_GPIO_ENABLE 0x00000003 -#define EFUSE_BTLC_GPIO_ENABLE_M ((EFUSE_BTLC_GPIO_ENABLE_V)<<(EFUSE_BTLC_GPIO_ENABLE_S)) -#define EFUSE_BTLC_GPIO_ENABLE_V 0x3 -#define EFUSE_BTLC_GPIO_ENABLE_S 27 -/* EFUSE_VDD_SPI_AS_GPIO : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: Set this bit to vdd spi pin function as gpio.*/ -#define EFUSE_VDD_SPI_AS_GPIO (BIT(26)) -#define EFUSE_VDD_SPI_AS_GPIO_M (BIT(26)) -#define EFUSE_VDD_SPI_AS_GPIO_V 0x1 -#define EFUSE_VDD_SPI_AS_GPIO_S 26 -/* EFUSE_USB_EXCHG_PINS : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: Set this bit to exchange USB D+ and D- pins.*/ -#define EFUSE_USB_EXCHG_PINS (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_M (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_V 0x1 -#define EFUSE_USB_EXCHG_PINS_S 25 -/* EFUSE_USB_DREFL : R/W ;bitpos:[24:23] ;default: 2'h0 ; */ -/*description: Controls single-end input threshold vrefl 0.8 V to 1.04 V with - step of 80 mV stored in eFuse.*/ -#define EFUSE_USB_DREFL 0x00000003 -#define EFUSE_USB_DREFL_M ((EFUSE_USB_DREFL_V)<<(EFUSE_USB_DREFL_S)) -#define EFUSE_USB_DREFL_V 0x3 -#define EFUSE_USB_DREFL_S 23 -/* EFUSE_USB_DREFH : R/W ;bitpos:[22:21] ;default: 2'h0 ; */ -/*description: Controls single-end input threshold vrefh 1.76 V to 2 V with - step of 80 mV stored in eFuse.*/ -#define EFUSE_USB_DREFH 0x00000003 -#define EFUSE_USB_DREFH_M ((EFUSE_USB_DREFH_V)<<(EFUSE_USB_DREFH_S)) -#define EFUSE_USB_DREFH_V 0x3 -#define EFUSE_USB_DREFH_S 21 -/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Set this bit to disable flash encryption when in download boot modes.*/ -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 -/* EFUSE_DIS_PAD_JTAG : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.*/ -#define EFUSE_DIS_PAD_JTAG (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_M (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_V 0x1 -#define EFUSE_DIS_PAD_JTAG_S 19 -/* EFUSE_SOFT_DIS_JTAG : R/W ;bitpos:[18:16] ;default: 3'h0 ; */ -/*description: Set these bits to disable JTAG in the soft way (odd number 1 - means disable ). JTAG can be enabled in HMAC module.*/ -#define EFUSE_SOFT_DIS_JTAG 0x00000007 -#define EFUSE_SOFT_DIS_JTAG_M ((EFUSE_SOFT_DIS_JTAG_V)<<(EFUSE_SOFT_DIS_JTAG_S)) -#define EFUSE_SOFT_DIS_JTAG_V 0x7 -#define EFUSE_SOFT_DIS_JTAG_S 16 -/* EFUSE_JTAG_SEL_ENABLE : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Set this bit to enable selection between usb_to_jtag and pad_to_jtag - through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.*/ -#define EFUSE_JTAG_SEL_ENABLE (BIT(15)) -#define EFUSE_JTAG_SEL_ENABLE_M (BIT(15)) -#define EFUSE_JTAG_SEL_ENABLE_V 0x1 -#define EFUSE_JTAG_SEL_ENABLE_S 15 -/* EFUSE_DIS_TWAI : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Set this bit to disable TWAI function.*/ -#define EFUSE_DIS_TWAI (BIT(14)) -#define EFUSE_DIS_TWAI_M (BIT(14)) -#define EFUSE_DIS_TWAI_V 0x1 -#define EFUSE_DIS_TWAI_S 14 -/* EFUSE_RPT4_RESERVED6_ERR : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Reserved..*/ -#define EFUSE_RPT4_RESERVED6 (BIT(13)) -#define EFUSE_RPT4_RESERVED6_M (BIT(13)) -#define EFUSE_RPT4_RESERVED6_V 0x1 -#define EFUSE_RPT4_RESERVED6_S 13 -/* EFUSE_DIS_FORCE_DOWNLOAD : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to disable the function that forces chip into download mode.*/ -#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_M (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x1 -#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 -/* EFUSE_DIS_USB_DEVICE : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to disable usb device.*/ -#define EFUSE_DIS_USB_DEVICE (BIT(11)) -#define EFUSE_DIS_USB_DEVICE_M (BIT(11)) -#define EFUSE_DIS_USB_DEVICE_V 0x1 -#define EFUSE_DIS_USB_DEVICE_S 11 -/* EFUSE_DIS_DOWNLOAD_ICACHE : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to disable Icache in download mode (boot_mode[3:0] - is 0 1 2 3 6 7).*/ -#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_M (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x1 -#define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 -/* EFUSE_DIS_USB_JTAG : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to disable function of usb switch to jtag in module of usb device.*/ -#define EFUSE_DIS_USB_JTAG (BIT(9)) -#define EFUSE_DIS_USB_JTAG_M (BIT(9)) -#define EFUSE_DIS_USB_JTAG_V 0x1 -#define EFUSE_DIS_USB_JTAG_S 9 -/* EFUSE_DIS_ICACHE : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to disable Icache.*/ -#define EFUSE_DIS_ICACHE (BIT(8)) -#define EFUSE_DIS_ICACHE_M (BIT(8)) -#define EFUSE_DIS_ICACHE_V 0x1 -#define EFUSE_DIS_ICACHE_S 8 -/* EFUSE_RPT4_RESERVED5 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED5 (BIT(7)) -#define EFUSE_RPT4_RESERVED5_M (BIT(7)) -#define EFUSE_RPT4_RESERVED5_V 0x1 -#define EFUSE_RPT4_RESERVED5_S 7 -/* EFUSE_RD_DIS : R/W ;bitpos:[6:0] ;default: 7'h0 ; */ -/*description: Set this bit to disable reading from BlOCK4-10.*/ -#define EFUSE_RD_DIS 0x0000007F -#define EFUSE_RD_DIS_M ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S)) -#define EFUSE_RD_DIS_V 0x7F -#define EFUSE_RD_DIS_S 0 +/** EFUSE_PGM_DATA0_REG register + * Register 0 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) +/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) +#define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_S 0 -#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x008) -/* EFUSE_KEY_PURPOSE_1 : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: Purpose of Key1.*/ -#define EFUSE_KEY_PURPOSE_1 0x0000000F -#define EFUSE_KEY_PURPOSE_1_M ((EFUSE_KEY_PURPOSE_1_V)<<(EFUSE_KEY_PURPOSE_1_S)) -#define EFUSE_KEY_PURPOSE_1_V 0xF -#define EFUSE_KEY_PURPOSE_1_S 28 -/* EFUSE_KEY_PURPOSE_0 : R/W ;bitpos:[27:24] ;default: 4'h0 ; */ -/*description: Purpose of Key0.*/ -#define EFUSE_KEY_PURPOSE_0 0x0000000F -#define EFUSE_KEY_PURPOSE_0_M ((EFUSE_KEY_PURPOSE_0_V)<<(EFUSE_KEY_PURPOSE_0_S)) -#define EFUSE_KEY_PURPOSE_0_V 0xF -#define EFUSE_KEY_PURPOSE_0_S 24 -/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Set this bit to enable revoking third secure boot key.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 -/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Set this bit to enable revoking second secure boot key.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 -/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to enable revoking first secure boot key.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 -/* EFUSE_SPI_BOOT_CRYPT_CNT : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: Set this bit to enable SPI boot encrypt/decrypt. Odd number of - 1: enable. even number of 1: disable.*/ -#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_M ((EFUSE_SPI_BOOT_CRYPT_CNT_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_S)) -#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x7 -#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 -/* EFUSE_WAT_DELAY_SEL : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: Selects RTC watchdog timeout threshold in unit of slow clock - cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.*/ -#define EFUSE_WAT_DELAY_SEL 0x00000003 -#define EFUSE_WAT_DELAY_SEL_M ((EFUSE_WAT_DELAY_SEL_V)<<(EFUSE_WAT_DELAY_SEL_S)) -#define EFUSE_WAT_DELAY_SEL_V 0x3 -#define EFUSE_WAT_DELAY_SEL_S 16 -/* EFUSE_RPT4_RESERVED2 : RO ;bitpos:[15:0] ;default: 2'h0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED2 0x0000FFFF -#define EFUSE_RPT4_RESERVED2_M ((EFUSE_RPT4_RESERVED2_V)<<(EFUSE_RPT4_RESERVED2_S)) -#define EFUSE_RPT4_RESERVED2_V 0xFFFF -#define EFUSE_RPT4_RESERVED2_S 0 +/** EFUSE_PGM_DATA1_REG register + * Register 1 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) +/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1st 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_1 0xFFFFFFFFU +#define EFUSE_PGM_DATA_1_M (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S) +#define EFUSE_PGM_DATA_1_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_1_S 0 -#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0x00C) -/* EFUSE_FLASH_TPUW : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: Configures flash waiting time after power-up in unit of ms. - If the value is less than 15 the waiting time is the configurable value*/ -#define EFUSE_FLASH_TPUW 0x0000000F -#define EFUSE_FLASH_TPUW_M ((EFUSE_FLASH_TPUW_V)<<(EFUSE_FLASH_TPUW_S)) -#define EFUSE_FLASH_TPUW_V 0xF -#define EFUSE_FLASH_TPUW_S 28 -/* EFUSE_RPT4_RESERVED0 : RO ;bitpos:[27:22] ;default: 6'h0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED0 0x0000003F -#define EFUSE_RPT4_RESERVED0_M ((EFUSE_RPT4_RESERVED0_V)<<(EFUSE_RPT4_RESERVED0_S)) -#define EFUSE_RPT4_RESERVED0_V 0x3F -#define EFUSE_RPT4_RESERVED0_S 22 -/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to enable revoking aggressive secure boot.*/ -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x1 -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 -/* EFUSE_SECURE_BOOT_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Set this bit to enable secure boot.*/ -#define EFUSE_SECURE_BOOT_EN (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_M (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_V 0x1 -#define EFUSE_SECURE_BOOT_EN_S 20 -/* EFUSE_RPT4_RESERVED3 : RO ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED3 0x0000000F -#define EFUSE_RPT4_RESERVED3_M ((EFUSE_RPT4_RESERVED3_V)<<(EFUSE_RPT4_RESERVED3_S)) -#define EFUSE_RPT4_RESERVED3_V 0xF -#define EFUSE_RPT4_RESERVED3_S 16 -/* EFUSE_KEY_PURPOSE_5 : R/W ;bitpos:[15:12] ;default: 4'h0 ; */ -/*description: Purpose of Key5.*/ -#define EFUSE_KEY_PURPOSE_5 0x0000000F -#define EFUSE_KEY_PURPOSE_5_M ((EFUSE_KEY_PURPOSE_5_V)<<(EFUSE_KEY_PURPOSE_5_S)) -#define EFUSE_KEY_PURPOSE_5_V 0xF -#define EFUSE_KEY_PURPOSE_5_S 12 -/* EFUSE_KEY_PURPOSE_4 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ -/*description: Purpose of Key4.*/ -#define EFUSE_KEY_PURPOSE_4 0x0000000F -#define EFUSE_KEY_PURPOSE_4_M ((EFUSE_KEY_PURPOSE_4_V)<<(EFUSE_KEY_PURPOSE_4_S)) -#define EFUSE_KEY_PURPOSE_4_V 0xF -#define EFUSE_KEY_PURPOSE_4_S 8 -/* EFUSE_KEY_PURPOSE_3 : R/W ;bitpos:[7:4] ;default: 4'h0 ; */ -/*description: Purpose of Key3.*/ -#define EFUSE_KEY_PURPOSE_3 0x0000000F -#define EFUSE_KEY_PURPOSE_3_M ((EFUSE_KEY_PURPOSE_3_V)<<(EFUSE_KEY_PURPOSE_3_S)) -#define EFUSE_KEY_PURPOSE_3_V 0xF -#define EFUSE_KEY_PURPOSE_3_S 4 -/* EFUSE_KEY_PURPOSE_2 : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: Purpose of Key2.*/ -#define EFUSE_KEY_PURPOSE_2 0x0000000F -#define EFUSE_KEY_PURPOSE_2_M ((EFUSE_KEY_PURPOSE_2_V)<<(EFUSE_KEY_PURPOSE_2_S)) -#define EFUSE_KEY_PURPOSE_2_V 0xF -#define EFUSE_KEY_PURPOSE_2_S 0 +/** EFUSE_PGM_DATA2_REG register + * Register 2 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) +/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2nd 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_2 0xFFFFFFFFU +#define EFUSE_PGM_DATA_2_M (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S) +#define EFUSE_PGM_DATA_2_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_2_S 0 -#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x010) -/* EFUSE_ERR_RST_ENABLE : RO ;bitpos:[31] ;default: 1'h0 ; */ -/*description: Use BLOCK0 to check error record registers, 0 - without check.*/ -#define EFUSE_ERR_RST_ENABLE (BIT(31)) -#define EFUSE_ERR_RST_ENABLE_M (BIT(31)) -#define EFUSE_ERR_RST_ENABLE_V 0x1 -#define EFUSE_ERR_RST_ENABLE_S 31 -/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[30] ;default: 1'h0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED1 (BIT(30)) -#define EFUSE_RPT4_RESERVED1_M (BIT(30)) -#define EFUSE_RPT4_RESERVED1_V 0x1 -#define EFUSE_RPT4_RESERVED1_S 30 -/* EFUSE_SECURE_VERSION : R/W ;bitpos:[29:14] ;default: 16'h0 ; */ -/*description: Secure version (used by ESP-IDF anti-rollback feature).*/ -#define EFUSE_SECURE_VERSION 0x0000FFFF -#define EFUSE_SECURE_VERSION_M ((EFUSE_SECURE_VERSION_V)<<(EFUSE_SECURE_VERSION_S)) -#define EFUSE_SECURE_VERSION_V 0xFFFF -#define EFUSE_SECURE_VERSION_S 14 -/* EFUSE_FORCE_SEND_RESUME : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to force ROM code to send a resume command during SPI boot.*/ -#define EFUSE_FORCE_SEND_RESUME (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_M (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_V 0x1 -#define EFUSE_FORCE_SEND_RESUME_S 13 -/* EFUSE_RPT4_RESERVED7 : R/W ;bitpos:[12:8] ;default: 5'h0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED7 0x0000001F -#define EFUSE_RPT4_RESERVED7_M ((EFUSE_RPT4_RESERVED7_V)<<(EFUSE_RPT4_RESERVED7_S)) -#define EFUSE_RPT4_RESERVED7_V 0x1F -#define EFUSE_RPT4_RESERVED7_S 8 -/* EFUSE_UART_PRINT_CONTROL : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: Set the default UARTboot message output mode. 00: Enabled. 01: - Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.*/ -#define EFUSE_UART_PRINT_CONTROL 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_M ((EFUSE_UART_PRINT_CONTROL_V)<<(EFUSE_UART_PRINT_CONTROL_S)) -#define EFUSE_UART_PRINT_CONTROL_V 0x3 -#define EFUSE_UART_PRINT_CONTROL_S 6 -/* EFUSE_ENABLE_SECURITY_DOWNLOAD : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to enable secure UART download mode.*/ -#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x1 -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 -/* EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to disable download through USB-Serial-JTAG.*/ -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x1 -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 4 -/* EFUSE_RPT4_RESERVED8 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED8 (BIT(3)) -#define EFUSE_RPT4_RESERVED8_M (BIT(3)) -#define EFUSE_RPT4_RESERVED8_V 0x1 -#define EFUSE_RPT4_RESERVED8_S 3 -/* EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Disable USB-Serial-JTAG print during rom boot.*/ -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x1 -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 2 -/* EFUSE_DIS_DIRECT_BOOT : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to disable direct boot*/ -#define EFUSE_DIS_DIRECT_BOOT (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_M (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_V 0x1 -#define EFUSE_DIS_DIRECT_BOOT_S 1 -/* EFUSE_DIS_DOWNLOAD_MODE : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to disable download mode (boot_mode[3:0] = 0 1 2 3 6 7).*/ -#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_M (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MODE_S 0 +/** EFUSE_PGM_DATA3_REG register + * Register 3 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc) +/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0; + * The content of the 3rd 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_3 0xFFFFFFFFU +#define EFUSE_PGM_DATA_3_M (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S) +#define EFUSE_PGM_DATA_3_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_3_S 0 -#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x014) -/* EFUSE_RPT4_RESERVED4 : RO ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED4 0x00FFFFFF -#define EFUSE_RPT4_RESERVED4_M ((EFUSE_RPT4_RESERVED4_V)<<(EFUSE_RPT4_RESERVED4_S)) -#define EFUSE_RPT4_RESERVED4_V 0xFFFFFF -#define EFUSE_RPT4_RESERVED4_S 0 - -#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x018) -/* EFUSE_PGM_DATA_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the sixth 32-bit data to be programmed.*/ -#define EFUSE_PGM_DATA_6 0xFFFFFFFF -#define EFUSE_PGM_DATA_6_M ((EFUSE_PGM_DATA_6_V)<<(EFUSE_PGM_DATA_6_S)) -#define EFUSE_PGM_DATA_6_V 0xFFFFFFFF +/** EFUSE_PGM_DATA4_REG register + * Register 4 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) +/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0; + * The content of the 4th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_4 0xFFFFFFFFU +#define EFUSE_PGM_DATA_4_M (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S) +#define EFUSE_PGM_DATA_4_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_4_S 0 + +/** EFUSE_PGM_DATA5_REG register + * Register 5 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) +/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0; + * The content of the 5th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_5 0xFFFFFFFFU +#define EFUSE_PGM_DATA_5_M (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S) +#define EFUSE_PGM_DATA_5_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_5_S 0 + +/** EFUSE_PGM_DATA6_REG register + * Register 6 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) +/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0; + * The content of the 6th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_6 0xFFFFFFFFU +#define EFUSE_PGM_DATA_6_M (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S) +#define EFUSE_PGM_DATA_6_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_6_S 0 -#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x01C) -/* EFUSE_PGM_DATA_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the seventh 32-bit data to be programmed.*/ -#define EFUSE_PGM_DATA_7 0xFFFFFFFF -#define EFUSE_PGM_DATA_7_M ((EFUSE_PGM_DATA_7_V)<<(EFUSE_PGM_DATA_7_S)) -#define EFUSE_PGM_DATA_7_V 0xFFFFFFFF +/** EFUSE_PGM_DATA7_REG register + * Register 7 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c) +/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0; + * The content of the 7th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_7 0xFFFFFFFFU +#define EFUSE_PGM_DATA_7_M (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S) +#define EFUSE_PGM_DATA_7_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_7_S 0 -#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x020) -/* EFUSE_PGM_RS_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 0th 32-bit RS code to be programmed.*/ -#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_0_M ((EFUSE_PGM_RS_DATA_0_V)<<(EFUSE_PGM_RS_DATA_0_S)) -#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFF +/** EFUSE_PGM_CHECK_VALUE0_REG register + * Register 0 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) +/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) +#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_0_S 0 -#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x024) -/* EFUSE_PGM_RS_DATA_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the first 32-bit RS code to be programmed.*/ -#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_1_M ((EFUSE_PGM_RS_DATA_1_V)<<(EFUSE_PGM_RS_DATA_1_S)) -#define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFF +/** EFUSE_PGM_CHECK_VALUE1_REG register + * Register 1 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) +/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1st 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_1_M (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S) +#define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_1_S 0 -#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x028) -/* EFUSE_PGM_RS_DATA_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the second 32-bit RS code to be programmed.*/ -#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_2_M ((EFUSE_PGM_RS_DATA_2_V)<<(EFUSE_PGM_RS_DATA_2_S)) -#define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFF +/** EFUSE_PGM_CHECK_VALUE2_REG register + * Register 2 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) +/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2nd 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_2_M (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S) +#define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_2_S 0 -#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x02C) -/* EFUSE_WR_DIS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The value of WR_DIS.*/ -#define EFUSE_WR_DIS 0xFFFFFFFF -#define EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S)) -#define EFUSE_WR_DIS_V 0xFFFFFFFF +/** EFUSE_RD_WR_DIS_REG register + * BLOCK0 data register 0. + */ +#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c) +/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; + * Disable programming of individual eFuses. + */ +#define EFUSE_WR_DIS 0xFFFFFFFFU +#define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) +#define EFUSE_WR_DIS_V 0xFFFFFFFFU #define EFUSE_WR_DIS_S 0 -#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x030) -/* EFUSE_POWER_GLITCH_DSENSE : RO ;bitpos:[31:30] ;default: 2'h0 ; */ -/*description: The value of POWER_GLITCH_DSENSE.*/ -#define EFUSE_POWER_GLITCH_DSENSE 0x00000003 -#define EFUSE_POWER_GLITCH_DSENSE_M ((EFUSE_POWER_GLITCH_DSENSE_V)<<(EFUSE_POWER_GLITCH_DSENSE_S)) -#define EFUSE_POWER_GLITCH_DSENSE_V 0x3 -#define EFUSE_POWER_GLITCH_DSENSE_S 30 -/* EFUSE_POWERGLITCH_EN : RO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: The value of POWERGLITCH_EN.*/ -#define EFUSE_POWERGLITCH_EN (BIT(29)) -#define EFUSE_POWERGLITCH_EN_M (BIT(29)) -#define EFUSE_POWERGLITCH_EN_V 0x1 -#define EFUSE_POWERGLITCH_EN_S 29 -/* EFUSE_BTLC_GPIO_ENABLE : RO ;bitpos:[28:27] ;default: 2'h0 ; */ -/*description: The value of BTLC_GPIO_ENABLE.*/ -#define EFUSE_BTLC_GPIO_ENABLE 0x00000003 -#define EFUSE_BTLC_GPIO_ENABLE_M ((EFUSE_BTLC_GPIO_ENABLE_V)<<(EFUSE_BTLC_GPIO_ENABLE_S)) -#define EFUSE_BTLC_GPIO_ENABLE_V 0x3 -#define EFUSE_BTLC_GPIO_ENABLE_S 27 -/* EFUSE_VDD_SPI_AS_GPIO : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: The value of VDD_SPI_AS_GPIO.*/ -#define EFUSE_VDD_SPI_AS_GPIO (BIT(26)) -#define EFUSE_VDD_SPI_AS_GPIO_M (BIT(26)) -#define EFUSE_VDD_SPI_AS_GPIO_V 0x1 -#define EFUSE_VDD_SPI_AS_GPIO_S 26 -/* EFUSE_USB_EXCHG_PINS : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: The value of USB_EXCHG_PINS.*/ -#define EFUSE_USB_EXCHG_PINS (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_M (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_V 0x1 -#define EFUSE_USB_EXCHG_PINS_S 25 -/* EFUSE_USB_DREFL : RO ;bitpos:[24:23] ;default: 2'h0 ; */ -/*description: The value of USB_DREFL.*/ -#define EFUSE_USB_DREFL 0x00000003 -#define EFUSE_USB_DREFL_M ((EFUSE_USB_DREFL_V)<<(EFUSE_USB_DREFL_S)) -#define EFUSE_USB_DREFL_V 0x3 -#define EFUSE_USB_DREFL_S 23 -/* EFUSE_USB_DREFH : RO ;bitpos:[22:21] ;default: 2'h0 ; */ -/*description: The value of USB_DREFH.*/ -#define EFUSE_USB_DREFH 0x00000003 -#define EFUSE_USB_DREFH_M ((EFUSE_USB_DREFH_V)<<(EFUSE_USB_DREFH_S)) -#define EFUSE_USB_DREFH_V 0x3 -#define EFUSE_USB_DREFH_S 21 -/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: The value of DIS_DOWNLOAD_MANUAL_ENCRYPT.*/ -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 -/* EFUSE_DIS_PAD_JTAG : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: The value of DIS_PAD_JTAG.*/ -#define EFUSE_DIS_PAD_JTAG (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_M (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_V 0x1 -#define EFUSE_DIS_PAD_JTAG_S 19 -/* EFUSE_SOFT_DIS_JTAG : RO ;bitpos:[18:16] ;default: 3'h0 ; */ -/*description: The value of SOFT_DIS_JTAG.*/ -#define EFUSE_SOFT_DIS_JTAG 0x00000007 -#define EFUSE_SOFT_DIS_JTAG_M ((EFUSE_SOFT_DIS_JTAG_V)<<(EFUSE_SOFT_DIS_JTAG_S)) -#define EFUSE_SOFT_DIS_JTAG_V 0x7 -#define EFUSE_SOFT_DIS_JTAG_S 16 -/* EFUSE_JTAG_SEL_ENABLE : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The value of JTAG_SEL_ENABLE.*/ -#define EFUSE_JTAG_SEL_ENABLE (BIT(15)) -#define EFUSE_JTAG_SEL_ENABLE_M (BIT(15)) -#define EFUSE_JTAG_SEL_ENABLE_V 0x1 -#define EFUSE_JTAG_SEL_ENABLE_S 15 -/* EFUSE_DIS_TWAI : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The value of DIS_TWAI.*/ -#define EFUSE_DIS_TWAI (BIT(14)) -#define EFUSE_DIS_TWAI_M (BIT(14)) -#define EFUSE_DIS_TWAI_V 0x1 -#define EFUSE_DIS_TWAI_S 14 -/* EFUSE_RPT4_RESERVED6 : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Reserved (used for four backups method)..*/ +/** EFUSE_RD_REPEAT_DATA0_REG register + * BLOCK0 data register 1. + */ +#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) +/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; + * Set this bit to disable reading from BlOCK4-10. + */ +#define EFUSE_RD_DIS 0x0000007FU +#define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) +#define EFUSE_RD_DIS_V 0x0000007FU +#define EFUSE_RD_DIS_S 0 +/** EFUSE_DIS_RTC_RAM_BOOT : RO; bitpos: [7]; default: 0; + * Set this bit to disable boot from RTC RAM. + */ +#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) +#define EFUSE_DIS_RTC_RAM_BOOT_M (EFUSE_DIS_RTC_RAM_BOOT_V << EFUSE_DIS_RTC_RAM_BOOT_S) +#define EFUSE_DIS_RTC_RAM_BOOT_V 0x00000001U +#define EFUSE_DIS_RTC_RAM_BOOT_S 7 +/** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0; + * Set this bit to disable Icache. + */ +#define EFUSE_DIS_ICACHE (BIT(8)) +#define EFUSE_DIS_ICACHE_M (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S) +#define EFUSE_DIS_ICACHE_V 0x00000001U +#define EFUSE_DIS_ICACHE_S 8 +/** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0; + * Set this bit to disable function of usb switch to jtag in module of usb device. + */ +#define EFUSE_DIS_USB_JTAG (BIT(9)) +#define EFUSE_DIS_USB_JTAG_M (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S) +#define EFUSE_DIS_USB_JTAG_V 0x00000001U +#define EFUSE_DIS_USB_JTAG_S 9 +/** EFUSE_DIS_DOWNLOAD_ICACHE : RO; bitpos: [10]; default: 0; + * Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, + * 7). + */ +#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) +#define EFUSE_DIS_DOWNLOAD_ICACHE_M (EFUSE_DIS_DOWNLOAD_ICACHE_V << EFUSE_DIS_DOWNLOAD_ICACHE_S) +#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 +/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [11]; default: 0; + * Represents whether USB-Serial-JTAG is disabled. 1: Disabled. 0: Enabled + */ +#define EFUSE_DIS_USB_SERIAL_JTAG (BIT(11)) +#define EFUSE_DIS_USB_SERIAL_JTAG_M (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_S 11 +/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0; + * Set this bit to disable the function that forces chip into download mode. + */ +#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x00000001U +#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 +/** EFUSE_RPT4_RESERVED6 : RO; bitpos: [13]; default: 0; + * Reserved (used for four backups method). + */ #define EFUSE_RPT4_RESERVED6 (BIT(13)) -#define EFUSE_RPT4_RESERVED6_M (BIT(13)) -#define EFUSE_RPT4_RESERVED6_V 0x1 +#define EFUSE_RPT4_RESERVED6_M (EFUSE_RPT4_RESERVED6_V << EFUSE_RPT4_RESERVED6_S) +#define EFUSE_RPT4_RESERVED6_V 0x00000001U #define EFUSE_RPT4_RESERVED6_S 13 -/* EFUSE_DIS_FORCE_DOWNLOAD : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The value of DIS_FORCE_DOWNLOAD.*/ -#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_M (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x1 -#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 -/* EFUSE_DIS_USB_DEVICE : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The value of DIS_USB_DEVICE.*/ -#define EFUSE_DIS_USB_DEVICE (BIT(11)) -#define EFUSE_DIS_USB_DEVICE_M (BIT(11)) -#define EFUSE_DIS_USB_DEVICE_V 0x1 -#define EFUSE_DIS_USB_DEVICE_S 11 -/* EFUSE_DIS_DOWNLOAD_ICACHE : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The value of DIS_DOWNLOAD_ICACHE.*/ -#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_M (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x1 -#define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 -/* EFUSE_DIS_USB_JTAG : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The value of DIS_USB_JTAG.*/ -#define EFUSE_DIS_USB_JTAG (BIT(9)) -#define EFUSE_DIS_USB_JTAG_M (BIT(9)) -#define EFUSE_DIS_USB_JTAG_V 0x1 -#define EFUSE_DIS_USB_JTAG_S 9 -/* EFUSE_DIS_ICACHE : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The value of DIS_ICACHE.*/ -#define EFUSE_DIS_ICACHE (BIT(8)) -#define EFUSE_DIS_ICACHE_M (BIT(8)) -#define EFUSE_DIS_ICACHE_V 0x1 -#define EFUSE_DIS_ICACHE_S 8 -/* EFUSE_RPT4_RESERVED5 : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED5 (BIT(7)) -#define EFUSE_RPT4_RESERVED5_M (BIT(7)) -#define EFUSE_RPT4_RESERVED5_V 0x1 -#define EFUSE_RPT4_RESERVED5_S 7 -/* EFUSE_RD_DIS : RO ;bitpos:[6:0] ;default: 7'h0 ; */ -/*description: The value of RD_DIS.*/ -#define EFUSE_RD_DIS 0x0000007F -#define EFUSE_RD_DIS_M ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S)) -#define EFUSE_RD_DIS_V 0x7F -#define EFUSE_RD_DIS_S 0 +/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0; + * Set this bit to disable CAN function. + */ +#define EFUSE_DIS_TWAI (BIT(14)) +#define EFUSE_DIS_TWAI_M (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S) +#define EFUSE_DIS_TWAI_V 0x00000001U +#define EFUSE_DIS_TWAI_S 14 +/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0; + * Set this bit to enable selection between usb_to_jtag and pad_to_jtag through + * strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0. + */ +#define EFUSE_JTAG_SEL_ENABLE (BIT(15)) +#define EFUSE_JTAG_SEL_ENABLE_M (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S) +#define EFUSE_JTAG_SEL_ENABLE_V 0x00000001U +#define EFUSE_JTAG_SEL_ENABLE_S 15 +/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0; + * Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG + * can be enabled in HMAC module. + */ +#define EFUSE_SOFT_DIS_JTAG 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_M (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S) +#define EFUSE_SOFT_DIS_JTAG_V 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_S 16 +/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0; + * Set this bit to disable JTAG in the hard way. JTAG is disabled permanently. + */ +#define EFUSE_DIS_PAD_JTAG (BIT(19)) +#define EFUSE_DIS_PAD_JTAG_M (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S) +#define EFUSE_DIS_PAD_JTAG_V 0x00000001U +#define EFUSE_DIS_PAD_JTAG_S 19 +/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0; + * Set this bit to disable flash encryption when in download boot modes. + */ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 +/** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0; + * Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored + * in eFuse. + */ +#define EFUSE_USB_DREFH 0x00000003U +#define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S) +#define EFUSE_USB_DREFH_V 0x00000003U +#define EFUSE_USB_DREFH_S 21 +/** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0; + * Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, + * stored in eFuse. + */ +#define EFUSE_USB_DREFL 0x00000003U +#define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S) +#define EFUSE_USB_DREFL_V 0x00000003U +#define EFUSE_USB_DREFL_S 23 +/** EFUSE_USB_EXCHG_PINS : RO; bitpos: [25]; default: 0; + * Set this bit to exchange USB D+ and D- pins. + */ +#define EFUSE_USB_EXCHG_PINS (BIT(25)) +#define EFUSE_USB_EXCHG_PINS_M (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S) +#define EFUSE_USB_EXCHG_PINS_V 0x00000001U +#define EFUSE_USB_EXCHG_PINS_S 25 +/** EFUSE_VDD_SPI_AS_GPIO : RO; bitpos: [26]; default: 0; + * Set this bit to vdd spi pin function as gpio. + */ +#define EFUSE_VDD_SPI_AS_GPIO (BIT(26)) +#define EFUSE_VDD_SPI_AS_GPIO_M (EFUSE_VDD_SPI_AS_GPIO_V << EFUSE_VDD_SPI_AS_GPIO_S) +#define EFUSE_VDD_SPI_AS_GPIO_V 0x00000001U +#define EFUSE_VDD_SPI_AS_GPIO_S 26 +/** EFUSE_BTLC_GPIO_ENABLE : RO; bitpos: [28:27]; default: 0; + * Enable btlc gpio. + */ +#define EFUSE_BTLC_GPIO_ENABLE 0x00000003U +#define EFUSE_BTLC_GPIO_ENABLE_M (EFUSE_BTLC_GPIO_ENABLE_V << EFUSE_BTLC_GPIO_ENABLE_S) +#define EFUSE_BTLC_GPIO_ENABLE_V 0x00000003U +#define EFUSE_BTLC_GPIO_ENABLE_S 27 +/** EFUSE_POWERGLITCH_EN : RO; bitpos: [29]; default: 0; + * Set this bit to enable power glitch function. + */ +#define EFUSE_POWERGLITCH_EN (BIT(29)) +#define EFUSE_POWERGLITCH_EN_M (EFUSE_POWERGLITCH_EN_V << EFUSE_POWERGLITCH_EN_S) +#define EFUSE_POWERGLITCH_EN_V 0x00000001U +#define EFUSE_POWERGLITCH_EN_S 29 +/** EFUSE_POWER_GLITCH_DSENSE : RO; bitpos: [31:30]; default: 0; + * Sample delay configuration of power glitch. + */ +#define EFUSE_POWER_GLITCH_DSENSE 0x00000003U +#define EFUSE_POWER_GLITCH_DSENSE_M (EFUSE_POWER_GLITCH_DSENSE_V << EFUSE_POWER_GLITCH_DSENSE_S) +#define EFUSE_POWER_GLITCH_DSENSE_V 0x00000003U +#define EFUSE_POWER_GLITCH_DSENSE_S 30 -#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x034) -/* EFUSE_KEY_PURPOSE_1 : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_1.*/ -#define EFUSE_KEY_PURPOSE_1 0x0000000F -#define EFUSE_KEY_PURPOSE_1_M ((EFUSE_KEY_PURPOSE_1_V)<<(EFUSE_KEY_PURPOSE_1_S)) -#define EFUSE_KEY_PURPOSE_1_V 0xF -#define EFUSE_KEY_PURPOSE_1_S 28 -/* EFUSE_KEY_PURPOSE_0 : RO ;bitpos:[27:24] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_0.*/ -#define EFUSE_KEY_PURPOSE_0 0x0000000F -#define EFUSE_KEY_PURPOSE_0_M ((EFUSE_KEY_PURPOSE_0_V)<<(EFUSE_KEY_PURPOSE_0_S)) -#define EFUSE_KEY_PURPOSE_0_V 0xF -#define EFUSE_KEY_PURPOSE_0_S 24 -/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: The value of SECURE_BOOT_KEY_REVOKE2.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 -/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: The value of SECURE_BOOT_KEY_REVOKE1.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 -/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: The value of SECURE_BOOT_KEY_REVOKE0.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 -/* EFUSE_SPI_BOOT_CRYPT_CNT : RO ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: The value of SPI_BOOT_CRYPT_CNT.*/ -#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_M ((EFUSE_SPI_BOOT_CRYPT_CNT_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_S)) -#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x7 -#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 -/* EFUSE_WDT_DELAY_SEL : RO ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: The value of WDT_DELAY_SEL.*/ -#define EFUSE_WDT_DELAY_SEL 0x00000003 -#define EFUSE_WDT_DELAY_SEL_M ((EFUSE_WDT_DELAY_SEL_V)<<(EFUSE_WDT_DELAY_SEL_S)) -#define EFUSE_WDT_DELAY_SEL_V 0x3 -#define EFUSE_WDT_DELAY_SEL_S 16 -/* EFUSE_RPT4_RESERVED2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED2 0x0000FFFF -#define EFUSE_RPT4_RESERVED2_M ((EFUSE_RPT4_RESERVED2_V)<<(EFUSE_RPT4_RESERVED2_S)) -#define EFUSE_RPT4_RESERVED2_V 0xFFFF +/** EFUSE_RD_REPEAT_DATA1_REG register + * BLOCK0 data register 2. + */ +#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) +/** EFUSE_RPT4_RESERVED2 : RO; bitpos: [15:0]; default: 0; + * Reserved (used for four backups method). + */ +#define EFUSE_RPT4_RESERVED2 0x0000FFFFU +#define EFUSE_RPT4_RESERVED2_M (EFUSE_RPT4_RESERVED2_V << EFUSE_RPT4_RESERVED2_S) +#define EFUSE_RPT4_RESERVED2_V 0x0000FFFFU #define EFUSE_RPT4_RESERVED2_S 0 +/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0; + * Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: + * 80000. 2: 160000. 3:320000. + */ +#define EFUSE_WDT_DELAY_SEL 0x00000003U +#define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) +#define EFUSE_WDT_DELAY_SEL_V 0x00000003U +#define EFUSE_WDT_DELAY_SEL_S 16 +/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0; + * Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even + * number of 1: disable. + */ +#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 +/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0; + * Set this bit to enable revoking first secure boot key. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 +/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0; + * Set this bit to enable revoking second secure boot key. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 +/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0; + * Set this bit to enable revoking third secure boot key. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 +/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0; + * Purpose of Key0. + */ +#define EFUSE_KEY_PURPOSE_0 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_M (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S) +#define EFUSE_KEY_PURPOSE_0_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_S 24 +/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0; + * Purpose of Key1. + */ +#define EFUSE_KEY_PURPOSE_1 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_M (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S) +#define EFUSE_KEY_PURPOSE_1_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_S 28 -#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x038) -/* EFUSE_FLASH_TPUW : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: The value of FLASH_TPUW.*/ -#define EFUSE_FLASH_TPUW 0x0000000F -#define EFUSE_FLASH_TPUW_M ((EFUSE_FLASH_TPUW_V)<<(EFUSE_FLASH_TPUW_S)) -#define EFUSE_FLASH_TPUW_V 0xF -#define EFUSE_FLASH_TPUW_S 28 -/* EFUSE_RPT4_RESERVED0 : RO ;bitpos:[27:22] ;default: 6'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED0 0x0000003F -#define EFUSE_RPT4_RESERVED0_M ((EFUSE_RPT4_RESERVED0_V)<<(EFUSE_RPT4_RESERVED0_S)) -#define EFUSE_RPT4_RESERVED0_V 0x3F -#define EFUSE_RPT4_RESERVED0_S 22 -/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: The value of SECURE_BOOT_AGGRESSIVE_REVOKE.*/ -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x1 -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 -/* EFUSE_SECURE_BOOT_EN : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: The value of SECURE_BOOT_EN.*/ -#define EFUSE_SECURE_BOOT_EN (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_M (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_V 0x1 -#define EFUSE_SECURE_BOOT_EN_S 20 -/* EFUSE_RPT4_RESERVED3 : RO ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED3 0x0000000F -#define EFUSE_RPT4_RESERVED3_M ((EFUSE_RPT4_RESERVED3_V)<<(EFUSE_RPT4_RESERVED3_S)) -#define EFUSE_RPT4_RESERVED3_V 0xF -#define EFUSE_RPT4_RESERVED3_S 16 -/* EFUSE_KEY_PURPOSE_5 : RO ;bitpos:[15:12] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_5.*/ -#define EFUSE_KEY_PURPOSE_5 0x0000000F -#define EFUSE_KEY_PURPOSE_5_M ((EFUSE_KEY_PURPOSE_5_V)<<(EFUSE_KEY_PURPOSE_5_S)) -#define EFUSE_KEY_PURPOSE_5_V 0xF -#define EFUSE_KEY_PURPOSE_5_S 12 -/* EFUSE_KEY_PURPOSE_4 : RO ;bitpos:[11:8] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_4.*/ -#define EFUSE_KEY_PURPOSE_4 0x0000000F -#define EFUSE_KEY_PURPOSE_4_M ((EFUSE_KEY_PURPOSE_4_V)<<(EFUSE_KEY_PURPOSE_4_S)) -#define EFUSE_KEY_PURPOSE_4_V 0xF -#define EFUSE_KEY_PURPOSE_4_S 8 -/* EFUSE_KEY_PURPOSE_3 : RO ;bitpos:[7:4] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_3.*/ -#define EFUSE_KEY_PURPOSE_3 0x0000000F -#define EFUSE_KEY_PURPOSE_3_M ((EFUSE_KEY_PURPOSE_3_V)<<(EFUSE_KEY_PURPOSE_3_S)) -#define EFUSE_KEY_PURPOSE_3_V 0xF -#define EFUSE_KEY_PURPOSE_3_S 4 -/* EFUSE_KEY_PURPOSE_2 : RO ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_2.*/ -#define EFUSE_KEY_PURPOSE_2 0x0000000F -#define EFUSE_KEY_PURPOSE_2_M ((EFUSE_KEY_PURPOSE_2_V)<<(EFUSE_KEY_PURPOSE_2_S)) -#define EFUSE_KEY_PURPOSE_2_V 0xF +/** EFUSE_RD_REPEAT_DATA2_REG register + * BLOCK0 data register 3. + */ +#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) +/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0; + * Purpose of Key2. + */ +#define EFUSE_KEY_PURPOSE_2 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_M (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S) +#define EFUSE_KEY_PURPOSE_2_V 0x0000000FU #define EFUSE_KEY_PURPOSE_2_S 0 +/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0; + * Purpose of Key3. + */ +#define EFUSE_KEY_PURPOSE_3 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_M (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S) +#define EFUSE_KEY_PURPOSE_3_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_S 4 +/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0; + * Purpose of Key4. + */ +#define EFUSE_KEY_PURPOSE_4 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_M (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S) +#define EFUSE_KEY_PURPOSE_4_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_S 8 +/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0; + * Purpose of Key5. + */ +#define EFUSE_KEY_PURPOSE_5 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S) +#define EFUSE_KEY_PURPOSE_5_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_S 12 +/** EFUSE_RPT4_RESERVED3 : RO; bitpos: [19:16]; default: 0; + * Reserved (used for four backups method). + */ +#define EFUSE_RPT4_RESERVED3 0x0000000FU +#define EFUSE_RPT4_RESERVED3_M (EFUSE_RPT4_RESERVED3_V << EFUSE_RPT4_RESERVED3_S) +#define EFUSE_RPT4_RESERVED3_V 0x0000000FU +#define EFUSE_RPT4_RESERVED3_S 16 +/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0; + * Set this bit to enable secure boot. + */ +#define EFUSE_SECURE_BOOT_EN (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) +#define EFUSE_SECURE_BOOT_EN_V 0x00000001U +#define EFUSE_SECURE_BOOT_EN_S 20 +/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0; + * Set this bit to enable revoking aggressive secure boot. + */ +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001U +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 +/** EFUSE_RPT4_RESERVED0 : RO; bitpos: [27:22]; default: 0; + * Reserved (used for four backups method). + */ +#define EFUSE_RPT4_RESERVED0 0x0000003FU +#define EFUSE_RPT4_RESERVED0_M (EFUSE_RPT4_RESERVED0_V << EFUSE_RPT4_RESERVED0_S) +#define EFUSE_RPT4_RESERVED0_V 0x0000003FU +#define EFUSE_RPT4_RESERVED0_S 22 +/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0; + * Configures flash waiting time after power-up, in unit of ms. If the value is less + * than 15, the waiting time is the configurable value; Otherwise, the waiting time is + * twice the configurable value. + */ +#define EFUSE_FLASH_TPUW 0x0000000FU +#define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S) +#define EFUSE_FLASH_TPUW_V 0x0000000FU +#define EFUSE_FLASH_TPUW_S 28 -#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x03C) -/* EFUSE_ERR_RST_ENABLE : RO ;bitpos:[31] ;default: 1'h0 ; */ -/*description: Use BLOCK0 to check error record registers, 0 - without check.*/ -#define EFUSE_ERR_RST_ENABLE (BIT(31)) -#define EFUSE_ERR_RST_ENABLE_M (BIT(31)) -#define EFUSE_ERR_RST_ENABLE_V 0x1 -#define EFUSE_ERR_RST_ENABLE_S 31 -/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[30] ;default: 1'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED1 (BIT(30)) -#define EFUSE_RPT4_RESERVED1_M (BIT(30)) -#define EFUSE_RPT4_RESERVED1_V 0x1 -#define EFUSE_RPT4_RESERVED1_S 30 -/* EFUSE_SECURE_VERSION : RO ;bitpos:[29:14] ;default: 16'h0 ; */ -/*description: The value of SECURE_VERSION.*/ -#define EFUSE_SECURE_VERSION 0x0000FFFF -#define EFUSE_SECURE_VERSION_M ((EFUSE_SECURE_VERSION_V)<<(EFUSE_SECURE_VERSION_S)) -#define EFUSE_SECURE_VERSION_V 0xFFFF -#define EFUSE_SECURE_VERSION_S 14 -/* EFUSE_FORCE_SEND_RESUME : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The value of FORCE_SEND_RESUME.*/ -#define EFUSE_FORCE_SEND_RESUME (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_M (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_V 0x1 -#define EFUSE_FORCE_SEND_RESUME_S 13 -/* EFUSE_RPT4_RESERVED7 : RO ;bitpos:[12:8] ;default: 5'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED7 0x0000001F -#define EFUSE_RPT4_RESERVED7_M ((EFUSE_RPT4_RESERVED7_V)<<(EFUSE_RPT4_RESERVED7_S)) -#define EFUSE_RPT4_RESERVED7_V 0x1F -#define EFUSE_RPT4_RESERVED7_S 8 -/* EFUSE_UART_PRINT_CONTROL : RO ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: The value of UART_PRINT_CONTROL.*/ -#define EFUSE_UART_PRINT_CONTROL 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_M ((EFUSE_UART_PRINT_CONTROL_V)<<(EFUSE_UART_PRINT_CONTROL_S)) -#define EFUSE_UART_PRINT_CONTROL_V 0x3 -#define EFUSE_UART_PRINT_CONTROL_S 6 -/* EFUSE_ENABLE_SECURITY_DOWNLOAD : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The value of ENABLE_SECURITY_DOWNLOAD.*/ -#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x1 -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 -/* EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The value of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.*/ -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x1 -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 4 -/* EFUSE_RPT4_RESERVED8 : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED8 (BIT(3)) -#define EFUSE_RPT4_RESERVED8_M (BIT(3)) -#define EFUSE_RPT4_RESERVED8_V 0x1 -#define EFUSE_RPT4_RESERVED8_S 3 -/* EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The value of DIS_USB_SERIAL_JTAG_ROM_PRINT.*/ -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x1 -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 2 -/* EFUSE_DIS_DIRECT_BOOT : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The value of DIS_DIRECT_BOOT.*/ -#define EFUSE_DIS_DIRECT_BOOT (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_M (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_V 0x1 -#define EFUSE_DIS_DIRECT_BOOT_S 1 -/* EFUSE_DIS_DOWNLOAD_MODE : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The value of DIS_DOWNLOAD_MODE.*/ -#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_M (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_V 0x1 +/** EFUSE_RD_REPEAT_DATA3_REG register + * BLOCK0 data register 4. + */ +#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) +/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; + * Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7). + */ +#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) +#define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MODE_S 0 +/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0; + * Disable direct boot mode + */ +#define EFUSE_DIS_DIRECT_BOOT (BIT(1)) +#define EFUSE_DIS_DIRECT_BOOT_M (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S) +#define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U +#define EFUSE_DIS_DIRECT_BOOT_S 1 +/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0; + * Represents whether USB printing is disabled or enabled. 1: Disabled. 0: Enabled + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 2 +/** EFUSE_FLASH_ECC_MODE : RO; bitpos: [3]; default: 0; + * Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would + * use 16to17 byte mode. + */ +#define EFUSE_FLASH_ECC_MODE (BIT(3)) +#define EFUSE_FLASH_ECC_MODE_M (EFUSE_FLASH_ECC_MODE_V << EFUSE_FLASH_ECC_MODE_S) +#define EFUSE_FLASH_ECC_MODE_V 0x00000001U +#define EFUSE_FLASH_ECC_MODE_S 3 +/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0; + * Disable UART download mode through USB-Serial-JTAG + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(4)) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 4 +/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0; + * Set this bit to enable secure UART download mode. + */ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001U +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 +/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0; + * Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 + * is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled. + */ +#define EFUSE_UART_PRINT_CONTROL 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) +#define EFUSE_UART_PRINT_CONTROL_V 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_S 6 +/** EFUSE_PIN_POWER_SELECTION : RO; bitpos: [8]; default: 0; + * GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI. + */ +#define EFUSE_PIN_POWER_SELECTION (BIT(8)) +#define EFUSE_PIN_POWER_SELECTION_M (EFUSE_PIN_POWER_SELECTION_V << EFUSE_PIN_POWER_SELECTION_S) +#define EFUSE_PIN_POWER_SELECTION_V 0x00000001U +#define EFUSE_PIN_POWER_SELECTION_S 8 +/** EFUSE_FLASH_TYPE : RO; bitpos: [9]; default: 0; + * Set the maximum lines of SPI flash. 0: four lines. 1: eight lines. + */ +#define EFUSE_FLASH_TYPE (BIT(9)) +#define EFUSE_FLASH_TYPE_M (EFUSE_FLASH_TYPE_V << EFUSE_FLASH_TYPE_S) +#define EFUSE_FLASH_TYPE_V 0x00000001U +#define EFUSE_FLASH_TYPE_S 9 +/** EFUSE_FLASH_PAGE_SIZE : RO; bitpos: [11:10]; default: 0; + * Set Flash page size. + */ +#define EFUSE_FLASH_PAGE_SIZE 0x00000003U +#define EFUSE_FLASH_PAGE_SIZE_M (EFUSE_FLASH_PAGE_SIZE_V << EFUSE_FLASH_PAGE_SIZE_S) +#define EFUSE_FLASH_PAGE_SIZE_V 0x00000003U +#define EFUSE_FLASH_PAGE_SIZE_S 10 +/** EFUSE_FLASH_ECC_EN : RO; bitpos: [12]; default: 0; + * Set 1 to enable ECC for flash boot. + */ +#define EFUSE_FLASH_ECC_EN (BIT(12)) +#define EFUSE_FLASH_ECC_EN_M (EFUSE_FLASH_ECC_EN_V << EFUSE_FLASH_ECC_EN_S) +#define EFUSE_FLASH_ECC_EN_V 0x00000001U +#define EFUSE_FLASH_ECC_EN_S 12 +/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [13]; default: 0; + * Set this bit to force ROM code to send a resume command during SPI boot. + */ +#define EFUSE_FORCE_SEND_RESUME (BIT(13)) +#define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) +#define EFUSE_FORCE_SEND_RESUME_V 0x00000001U +#define EFUSE_FORCE_SEND_RESUME_S 13 +/** EFUSE_SECURE_VERSION : RO; bitpos: [29:14]; default: 0; + * Secure version (used by ESP-IDF anti-rollback feature). + */ +#define EFUSE_SECURE_VERSION 0x0000FFFFU +#define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) +#define EFUSE_SECURE_VERSION_V 0x0000FFFFU +#define EFUSE_SECURE_VERSION_S 14 +/** EFUSE_RESERVED_0_158 : R; bitpos: [30]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_0_158 (BIT(30)) +#define EFUSE_RESERVED_0_158_M (EFUSE_RESERVED_0_158_V << EFUSE_RESERVED_0_158_S) +#define EFUSE_RESERVED_0_158_V 0x00000001U +#define EFUSE_RESERVED_0_158_S 30 +/** EFUSE_ERR_RST_ENABLE : R; bitpos: [31]; default: 0; + * Use BLOCK0 to check error record registers + */ +#define EFUSE_ERR_RST_ENABLE (BIT(31)) +#define EFUSE_ERR_RST_ENABLE_M (EFUSE_ERR_RST_ENABLE_V << EFUSE_ERR_RST_ENABLE_S) +#define EFUSE_ERR_RST_ENABLE_V 0x00000001U +#define EFUSE_ERR_RST_ENABLE_S 31 -#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x040) -/* EFUSE_RPT4_RESERVED4 : RO ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED4 0x00FFFFFF -#define EFUSE_RPT4_RESERVED4_M ((EFUSE_RPT4_RESERVED4_V)<<(EFUSE_RPT4_RESERVED4_S)) -#define EFUSE_RPT4_RESERVED4_V 0xFFFFFF -#define EFUSE_RPT4_RESERVED4_S 0 - -#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x044) -/* EFUSE_MAC_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the low 32 bits of MAC address.*/ -#define EFUSE_MAC_0 0xFFFFFFFF -#define EFUSE_MAC_0_M ((EFUSE_MAC_0_V)<<(EFUSE_MAC_0_S)) -#define EFUSE_MAC_0_V 0xFFFFFFFF +/** EFUSE_RD_REPEAT_DATA4_REG register + * BLOCK0 data register 5. + */ +#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) +/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [0]; default: 0; + * Disables check of wafer version major + */ +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR (BIT(0)) +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S) +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V 0x00000001U +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S 0 +/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [1]; default: 0; + * Disables check of blk version major + */ +#define EFUSE_DISABLE_BLK_VERSION_MAJOR (BIT(1)) +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S) +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V 0x00000001U +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S 1 +/** EFUSE_RESERVED_0_162 : R; bitpos: [23:2]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_0_162 0x003FFFFFU +#define EFUSE_RESERVED_0_162_M (EFUSE_RESERVED_0_162_V << EFUSE_RESERVED_0_162_S) +#define EFUSE_RESERVED_0_162_V 0x003FFFFFU +#define EFUSE_RESERVED_0_162_S 2 + +/** EFUSE_RD_MAC_SPI_SYS_0_REG register + * BLOCK1 data register 0. + */ +#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44) +/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0; + * Stores the low 32 bits of MAC address. + */ +#define EFUSE_MAC_0 0xFFFFFFFFU +#define EFUSE_MAC_0_M (EFUSE_MAC_0_V << EFUSE_MAC_0_S) +#define EFUSE_MAC_0_V 0xFFFFFFFFU #define EFUSE_MAC_0_S 0 -#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x048) -/* EFUSE_SPI_PAD_CONF_0 : RO ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: Stores the zeroth part of SPI_PAD_CONF.*/ -#define EFUSE_SPI_PAD_CONF_0 0x0000FFFF -#define EFUSE_SPI_PAD_CONF_0_M ((EFUSE_SPI_PAD_CONF_0_V)<<(EFUSE_SPI_PAD_CONF_0_S)) -#define EFUSE_SPI_PAD_CONF_0_V 0xFFFF -#define EFUSE_SPI_PAD_CONF_0_S 16 -/* EFUSE_MAC_1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: Stores the high 16 bits of MAC address.*/ -#define EFUSE_MAC_1 0x0000FFFF -#define EFUSE_MAC_1_M ((EFUSE_MAC_1_V)<<(EFUSE_MAC_1_S)) -#define EFUSE_MAC_1_V 0xFFFF +/** EFUSE_RD_MAC_SPI_SYS_1_REG register + * BLOCK1 data register 1. + */ +#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48) +/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0; + * Stores the high 16 bits of MAC address. + */ +#define EFUSE_MAC_1 0x0000FFFFU +#define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) +#define EFUSE_MAC_1_V 0x0000FFFFU #define EFUSE_MAC_1_S 0 +/** EFUSE_SPI_PAD_CONFIG_CLK : R; bitpos: [21:16]; default: 0; + * SPI PAD CLK + */ +#define EFUSE_SPI_PAD_CONFIG_CLK 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_CLK_M (EFUSE_SPI_PAD_CONFIG_CLK_V << EFUSE_SPI_PAD_CONFIG_CLK_S) +#define EFUSE_SPI_PAD_CONFIG_CLK_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_CLK_S 16 +/** EFUSE_SPI_PAD_CONFIG_Q : R; bitpos: [27:22]; default: 0; + * SPI PAD Q(D1) + */ +#define EFUSE_SPI_PAD_CONFIG_Q 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_Q_M (EFUSE_SPI_PAD_CONFIG_Q_V << EFUSE_SPI_PAD_CONFIG_Q_S) +#define EFUSE_SPI_PAD_CONFIG_Q_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_Q_S 22 +/** EFUSE_SPI_PAD_CONFIG_D : R; bitpos: [31:28]; default: 0; + * SPI PAD D(D0) + */ +#define EFUSE_SPI_PAD_CONFIG_D 0x0000000FU +#define EFUSE_SPI_PAD_CONFIG_D_M (EFUSE_SPI_PAD_CONFIG_D_V << EFUSE_SPI_PAD_CONFIG_D_S) +#define EFUSE_SPI_PAD_CONFIG_D_V 0x0000000FU +#define EFUSE_SPI_PAD_CONFIG_D_S 28 + +/** EFUSE_RD_MAC_SPI_SYS_2_REG register + * BLOCK1 data register 2. + */ +#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c) +/** EFUSE_SPI_PAD_CONFIG_D_1 : R; bitpos: [1:0]; default: 0; + * SPI PAD D(D0) + */ +#define EFUSE_SPI_PAD_CONFIG_D_1 0x00000003U +#define EFUSE_SPI_PAD_CONFIG_D_1_M (EFUSE_SPI_PAD_CONFIG_D_1_V << EFUSE_SPI_PAD_CONFIG_D_1_S) +#define EFUSE_SPI_PAD_CONFIG_D_1_V 0x00000003U +#define EFUSE_SPI_PAD_CONFIG_D_1_S 0 +/** EFUSE_SPI_PAD_CONFIG_CS : R; bitpos: [7:2]; default: 0; + * SPI PAD CS + */ +#define EFUSE_SPI_PAD_CONFIG_CS 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_CS_M (EFUSE_SPI_PAD_CONFIG_CS_V << EFUSE_SPI_PAD_CONFIG_CS_S) +#define EFUSE_SPI_PAD_CONFIG_CS_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_CS_S 2 +/** EFUSE_SPI_PAD_CONFIG_HD : R; bitpos: [13:8]; default: 0; + * SPI PAD HD(D3) + */ +#define EFUSE_SPI_PAD_CONFIG_HD 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_HD_M (EFUSE_SPI_PAD_CONFIG_HD_V << EFUSE_SPI_PAD_CONFIG_HD_S) +#define EFUSE_SPI_PAD_CONFIG_HD_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_HD_S 8 +/** EFUSE_SPI_PAD_CONFIG_WP : R; bitpos: [19:14]; default: 0; + * SPI PAD WP(D2) + */ +#define EFUSE_SPI_PAD_CONFIG_WP 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_WP_M (EFUSE_SPI_PAD_CONFIG_WP_V << EFUSE_SPI_PAD_CONFIG_WP_S) +#define EFUSE_SPI_PAD_CONFIG_WP_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_WP_S 14 +/** EFUSE_SPI_PAD_CONFIG_DQS : R; bitpos: [25:20]; default: 0; + * SPI PAD DQS + */ +#define EFUSE_SPI_PAD_CONFIG_DQS 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_DQS_M (EFUSE_SPI_PAD_CONFIG_DQS_V << EFUSE_SPI_PAD_CONFIG_DQS_S) +#define EFUSE_SPI_PAD_CONFIG_DQS_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_DQS_S 20 +/** EFUSE_SPI_PAD_CONFIG_D4 : R; bitpos: [31:26]; default: 0; + * SPI PAD D4 + */ +#define EFUSE_SPI_PAD_CONFIG_D4 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D4_M (EFUSE_SPI_PAD_CONFIG_D4_V << EFUSE_SPI_PAD_CONFIG_D4_S) +#define EFUSE_SPI_PAD_CONFIG_D4_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D4_S 26 -#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x04C) -/* EFUSE_SPI_PAD_CONF_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first part of SPI_PAD_CONF.*/ -#define EFUSE_SPI_PAD_CONF_1 0xFFFFFFFF -#define EFUSE_SPI_PAD_CONF_1_M ((EFUSE_SPI_PAD_CONF_1_V)<<(EFUSE_SPI_PAD_CONF_1_S)) -#define EFUSE_SPI_PAD_CONF_1_V 0xFFFFFFFF -#define EFUSE_SPI_PAD_CONF_1_S 0 - -#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x050) -/* EFUSE_SYS_DATA_PART0_0 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: Stores the fist 8 bits of the zeroth part of system data.*/ -#define EFUSE_SYS_DATA_PART0_0 0x000000FF -#define EFUSE_SYS_DATA_PART0_0_M ((EFUSE_SYS_DATA_PART0_0_V)<<(EFUSE_SYS_DATA_PART0_0_S)) -#define EFUSE_SYS_DATA_PART0_0_V 0xFF -#define EFUSE_SYS_DATA_PART0_0_S 25 -/* EFUSE_PKG_VERSION : RO ;bitpos:[23:21] ;default: 3'h0 ; */ -/*description: Package version 0:ESP32-C3 */ -#define EFUSE_PKG_VERSION 0x00000007 -#define EFUSE_PKG_VERSION_M ((EFUSE_PKG_VERSION_V)<<(EFUSE_PKG_VERSION_S)) -#define EFUSE_PKG_VERSION_V 0x7 +/** EFUSE_RD_MAC_SPI_SYS_3_REG register + * BLOCK1 data register 3. + */ +#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) +/** EFUSE_SPI_PAD_CONFIG_D5 : R; bitpos: [5:0]; default: 0; + * SPI PAD D5 + */ +#define EFUSE_SPI_PAD_CONFIG_D5 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D5_M (EFUSE_SPI_PAD_CONFIG_D5_V << EFUSE_SPI_PAD_CONFIG_D5_S) +#define EFUSE_SPI_PAD_CONFIG_D5_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D5_S 0 +/** EFUSE_SPI_PAD_CONFIG_D6 : R; bitpos: [11:6]; default: 0; + * SPI PAD D6 + */ +#define EFUSE_SPI_PAD_CONFIG_D6 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D6_M (EFUSE_SPI_PAD_CONFIG_D6_V << EFUSE_SPI_PAD_CONFIG_D6_S) +#define EFUSE_SPI_PAD_CONFIG_D6_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D6_S 6 +/** EFUSE_SPI_PAD_CONFIG_D7 : R; bitpos: [17:12]; default: 0; + * SPI PAD D7 + */ +#define EFUSE_SPI_PAD_CONFIG_D7 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D7_M (EFUSE_SPI_PAD_CONFIG_D7_V << EFUSE_SPI_PAD_CONFIG_D7_S) +#define EFUSE_SPI_PAD_CONFIG_D7_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D7_S 12 +/** EFUSE_WAFER_VERSION_MINOR_LO : R; bitpos: [20:18]; default: 0; + * WAFER_VERSION_MINOR least significant bits + */ +#define EFUSE_WAFER_VERSION_MINOR_LO 0x00000007U +#define EFUSE_WAFER_VERSION_MINOR_LO_M (EFUSE_WAFER_VERSION_MINOR_LO_V << EFUSE_WAFER_VERSION_MINOR_LO_S) +#define EFUSE_WAFER_VERSION_MINOR_LO_V 0x00000007U +#define EFUSE_WAFER_VERSION_MINOR_LO_S 18 +/** EFUSE_PKG_VERSION : R; bitpos: [23:21]; default: 0; + * Package version + */ +#define EFUSE_PKG_VERSION 0x00000007U +#define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S) +#define EFUSE_PKG_VERSION_V 0x00000007U #define EFUSE_PKG_VERSION_S 21 -/* EFUSE_WAFER_VERSION : RO ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: WAFER version 0:A */ -#define EFUSE_WAFER_VERSION 0x00000007 -#define EFUSE_WAFER_VERSION_M ((EFUSE_WAFER_VERSION_V)<<(EFUSE_WAFER_VERSION_S)) -#define EFUSE_WAFER_VERSION_V 0x7 -#define EFUSE_WAFER_VERSION_S 18 -/* EFUSE_SPI_PAD_CONF_2 : RO ;bitpos:[17:0] ;default: 18'h0 ; */ -/*description: Stores the second part of SPI_PAD_CONF.*/ -#define EFUSE_SPI_PAD_CONF_2 0x0003FFFF -#define EFUSE_SPI_PAD_CONF_2_M ((EFUSE_SPI_PAD_CONF_2_V)<<(EFUSE_SPI_PAD_CONF_2_S)) -#define EFUSE_SPI_PAD_CONF_2_V 0x3FFFF -#define EFUSE_SPI_PAD_CONF_2_S 0 - -#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x054) -/* EFUSE_SYS_DATA_PART0_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fist 32 bits of the zeroth part of system data.*/ -#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_1_M ((EFUSE_SYS_DATA_PART0_1_V)<<(EFUSE_SYS_DATA_PART0_1_S)) -#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_1_S 0 - -#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x058) -/* EFUSE_SYS_DATA_PART0_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of the zeroth part of system data.*/ -#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_2_M ((EFUSE_SYS_DATA_PART0_2_V)<<(EFUSE_SYS_DATA_PART0_2_S)) -#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_2_S 0 - -#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x05C) -/* EFUSE_SYS_DATA_PART1_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_0_M ((EFUSE_SYS_DATA_PART1_0_V)<<(EFUSE_SYS_DATA_PART1_0_S)) -#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_0_S 0 - -#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x060) -/* EFUSE_SYS_DATA_PART1_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_1_M ((EFUSE_SYS_DATA_PART1_1_V)<<(EFUSE_SYS_DATA_PART1_1_S)) -#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_1_S 0 - -#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x064) -/* EFUSE_SYS_DATA_PART1_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_2_M ((EFUSE_SYS_DATA_PART1_2_V)<<(EFUSE_SYS_DATA_PART1_2_S)) -#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_2_S 0 - -#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x068) -/* EFUSE_SYS_DATA_PART1_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_3_M ((EFUSE_SYS_DATA_PART1_3_V)<<(EFUSE_SYS_DATA_PART1_3_S)) -#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_3_S 0 - -#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x06C) -/* EFUSE_SYS_DATA_PART1_4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_4_M ((EFUSE_SYS_DATA_PART1_4_V)<<(EFUSE_SYS_DATA_PART1_4_S)) -#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_4_S 0 - -#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x070) -/* EFUSE_SYS_DATA_PART1_5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_5_M ((EFUSE_SYS_DATA_PART1_5_V)<<(EFUSE_SYS_DATA_PART1_5_S)) -#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_5_S 0 - -#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x074) -/* EFUSE_SYS_DATA_PART1_6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_6_M ((EFUSE_SYS_DATA_PART1_6_V)<<(EFUSE_SYS_DATA_PART1_6_S)) -#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_6_S 0 - -#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x078) -/* EFUSE_SYS_DATA_PART1_7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_7_M ((EFUSE_SYS_DATA_PART1_7_V)<<(EFUSE_SYS_DATA_PART1_7_S)) -#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_7_S 0 - -#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x07C) -/* EFUSE_USR_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA0 0xFFFFFFFF -#define EFUSE_USR_DATA0_M ((EFUSE_USR_DATA0_V)<<(EFUSE_USR_DATA0_S)) -#define EFUSE_USR_DATA0_V 0xFFFFFFFF +/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [26:24]; default: 0; + * BLK_VERSION_MINOR + */ +#define EFUSE_BLK_VERSION_MINOR 0x00000007U +#define EFUSE_BLK_VERSION_MINOR_M (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S) +#define EFUSE_BLK_VERSION_MINOR_V 0x00000007U +#define EFUSE_BLK_VERSION_MINOR_S 24 +/** EFUSE_RESERVED_1_123 : R; bitpos: [31:27]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_1_123 0x0000001FU +#define EFUSE_RESERVED_1_123_M (EFUSE_RESERVED_1_123_V << EFUSE_RESERVED_1_123_S) +#define EFUSE_RESERVED_1_123_V 0x0000001FU +#define EFUSE_RESERVED_1_123_S 27 + +/** EFUSE_RD_MAC_SPI_SYS_4_REG register + * BLOCK1 data register 4. + */ +#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) +/** EFUSE_RESERVED_1_128 : R; bitpos: [6:0]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_1_128 0x0000007FU +#define EFUSE_RESERVED_1_128_M (EFUSE_RESERVED_1_128_V << EFUSE_RESERVED_1_128_S) +#define EFUSE_RESERVED_1_128_V 0x0000007FU +#define EFUSE_RESERVED_1_128_S 0 +/** EFUSE_K_RTC_LDO : R; bitpos: [13:7]; default: 0; + * BLOCK1 K_RTC_LDO + */ +#define EFUSE_K_RTC_LDO 0x0000007FU +#define EFUSE_K_RTC_LDO_M (EFUSE_K_RTC_LDO_V << EFUSE_K_RTC_LDO_S) +#define EFUSE_K_RTC_LDO_V 0x0000007FU +#define EFUSE_K_RTC_LDO_S 7 +/** EFUSE_K_DIG_LDO : R; bitpos: [20:14]; default: 0; + * BLOCK1 K_DIG_LDO + */ +#define EFUSE_K_DIG_LDO 0x0000007FU +#define EFUSE_K_DIG_LDO_M (EFUSE_K_DIG_LDO_V << EFUSE_K_DIG_LDO_S) +#define EFUSE_K_DIG_LDO_V 0x0000007FU +#define EFUSE_K_DIG_LDO_S 14 +/** EFUSE_V_RTC_DBIAS20 : R; bitpos: [28:21]; default: 0; + * BLOCK1 voltage of rtc dbias20 + */ +#define EFUSE_V_RTC_DBIAS20 0x000000FFU +#define EFUSE_V_RTC_DBIAS20_M (EFUSE_V_RTC_DBIAS20_V << EFUSE_V_RTC_DBIAS20_S) +#define EFUSE_V_RTC_DBIAS20_V 0x000000FFU +#define EFUSE_V_RTC_DBIAS20_S 21 +/** EFUSE_V_DIG_DBIAS20 : R; bitpos: [31:29]; default: 0; + * BLOCK1 voltage of digital dbias20 + */ +#define EFUSE_V_DIG_DBIAS20 0x00000007U +#define EFUSE_V_DIG_DBIAS20_M (EFUSE_V_DIG_DBIAS20_V << EFUSE_V_DIG_DBIAS20_S) +#define EFUSE_V_DIG_DBIAS20_V 0x00000007U +#define EFUSE_V_DIG_DBIAS20_S 29 + +/** EFUSE_RD_MAC_SPI_SYS_5_REG register + * BLOCK1 data register 5. + */ +#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58) +/** EFUSE_V_DIG_DBIAS20_1 : R; bitpos: [4:0]; default: 0; + * BLOCK1 voltage of digital dbias20 + */ +#define EFUSE_V_DIG_DBIAS20_1 0x0000001FU +#define EFUSE_V_DIG_DBIAS20_1_M (EFUSE_V_DIG_DBIAS20_1_V << EFUSE_V_DIG_DBIAS20_1_S) +#define EFUSE_V_DIG_DBIAS20_1_V 0x0000001FU +#define EFUSE_V_DIG_DBIAS20_1_S 0 +/** EFUSE_DIG_DBIAS_HVT : R; bitpos: [9:5]; default: 0; + * BLOCK1 digital dbias when hvt + */ +#define EFUSE_DIG_DBIAS_HVT 0x0000001FU +#define EFUSE_DIG_DBIAS_HVT_M (EFUSE_DIG_DBIAS_HVT_V << EFUSE_DIG_DBIAS_HVT_S) +#define EFUSE_DIG_DBIAS_HVT_V 0x0000001FU +#define EFUSE_DIG_DBIAS_HVT_S 5 +/** EFUSE_THRES_HVT : R; bitpos: [19:10]; default: 0; + * BLOCK1 pvt threshold when hvt + */ +#define EFUSE_THRES_HVT 0x000003FFU +#define EFUSE_THRES_HVT_M (EFUSE_THRES_HVT_V << EFUSE_THRES_HVT_S) +#define EFUSE_THRES_HVT_V 0x000003FFU +#define EFUSE_THRES_HVT_S 10 +/** EFUSE_RESERVED_1_180 : R; bitpos: [22:20]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_1_180 0x00000007U +#define EFUSE_RESERVED_1_180_M (EFUSE_RESERVED_1_180_V << EFUSE_RESERVED_1_180_S) +#define EFUSE_RESERVED_1_180_V 0x00000007U +#define EFUSE_RESERVED_1_180_S 20 +/** EFUSE_WAFER_VERSION_MINOR_HI : R; bitpos: [23]; default: 0; + * WAFER_VERSION_MINOR most significant bit + */ +#define EFUSE_WAFER_VERSION_MINOR_HI (BIT(23)) +#define EFUSE_WAFER_VERSION_MINOR_HI_M (EFUSE_WAFER_VERSION_MINOR_HI_V << EFUSE_WAFER_VERSION_MINOR_HI_S) +#define EFUSE_WAFER_VERSION_MINOR_HI_V 0x00000001U +#define EFUSE_WAFER_VERSION_MINOR_HI_S 23 +/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [25:24]; default: 0; + * WAFER_VERSION_MAJOR + */ +#define EFUSE_WAFER_VERSION_MAJOR 0x00000003U +#define EFUSE_WAFER_VERSION_MAJOR_M (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S) +#define EFUSE_WAFER_VERSION_MAJOR_V 0x00000003U +#define EFUSE_WAFER_VERSION_MAJOR_S 24 +/** EFUSE_RESERVED_1_186 : R; bitpos: [31:26]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_1_186 0x0000003FU +#define EFUSE_RESERVED_1_186_M (EFUSE_RESERVED_1_186_V << EFUSE_RESERVED_1_186_S) +#define EFUSE_RESERVED_1_186_V 0x0000003FU +#define EFUSE_RESERVED_1_186_S 26 + +/** EFUSE_RD_SYS_PART1_DATA0_REG register + * Register 0 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c) +/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ +#define EFUSE_OPTIONAL_UNIQUE_ID 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_M (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_S 0 + +/** EFUSE_RD_SYS_PART1_DATA1_REG register + * Register 1 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60) +/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ +#define EFUSE_OPTIONAL_UNIQUE_ID_1 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_1_M (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_1_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_1_S 0 + +/** EFUSE_RD_SYS_PART1_DATA2_REG register + * Register 2 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64) +/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ +#define EFUSE_OPTIONAL_UNIQUE_ID_2 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_2_M (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_2_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_2_S 0 + +/** EFUSE_RD_SYS_PART1_DATA3_REG register + * Register 3 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68) +/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ +#define EFUSE_OPTIONAL_UNIQUE_ID_3 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_3_M (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_3_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_3_S 0 + +/** EFUSE_RD_SYS_PART1_DATA4_REG register + * Register 4 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c) +/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [1:0]; default: 0; + * BLK_VERSION_MAJOR of BLOCK2 + */ +#define EFUSE_BLK_VERSION_MAJOR 0x00000003U +#define EFUSE_BLK_VERSION_MAJOR_M (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S) +#define EFUSE_BLK_VERSION_MAJOR_V 0x00000003U +#define EFUSE_BLK_VERSION_MAJOR_S 0 +/** EFUSE_RESERVED_2_130 : R; bitpos: [2]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_2_130 (BIT(2)) +#define EFUSE_RESERVED_2_130_M (EFUSE_RESERVED_2_130_V << EFUSE_RESERVED_2_130_S) +#define EFUSE_RESERVED_2_130_V 0x00000001U +#define EFUSE_RESERVED_2_130_S 2 +/** EFUSE_TEMP_CALIB : R; bitpos: [11:3]; default: 0; + * Temperature calibration data + */ +#define EFUSE_TEMP_CALIB 0x000001FFU +#define EFUSE_TEMP_CALIB_M (EFUSE_TEMP_CALIB_V << EFUSE_TEMP_CALIB_S) +#define EFUSE_TEMP_CALIB_V 0x000001FFU +#define EFUSE_TEMP_CALIB_S 3 +/** EFUSE_OCODE : R; bitpos: [19:12]; default: 0; + * ADC OCode + */ +#define EFUSE_OCODE 0x000000FFU +#define EFUSE_OCODE_M (EFUSE_OCODE_V << EFUSE_OCODE_S) +#define EFUSE_OCODE_V 0x000000FFU +#define EFUSE_OCODE_S 12 +/** EFUSE_ADC1_INIT_CODE_ATTEN0 : R; bitpos: [29:20]; default: 0; + * ADC1 init code at atten0 + */ +#define EFUSE_ADC1_INIT_CODE_ATTEN0 0x000003FFU +#define EFUSE_ADC1_INIT_CODE_ATTEN0_M (EFUSE_ADC1_INIT_CODE_ATTEN0_V << EFUSE_ADC1_INIT_CODE_ATTEN0_S) +#define EFUSE_ADC1_INIT_CODE_ATTEN0_V 0x000003FFU +#define EFUSE_ADC1_INIT_CODE_ATTEN0_S 20 +/** EFUSE_ADC1_INIT_CODE_ATTEN1 : R; bitpos: [31:30]; default: 0; + * ADC1 init code at atten1 + */ +#define EFUSE_ADC1_INIT_CODE_ATTEN1 0x00000003U +#define EFUSE_ADC1_INIT_CODE_ATTEN1_M (EFUSE_ADC1_INIT_CODE_ATTEN1_V << EFUSE_ADC1_INIT_CODE_ATTEN1_S) +#define EFUSE_ADC1_INIT_CODE_ATTEN1_V 0x00000003U +#define EFUSE_ADC1_INIT_CODE_ATTEN1_S 30 + +/** EFUSE_RD_SYS_PART1_DATA5_REG register + * Register 5 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70) +/** EFUSE_ADC1_INIT_CODE_ATTEN1_1 : R; bitpos: [7:0]; default: 0; + * ADC1 init code at atten1 + */ +#define EFUSE_ADC1_INIT_CODE_ATTEN1_1 0x000000FFU +#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_M (EFUSE_ADC1_INIT_CODE_ATTEN1_1_V << EFUSE_ADC1_INIT_CODE_ATTEN1_1_S) +#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_V 0x000000FFU +#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_S 0 +/** EFUSE_ADC1_INIT_CODE_ATTEN2 : R; bitpos: [17:8]; default: 0; + * ADC1 init code at atten2 + */ +#define EFUSE_ADC1_INIT_CODE_ATTEN2 0x000003FFU +#define EFUSE_ADC1_INIT_CODE_ATTEN2_M (EFUSE_ADC1_INIT_CODE_ATTEN2_V << EFUSE_ADC1_INIT_CODE_ATTEN2_S) +#define EFUSE_ADC1_INIT_CODE_ATTEN2_V 0x000003FFU +#define EFUSE_ADC1_INIT_CODE_ATTEN2_S 8 +/** EFUSE_ADC1_INIT_CODE_ATTEN3 : R; bitpos: [27:18]; default: 0; + * ADC1 init code at atten3 + */ +#define EFUSE_ADC1_INIT_CODE_ATTEN3 0x000003FFU +#define EFUSE_ADC1_INIT_CODE_ATTEN3_M (EFUSE_ADC1_INIT_CODE_ATTEN3_V << EFUSE_ADC1_INIT_CODE_ATTEN3_S) +#define EFUSE_ADC1_INIT_CODE_ATTEN3_V 0x000003FFU +#define EFUSE_ADC1_INIT_CODE_ATTEN3_S 18 +/** EFUSE_ADC1_CAL_VOL_ATTEN0 : R; bitpos: [31:28]; default: 0; + * ADC1 calibration voltage at atten0 + */ +#define EFUSE_ADC1_CAL_VOL_ATTEN0 0x0000000FU +#define EFUSE_ADC1_CAL_VOL_ATTEN0_M (EFUSE_ADC1_CAL_VOL_ATTEN0_V << EFUSE_ADC1_CAL_VOL_ATTEN0_S) +#define EFUSE_ADC1_CAL_VOL_ATTEN0_V 0x0000000FU +#define EFUSE_ADC1_CAL_VOL_ATTEN0_S 28 + +/** EFUSE_RD_SYS_PART1_DATA6_REG register + * Register 6 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74) +/** EFUSE_ADC1_CAL_VOL_ATTEN0_1 : R; bitpos: [5:0]; default: 0; + * ADC1 calibration voltage at atten0 + */ +#define EFUSE_ADC1_CAL_VOL_ATTEN0_1 0x0000003FU +#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_M (EFUSE_ADC1_CAL_VOL_ATTEN0_1_V << EFUSE_ADC1_CAL_VOL_ATTEN0_1_S) +#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_V 0x0000003FU +#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_S 0 +/** EFUSE_ADC1_CAL_VOL_ATTEN1 : R; bitpos: [15:6]; default: 0; + * ADC1 calibration voltage at atten1 + */ +#define EFUSE_ADC1_CAL_VOL_ATTEN1 0x000003FFU +#define EFUSE_ADC1_CAL_VOL_ATTEN1_M (EFUSE_ADC1_CAL_VOL_ATTEN1_V << EFUSE_ADC1_CAL_VOL_ATTEN1_S) +#define EFUSE_ADC1_CAL_VOL_ATTEN1_V 0x000003FFU +#define EFUSE_ADC1_CAL_VOL_ATTEN1_S 6 +/** EFUSE_ADC1_CAL_VOL_ATTEN2 : R; bitpos: [25:16]; default: 0; + * ADC1 calibration voltage at atten2 + */ +#define EFUSE_ADC1_CAL_VOL_ATTEN2 0x000003FFU +#define EFUSE_ADC1_CAL_VOL_ATTEN2_M (EFUSE_ADC1_CAL_VOL_ATTEN2_V << EFUSE_ADC1_CAL_VOL_ATTEN2_S) +#define EFUSE_ADC1_CAL_VOL_ATTEN2_V 0x000003FFU +#define EFUSE_ADC1_CAL_VOL_ATTEN2_S 16 +/** EFUSE_ADC1_CAL_VOL_ATTEN3 : R; bitpos: [31:26]; default: 0; + * ADC1 calibration voltage at atten3 + */ +#define EFUSE_ADC1_CAL_VOL_ATTEN3 0x0000003FU +#define EFUSE_ADC1_CAL_VOL_ATTEN3_M (EFUSE_ADC1_CAL_VOL_ATTEN3_V << EFUSE_ADC1_CAL_VOL_ATTEN3_S) +#define EFUSE_ADC1_CAL_VOL_ATTEN3_V 0x0000003FU +#define EFUSE_ADC1_CAL_VOL_ATTEN3_S 26 + +/** EFUSE_RD_SYS_PART1_DATA7_REG register + * Register 7 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78) +/** EFUSE_ADC1_CAL_VOL_ATTEN3_1 : R; bitpos: [3:0]; default: 0; + * ADC1 calibration voltage at atten3 + */ +#define EFUSE_ADC1_CAL_VOL_ATTEN3_1 0x0000000FU +#define EFUSE_ADC1_CAL_VOL_ATTEN3_1_M (EFUSE_ADC1_CAL_VOL_ATTEN3_1_V << EFUSE_ADC1_CAL_VOL_ATTEN3_1_S) +#define EFUSE_ADC1_CAL_VOL_ATTEN3_1_V 0x0000000FU +#define EFUSE_ADC1_CAL_VOL_ATTEN3_1_S 0 +/** EFUSE_RESERVED_2_228 : R; bitpos: [31:4]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_2_228 0x0FFFFFFFU +#define EFUSE_RESERVED_2_228_M (EFUSE_RESERVED_2_228_V << EFUSE_RESERVED_2_228_S) +#define EFUSE_RESERVED_2_228_V 0x0FFFFFFFU +#define EFUSE_RESERVED_2_228_S 4 + +/** EFUSE_RD_USR_DATA0_REG register + * Register 0 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c) +/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA0 0xFFFFFFFFU +#define EFUSE_USR_DATA0_M (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S) +#define EFUSE_USR_DATA0_V 0xFFFFFFFFU #define EFUSE_USR_DATA0_S 0 -#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x080) -/* EFUSE_USR_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA1 0xFFFFFFFF -#define EFUSE_USR_DATA1_M ((EFUSE_USR_DATA1_V)<<(EFUSE_USR_DATA1_S)) -#define EFUSE_USR_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA1_REG register + * Register 1 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) +/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA1 0xFFFFFFFFU +#define EFUSE_USR_DATA1_M (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S) +#define EFUSE_USR_DATA1_V 0xFFFFFFFFU #define EFUSE_USR_DATA1_S 0 -#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x084) -/* EFUSE_USR_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA2 0xFFFFFFFF -#define EFUSE_USR_DATA2_M ((EFUSE_USR_DATA2_V)<<(EFUSE_USR_DATA2_S)) -#define EFUSE_USR_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA2_REG register + * Register 2 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) +/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA2 0xFFFFFFFFU +#define EFUSE_USR_DATA2_M (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S) +#define EFUSE_USR_DATA2_V 0xFFFFFFFFU #define EFUSE_USR_DATA2_S 0 -#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x088) -/* EFUSE_USR_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA3 0xFFFFFFFF -#define EFUSE_USR_DATA3_M ((EFUSE_USR_DATA3_V)<<(EFUSE_USR_DATA3_S)) -#define EFUSE_USR_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA3_REG register + * Register 3 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) +/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA3 0xFFFFFFFFU +#define EFUSE_USR_DATA3_M (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S) +#define EFUSE_USR_DATA3_V 0xFFFFFFFFU #define EFUSE_USR_DATA3_S 0 -#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x08C) -/* EFUSE_USR_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA4 0xFFFFFFFF -#define EFUSE_USR_DATA4_M ((EFUSE_USR_DATA4_V)<<(EFUSE_USR_DATA4_S)) -#define EFUSE_USR_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA4_REG register + * Register 4 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c) +/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA4 0xFFFFFFFFU +#define EFUSE_USR_DATA4_M (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S) +#define EFUSE_USR_DATA4_V 0xFFFFFFFFU #define EFUSE_USR_DATA4_S 0 -#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x090) -/* EFUSE_USR_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA5 0xFFFFFFFF -#define EFUSE_USR_DATA5_M ((EFUSE_USR_DATA5_V)<<(EFUSE_USR_DATA5_S)) -#define EFUSE_USR_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA5_REG register + * Register 5 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) +/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA5 0xFFFFFFFFU +#define EFUSE_USR_DATA5_M (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S) +#define EFUSE_USR_DATA5_V 0xFFFFFFFFU #define EFUSE_USR_DATA5_S 0 -#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x094) -/* EFUSE_USR_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA6 0xFFFFFFFF -#define EFUSE_USR_DATA6_M ((EFUSE_USR_DATA6_V)<<(EFUSE_USR_DATA6_S)) -#define EFUSE_USR_DATA6_V 0xFFFFFFFF -#define EFUSE_USR_DATA6_S 0 - -#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x098) -/* EFUSE_USR_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA7 0xFFFFFFFF -#define EFUSE_USR_DATA7_M ((EFUSE_USR_DATA7_V)<<(EFUSE_USR_DATA7_S)) -#define EFUSE_USR_DATA7_V 0xFFFFFFFF -#define EFUSE_USR_DATA7_S 0 - -#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x09C) -/* EFUSE_KEY0_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA0 0xFFFFFFFF -#define EFUSE_KEY0_DATA0_M ((EFUSE_KEY0_DATA0_V)<<(EFUSE_KEY0_DATA0_S)) -#define EFUSE_KEY0_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA6_REG register + * Register 6 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) +/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_3_192 0x000000FFU +#define EFUSE_RESERVED_3_192_M (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S) +#define EFUSE_RESERVED_3_192_V 0x000000FFU +#define EFUSE_RESERVED_3_192_S 0 +/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0; + * Custom MAC address + */ +#define EFUSE_CUSTOM_MAC 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_M (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S) +#define EFUSE_CUSTOM_MAC_V 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_S 8 + +/** EFUSE_RD_USR_DATA7_REG register + * Register 7 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) +/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0; + * Custom MAC address + */ +#define EFUSE_CUSTOM_MAC_1 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_1_M (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S) +#define EFUSE_CUSTOM_MAC_1_V 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_1_S 0 +/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_3_248 0x000000FFU +#define EFUSE_RESERVED_3_248_M (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S) +#define EFUSE_RESERVED_3_248_V 0x000000FFU +#define EFUSE_RESERVED_3_248_S 24 + +/** EFUSE_RD_KEY0_DATA0_REG register + * Register 0 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c) +/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA0 0xFFFFFFFFU +#define EFUSE_KEY0_DATA0_M (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S) +#define EFUSE_KEY0_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA0_S 0 -#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0x0A0) -/* EFUSE_KEY0_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA1 0xFFFFFFFF -#define EFUSE_KEY0_DATA1_M ((EFUSE_KEY0_DATA1_V)<<(EFUSE_KEY0_DATA1_S)) -#define EFUSE_KEY0_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA1_REG register + * Register 1 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0) +/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA1 0xFFFFFFFFU +#define EFUSE_KEY0_DATA1_M (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S) +#define EFUSE_KEY0_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA1_S 0 -#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0x0A4) -/* EFUSE_KEY0_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA2 0xFFFFFFFF -#define EFUSE_KEY0_DATA2_M ((EFUSE_KEY0_DATA2_V)<<(EFUSE_KEY0_DATA2_S)) -#define EFUSE_KEY0_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA2_REG register + * Register 2 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4) +/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA2 0xFFFFFFFFU +#define EFUSE_KEY0_DATA2_M (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S) +#define EFUSE_KEY0_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA2_S 0 -#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0x0A8) -/* EFUSE_KEY0_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA3 0xFFFFFFFF -#define EFUSE_KEY0_DATA3_M ((EFUSE_KEY0_DATA3_V)<<(EFUSE_KEY0_DATA3_S)) -#define EFUSE_KEY0_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA3_REG register + * Register 3 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8) +/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA3 0xFFFFFFFFU +#define EFUSE_KEY0_DATA3_M (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S) +#define EFUSE_KEY0_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA3_S 0 -#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0x0AC) -/* EFUSE_KEY0_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA4 0xFFFFFFFF -#define EFUSE_KEY0_DATA4_M ((EFUSE_KEY0_DATA4_V)<<(EFUSE_KEY0_DATA4_S)) -#define EFUSE_KEY0_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA4_REG register + * Register 4 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac) +/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA4 0xFFFFFFFFU +#define EFUSE_KEY0_DATA4_M (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S) +#define EFUSE_KEY0_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA4_S 0 -#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0x0B0) -/* EFUSE_KEY0_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA5 0xFFFFFFFF -#define EFUSE_KEY0_DATA5_M ((EFUSE_KEY0_DATA5_V)<<(EFUSE_KEY0_DATA5_S)) -#define EFUSE_KEY0_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA5_REG register + * Register 5 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0) +/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA5 0xFFFFFFFFU +#define EFUSE_KEY0_DATA5_M (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S) +#define EFUSE_KEY0_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA5_S 0 -#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0x0B4) -/* EFUSE_KEY0_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA6 0xFFFFFFFF -#define EFUSE_KEY0_DATA6_M ((EFUSE_KEY0_DATA6_V)<<(EFUSE_KEY0_DATA6_S)) -#define EFUSE_KEY0_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA6_REG register + * Register 6 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4) +/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA6 0xFFFFFFFFU +#define EFUSE_KEY0_DATA6_M (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S) +#define EFUSE_KEY0_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA6_S 0 -#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0x0B8) -/* EFUSE_KEY0_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA7 0xFFFFFFFF -#define EFUSE_KEY0_DATA7_M ((EFUSE_KEY0_DATA7_V)<<(EFUSE_KEY0_DATA7_S)) -#define EFUSE_KEY0_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA7_REG register + * Register 7 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8) +/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA7 0xFFFFFFFFU +#define EFUSE_KEY0_DATA7_M (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S) +#define EFUSE_KEY0_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA7_S 0 -#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0x0BC) -/* EFUSE_KEY1_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA0 0xFFFFFFFF -#define EFUSE_KEY1_DATA0_M ((EFUSE_KEY1_DATA0_V)<<(EFUSE_KEY1_DATA0_S)) -#define EFUSE_KEY1_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA0_REG register + * Register 0 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc) +/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA0 0xFFFFFFFFU +#define EFUSE_KEY1_DATA0_M (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S) +#define EFUSE_KEY1_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA0_S 0 -#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0x0C0) -/* EFUSE_KEY1_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA1 0xFFFFFFFF -#define EFUSE_KEY1_DATA1_M ((EFUSE_KEY1_DATA1_V)<<(EFUSE_KEY1_DATA1_S)) -#define EFUSE_KEY1_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA1_REG register + * Register 1 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0) +/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA1 0xFFFFFFFFU +#define EFUSE_KEY1_DATA1_M (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S) +#define EFUSE_KEY1_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA1_S 0 -#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0x0C4) -/* EFUSE_KEY1_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA2 0xFFFFFFFF -#define EFUSE_KEY1_DATA2_M ((EFUSE_KEY1_DATA2_V)<<(EFUSE_KEY1_DATA2_S)) -#define EFUSE_KEY1_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA2_REG register + * Register 2 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4) +/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA2 0xFFFFFFFFU +#define EFUSE_KEY1_DATA2_M (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S) +#define EFUSE_KEY1_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA2_S 0 -#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0x0C8) -/* EFUSE_KEY1_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA3 0xFFFFFFFF -#define EFUSE_KEY1_DATA3_M ((EFUSE_KEY1_DATA3_V)<<(EFUSE_KEY1_DATA3_S)) -#define EFUSE_KEY1_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA3_REG register + * Register 3 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8) +/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA3 0xFFFFFFFFU +#define EFUSE_KEY1_DATA3_M (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S) +#define EFUSE_KEY1_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA3_S 0 -#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0x0CC) -/* EFUSE_KEY1_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA4 0xFFFFFFFF -#define EFUSE_KEY1_DATA4_M ((EFUSE_KEY1_DATA4_V)<<(EFUSE_KEY1_DATA4_S)) -#define EFUSE_KEY1_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA4_REG register + * Register 4 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc) +/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA4 0xFFFFFFFFU +#define EFUSE_KEY1_DATA4_M (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S) +#define EFUSE_KEY1_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA4_S 0 -#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0x0D0) -/* EFUSE_KEY1_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA5 0xFFFFFFFF -#define EFUSE_KEY1_DATA5_M ((EFUSE_KEY1_DATA5_V)<<(EFUSE_KEY1_DATA5_S)) -#define EFUSE_KEY1_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA5_REG register + * Register 5 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0) +/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA5 0xFFFFFFFFU +#define EFUSE_KEY1_DATA5_M (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S) +#define EFUSE_KEY1_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA5_S 0 -#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0x0D4) -/* EFUSE_KEY1_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA6 0xFFFFFFFF -#define EFUSE_KEY1_DATA6_M ((EFUSE_KEY1_DATA6_V)<<(EFUSE_KEY1_DATA6_S)) -#define EFUSE_KEY1_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA6_REG register + * Register 6 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4) +/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA6 0xFFFFFFFFU +#define EFUSE_KEY1_DATA6_M (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S) +#define EFUSE_KEY1_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA6_S 0 -#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0x0D8) -/* EFUSE_KEY1_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA7 0xFFFFFFFF -#define EFUSE_KEY1_DATA7_M ((EFUSE_KEY1_DATA7_V)<<(EFUSE_KEY1_DATA7_S)) -#define EFUSE_KEY1_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA7_REG register + * Register 7 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8) +/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA7 0xFFFFFFFFU +#define EFUSE_KEY1_DATA7_M (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S) +#define EFUSE_KEY1_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA7_S 0 -#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0x0DC) -/* EFUSE_KEY2_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA0 0xFFFFFFFF -#define EFUSE_KEY2_DATA0_M ((EFUSE_KEY2_DATA0_V)<<(EFUSE_KEY2_DATA0_S)) -#define EFUSE_KEY2_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA0_REG register + * Register 0 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc) +/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA0 0xFFFFFFFFU +#define EFUSE_KEY2_DATA0_M (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S) +#define EFUSE_KEY2_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA0_S 0 -#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0x0E0) -/* EFUSE_KEY2_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA1 0xFFFFFFFF -#define EFUSE_KEY2_DATA1_M ((EFUSE_KEY2_DATA1_V)<<(EFUSE_KEY2_DATA1_S)) -#define EFUSE_KEY2_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA1_REG register + * Register 1 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0) +/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA1 0xFFFFFFFFU +#define EFUSE_KEY2_DATA1_M (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S) +#define EFUSE_KEY2_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA1_S 0 -#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0x0E4) -/* EFUSE_KEY2_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA2 0xFFFFFFFF -#define EFUSE_KEY2_DATA2_M ((EFUSE_KEY2_DATA2_V)<<(EFUSE_KEY2_DATA2_S)) -#define EFUSE_KEY2_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA2_REG register + * Register 2 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4) +/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA2 0xFFFFFFFFU +#define EFUSE_KEY2_DATA2_M (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S) +#define EFUSE_KEY2_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA2_S 0 -#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0x0E8) -/* EFUSE_KEY2_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA3 0xFFFFFFFF -#define EFUSE_KEY2_DATA3_M ((EFUSE_KEY2_DATA3_V)<<(EFUSE_KEY2_DATA3_S)) -#define EFUSE_KEY2_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA3_REG register + * Register 3 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8) +/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA3 0xFFFFFFFFU +#define EFUSE_KEY2_DATA3_M (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S) +#define EFUSE_KEY2_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA3_S 0 -#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0x0EC) -/* EFUSE_KEY2_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA4 0xFFFFFFFF -#define EFUSE_KEY2_DATA4_M ((EFUSE_KEY2_DATA4_V)<<(EFUSE_KEY2_DATA4_S)) -#define EFUSE_KEY2_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA4_REG register + * Register 4 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec) +/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA4 0xFFFFFFFFU +#define EFUSE_KEY2_DATA4_M (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S) +#define EFUSE_KEY2_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA4_S 0 -#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0x0F0) -/* EFUSE_KEY2_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA5 0xFFFFFFFF -#define EFUSE_KEY2_DATA5_M ((EFUSE_KEY2_DATA5_V)<<(EFUSE_KEY2_DATA5_S)) -#define EFUSE_KEY2_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA5_REG register + * Register 5 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0) +/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA5 0xFFFFFFFFU +#define EFUSE_KEY2_DATA5_M (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S) +#define EFUSE_KEY2_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA5_S 0 -#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0x0F4) -/* EFUSE_KEY2_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA6 0xFFFFFFFF -#define EFUSE_KEY2_DATA6_M ((EFUSE_KEY2_DATA6_V)<<(EFUSE_KEY2_DATA6_S)) -#define EFUSE_KEY2_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA6_REG register + * Register 6 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4) +/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA6 0xFFFFFFFFU +#define EFUSE_KEY2_DATA6_M (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S) +#define EFUSE_KEY2_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA6_S 0 -#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0x0F8) -/* EFUSE_KEY2_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA7 0xFFFFFFFF -#define EFUSE_KEY2_DATA7_M ((EFUSE_KEY2_DATA7_V)<<(EFUSE_KEY2_DATA7_S)) -#define EFUSE_KEY2_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA7_REG register + * Register 7 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8) +/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA7 0xFFFFFFFFU +#define EFUSE_KEY2_DATA7_M (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S) +#define EFUSE_KEY2_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA7_S 0 -#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0x0FC) -/* EFUSE_KEY3_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA0 0xFFFFFFFF -#define EFUSE_KEY3_DATA0_M ((EFUSE_KEY3_DATA0_V)<<(EFUSE_KEY3_DATA0_S)) -#define EFUSE_KEY3_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA0_REG register + * Register 0 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc) +/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA0 0xFFFFFFFFU +#define EFUSE_KEY3_DATA0_M (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S) +#define EFUSE_KEY3_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA0_S 0 -#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) -/* EFUSE_KEY3_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA1 0xFFFFFFFF -#define EFUSE_KEY3_DATA1_M ((EFUSE_KEY3_DATA1_V)<<(EFUSE_KEY3_DATA1_S)) -#define EFUSE_KEY3_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA1_REG register + * Register 1 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) +/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA1 0xFFFFFFFFU +#define EFUSE_KEY3_DATA1_M (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S) +#define EFUSE_KEY3_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA1_S 0 -#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) -/* EFUSE_KEY3_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA2 0xFFFFFFFF -#define EFUSE_KEY3_DATA2_M ((EFUSE_KEY3_DATA2_V)<<(EFUSE_KEY3_DATA2_S)) -#define EFUSE_KEY3_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA2_REG register + * Register 2 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) +/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA2 0xFFFFFFFFU +#define EFUSE_KEY3_DATA2_M (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S) +#define EFUSE_KEY3_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA2_S 0 -#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) -/* EFUSE_KEY3_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA3 0xFFFFFFFF -#define EFUSE_KEY3_DATA3_M ((EFUSE_KEY3_DATA3_V)<<(EFUSE_KEY3_DATA3_S)) -#define EFUSE_KEY3_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA3_REG register + * Register 3 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) +/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA3 0xFFFFFFFFU +#define EFUSE_KEY3_DATA3_M (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S) +#define EFUSE_KEY3_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA3_S 0 -#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10C) -/* EFUSE_KEY3_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA4 0xFFFFFFFF -#define EFUSE_KEY3_DATA4_M ((EFUSE_KEY3_DATA4_V)<<(EFUSE_KEY3_DATA4_S)) -#define EFUSE_KEY3_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA4_REG register + * Register 4 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c) +/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA4 0xFFFFFFFFU +#define EFUSE_KEY3_DATA4_M (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S) +#define EFUSE_KEY3_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA4_S 0 -#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) -/* EFUSE_KEY3_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA5 0xFFFFFFFF -#define EFUSE_KEY3_DATA5_M ((EFUSE_KEY3_DATA5_V)<<(EFUSE_KEY3_DATA5_S)) -#define EFUSE_KEY3_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA5_REG register + * Register 5 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) +/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA5 0xFFFFFFFFU +#define EFUSE_KEY3_DATA5_M (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S) +#define EFUSE_KEY3_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA5_S 0 -#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) -/* EFUSE_KEY3_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA6 0xFFFFFFFF -#define EFUSE_KEY3_DATA6_M ((EFUSE_KEY3_DATA6_V)<<(EFUSE_KEY3_DATA6_S)) -#define EFUSE_KEY3_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA6_REG register + * Register 6 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) +/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA6 0xFFFFFFFFU +#define EFUSE_KEY3_DATA6_M (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S) +#define EFUSE_KEY3_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA6_S 0 -#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) -/* EFUSE_KEY3_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA7 0xFFFFFFFF -#define EFUSE_KEY3_DATA7_M ((EFUSE_KEY3_DATA7_V)<<(EFUSE_KEY3_DATA7_S)) -#define EFUSE_KEY3_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA7_REG register + * Register 7 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) +/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA7 0xFFFFFFFFU +#define EFUSE_KEY3_DATA7_M (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S) +#define EFUSE_KEY3_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA7_S 0 -#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11C) -/* EFUSE_KEY4_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA0 0xFFFFFFFF -#define EFUSE_KEY4_DATA0_M ((EFUSE_KEY4_DATA0_V)<<(EFUSE_KEY4_DATA0_S)) -#define EFUSE_KEY4_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA0_REG register + * Register 0 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c) +/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA0 0xFFFFFFFFU +#define EFUSE_KEY4_DATA0_M (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S) +#define EFUSE_KEY4_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA0_S 0 -#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) -/* EFUSE_KEY4_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA1 0xFFFFFFFF -#define EFUSE_KEY4_DATA1_M ((EFUSE_KEY4_DATA1_V)<<(EFUSE_KEY4_DATA1_S)) -#define EFUSE_KEY4_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA1_REG register + * Register 1 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) +/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA1 0xFFFFFFFFU +#define EFUSE_KEY4_DATA1_M (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S) +#define EFUSE_KEY4_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA1_S 0 -#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) -/* EFUSE_KEY4_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA2 0xFFFFFFFF -#define EFUSE_KEY4_DATA2_M ((EFUSE_KEY4_DATA2_V)<<(EFUSE_KEY4_DATA2_S)) -#define EFUSE_KEY4_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA2_REG register + * Register 2 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) +/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA2 0xFFFFFFFFU +#define EFUSE_KEY4_DATA2_M (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S) +#define EFUSE_KEY4_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA2_S 0 -#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) -/* EFUSE_KEY4_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA3 0xFFFFFFFF -#define EFUSE_KEY4_DATA3_M ((EFUSE_KEY4_DATA3_V)<<(EFUSE_KEY4_DATA3_S)) -#define EFUSE_KEY4_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA3_REG register + * Register 3 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) +/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA3 0xFFFFFFFFU +#define EFUSE_KEY4_DATA3_M (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S) +#define EFUSE_KEY4_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA3_S 0 -#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12C) -/* EFUSE_KEY4_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA4 0xFFFFFFFF -#define EFUSE_KEY4_DATA4_M ((EFUSE_KEY4_DATA4_V)<<(EFUSE_KEY4_DATA4_S)) -#define EFUSE_KEY4_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA4_REG register + * Register 4 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c) +/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA4 0xFFFFFFFFU +#define EFUSE_KEY4_DATA4_M (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S) +#define EFUSE_KEY4_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA4_S 0 -#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) -/* EFUSE_KEY4_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA5 0xFFFFFFFF -#define EFUSE_KEY4_DATA5_M ((EFUSE_KEY4_DATA5_V)<<(EFUSE_KEY4_DATA5_S)) -#define EFUSE_KEY4_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA5_REG register + * Register 5 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) +/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA5 0xFFFFFFFFU +#define EFUSE_KEY4_DATA5_M (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S) +#define EFUSE_KEY4_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA5_S 0 -#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) -/* EFUSE_KEY4_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA6 0xFFFFFFFF -#define EFUSE_KEY4_DATA6_M ((EFUSE_KEY4_DATA6_V)<<(EFUSE_KEY4_DATA6_S)) -#define EFUSE_KEY4_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA6_REG register + * Register 6 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) +/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA6 0xFFFFFFFFU +#define EFUSE_KEY4_DATA6_M (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S) +#define EFUSE_KEY4_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA6_S 0 -#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) -/* EFUSE_KEY4_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA7 0xFFFFFFFF -#define EFUSE_KEY4_DATA7_M ((EFUSE_KEY4_DATA7_V)<<(EFUSE_KEY4_DATA7_S)) -#define EFUSE_KEY4_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA7_REG register + * Register 7 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) +/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA7 0xFFFFFFFFU +#define EFUSE_KEY4_DATA7_M (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S) +#define EFUSE_KEY4_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA7_S 0 -#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13C) -/* EFUSE_KEY5_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA0 0xFFFFFFFF -#define EFUSE_KEY5_DATA0_M ((EFUSE_KEY5_DATA0_V)<<(EFUSE_KEY5_DATA0_S)) -#define EFUSE_KEY5_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA0_REG register + * Register 0 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c) +/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA0 0xFFFFFFFFU +#define EFUSE_KEY5_DATA0_M (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S) +#define EFUSE_KEY5_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA0_S 0 -#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) -/* EFUSE_KEY5_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA1 0xFFFFFFFF -#define EFUSE_KEY5_DATA1_M ((EFUSE_KEY5_DATA1_V)<<(EFUSE_KEY5_DATA1_S)) -#define EFUSE_KEY5_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA1_REG register + * Register 1 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) +/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA1 0xFFFFFFFFU +#define EFUSE_KEY5_DATA1_M (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S) +#define EFUSE_KEY5_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA1_S 0 -#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) -/* EFUSE_KEY5_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA2 0xFFFFFFFF -#define EFUSE_KEY5_DATA2_M ((EFUSE_KEY5_DATA2_V)<<(EFUSE_KEY5_DATA2_S)) -#define EFUSE_KEY5_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA2_REG register + * Register 2 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) +/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA2 0xFFFFFFFFU +#define EFUSE_KEY5_DATA2_M (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S) +#define EFUSE_KEY5_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA2_S 0 -#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) -/* EFUSE_KEY5_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA3 0xFFFFFFFF -#define EFUSE_KEY5_DATA3_M ((EFUSE_KEY5_DATA3_V)<<(EFUSE_KEY5_DATA3_S)) -#define EFUSE_KEY5_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA3_REG register + * Register 3 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) +/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA3 0xFFFFFFFFU +#define EFUSE_KEY5_DATA3_M (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S) +#define EFUSE_KEY5_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA3_S 0 -#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14C) -/* EFUSE_KEY5_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA4 0xFFFFFFFF -#define EFUSE_KEY5_DATA4_M ((EFUSE_KEY5_DATA4_V)<<(EFUSE_KEY5_DATA4_S)) -#define EFUSE_KEY5_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA4_REG register + * Register 4 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c) +/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA4 0xFFFFFFFFU +#define EFUSE_KEY5_DATA4_M (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S) +#define EFUSE_KEY5_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA4_S 0 -#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) -/* EFUSE_KEY5_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA5 0xFFFFFFFF -#define EFUSE_KEY5_DATA5_M ((EFUSE_KEY5_DATA5_V)<<(EFUSE_KEY5_DATA5_S)) -#define EFUSE_KEY5_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA5_REG register + * Register 5 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) +/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA5 0xFFFFFFFFU +#define EFUSE_KEY5_DATA5_M (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S) +#define EFUSE_KEY5_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA5_S 0 -#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) -/* EFUSE_KEY5_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA6 0xFFFFFFFF -#define EFUSE_KEY5_DATA6_M ((EFUSE_KEY5_DATA6_V)<<(EFUSE_KEY5_DATA6_S)) -#define EFUSE_KEY5_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA6_REG register + * Register 6 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) +/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA6 0xFFFFFFFFU +#define EFUSE_KEY5_DATA6_M (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S) +#define EFUSE_KEY5_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA6_S 0 -#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) -/* EFUSE_KEY5_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA7 0xFFFFFFFF -#define EFUSE_KEY5_DATA7_M ((EFUSE_KEY5_DATA7_V)<<(EFUSE_KEY5_DATA7_S)) -#define EFUSE_KEY5_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA7_REG register + * Register 7 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) +/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA7 0xFFFFFFFFU +#define EFUSE_KEY5_DATA7_M (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S) +#define EFUSE_KEY5_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA7_S 0 -#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15C) -/* EFUSE_SYS_DATA_PART2_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_0_M ((EFUSE_SYS_DATA_PART2_0_V)<<(EFUSE_SYS_DATA_PART2_0_S)) -#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA0_REG register + * Register 0 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c) +/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S) +#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_0_S 0 -#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) -/* EFUSE_SYS_DATA_PART2_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_1_M ((EFUSE_SYS_DATA_PART2_1_V)<<(EFUSE_SYS_DATA_PART2_1_S)) -#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA1_REG register + * Register 1 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) +/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1st 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S) +#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_1_S 0 -#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) -/* EFUSE_SYS_DATA_PART2_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_2_M ((EFUSE_SYS_DATA_PART2_2_V)<<(EFUSE_SYS_DATA_PART2_2_S)) -#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA2_REG register + * Register 2 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) +/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2nd 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S) +#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_2_S 0 -#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) -/* EFUSE_SYS_DATA_PART2_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_3_M ((EFUSE_SYS_DATA_PART2_3_V)<<(EFUSE_SYS_DATA_PART2_3_S)) -#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA3_REG register + * Register 3 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) +/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3rd 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S) +#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_3_S 0 -#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16C) -/* EFUSE_SYS_DATA_PART2_4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_4_M ((EFUSE_SYS_DATA_PART2_4_V)<<(EFUSE_SYS_DATA_PART2_4_S)) -#define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA4_REG register + * Register 4 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c) +/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_4_M (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S) +#define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_4_S 0 -#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) -/* EFUSE_SYS_DATA_PART2_5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_5_M ((EFUSE_SYS_DATA_PART2_5_V)<<(EFUSE_SYS_DATA_PART2_5_S)) -#define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA5_REG register + * Register 5 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) +/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_5_M (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S) +#define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_5_S 0 -#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) -/* EFUSE_SYS_DATA_PART2_6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_6_M ((EFUSE_SYS_DATA_PART2_6_V)<<(EFUSE_SYS_DATA_PART2_6_S)) -#define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA6_REG register + * Register 6 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) +/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_6_M (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S) +#define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_6_S 0 -#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) -/* EFUSE_SYS_DATA_PART2_7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_7_M ((EFUSE_SYS_DATA_PART2_7_V)<<(EFUSE_SYS_DATA_PART2_7_S)) -#define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA7_REG register + * Register 7 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) +/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_7_M (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S) +#define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_7_S 0 -#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17C) -/* EFUSE_POWER_GLITCH_DSENSE_ERR : RO ;bitpos:[31:30] ;default: 2'h0 ; */ -/*description: If any bit in POWER_GLITCH_DSENSE is 1 then it indicates a programming error.*/ -#define EFUSE_POWER_GLITCH_DSENSE_ERR 0x00000003 -#define EFUSE_POWER_GLITCH_DSENSE_ERR_M ((EFUSE_POWER_GLITCH_DSENSE_ERR_V)<<(EFUSE_POWER_GLITCH_DSENSE_ERR_S)) -#define EFUSE_POWER_GLITCH_DSENSE_ERR_V 0x3 -#define EFUSE_POWER_GLITCH_DSENSE_ERR_S 30 -/* EFUSE_POWERGLITCH_EN_ERR : RO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: If POWERGLITCH_EN is 1 then it indicates a programming error.*/ -#define EFUSE_POWERGLITCH_EN_ERR (BIT(29)) -#define EFUSE_POWERGLITCH_EN_ERR_M (BIT(29)) -#define EFUSE_POWERGLITCH_EN_ERR_V 0x1 -#define EFUSE_POWERGLITCH_EN_ERR_S 29 -/* EFUSE_BTLC_GPIO_ENABLE_ERR : RO ;bitpos:[28:27] ;default: 2'h0 ; */ -/*description: If any bit in BTLC_GPIO_ENABLE is 1 then it indicates a programming error.*/ -#define EFUSE_BTLC_GPIO_ENABLE_ERR 0x00000003 -#define EFUSE_BTLC_GPIO_ENABLE_ERR_M ((EFUSE_BTLC_GPIO_ENABLE_ERR_V)<<(EFUSE_BTLC_GPIO_ENABLE_ERR_S)) -#define EFUSE_BTLC_GPIO_ENABLE_ERR_V 0x3 -#define EFUSE_BTLC_GPIO_ENABLE_ERR_S 27 -/* EFUSE_VDD_SPI_AS_GPIO_ERR : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: If VDD_SPI_AS_GPIO is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_AS_GPIO_ERR (BIT(26)) -#define EFUSE_VDD_SPI_AS_GPIO_ERR_M (BIT(26)) -#define EFUSE_VDD_SPI_AS_GPIO_ERR_V 0x1 -#define EFUSE_VDD_SPI_AS_GPIO_ERR_S 26 -/* EFUSE_USB_EXCHG_PINS_ERR : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: If USB_EXCHG_PINS is 1 then it indicates a programming error.*/ -#define EFUSE_USB_EXCHG_PINS_ERR (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_ERR_M (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_ERR_V 0x1 -#define EFUSE_USB_EXCHG_PINS_ERR_S 25 -/* EFUSE_USB_DREFL_ERR : RO ;bitpos:[24:23] ;default: 2'h0 ; */ -/*description: If any bit in USB_DREFL is 1 then it indicates a programming error.*/ -#define EFUSE_USB_DREFL_ERR 0x00000003 -#define EFUSE_USB_DREFL_ERR_M ((EFUSE_USB_DREFL_ERR_V)<<(EFUSE_USB_DREFL_ERR_S)) -#define EFUSE_USB_DREFL_ERR_V 0x3 -#define EFUSE_USB_DREFL_ERR_S 23 -/* EFUSE_USB_DREFH_ERR : RO ;bitpos:[22:21] ;default: 2'h0 ; */ -/*description: If any bit in USB_DREFH is 1 then it indicates a programming error.*/ -#define EFUSE_USB_DREFH_ERR 0x00000003 -#define EFUSE_USB_DREFH_ERR_M ((EFUSE_USB_DREFH_ERR_V)<<(EFUSE_USB_DREFH_ERR_S)) -#define EFUSE_USB_DREFH_ERR_V 0x3 -#define EFUSE_USB_DREFH_ERR_S 21 -/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20 -/* EFUSE_DIS_PAD_JTAG_ERR : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: If DIS_PAD_JTAG is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_PAD_JTAG_ERR (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_ERR_M (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_ERR_V 0x1 -#define EFUSE_DIS_PAD_JTAG_ERR_S 19 -/* EFUSE_SOFT_DIS_JTAG_ERR : RO ;bitpos:[18:16] ;default: 3'h0 ; */ -/*description: If SOFT_DIS_JTAG is 1 then it indicates a programming error.*/ -#define EFUSE_SOFT_DIS_JTAG_ERR 0x00000007 -#define EFUSE_SOFT_DIS_JTAG_ERR_M ((EFUSE_SOFT_DIS_JTAG_ERR_V)<<(EFUSE_SOFT_DIS_JTAG_ERR_S)) -#define EFUSE_SOFT_DIS_JTAG_ERR_V 0x7 -#define EFUSE_SOFT_DIS_JTAG_ERR_S 16 -/* EFUSE_JTAG_SEL_ENABLE_ERR : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: If JTAG_SEL_ENABLE is 1 then it indicates a programming error.*/ -#define EFUSE_JTAG_SEL_ENABLE_ERR (BIT(15)) -#define EFUSE_JTAG_SEL_ENABLE_ERR_M (BIT(15)) -#define EFUSE_JTAG_SEL_ENABLE_ERR_V 0x1 -#define EFUSE_JTAG_SEL_ENABLE_ERR_S 15 -/* EFUSE_DIS_TWAI_ERR : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: If DIS_TWAI is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_TWAI_ERR (BIT(14)) -#define EFUSE_DIS_TWAI_ERR_M (BIT(14)) -#define EFUSE_DIS_TWAI_ERR_V 0x1 -#define EFUSE_DIS_TWAI_ERR_S 14 -/* EFUSE_RPT4_RESERVED6_ERR : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Reserved..*/ +/** EFUSE_RD_REPEAT_ERR0_REG register + * Programming error record register 0 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) +/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0; + * If any bit in RD_DIS is 1, then it indicates a programming error. + */ +#define EFUSE_RD_DIS_ERR 0x0000007FU +#define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S) +#define EFUSE_RD_DIS_ERR_V 0x0000007FU +#define EFUSE_RD_DIS_ERR_S 0 +/** EFUSE_DIS_RTC_RAM_BOOT_ERR : RO; bitpos: [7]; default: 0; + * If DIS_RTC_RAM_BOOT is 1, then it indicates a programming error. + */ +#define EFUSE_DIS_RTC_RAM_BOOT_ERR (BIT(7)) +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_M (EFUSE_DIS_RTC_RAM_BOOT_ERR_V << EFUSE_DIS_RTC_RAM_BOOT_ERR_S) +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_V 0x00000001U +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_S 7 +/** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0; + * If DIS_ICACHE is 1, then it indicates a programming error. + */ +#define EFUSE_DIS_ICACHE_ERR (BIT(8)) +#define EFUSE_DIS_ICACHE_ERR_M (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S) +#define EFUSE_DIS_ICACHE_ERR_V 0x00000001U +#define EFUSE_DIS_ICACHE_ERR_S 8 +/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0; + * If DIS_USB_JTAG is 1, then it indicates a programming error. + */ +#define EFUSE_DIS_USB_JTAG_ERR (BIT(9)) +#define EFUSE_DIS_USB_JTAG_ERR_M (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S) +#define EFUSE_DIS_USB_JTAG_ERR_V 0x00000001U +#define EFUSE_DIS_USB_JTAG_ERR_S 9 +/** EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO; bitpos: [10]; default: 0; + * If DIS_DOWNLOAD_ICACHE is 1, then it indicates a programming error. + */ +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR (BIT(10)) +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M (EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V << EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S 10 +/** EFUSE_DIS_USB_DEVICE_ERR : RO; bitpos: [11]; default: 0; + * If DIS_USB_DEVICE is 1, then it indicates a programming error. + */ +#define EFUSE_DIS_USB_DEVICE_ERR (BIT(11)) +#define EFUSE_DIS_USB_DEVICE_ERR_M (EFUSE_DIS_USB_DEVICE_ERR_V << EFUSE_DIS_USB_DEVICE_ERR_S) +#define EFUSE_DIS_USB_DEVICE_ERR_V 0x00000001U +#define EFUSE_DIS_USB_DEVICE_ERR_S 11 +/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0; + * If DIS_FORCE_DOWNLOAD is 1, then it indicates a programming error. + */ +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x00000001U +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 +/** EFUSE_RPT4_RESERVED6_ERR : RO; bitpos: [13]; default: 0; + * Reserved. + */ #define EFUSE_RPT4_RESERVED6_ERR (BIT(13)) -#define EFUSE_RPT4_RESERVED6_ERR_M (BIT(13)) -#define EFUSE_RPT4_RESERVED6_ERR_V 0x1 +#define EFUSE_RPT4_RESERVED6_ERR_M (EFUSE_RPT4_RESERVED6_ERR_V << EFUSE_RPT4_RESERVED6_ERR_S) +#define EFUSE_RPT4_RESERVED6_ERR_V 0x00000001U #define EFUSE_RPT4_RESERVED6_ERR_S 13 -/* EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: If DIS_FORCE_DOWNLOAD is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x1 -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 -/* EFUSE_DIS_USB_DEVICE_ERR : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: If DIS_USB_DEVICE is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_USB_DEVICE_ERR (BIT(11)) -#define EFUSE_DIS_USB_DEVICE_ERR_M (BIT(11)) -#define EFUSE_DIS_USB_DEVICE_ERR_V 0x1 -#define EFUSE_DIS_USB_DEVICE_ERR_S 11 -/* EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: If DIS_DOWNLOAD_ICACHE is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V 0x1 -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S 10 -/* EFUSE_DIS_USB_JTAG_ERR : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: If DIS_USB_JTAG is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_USB_JTAG_ERR (BIT(9)) -#define EFUSE_DIS_USB_JTAG_ERR_M (BIT(9)) -#define EFUSE_DIS_USB_JTAG_ERR_V 0x1 -#define EFUSE_DIS_USB_JTAG_ERR_S 9 -/* EFUSE_DIS_ICACHE_ERR : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: If DIS_ICACHE is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_ICACHE_ERR (BIT(8)) -#define EFUSE_DIS_ICACHE_ERR_M (BIT(8)) -#define EFUSE_DIS_ICACHE_ERR_V 0x1 -#define EFUSE_DIS_ICACHE_ERR_S 8 -/* EFUSE_RPT4_RESERVED5_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Reserved..*/ -#define EFUSE_RPT4_RESERVED5_ERR (BIT(7)) -#define EFUSE_RPT4_RESERVED5_ERR_M (BIT(7)) -#define EFUSE_RPT4_RESERVED5_ERR_V 0x1 -#define EFUSE_RPT4_RESERVED5_ERR_S 7 -/* EFUSE_RD_DIS_ERR : RO ;bitpos:[6:0] ;default: 7'h0 ; */ -/*description: If any bit in RD_DIS is 1 then it indicates a programming error.*/ -#define EFUSE_RD_DIS_ERR 0x0000007F -#define EFUSE_RD_DIS_ERR_M ((EFUSE_RD_DIS_ERR_V)<<(EFUSE_RD_DIS_ERR_S)) -#define EFUSE_RD_DIS_ERR_V 0x7F -#define EFUSE_RD_DIS_ERR_S 0 +/** EFUSE_DIS_CAN_ERR : RO; bitpos: [14]; default: 0; + * If DIS_CAN is 1, then it indicates a programming error. + */ +#define EFUSE_DIS_CAN_ERR (BIT(14)) +#define EFUSE_DIS_CAN_ERR_M (EFUSE_DIS_CAN_ERR_V << EFUSE_DIS_CAN_ERR_S) +#define EFUSE_DIS_CAN_ERR_V 0x00000001U +#define EFUSE_DIS_CAN_ERR_S 14 +/** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0; + * If JTAG_SEL_ENABLE is 1, then it indicates a programming error. + */ +#define EFUSE_JTAG_SEL_ENABLE_ERR (BIT(15)) +#define EFUSE_JTAG_SEL_ENABLE_ERR_M (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S) +#define EFUSE_JTAG_SEL_ENABLE_ERR_V 0x00000001U +#define EFUSE_JTAG_SEL_ENABLE_ERR_S 15 +/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0; + * If SOFT_DIS_JTAG is 1, then it indicates a programming error. + */ +#define EFUSE_SOFT_DIS_JTAG_ERR 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_ERR_M (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S) +#define EFUSE_SOFT_DIS_JTAG_ERR_V 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_ERR_S 16 +/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0; + * If DIS_PAD_JTAG is 1, then it indicates a programming error. + */ +#define EFUSE_DIS_PAD_JTAG_ERR (BIT(19)) +#define EFUSE_DIS_PAD_JTAG_ERR_M (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S) +#define EFUSE_DIS_PAD_JTAG_ERR_V 0x00000001U +#define EFUSE_DIS_PAD_JTAG_ERR_S 19 +/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0; + * If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error. + */ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(20)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20 +/** EFUSE_USB_DREFH_ERR : RO; bitpos: [22:21]; default: 0; + * If any bit in USB_DREFH is 1, then it indicates a programming error. + */ +#define EFUSE_USB_DREFH_ERR 0x00000003U +#define EFUSE_USB_DREFH_ERR_M (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S) +#define EFUSE_USB_DREFH_ERR_V 0x00000003U +#define EFUSE_USB_DREFH_ERR_S 21 +/** EFUSE_USB_DREFL_ERR : RO; bitpos: [24:23]; default: 0; + * If any bit in USB_DREFL is 1, then it indicates a programming error. + */ +#define EFUSE_USB_DREFL_ERR 0x00000003U +#define EFUSE_USB_DREFL_ERR_M (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S) +#define EFUSE_USB_DREFL_ERR_V 0x00000003U +#define EFUSE_USB_DREFL_ERR_S 23 +/** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [25]; default: 0; + * If USB_EXCHG_PINS is 1, then it indicates a programming error. + */ +#define EFUSE_USB_EXCHG_PINS_ERR (BIT(25)) +#define EFUSE_USB_EXCHG_PINS_ERR_M (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S) +#define EFUSE_USB_EXCHG_PINS_ERR_V 0x00000001U +#define EFUSE_USB_EXCHG_PINS_ERR_S 25 +/** EFUSE_VDD_SPI_AS_GPIO_ERR : RO; bitpos: [26]; default: 0; + * If VDD_SPI_AS_GPIO is 1, then it indicates a programming error. + */ +#define EFUSE_VDD_SPI_AS_GPIO_ERR (BIT(26)) +#define EFUSE_VDD_SPI_AS_GPIO_ERR_M (EFUSE_VDD_SPI_AS_GPIO_ERR_V << EFUSE_VDD_SPI_AS_GPIO_ERR_S) +#define EFUSE_VDD_SPI_AS_GPIO_ERR_V 0x00000001U +#define EFUSE_VDD_SPI_AS_GPIO_ERR_S 26 +/** EFUSE_BTLC_GPIO_ENABLE_ERR : RO; bitpos: [28:27]; default: 0; + * If any bit in BTLC_GPIO_ENABLE is 1, then it indicates a programming error. + */ +#define EFUSE_BTLC_GPIO_ENABLE_ERR 0x00000003U +#define EFUSE_BTLC_GPIO_ENABLE_ERR_M (EFUSE_BTLC_GPIO_ENABLE_ERR_V << EFUSE_BTLC_GPIO_ENABLE_ERR_S) +#define EFUSE_BTLC_GPIO_ENABLE_ERR_V 0x00000003U +#define EFUSE_BTLC_GPIO_ENABLE_ERR_S 27 +/** EFUSE_POWERGLITCH_EN_ERR : RO; bitpos: [29]; default: 0; + * If POWERGLITCH_EN is 1, then it indicates a programming error. + */ +#define EFUSE_POWERGLITCH_EN_ERR (BIT(29)) +#define EFUSE_POWERGLITCH_EN_ERR_M (EFUSE_POWERGLITCH_EN_ERR_V << EFUSE_POWERGLITCH_EN_ERR_S) +#define EFUSE_POWERGLITCH_EN_ERR_V 0x00000001U +#define EFUSE_POWERGLITCH_EN_ERR_S 29 +/** EFUSE_POWER_GLITCH_DSENSE_ERR : RO; bitpos: [31:30]; default: 0; + * If any bit in POWER_GLITCH_DSENSE is 1, then it indicates a programming error. + */ +#define EFUSE_POWER_GLITCH_DSENSE_ERR 0x00000003U +#define EFUSE_POWER_GLITCH_DSENSE_ERR_M (EFUSE_POWER_GLITCH_DSENSE_ERR_V << EFUSE_POWER_GLITCH_DSENSE_ERR_S) +#define EFUSE_POWER_GLITCH_DSENSE_ERR_V 0x00000003U +#define EFUSE_POWER_GLITCH_DSENSE_ERR_S 30 -#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) -/* EFUSE_KEY_PURPOSE_1_ERR : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_1 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_1_ERR_M ((EFUSE_KEY_PURPOSE_1_ERR_V)<<(EFUSE_KEY_PURPOSE_1_ERR_S)) -#define EFUSE_KEY_PURPOSE_1_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_1_ERR_S 28 -/* EFUSE_KEY_PURPOSE_0_ERR : RO ;bitpos:[27:24] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_0 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_0_ERR_M ((EFUSE_KEY_PURPOSE_0_ERR_V)<<(EFUSE_KEY_PURPOSE_0_ERR_S)) -#define EFUSE_KEY_PURPOSE_0_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_0_ERR_S 24 -/* EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: If SECURE_BOOT_KEY_REVOKE2 is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 -/* EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: If SECURE_BOOT_KEY_REVOKE1 is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 -/* EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: If SECURE_BOOT_KEY_REVOKE0 is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 -/* EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: If any bit in SPI_BOOT_CRYPT_CNT is 1 then it indicates a programming error.*/ -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M ((EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)) -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x7 -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 -/* EFUSE_WDT_DELAY_SEL_ERR : RO ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: If any bit in WDT_DELAY_SEL is 1 then it indicates a programming error.*/ -#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003 -#define EFUSE_WDT_DELAY_SEL_ERR_M ((EFUSE_WDT_DELAY_SEL_ERR_V)<<(EFUSE_WDT_DELAY_SEL_ERR_S)) -#define EFUSE_WDT_DELAY_SEL_ERR_V 0x3 -#define EFUSE_WDT_DELAY_SEL_ERR_S 16 -/* EFUSE_RPT4_RESERVED2_ERR : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED2_ERR 0x0000FFFF -#define EFUSE_RPT4_RESERVED2_ERR_M ((EFUSE_RPT4_RESERVED2_ERR_V)<<(EFUSE_RPT4_RESERVED2_ERR_S)) -#define EFUSE_RPT4_RESERVED2_ERR_V 0xFFFF +/** EFUSE_RD_REPEAT_ERR1_REG register + * Programming error record register 1 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) +/** EFUSE_RPT4_RESERVED2_ERR : RO; bitpos: [15:0]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED2_ERR 0x0000FFFFU +#define EFUSE_RPT4_RESERVED2_ERR_M (EFUSE_RPT4_RESERVED2_ERR_V << EFUSE_RPT4_RESERVED2_ERR_S) +#define EFUSE_RPT4_RESERVED2_ERR_V 0x0000FFFFU #define EFUSE_RPT4_RESERVED2_ERR_S 0 +/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0; + * If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error. + */ +#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003U +#define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) +#define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003U +#define EFUSE_WDT_DELAY_SEL_ERR_S 16 +/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0; + * If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a programming error. + */ +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 +/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0; + * If SECURE_BOOT_KEY_REVOKE0 is 1, then it indicates a programming error. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 +/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0; + * If SECURE_BOOT_KEY_REVOKE1 is 1, then it indicates a programming error. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 +/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0; + * If SECURE_BOOT_KEY_REVOKE2 is 1, then it indicates a programming error. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 +/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0; + * If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming error. + */ +#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_ERR_M (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S) +#define EFUSE_KEY_PURPOSE_0_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_ERR_S 24 +/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0; + * If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming error. + */ +#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_ERR_M (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S) +#define EFUSE_KEY_PURPOSE_1_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_ERR_S 28 -#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) -/* EFUSE_FLASH_TPUW_ERR : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: If any bit in FLASH_TPUM is 1 then it indicates a programming error.*/ -#define EFUSE_FLASH_TPUW_ERR 0x0000000F -#define EFUSE_FLASH_TPUW_ERR_M ((EFUSE_FLASH_TPUW_ERR_V)<<(EFUSE_FLASH_TPUW_ERR_S)) -#define EFUSE_FLASH_TPUW_ERR_V 0xF -#define EFUSE_FLASH_TPUW_ERR_S 28 -/* EFUSE_RPT4_RESERVED0_ERR : RO ;bitpos:[27:22] ;default: 6'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED0_ERR 0x0000003F -#define EFUSE_RPT4_RESERVED0_ERR_M ((EFUSE_RPT4_RESERVED0_ERR_V)<<(EFUSE_RPT4_RESERVED0_ERR_S)) -#define EFUSE_RPT4_RESERVED0_ERR_V 0x3F -#define EFUSE_RPT4_RESERVED0_ERR_S 22 -/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: If SECURE_BOOT_AGGRESSIVE_REVOKE is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 -/* EFUSE_SECURE_BOOT_EN_ERR : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: If SECURE_BOOT_EN is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_ERR_M (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_EN_ERR_S 20 -/* EFUSE_RPT4_RESERVED3_ERR : RO ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED3_ERR 0x0000000F -#define EFUSE_RPT4_RESERVED3_ERR_M ((EFUSE_RPT4_RESERVED3_ERR_V)<<(EFUSE_RPT4_RESERVED3_ERR_S)) -#define EFUSE_RPT4_RESERVED3_ERR_V 0xF -#define EFUSE_RPT4_RESERVED3_ERR_S 16 -/* EFUSE_KEY_PURPOSE_5_ERR : RO ;bitpos:[15:12] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_5 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_5_ERR_M ((EFUSE_KEY_PURPOSE_5_ERR_V)<<(EFUSE_KEY_PURPOSE_5_ERR_S)) -#define EFUSE_KEY_PURPOSE_5_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_5_ERR_S 12 -/* EFUSE_KEY_PURPOSE_4_ERR : RO ;bitpos:[11:8] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_4 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_4_ERR_M ((EFUSE_KEY_PURPOSE_4_ERR_V)<<(EFUSE_KEY_PURPOSE_4_ERR_S)) -#define EFUSE_KEY_PURPOSE_4_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_4_ERR_S 8 -/* EFUSE_KEY_PURPOSE_3_ERR : RO ;bitpos:[7:4] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_3 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_3_ERR_M ((EFUSE_KEY_PURPOSE_3_ERR_V)<<(EFUSE_KEY_PURPOSE_3_ERR_S)) -#define EFUSE_KEY_PURPOSE_3_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_3_ERR_S 4 -/* EFUSE_KEY_PURPOSE_2_ERR : RO ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_2 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_2_ERR_M ((EFUSE_KEY_PURPOSE_2_ERR_V)<<(EFUSE_KEY_PURPOSE_2_ERR_S)) -#define EFUSE_KEY_PURPOSE_2_ERR_V 0xF +/** EFUSE_RD_REPEAT_ERR2_REG register + * Programming error record register 2 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) +/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0; + * If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming error. + */ +#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_ERR_M (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S) +#define EFUSE_KEY_PURPOSE_2_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_2_ERR_S 0 +/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0; + * If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming error. + */ +#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_ERR_M (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S) +#define EFUSE_KEY_PURPOSE_3_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_ERR_S 4 +/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0; + * If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming error. + */ +#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_ERR_M (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S) +#define EFUSE_KEY_PURPOSE_4_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_ERR_S 8 +/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0; + * If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming error. + */ +#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_ERR_M (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S) +#define EFUSE_KEY_PURPOSE_5_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_ERR_S 12 +/** EFUSE_RPT4_RESERVED3_ERR : RO; bitpos: [19:16]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED3_ERR 0x0000000FU +#define EFUSE_RPT4_RESERVED3_ERR_M (EFUSE_RPT4_RESERVED3_ERR_V << EFUSE_RPT4_RESERVED3_ERR_S) +#define EFUSE_RPT4_RESERVED3_ERR_V 0x0000000FU +#define EFUSE_RPT4_RESERVED3_ERR_S 16 +/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0; + * If SECURE_BOOT_EN is 1, then it indicates a programming error. + */ +#define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S) +#define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_EN_ERR_S 20 +/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0; + * If SECURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error. + */ +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 +/** EFUSE_RPT4_RESERVED0_ERR : RO; bitpos: [27:22]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED0_ERR 0x0000003FU +#define EFUSE_RPT4_RESERVED0_ERR_M (EFUSE_RPT4_RESERVED0_ERR_V << EFUSE_RPT4_RESERVED0_ERR_S) +#define EFUSE_RPT4_RESERVED0_ERR_V 0x0000003FU +#define EFUSE_RPT4_RESERVED0_ERR_S 22 +/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0; + * If any bit in FLASH_TPUM is 1, then it indicates a programming error. + */ +#define EFUSE_FLASH_TPUW_ERR 0x0000000FU +#define EFUSE_FLASH_TPUW_ERR_M (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S) +#define EFUSE_FLASH_TPUW_ERR_V 0x0000000FU +#define EFUSE_FLASH_TPUW_ERR_S 28 -#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) -/* EFUSE_ERR_RST_ENABLE_ERR : RO ;bitpos:[31] ;default: 1'h0 ; */ -/*description: Use BLOCK0 to check error record registers, 0 - without check.*/ -#define EFUSE_ERR_RST_ENABLE_ERR (BIT(31)) -#define EFUSE_ERR_RST_ENABLE_ERR_M (BIT(31)) -#define EFUSE_ERR_RST_ENABLE_ERR_V 0x1 -#define EFUSE_ERR_RST_ENABLE_ERR_S 31 -/* EFUSE_RPT4_RESERVED1_ERR : RO ;bitpos:[30] ;default: 1'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED1_ERR (BIT(30)) -#define EFUSE_RPT4_RESERVED1_ERR_M (BIT(30)) -#define EFUSE_RPT4_RESERVED1_ERR_V 0x1 -#define EFUSE_RPT4_RESERVED1_ERR_S 30 -/* EFUSE_SECURE_VERSION_ERR : RO ;bitpos:[29:14] ;default: 16'h0 ; */ -/*description: If any bit in SECURE_VERSION is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_VERSION_ERR 0x0000FFFF -#define EFUSE_SECURE_VERSION_ERR_M ((EFUSE_SECURE_VERSION_ERR_V)<<(EFUSE_SECURE_VERSION_ERR_S)) -#define EFUSE_SECURE_VERSION_ERR_V 0xFFFF -#define EFUSE_SECURE_VERSION_ERR_S 14 -/* EFUSE_FORCE_SEND_RESUME_ERR : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: If FORCE_SEND_RESUME is 1 then it indicates a programming error.*/ -#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_ERR_M (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x1 -#define EFUSE_FORCE_SEND_RESUME_ERR_S 13 -/* EFUSE_RPT4_RESERVED7_ERR : RO ;bitpos:[12:8] ;default: 5'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED7_ERR 0x0000001F -#define EFUSE_RPT4_RESERVED7_ERR_M ((EFUSE_RPT4_RESERVED7_ERR_V)<<(EFUSE_RPT4_RESERVED7_ERR_S)) -#define EFUSE_RPT4_RESERVED7_ERR_V 0x1F -#define EFUSE_RPT4_RESERVED7_ERR_S 8 -/* EFUSE_UART_PRINT_CONTROL_ERR : RO ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: If any bit in UART_PRINT_CONTROL is 1 then it indicates a programming error.*/ -#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_ERR_M ((EFUSE_UART_PRINT_CONTROL_ERR_V)<<(EFUSE_UART_PRINT_CONTROL_ERR_S)) -#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x3 -#define EFUSE_UART_PRINT_CONTROL_ERR_S 6 -/* EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: If ENABLE_SECURITY_DOWNLOAD is 1 then it indicates a programming error.*/ -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x1 -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 -/* EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: If DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V 0x1 -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S 4 -/* EFUSE_RPT4_RESERVED8_ERR : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED8_ERR (BIT(3)) -#define EFUSE_RPT4_RESERVED8_ERR_M (BIT(3)) -#define EFUSE_RPT4_RESERVED8_ERR_V 0x1 -#define EFUSE_RPT4_RESERVED8_ERR_S 3 -/* EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: If DIS_USB_SERIAL_JTAG_ROM_PRINT is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_M (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V 0x1 -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S 2 -/* EFUSE_DIS_DIRECT_BOOT_ERR : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: If DIS_DIRECT_BOOT is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_DIRECT_BOOT_ERR (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_ERR_M (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_ERR_V 0x1 -#define EFUSE_DIS_DIRECT_BOOT_ERR_S 1 -/* EFUSE_DIS_DOWNLOAD_MODE_ERR : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: If DIS_DOWNLOAD_MODE is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x1 +/** EFUSE_RD_REPEAT_ERR3_REG register + * Programming error record register 3 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) +/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0; + * If DIS_DOWNLOAD_MODE is 1, then it indicates a programming error. + */ +#define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 +/** EFUSE_DIS_LEGACY_SPI_BOOT_ERR : RO; bitpos: [1]; default: 0; + * If DIS_LEGACY_SPI_BOOT is 1, then it indicates a programming error. + */ +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR (BIT(1)) +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_M (EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V << EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S) +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V 0x00000001U +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S 1 +/** EFUSE_UART_PRINT_CHANNEL_ERR : RO; bitpos: [2]; default: 0; + * If UART_PRINT_CHANNEL is 1, then it indicates a programming error. + */ +#define EFUSE_UART_PRINT_CHANNEL_ERR (BIT(2)) +#define EFUSE_UART_PRINT_CHANNEL_ERR_M (EFUSE_UART_PRINT_CHANNEL_ERR_V << EFUSE_UART_PRINT_CHANNEL_ERR_S) +#define EFUSE_UART_PRINT_CHANNEL_ERR_V 0x00000001U +#define EFUSE_UART_PRINT_CHANNEL_ERR_S 2 +/** EFUSE_FLASH_ECC_MODE_ERR : RO; bitpos: [3]; default: 0; + * If FLASH_ECC_MODE is 1, then it indicates a programming error. + */ +#define EFUSE_FLASH_ECC_MODE_ERR (BIT(3)) +#define EFUSE_FLASH_ECC_MODE_ERR_M (EFUSE_FLASH_ECC_MODE_ERR_V << EFUSE_FLASH_ECC_MODE_ERR_S) +#define EFUSE_FLASH_ECC_MODE_ERR_V 0x00000001U +#define EFUSE_FLASH_ECC_MODE_ERR_S 3 +/** EFUSE_DIS_USB_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0; + * If DIS_USB_DOWNLOAD_MODE is 1, then it indicates a programming error. + */ +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR (BIT(4)) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V 0x00000001U +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S 4 +/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0; + * If ENABLE_SECURITY_DOWNLOAD is 1, then it indicates a programming error. + */ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x00000001U +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 +/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0; + * If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error. + */ +#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_ERR_M (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S) +#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_ERR_S 6 +/** EFUSE_PIN_POWER_SELECTION_ERR : RO; bitpos: [8]; default: 0; + * If PIN_POWER_SELECTION is 1, then it indicates a programming error. + */ +#define EFUSE_PIN_POWER_SELECTION_ERR (BIT(8)) +#define EFUSE_PIN_POWER_SELECTION_ERR_M (EFUSE_PIN_POWER_SELECTION_ERR_V << EFUSE_PIN_POWER_SELECTION_ERR_S) +#define EFUSE_PIN_POWER_SELECTION_ERR_V 0x00000001U +#define EFUSE_PIN_POWER_SELECTION_ERR_S 8 +/** EFUSE_FLASH_TYPE_ERR : RO; bitpos: [9]; default: 0; + * If FLASH_TYPE is 1, then it indicates a programming error. + */ +#define EFUSE_FLASH_TYPE_ERR (BIT(9)) +#define EFUSE_FLASH_TYPE_ERR_M (EFUSE_FLASH_TYPE_ERR_V << EFUSE_FLASH_TYPE_ERR_S) +#define EFUSE_FLASH_TYPE_ERR_V 0x00000001U +#define EFUSE_FLASH_TYPE_ERR_S 9 +/** EFUSE_FLASH_PAGE_SIZE_ERR : RO; bitpos: [11:10]; default: 0; + * If any bits in FLASH_PAGE_SIZE is 1, then it indicates a programming error. + */ +#define EFUSE_FLASH_PAGE_SIZE_ERR 0x00000003U +#define EFUSE_FLASH_PAGE_SIZE_ERR_M (EFUSE_FLASH_PAGE_SIZE_ERR_V << EFUSE_FLASH_PAGE_SIZE_ERR_S) +#define EFUSE_FLASH_PAGE_SIZE_ERR_V 0x00000003U +#define EFUSE_FLASH_PAGE_SIZE_ERR_S 10 +/** EFUSE_FLASH_ECC_EN_ERR : RO; bitpos: [12]; default: 0; + * If FLASH_ECC_EN_ERR is 1, then it indicates a programming error. + */ +#define EFUSE_FLASH_ECC_EN_ERR (BIT(12)) +#define EFUSE_FLASH_ECC_EN_ERR_M (EFUSE_FLASH_ECC_EN_ERR_V << EFUSE_FLASH_ECC_EN_ERR_S) +#define EFUSE_FLASH_ECC_EN_ERR_V 0x00000001U +#define EFUSE_FLASH_ECC_EN_ERR_S 12 +/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [13]; default: 0; + * If FORCE_SEND_RESUME is 1, then it indicates a programming error. + */ +#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(13)) +#define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S) +#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001U +#define EFUSE_FORCE_SEND_RESUME_ERR_S 13 +/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [29:14]; default: 0; + * If any bit in SECURE_VERSION is 1, then it indicates a programming error. + */ +#define EFUSE_SECURE_VERSION_ERR 0x0000FFFFU +#define EFUSE_SECURE_VERSION_ERR_M (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S) +#define EFUSE_SECURE_VERSION_ERR_V 0x0000FFFFU +#define EFUSE_SECURE_VERSION_ERR_S 14 +/** EFUSE_RPT4_RESERVED1_ERR : RO; bitpos: [31:30]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED1_ERR 0x00000003U +#define EFUSE_RPT4_RESERVED1_ERR_M (EFUSE_RPT4_RESERVED1_ERR_V << EFUSE_RPT4_RESERVED1_ERR_S) +#define EFUSE_RPT4_RESERVED1_ERR_V 0x00000003U +#define EFUSE_RPT4_RESERVED1_ERR_S 30 -#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x18C) -/* EFUSE_RPT4_RESERVED4_ERR : RO ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED4_ERR 0x00FFFFFF -#define EFUSE_RPT4_RESERVED4_ERR_M ((EFUSE_RPT4_RESERVED4_ERR_V)<<(EFUSE_RPT4_RESERVED4_ERR_S)) -#define EFUSE_RPT4_RESERVED4_ERR_V 0xFFFFFF +/** EFUSE_RD_REPEAT_ERR4_REG register + * Programming error record register 4 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x190) +/** EFUSE_RPT4_RESERVED4_ERR : RO; bitpos: [23:0]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED4_ERR 0x00FFFFFFU +#define EFUSE_RPT4_RESERVED4_ERR_M (EFUSE_RPT4_RESERVED4_ERR_V << EFUSE_RPT4_RESERVED4_ERR_S) +#define EFUSE_RPT4_RESERVED4_ERR_V 0x00FFFFFFU #define EFUSE_RPT4_RESERVED4_ERR_S 0 -#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1C0) -/* EFUSE_KEY3_FAIL : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key3 is reliable 1: - Means that programming key3 failed and the number of error bytes is over 6.*/ -#define EFUSE_KEY3_FAIL (BIT(31)) -#define EFUSE_KEY3_FAIL_M (BIT(31)) -#define EFUSE_KEY3_FAIL_V 0x1 -#define EFUSE_KEY3_FAIL_S 31 -/* EFUSE_KEY4_ERR_NUM : RO ;bitpos:[30:28] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY4_ERR_NUM 0x00000007 -#define EFUSE_KEY4_ERR_NUM_M ((EFUSE_KEY4_ERR_NUM_V)<<(EFUSE_KEY4_ERR_NUM_S)) -#define EFUSE_KEY4_ERR_NUM_V 0x7 -#define EFUSE_KEY4_ERR_NUM_S 28 -/* EFUSE_KEY2_FAIL : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key2 is reliable 1: - Means that programming key2 failed and the number of error bytes is over 6.*/ -#define EFUSE_KEY2_FAIL (BIT(27)) -#define EFUSE_KEY2_FAIL_M (BIT(27)) -#define EFUSE_KEY2_FAIL_V 0x1 -#define EFUSE_KEY2_FAIL_S 27 -/* EFUSE_KEY3_ERR_NUM : RO ;bitpos:[26:24] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY3_ERR_NUM 0x00000007 -#define EFUSE_KEY3_ERR_NUM_M ((EFUSE_KEY3_ERR_NUM_V)<<(EFUSE_KEY3_ERR_NUM_S)) -#define EFUSE_KEY3_ERR_NUM_V 0x7 -#define EFUSE_KEY3_ERR_NUM_S 24 -/* EFUSE_KEY1_FAIL : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key1 is reliable 1: - Means that programming key1 failed and the number of error bytes is over 6.*/ -#define EFUSE_KEY1_FAIL (BIT(23)) -#define EFUSE_KEY1_FAIL_M (BIT(23)) -#define EFUSE_KEY1_FAIL_V 0x1 -#define EFUSE_KEY1_FAIL_S 23 -/* EFUSE_KEY2_ERR_NUM : RO ;bitpos:[22:20] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY2_ERR_NUM 0x00000007 -#define EFUSE_KEY2_ERR_NUM_M ((EFUSE_KEY2_ERR_NUM_V)<<(EFUSE_KEY2_ERR_NUM_S)) -#define EFUSE_KEY2_ERR_NUM_V 0x7 -#define EFUSE_KEY2_ERR_NUM_S 20 -/* EFUSE_KEY0_FAIL : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key0 is reliable 1: - Means that programming key0 failed and the number of error bytes is over 6.*/ -#define EFUSE_KEY0_FAIL (BIT(19)) -#define EFUSE_KEY0_FAIL_M (BIT(19)) -#define EFUSE_KEY0_FAIL_V 0x1 -#define EFUSE_KEY0_FAIL_S 19 -/* EFUSE_KEY1_ERR_NUM : RO ;bitpos:[18:16] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY1_ERR_NUM 0x00000007 -#define EFUSE_KEY1_ERR_NUM_M ((EFUSE_KEY1_ERR_NUM_V)<<(EFUSE_KEY1_ERR_NUM_S)) -#define EFUSE_KEY1_ERR_NUM_V 0x7 -#define EFUSE_KEY1_ERR_NUM_S 16 -/* EFUSE_USR_DATA_FAIL : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of user data is reliable - 1: Means that programming user data failed and the number of error bytes is over 6.*/ -#define EFUSE_USR_DATA_FAIL (BIT(15)) -#define EFUSE_USR_DATA_FAIL_M (BIT(15)) -#define EFUSE_USR_DATA_FAIL_V 0x1 -#define EFUSE_USR_DATA_FAIL_S 15 -/* EFUSE_KEY0_ERR_NUM : RO ;bitpos:[14:12] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY0_ERR_NUM 0x00000007 -#define EFUSE_KEY0_ERR_NUM_M ((EFUSE_KEY0_ERR_NUM_V)<<(EFUSE_KEY0_ERR_NUM_S)) -#define EFUSE_KEY0_ERR_NUM_V 0x7 -#define EFUSE_KEY0_ERR_NUM_S 12 -/* EFUSE_SYS_PART1_FAIL : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of system part1 is reliable - 1: Means that programming data of system part1 failed and the number of error bytes is over 6.*/ -#define EFUSE_SYS_PART1_FAIL (BIT(11)) -#define EFUSE_SYS_PART1_FAIL_M (BIT(11)) -#define EFUSE_SYS_PART1_FAIL_V 0x1 -#define EFUSE_SYS_PART1_FAIL_S 11 -/* EFUSE_USR_DATA_ERR_NUM : RO ;bitpos:[10:8] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_USR_DATA_ERR_NUM 0x00000007 -#define EFUSE_USR_DATA_ERR_NUM_M ((EFUSE_USR_DATA_ERR_NUM_V)<<(EFUSE_USR_DATA_ERR_NUM_S)) -#define EFUSE_USR_DATA_ERR_NUM_V 0x7 -#define EFUSE_USR_DATA_ERR_NUM_S 8 -/* EFUSE_MAC_SPI_8M_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of MAC_SPI_8M is reliable - 1: Means that programming MAC_SPI_8M failed and the number of error bytes is over 6.*/ -#define EFUSE_MAC_SPI_8M_FAIL (BIT(7)) -#define EFUSE_MAC_SPI_8M_FAIL_M (BIT(7)) -#define EFUSE_MAC_SPI_8M_FAIL_V 0x1 -#define EFUSE_MAC_SPI_8M_FAIL_S 7 -/* EFUSE_SYS_PART1_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_SYS_PART1_NUM 0x00000007 -#define EFUSE_SYS_PART1_NUM_M ((EFUSE_SYS_PART1_NUM_V)<<(EFUSE_SYS_PART1_NUM_S)) -#define EFUSE_SYS_PART1_NUM_V 0x7 -#define EFUSE_SYS_PART1_NUM_S 4 -/* EFUSE_MAC_SPI_8M_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_MAC_SPI_8M_ERR_NUM 0x00000007 -#define EFUSE_MAC_SPI_8M_ERR_NUM_M ((EFUSE_MAC_SPI_8M_ERR_NUM_V)<<(EFUSE_MAC_SPI_8M_ERR_NUM_S)) -#define EFUSE_MAC_SPI_8M_ERR_NUM_V 0x7 +/** EFUSE_RD_RS_ERR0_REG register + * Programming error record register 0 of BLOCK1-10. + */ +#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0) +/** EFUSE_MAC_SPI_8M_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_MAC_SPI_8M_ERR_NUM 0x00000007U +#define EFUSE_MAC_SPI_8M_ERR_NUM_M (EFUSE_MAC_SPI_8M_ERR_NUM_V << EFUSE_MAC_SPI_8M_ERR_NUM_S) +#define EFUSE_MAC_SPI_8M_ERR_NUM_V 0x00000007U #define EFUSE_MAC_SPI_8M_ERR_NUM_S 0 +/** EFUSE_RESERVED_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ +#define EFUSE_RESERVED_FAIL (BIT(3)) +#define EFUSE_RESERVED_FAIL_M (EFUSE_RESERVED_FAIL_V << EFUSE_RESERVED_FAIL_S) +#define EFUSE_RESERVED_FAIL_V 0x00000001U +#define EFUSE_RESERVED_FAIL_S 3 +/** EFUSE_SYS_PART1_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_SYS_PART1_NUM 0x00000007U +#define EFUSE_SYS_PART1_NUM_M (EFUSE_SYS_PART1_NUM_V << EFUSE_SYS_PART1_NUM_S) +#define EFUSE_SYS_PART1_NUM_V 0x00000007U +#define EFUSE_SYS_PART1_NUM_S 4 +/** EFUSE_MAC_SPI_8M_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part1 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ +#define EFUSE_MAC_SPI_8M_FAIL (BIT(7)) +#define EFUSE_MAC_SPI_8M_FAIL_M (EFUSE_MAC_SPI_8M_FAIL_V << EFUSE_MAC_SPI_8M_FAIL_S) +#define EFUSE_MAC_SPI_8M_FAIL_V 0x00000001U +#define EFUSE_MAC_SPI_8M_FAIL_S 7 +/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_USR_DATA_ERR_NUM 0x00000007U +#define EFUSE_USR_DATA_ERR_NUM_M (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S) +#define EFUSE_USR_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_USR_DATA_ERR_NUM_S 8 +/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [11]; default: 0; + * 0: Means no failure and that the user data is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. + */ +#define EFUSE_SYS_PART1_FAIL (BIT(11)) +#define EFUSE_SYS_PART1_FAIL_M (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S) +#define EFUSE_SYS_PART1_FAIL_V 0x00000001U +#define EFUSE_SYS_PART1_FAIL_S 11 +/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY0_ERR_NUM 0x00000007U +#define EFUSE_KEY0_ERR_NUM_M (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S) +#define EFUSE_KEY0_ERR_NUM_V 0x00000007U +#define EFUSE_KEY0_ERR_NUM_S 12 +/** EFUSE_USR_DATA_FAIL : RO; bitpos: [15]; default: 0; + * 0: Means no failure and that the data of key0 is reliable 1: Means that programming + * key0 failed and the number of error bytes is over 6. + */ +#define EFUSE_USR_DATA_FAIL (BIT(15)) +#define EFUSE_USR_DATA_FAIL_M (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S) +#define EFUSE_USR_DATA_FAIL_V 0x00000001U +#define EFUSE_USR_DATA_FAIL_S 15 +/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY1_ERR_NUM 0x00000007U +#define EFUSE_KEY1_ERR_NUM_M (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S) +#define EFUSE_KEY1_ERR_NUM_V 0x00000007U +#define EFUSE_KEY1_ERR_NUM_S 16 +/** EFUSE_KEY0_FAIL : RO; bitpos: [19]; default: 0; + * 0: Means no failure and that the data of key1 is reliable 1: Means that programming + * key1 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY0_FAIL (BIT(19)) +#define EFUSE_KEY0_FAIL_M (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S) +#define EFUSE_KEY0_FAIL_V 0x00000001U +#define EFUSE_KEY0_FAIL_S 19 +/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY2_ERR_NUM 0x00000007U +#define EFUSE_KEY2_ERR_NUM_M (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S) +#define EFUSE_KEY2_ERR_NUM_V 0x00000007U +#define EFUSE_KEY2_ERR_NUM_S 20 +/** EFUSE_KEY1_FAIL : RO; bitpos: [23]; default: 0; + * 0: Means no failure and that the data of key2 is reliable 1: Means that programming + * key2 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY1_FAIL (BIT(23)) +#define EFUSE_KEY1_FAIL_M (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S) +#define EFUSE_KEY1_FAIL_V 0x00000001U +#define EFUSE_KEY1_FAIL_S 23 +/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY3_ERR_NUM 0x00000007U +#define EFUSE_KEY3_ERR_NUM_M (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S) +#define EFUSE_KEY3_ERR_NUM_V 0x00000007U +#define EFUSE_KEY3_ERR_NUM_S 24 +/** EFUSE_KEY2_FAIL : RO; bitpos: [27]; default: 0; + * 0: Means no failure and that the data of key3 is reliable 1: Means that programming + * key3 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY2_FAIL (BIT(27)) +#define EFUSE_KEY2_FAIL_M (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S) +#define EFUSE_KEY2_FAIL_V 0x00000001U +#define EFUSE_KEY2_FAIL_S 27 +/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY4_ERR_NUM 0x00000007U +#define EFUSE_KEY4_ERR_NUM_M (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S) +#define EFUSE_KEY4_ERR_NUM_V 0x00000007U +#define EFUSE_KEY4_ERR_NUM_S 28 +/** EFUSE_KEY3_FAIL : RO; bitpos: [31]; default: 0; + * 0: Means no failure and that the data of key4 is reliable 1: Means that programming + * key4 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY3_FAIL (BIT(31)) +#define EFUSE_KEY3_FAIL_M (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S) +#define EFUSE_KEY3_FAIL_V 0x00000001U +#define EFUSE_KEY3_FAIL_S 31 -#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1C4) -/* EFUSE_KEY5_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of KEY5 is reliable 1: - Means that programming KEY5 failed and the number of error bytes is over 6.*/ -#define EFUSE_KEY5_FAIL (BIT(7)) -#define EFUSE_KEY5_FAIL_M (BIT(7)) -#define EFUSE_KEY5_FAIL_V 0x1 -#define EFUSE_KEY5_FAIL_S 7 -/* EFUSE_SYS_PART2_ERR_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_SYS_PART2_ERR_NUM 0x00000007 -#define EFUSE_SYS_PART2_ERR_NUM_M ((EFUSE_SYS_PART2_ERR_NUM_V)<<(EFUSE_SYS_PART2_ERR_NUM_S)) -#define EFUSE_SYS_PART2_ERR_NUM_V 0x7 -#define EFUSE_SYS_PART2_ERR_NUM_S 4 -/* EFUSE_KEY4_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of KEY4 is reliable 1: - Means that programming KEY4 failed and the number of error bytes is over 6.*/ -#define EFUSE_KEY4_FAIL (BIT(3)) -#define EFUSE_KEY4_FAIL_M (BIT(3)) -#define EFUSE_KEY4_FAIL_V 0x1 -#define EFUSE_KEY4_FAIL_S 3 -/* EFUSE_KEY5_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY5_ERR_NUM 0x00000007 -#define EFUSE_KEY5_ERR_NUM_M ((EFUSE_KEY5_ERR_NUM_V)<<(EFUSE_KEY5_ERR_NUM_S)) -#define EFUSE_KEY5_ERR_NUM_V 0x7 +/** EFUSE_RD_RS_ERR1_REG register + * Programming error record register 1 of BLOCK1-10. + */ +#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4) +/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY5_ERR_NUM 0x00000007U +#define EFUSE_KEY5_ERR_NUM_M (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S) +#define EFUSE_KEY5_ERR_NUM_V 0x00000007U #define EFUSE_KEY5_ERR_NUM_S 0 +/** EFUSE_KEY4_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of KEY5 is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY4_FAIL (BIT(3)) +#define EFUSE_KEY4_FAIL_M (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S) +#define EFUSE_KEY4_FAIL_V 0x00000001U +#define EFUSE_KEY4_FAIL_S 3 +/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_SYS_PART2_ERR_NUM 0x00000007U +#define EFUSE_SYS_PART2_ERR_NUM_M (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S) +#define EFUSE_SYS_PART2_ERR_NUM_V 0x00000007U +#define EFUSE_SYS_PART2_ERR_NUM_S 4 +/** EFUSE_KEY5_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part2 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY5_FAIL (BIT(7)) +#define EFUSE_KEY5_FAIL_M (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S) +#define EFUSE_KEY5_FAIL_V 0x00000001U +#define EFUSE_KEY5_FAIL_S 7 -#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1C8) -/* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Set this bit and force to enable clock signal of eFuse memory.*/ -#define EFUSE_CLK_EN (BIT(16)) -#define EFUSE_CLK_EN_M (BIT(16)) -#define EFUSE_CLK_EN_V 0x1 -#define EFUSE_CLK_EN_S 16 -/* EFUSE_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to force eFuse SRAM into working mode.*/ -#define EFUSE_MEM_FORCE_PU (BIT(2)) -#define EFUSE_MEM_FORCE_PU_M (BIT(2)) -#define EFUSE_MEM_FORCE_PU_V 0x1 -#define EFUSE_MEM_FORCE_PU_S 2 -/* EFUSE_MEM_CLK_FORCE_ON : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: Set this bit and force to activate clock signal of eFuse SRAM.*/ -#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) -#define EFUSE_MEM_CLK_FORCE_ON_M (BIT(1)) -#define EFUSE_MEM_CLK_FORCE_ON_V 0x1 +/** EFUSE_CLK_REG register + * eFuse clcok configuration register. + */ +#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) +/** EFUSE_EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; + * Set this bit to force eFuse SRAM into power-saving mode. + */ +#define EFUSE_EFUSE_MEM_FORCE_PD (BIT(0)) +#define EFUSE_EFUSE_MEM_FORCE_PD_M (EFUSE_EFUSE_MEM_FORCE_PD_V << EFUSE_EFUSE_MEM_FORCE_PD_S) +#define EFUSE_EFUSE_MEM_FORCE_PD_V 0x00000001U +#define EFUSE_EFUSE_MEM_FORCE_PD_S 0 +/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1; + * Set this bit and force to activate clock signal of eFuse SRAM. + */ +#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) +#define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) +#define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001U #define EFUSE_MEM_CLK_FORCE_ON_S 1 -/* EFUSE_MEM_FORCE_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to force eFuse SRAM into power-saving mode.*/ -#define EFUSE_MEM_FORCE_PD (BIT(0)) -#define EFUSE_MEM_FORCE_PD_M (BIT(0)) -#define EFUSE_MEM_FORCE_PD_V 0x1 -#define EFUSE_MEM_FORCE_PD_S 0 - -#define EFUSE_WRITE_OP_CODE 0x5a5a -#define EFUSE_READ_OP_CODE 0x5aa5 - -#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1CC) -/* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: 0x5A5A: Operate programming command 0x5AA5: Operate read command.*/ -#define EFUSE_OP_CODE 0x0000FFFF -#define EFUSE_OP_CODE_M ((EFUSE_OP_CODE_V)<<(EFUSE_OP_CODE_S)) -#define EFUSE_OP_CODE_V 0xFFFF -#define EFUSE_OP_CODE_S 0 +/** EFUSE_EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; + * Set this bit to force eFuse SRAM into working mode. + */ +#define EFUSE_EFUSE_MEM_FORCE_PU (BIT(2)) +#define EFUSE_EFUSE_MEM_FORCE_PU_M (EFUSE_EFUSE_MEM_FORCE_PU_V << EFUSE_EFUSE_MEM_FORCE_PU_S) +#define EFUSE_EFUSE_MEM_FORCE_PU_V 0x00000001U +#define EFUSE_EFUSE_MEM_FORCE_PU_S 2 +/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; + * Set this bit and force to enable clock signal of eFuse memory. + */ +#define EFUSE_CLK_EN (BIT(16)) +#define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) +#define EFUSE_CLK_EN_V 0x00000001U +#define EFUSE_CLK_EN_S 16 -#define EFUSE_WRITE_OP_CODE 0x5a5a -#define EFUSE_READ_OP_CODE 0x5aa5 +/** EFUSE_CONF_REG register + * eFuse operation mode configuraiton register; + */ +#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) +/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; + * 0x5A5A: Operate programming command 0x5AA5: Operate read command. + */ +#define EFUSE_OP_CODE 0x0000FFFFU +#define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) +#define EFUSE_OP_CODE_V 0x0000FFFFU +#define EFUSE_OP_CODE_S 0 -#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1D0) -/* EFUSE_REPEAT_ERR_CNT : RO ;bitpos:[17:10] ;default: 8'h0 ; */ -/*description: Indicates the number of error bits during programming BLOCK0.*/ -#define EFUSE_REPEAT_ERR_CNT 0x000000FF -#define EFUSE_REPEAT_ERR_CNT_M ((EFUSE_REPEAT_ERR_CNT_V)<<(EFUSE_REPEAT_ERR_CNT_S)) -#define EFUSE_REPEAT_ERR_CNT_V 0xFF -#define EFUSE_REPEAT_ERR_CNT_S 10 -/* EFUSE_OTP_VDDQ_IS_SW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The value of OTP_VDDQ_IS_SW.*/ -#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) -#define EFUSE_OTP_VDDQ_IS_SW_M (BIT(9)) -#define EFUSE_OTP_VDDQ_IS_SW_V 0x1 -#define EFUSE_OTP_VDDQ_IS_SW_S 9 -/* EFUSE_OTP_PGENB_SW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The value of OTP_PGENB_SW.*/ -#define EFUSE_OTP_PGENB_SW (BIT(8)) -#define EFUSE_OTP_PGENB_SW_M (BIT(8)) -#define EFUSE_OTP_PGENB_SW_V 0x1 -#define EFUSE_OTP_PGENB_SW_S 8 -/* EFUSE_OTP_CSB_SW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The value of OTP_CSB_SW.*/ -#define EFUSE_OTP_CSB_SW (BIT(7)) -#define EFUSE_OTP_CSB_SW_M (BIT(7)) -#define EFUSE_OTP_CSB_SW_V 0x1 -#define EFUSE_OTP_CSB_SW_S 7 -/* EFUSE_OTP_STROBE_SW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The value of OTP_STROBE_SW.*/ -#define EFUSE_OTP_STROBE_SW (BIT(6)) -#define EFUSE_OTP_STROBE_SW_M (BIT(6)) -#define EFUSE_OTP_STROBE_SW_V 0x1 -#define EFUSE_OTP_STROBE_SW_S 6 -/* EFUSE_OTP_VDDQ_C_SYNC2 : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The value of OTP_VDDQ_C_SYNC2.*/ -#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) -#define EFUSE_OTP_VDDQ_C_SYNC2_M (BIT(5)) -#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x1 -#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 -/* EFUSE_OTP_LOAD_SW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The value of OTP_LOAD_SW.*/ -#define EFUSE_OTP_LOAD_SW (BIT(4)) -#define EFUSE_OTP_LOAD_SW_M (BIT(4)) -#define EFUSE_OTP_LOAD_SW_V 0x1 -#define EFUSE_OTP_LOAD_SW_S 4 -/* EFUSE_STATE : RO ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: Indicates the state of the eFuse state machine.*/ -#define EFUSE_STATE 0x0000000F -#define EFUSE_STATE_M ((EFUSE_STATE_V)<<(EFUSE_STATE_S)) -#define EFUSE_STATE_V 0xF +/** EFUSE_STATUS_REG register + * eFuse status register. + */ +#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0) +/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0; + * Indicates the state of the eFuse state machine. + */ +#define EFUSE_STATE 0x0000000FU +#define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) +#define EFUSE_STATE_V 0x0000000FU #define EFUSE_STATE_S 0 +/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0; + * The value of OTP_LOAD_SW. + */ +#define EFUSE_OTP_LOAD_SW (BIT(4)) +#define EFUSE_OTP_LOAD_SW_M (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S) +#define EFUSE_OTP_LOAD_SW_V 0x00000001U +#define EFUSE_OTP_LOAD_SW_S 4 +/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0; + * The value of OTP_VDDQ_C_SYNC2. + */ +#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) +#define EFUSE_OTP_VDDQ_C_SYNC2_M (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S) +#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x00000001U +#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 +/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0; + * The value of OTP_STROBE_SW. + */ +#define EFUSE_OTP_STROBE_SW (BIT(6)) +#define EFUSE_OTP_STROBE_SW_M (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S) +#define EFUSE_OTP_STROBE_SW_V 0x00000001U +#define EFUSE_OTP_STROBE_SW_S 6 +/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0; + * The value of OTP_CSB_SW. + */ +#define EFUSE_OTP_CSB_SW (BIT(7)) +#define EFUSE_OTP_CSB_SW_M (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S) +#define EFUSE_OTP_CSB_SW_V 0x00000001U +#define EFUSE_OTP_CSB_SW_S 7 +/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0; + * The value of OTP_PGENB_SW. + */ +#define EFUSE_OTP_PGENB_SW (BIT(8)) +#define EFUSE_OTP_PGENB_SW_M (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S) +#define EFUSE_OTP_PGENB_SW_V 0x00000001U +#define EFUSE_OTP_PGENB_SW_S 8 +/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0; + * The value of OTP_VDDQ_IS_SW. + */ +#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) +#define EFUSE_OTP_VDDQ_IS_SW_M (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S) +#define EFUSE_OTP_VDDQ_IS_SW_V 0x00000001U +#define EFUSE_OTP_VDDQ_IS_SW_S 9 +/** EFUSE_REPEAT_ERR_CNT : RO; bitpos: [17:10]; default: 0; + * Indicates the number of error bits during programming BLOCK0. + */ +#define EFUSE_REPEAT_ERR_CNT 0x000000FFU +#define EFUSE_REPEAT_ERR_CNT_M (EFUSE_REPEAT_ERR_CNT_V << EFUSE_REPEAT_ERR_CNT_S) +#define EFUSE_REPEAT_ERR_CNT_V 0x000000FFU +#define EFUSE_REPEAT_ERR_CNT_S 10 -#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1D4) -/* EFUSE_BLK_NUM : R/W ;bitpos:[5:2] ;default: 4'h0 ; */ -/*description: The serial number of the block to be programmed. Value 0-10 corresponds - to block number 0-10 respectively.*/ -#define EFUSE_BLK_NUM 0x0000000F -#define EFUSE_BLK_NUM_M ((EFUSE_BLK_NUM_V)<<(EFUSE_BLK_NUM_S)) -#define EFUSE_BLK_NUM_V 0xF -#define EFUSE_BLK_NUM_S 2 -/* EFUSE_PGM_CMD : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to send programming command.*/ -#define EFUSE_PGM_CMD (BIT(1)) -#define EFUSE_PGM_CMD_M (BIT(1)) -#define EFUSE_PGM_CMD_V 0x1 -#define EFUSE_PGM_CMD_S 1 -/* EFUSE_READ_CMD : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to send read command.*/ -#define EFUSE_READ_CMD (BIT(0)) -#define EFUSE_READ_CMD_M (BIT(0)) -#define EFUSE_READ_CMD_V 0x1 +/** EFUSE_CMD_REG register + * eFuse command register. + */ +#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4) +/** EFUSE_READ_CMD : R/WS/SC; bitpos: [0]; default: 0; + * Set this bit to send read command. + */ +#define EFUSE_READ_CMD (BIT(0)) +#define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) +#define EFUSE_READ_CMD_V 0x00000001U #define EFUSE_READ_CMD_S 0 +/** EFUSE_PGM_CMD : R/WS/SC; bitpos: [1]; default: 0; + * Set this bit to send programming command. + */ +#define EFUSE_PGM_CMD (BIT(1)) +#define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) +#define EFUSE_PGM_CMD_V 0x00000001U +#define EFUSE_PGM_CMD_S 1 +/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0; + * The serial number of the block to be programmed. Value 0-10 corresponds to block + * number 0-10, respectively. + */ +#define EFUSE_BLK_NUM 0x0000000FU +#define EFUSE_BLK_NUM_M (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S) +#define EFUSE_BLK_NUM_V 0x0000000FU +#define EFUSE_BLK_NUM_S 2 -#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1D8) -/* EFUSE_PGM_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw bit signal for pgm_done interrupt.*/ -#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) -#define EFUSE_PGM_DONE_INT_RAW_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_RAW_V 0x1 -#define EFUSE_PGM_DONE_INT_RAW_S 1 -/* EFUSE_READ_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw bit signal for read_done interrupt.*/ -#define EFUSE_READ_DONE_INT_RAW (BIT(0)) -#define EFUSE_READ_DONE_INT_RAW_M (BIT(0)) -#define EFUSE_READ_DONE_INT_RAW_V 0x1 +/** EFUSE_INT_RAW_REG register + * eFuse raw interrupt register. + */ +#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8) +/** EFUSE_READ_DONE_INT_RAW : R/WC/SS; bitpos: [0]; default: 0; + * The raw bit signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_RAW (BIT(0)) +#define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) +#define EFUSE_READ_DONE_INT_RAW_V 0x00000001U #define EFUSE_READ_DONE_INT_RAW_S 0 +/** EFUSE_PGM_DONE_INT_RAW : R/WC/SS; bitpos: [1]; default: 0; + * The raw bit signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) +#define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) +#define EFUSE_PGM_DONE_INT_RAW_V 0x00000001U +#define EFUSE_PGM_DONE_INT_RAW_S 1 -#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1DC) -/* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The status signal for pgm_done interrupt.*/ -#define EFUSE_PGM_DONE_INT_ST (BIT(1)) -#define EFUSE_PGM_DONE_INT_ST_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_ST_V 0x1 -#define EFUSE_PGM_DONE_INT_ST_S 1 -/* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The status signal for read_done interrupt.*/ -#define EFUSE_READ_DONE_INT_ST (BIT(0)) -#define EFUSE_READ_DONE_INT_ST_M (BIT(0)) -#define EFUSE_READ_DONE_INT_ST_V 0x1 +/** EFUSE_INT_ST_REG register + * eFuse interrupt status register. + */ +#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc) +/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The status signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_ST (BIT(0)) +#define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) +#define EFUSE_READ_DONE_INT_ST_V 0x00000001U #define EFUSE_READ_DONE_INT_ST_S 0 +/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The status signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_ST (BIT(1)) +#define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) +#define EFUSE_PGM_DONE_INT_ST_V 0x00000001U +#define EFUSE_PGM_DONE_INT_ST_S 1 -#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1E0) -/* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The enable signal for pgm_done interrupt.*/ -#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) -#define EFUSE_PGM_DONE_INT_ENA_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_ENA_V 0x1 -#define EFUSE_PGM_DONE_INT_ENA_S 1 -/* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The enable signal for read_done interrupt.*/ -#define EFUSE_READ_DONE_INT_ENA (BIT(0)) -#define EFUSE_READ_DONE_INT_ENA_M (BIT(0)) -#define EFUSE_READ_DONE_INT_ENA_V 0x1 +/** EFUSE_INT_ENA_REG register + * eFuse interrupt enable register. + */ +#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0) +/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_ENA (BIT(0)) +#define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) +#define EFUSE_READ_DONE_INT_ENA_V 0x00000001U #define EFUSE_READ_DONE_INT_ENA_S 0 +/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) +#define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) +#define EFUSE_PGM_DONE_INT_ENA_V 0x00000001U +#define EFUSE_PGM_DONE_INT_ENA_S 1 -#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1E4) -/* EFUSE_PGM_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The clear signal for pgm_done interrupt.*/ -#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) -#define EFUSE_PGM_DONE_INT_CLR_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_CLR_V 0x1 -#define EFUSE_PGM_DONE_INT_CLR_S 1 -/* EFUSE_READ_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The clear signal for read_done interrupt.*/ -#define EFUSE_READ_DONE_INT_CLR (BIT(0)) -#define EFUSE_READ_DONE_INT_CLR_M (BIT(0)) -#define EFUSE_READ_DONE_INT_CLR_V 0x1 +/** EFUSE_INT_CLR_REG register + * eFuse interrupt clear register. + */ +#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4) +/** EFUSE_READ_DONE_INT_CLR : WO; bitpos: [0]; default: 0; + * The clear signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_CLR (BIT(0)) +#define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) +#define EFUSE_READ_DONE_INT_CLR_V 0x00000001U #define EFUSE_READ_DONE_INT_CLR_S 0 +/** EFUSE_PGM_DONE_INT_CLR : WO; bitpos: [1]; default: 0; + * The clear signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) +#define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) +#define EFUSE_PGM_DONE_INT_CLR_V 0x00000001U +#define EFUSE_PGM_DONE_INT_CLR_S 1 -#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1E8) -/* EFUSE_OE_CLR : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: Reduces the power supply of the programming voltage.*/ -#define EFUSE_OE_CLR (BIT(17)) -#define EFUSE_OE_CLR_M (BIT(17)) -#define EFUSE_OE_CLR_V 0x1 -#define EFUSE_OE_CLR_S 17 -/* EFUSE_DAC_NUM : R/W ;bitpos:[16:9] ;default: 8'd255 ; */ -/*description: Controls the rising period of the programming voltage.*/ -#define EFUSE_DAC_NUM 0x000000FF -#define EFUSE_DAC_NUM_M ((EFUSE_DAC_NUM_V)<<(EFUSE_DAC_NUM_S)) -#define EFUSE_DAC_NUM_V 0xFF -#define EFUSE_DAC_NUM_S 9 -/* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Don't care.*/ -#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) -#define EFUSE_DAC_CLK_PAD_SEL_M (BIT(8)) -#define EFUSE_DAC_CLK_PAD_SEL_V 0x1 -#define EFUSE_DAC_CLK_PAD_SEL_S 8 -/* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd28 ; */ -/*description: Controls the division factor of the rising clock of the programming voltage.*/ -#define EFUSE_DAC_CLK_DIV 0x000000FF -#define EFUSE_DAC_CLK_DIV_M ((EFUSE_DAC_CLK_DIV_V)<<(EFUSE_DAC_CLK_DIV_S)) -#define EFUSE_DAC_CLK_DIV_V 0xFF +/** EFUSE_DAC_CONF_REG register + * Controls the eFuse programming voltage. + */ +#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8) +/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 28; + * Controls the division factor of the rising clock of the programming voltage. + */ +#define EFUSE_DAC_CLK_DIV 0x000000FFU +#define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) +#define EFUSE_DAC_CLK_DIV_V 0x000000FFU #define EFUSE_DAC_CLK_DIV_S 0 +/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0; + * Don't care. + */ +#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) +#define EFUSE_DAC_CLK_PAD_SEL_M (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S) +#define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001U +#define EFUSE_DAC_CLK_PAD_SEL_S 8 +/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ +#define EFUSE_DAC_NUM 0x000000FFU +#define EFUSE_DAC_NUM_M (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S) +#define EFUSE_DAC_NUM_V 0x000000FFU +#define EFUSE_DAC_NUM_S 9 +/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ +#define EFUSE_OE_CLR (BIT(17)) +#define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) +#define EFUSE_OE_CLR_V 0x00000001U +#define EFUSE_OE_CLR_S 17 -#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1EC) -/* EFUSE_READ_INIT_NUM : R/W ;bitpos:[31:24] ;default: 8'h12 ; */ -/*description: Configures the initial read time of eFuse.*/ -#define EFUSE_READ_INIT_NUM 0x000000FF -#define EFUSE_READ_INIT_NUM_M ((EFUSE_READ_INIT_NUM_V)<<(EFUSE_READ_INIT_NUM_S)) -#define EFUSE_READ_INIT_NUM_V 0xFF +/** EFUSE_RD_TIM_CONF_REG register + * Configures read timing parameters. + */ +#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) +/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18; + * Configures the initial read time of eFuse. + */ +#define EFUSE_READ_INIT_NUM 0x000000FFU +#define EFUSE_READ_INIT_NUM_M (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S) +#define EFUSE_READ_INIT_NUM_V 0x000000FFU #define EFUSE_READ_INIT_NUM_S 24 -#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1F0) -/* EFUSE_PWR_ON_NUM : R/W ;bitpos:[23:8] ;default: 16'h2880 ; */ -/*description: Configures the power up time for VDDQ.*/ -#define EFUSE_PWR_ON_NUM 0x0000FFFF -#define EFUSE_PWR_ON_NUM_M ((EFUSE_PWR_ON_NUM_V)<<(EFUSE_PWR_ON_NUM_S)) -#define EFUSE_PWR_ON_NUM_V 0xFFFF +/** EFUSE_WR_TIM_CONF1_REG register + * Configurarion register 1 of eFuse programming timing parameters. + */ +#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f0) +/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 10368; + * Configures the power up time for VDDQ. + */ +#define EFUSE_PWR_ON_NUM 0x0000FFFFU +#define EFUSE_PWR_ON_NUM_M (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S) +#define EFUSE_PWR_ON_NUM_V 0x0000FFFFU #define EFUSE_PWR_ON_NUM_S 8 -#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1F4) -/* EFUSE_PWR_OFF_NUM : R/W ;bitpos:[15:0] ;default: 16'h190 ; */ -/*description: Configures the power outage time for VDDQ.*/ -#define EFUSE_PWR_OFF_NUM 0x0000FFFF -#define EFUSE_PWR_OFF_NUM_M ((EFUSE_PWR_OFF_NUM_V)<<(EFUSE_PWR_OFF_NUM_S)) -#define EFUSE_PWR_OFF_NUM_V 0xFFFF +/** EFUSE_WR_TIM_CONF2_REG register + * Configurarion register 2 of eFuse programming timing parameters. + */ +#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f4) +/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400; + * Configures the power outage time for VDDQ. + */ +#define EFUSE_PWR_OFF_NUM 0x0000FFFFU +#define EFUSE_PWR_OFF_NUM_M (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S) +#define EFUSE_PWR_OFF_NUM_V 0x0000FFFFU #define EFUSE_PWR_OFF_NUM_S 0 -#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1FC) -/* EFUSE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007200 ; */ -/*description: Stores eFuse version.*/ -#define EFUSE_DATE 0x0FFFFFFF -#define EFUSE_DATE_M ((EFUSE_DATE_V)<<(EFUSE_DATE_S)) -#define EFUSE_DATE_V 0xFFFFFFF +/** EFUSE_DATE_REG register + * eFuse version register. + */ +#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) +/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 33583616; + * Stores eFuse version. + */ +#define EFUSE_DATE 0x0FFFFFFFU +#define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S) +#define EFUSE_DATE_V 0x0FFFFFFFU #define EFUSE_DATE_S 0 #ifdef __cplusplus } #endif - - - -#endif /*_SOC_EFUSE_REG_H_ */ diff --git a/tools/sdk/esp32c3/include/soc/esp32c3/include/soc/efuse_struct.h b/tools/sdk/esp32c3/include/soc/esp32c3/include/soc/efuse_struct.h index 230064321e7..459c5483deb 100644 --- a/tools/sdk/esp32c3/include/soc/esp32c3/include/soc/efuse_struct.h +++ b/tools/sdk/esp32c3/include/soc/esp32c3/include/soc/efuse_struct.h @@ -1,532 +1,2378 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once #include - #ifdef __cplusplus extern "C" { #endif -typedef volatile struct efuse_dev_s { - uint32_t pgm_data0; /*Register 0 that stores data to be programmed.*/ - union { - struct { - uint32_t rd_dis: 7; /*Set this bit to disable reading from BlOCK4-10.*/ - uint32_t rpt4_reserved5: 1; /*Reserved*/ - uint32_t dis_icache: 1; /*Set this bit to disable Icache.*/ - uint32_t dis_usb_jtag: 1; /*Set this bit to disable function of usb switch to jtag in module of usb device.*/ - uint32_t dis_download_icache: 1; /*Set this bit to disable Icache in download mode (boot_mode[3:0] is 0 1 2 3 6 7).*/ - uint32_t dis_usb_device: 1; /*Set this bit to disable usb device.*/ - uint32_t dis_force_download: 1; /*Set this bit to disable the function that forces chip into download mode.*/ - uint32_t dis_usb: 1; /*Set this bit to disable USB function.*/ - uint32_t dis_can: 1; /*Set this bit to disable CAN function.*/ - uint32_t jtag_sel_enable: 1; /*Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.*/ - uint32_t soft_dis_jtag: 3; /*Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module.*/ - uint32_t dis_pad_jtag: 1; /*Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.*/ - uint32_t dis_download_manual_encrypt: 1; /*Set this bit to disable flash encryption when in download boot modes.*/ - uint32_t usb_drefh: 2; /*Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse.*/ - uint32_t usb_drefl: 2; /*Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse.*/ - uint32_t usb_exchg_pins: 1; /*Set this bit to exchange USB D+ and D- pins.*/ - uint32_t vdd_spi_as_gpio: 1; /*Set this bit to vdd spi pin function as gpio.*/ - uint32_t btlc_gpio_enable: 2; /*Enable btlc gpio.*/ - uint32_t powerglitch_en: 1; /*Set this bit to enable power glitch function.*/ - uint32_t power_glitch_dsense: 2; /*Sample delay configuration of power glitch.*/ - }; - uint32_t val; - } pgm_data1; - union { - struct { - uint32_t rpt4_reserved2: 16; /*Reserved (used for four backups method).*/ - uint32_t wat_delay_sel: 2; /*Selects RTC watchdog timeout threshold in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.*/ - uint32_t spi_boot_crypt_cnt: 3; /*Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable.*/ - uint32_t secure_boot_key_revoke0: 1; /*Set this bit to enable revoking first secure boot key.*/ - uint32_t secure_boot_key_revoke1: 1; /*Set this bit to enable revoking second secure boot key.*/ - uint32_t secure_boot_key_revoke2: 1; /*Set this bit to enable revoking third secure boot key.*/ - uint32_t key_purpose_0: 4; /*Purpose of Key0.*/ - uint32_t key_purpose_1: 4; /*Purpose of Key1.*/ - }; - uint32_t val; - } pgm_data2; - union { - struct { - uint32_t key_purpose_2: 4; /*Purpose of Key2.*/ - uint32_t key_purpose_3: 4; /*Purpose of Key3.*/ - uint32_t key_purpose_4: 4; /*Purpose of Key4.*/ - uint32_t key_purpose_5: 4; /*Purpose of Key5.*/ - uint32_t rpt4_reserved3: 4; /*Reserved (used for four backups method).*/ - uint32_t secure_boot_en: 1; /*Set this bit to enable secure boot.*/ - uint32_t secure_boot_aggressive_revoke: 1; /*Set this bit to enable revoking aggressive secure boot.*/ - uint32_t rpt4_reserved0: 6; /*Reserved (used for four backups method).*/ - uint32_t flash_tpuw: 4; /*Configures flash waiting time after power-up in unit of ms. If the value is less than 15 the waiting time is the configurable value*/ - }; - uint32_t val; - } pgm_data3; - union { - struct { - uint32_t dis_download_mode: 1; /*Set this bit to disable download mode (boot_mode[3:0] = 0 1 2 3 6 7).*/ - uint32_t dis_direct_boot: 1; /*Set this bit to disable direct boot.*/ - uint32_t dis_usb_serial_jtag_rom_print: 1; /*Set this bit to disable USB-Serial-JTAG print during rom boot*/ - uint32_t rpt4_reserved8: 1; /*Reserved (used for four backups method).*/ - uint32_t dis_usb_serial_jtag_download_mode: 1; /*Set this bit to disable download mode through USB-Serial-JTAG.*/ - uint32_t enable_security_download: 1; /*Set this bit to enable secure UART download mode.*/ - uint32_t uart_print_control: 2; /*Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.*/ - uint32_t rpt4_reserved7: 5; /*Reserved (used for four backups method).*/ - uint32_t force_send_resume: 1; /*Set this bit to force ROM code to send a resume command during SPI boot.*/ - uint32_t secure_version: 16; /*Secure version (used by ESP-IDF anti-rollback feature).*/ - uint32_t rpt4_reserved1: 1; /*Reserved (used for four backups method).*/ - uint32_t err_rst_enable: 1; /*Use BLOCK0 to check error record registers, 0 - without check.*/ - }; - uint32_t val; - } pgm_data4; - union { - struct { - uint32_t rpt4_reserved4:24; /*Reserved (used for four backups method).*/ - uint32_t reserved24: 8; /*Reserved.*/ - }; - uint32_t val; - } pgm_data5; - uint32_t pgm_data6; /*Register 6 that stores data to be programmed.*/ - uint32_t pgm_data7; /*Register 7 that stores data to be programmed.*/ - uint32_t pgm_check_value0; /*Register 0 that stores the RS code to be programmed.*/ - uint32_t pgm_check_value1; /*Register 1 that stores the RS code to be programmed.*/ - uint32_t pgm_check_value2; /*Register 2 that stores the RS code to be programmed.*/ - uint32_t rd_wr_dis; /*BLOCK0 data register $n.*/ - union { - struct { - uint32_t rd_dis: 7; /*The value of RD_DIS.*/ - uint32_t rpt4_reserved5: 1; /*Reserved*/ - uint32_t dis_icache: 1; /*The value of DIS_ICACHE.*/ - uint32_t dis_usb_jtag: 1; /*The value of DIS_USB_JTAG.*/ - uint32_t dis_download_icache: 1; /*The value of DIS_DOWNLOAD_ICACHE.*/ - uint32_t dis_usb_device: 1; /*The value of DIS_USB_DEVICE.*/ - uint32_t dis_force_download: 1; /*The value of DIS_FORCE_DOWNLOAD.*/ - uint32_t dis_usb: 1; /*The value of DIS_USB.*/ - uint32_t dis_can: 1; /*The value of DIS_CAN.*/ - uint32_t jtag_sel_enable: 1; /*The value of JTAG_SEL_ENABLE.*/ - uint32_t soft_dis_jtag: 3; /*The value of SOFT_DIS_JTAG.*/ - uint32_t dis_pad_jtag: 1; /*The value of DIS_PAD_JTAG.*/ - uint32_t dis_download_manual_encrypt: 1; /*The value of DIS_DOWNLOAD_MANUAL_ENCRYPT.*/ - uint32_t usb_drefh: 2; /*The value of USB_DREFH.*/ - uint32_t usb_drefl: 2; /*The value of USB_DREFL.*/ - uint32_t usb_exchg_pins: 1; /*The value of USB_EXCHG_PINS.*/ - uint32_t vdd_spi_as_gpio: 1; /*The value of VDD_SPI_AS_GPIO.*/ - uint32_t btlc_gpio_enable: 2; /*The value of BTLC_GPIO_ENABLE.*/ - uint32_t powerglitch_en: 1; /*The value of POWERGLITCH_EN.*/ - uint32_t power_glitch_dsense: 2; /*The value of POWER_GLITCH_DSENSE.*/ - }; - uint32_t val; - } rd_repeat_data0; - union { - struct { - uint32_t rpt4_reserved2: 16; /*Reserved.*/ - uint32_t wdt_delay_sel: 2; /*The value of WDT_DELAY_SEL.*/ - uint32_t spi_boot_crypt_cnt: 3; /*The value of SPI_BOOT_CRYPT_CNT.*/ - uint32_t secure_boot_key_revoke0: 1; /*The value of SECURE_BOOT_KEY_REVOKE0.*/ - uint32_t secure_boot_key_revoke1: 1; /*The value of SECURE_BOOT_KEY_REVOKE1.*/ - uint32_t secure_boot_key_revoke2: 1; /*The value of SECURE_BOOT_KEY_REVOKE2.*/ - uint32_t key_purpose_0: 4; /*The value of KEY_PURPOSE_0.*/ - uint32_t key_purpose_1: 4; /*The value of KEY_PURPOSE_1.*/ - }; - uint32_t val; - } rd_repeat_data1; - union { - struct { - uint32_t key_purpose_2: 4; /*The value of KEY_PURPOSE_2.*/ - uint32_t key_purpose_3: 4; /*The value of KEY_PURPOSE_3.*/ - uint32_t key_purpose_4: 4; /*The value of KEY_PURPOSE_4.*/ - uint32_t key_purpose_5: 4; /*The value of KEY_PURPOSE_5.*/ - uint32_t rpt4_reserved3: 4; /*Reserved.*/ - uint32_t secure_boot_en: 1; /*The value of SECURE_BOOT_EN.*/ - uint32_t secure_boot_aggressive_revoke: 1; /*The value of SECURE_BOOT_AGGRESSIVE_REVOKE.*/ - uint32_t rpt4_reserved0: 6; /*Reserved.*/ - uint32_t flash_tpuw: 4; /*The value of FLASH_TPUW.*/ - }; - uint32_t val; - } rd_repeat_data2; - union { - struct { - uint32_t dis_download_mode: 1; /*The value of DIS_DOWNLOAD_MODE.*/ - uint32_t dis_direct_boot: 1; /*The value of DIS_DIRECT_BOOT.*/ - uint32_t dis_usb_serial_jtag_rom_print:1; /*The value of DIS_USB_SERIAL_JTAG_ROM_PRINT.*/ - uint32_t rpt4_reserved8: 1; /*Reserved.*/ - uint32_t dis_usb_serial_jtag_download_mode: 1; /*The value of dis_usb_serial_jtag_download_mode.*/ - uint32_t enable_security_download: 1; /*The value of ENABLE_SECURITY_DOWNLOAD.*/ - uint32_t uart_print_control: 2; /*The value of UART_PRINT_CONTROL.*/ - uint32_t rpt4_reserved7: 5; /*Reserved.*/ - uint32_t force_send_resume: 1; /*The value of FORCE_SEND_RESUME.*/ - uint32_t secure_version: 16; /*The value of SECURE_VERSION.*/ - uint32_t rpt4_reserved1: 1; /*Reserved.*/ - uint32_t err_rst_enable: 1; /*Use BLOCK0 to check error record registers, 0 - without check.*/ - }; - uint32_t val; - } rd_repeat_data3; - union { - struct { - uint32_t disable_wafer_version_major: 1; - uint32_t disable_blk_version_major: 1; - uint32_t rpt4_reserved4:22; /*Reserved.*/ - uint32_t reserved24: 8; /*Reserved.*/ - }; - uint32_t val; - } rd_repeat_data4; - uint32_t rd_mac_spi_sys_0; /*BLOCK1 data register $n.*/ - union { - struct { - uint32_t mac_1: 16; /*Stores the high 16 bits of MAC address.*/ - uint32_t spi_pad_conf_0:16; /*Stores the zeroth part of SPI_PAD_CONF.*/ - }; - uint32_t val; - } rd_mac_spi_sys_1; - uint32_t rd_mac_spi_sys_2; /*BLOCK1 data register $n.*/ - union { - struct { - uint32_t spi_pad_conf_2: 18; /*Stores the second part of SPI_PAD_CONF.*/ - uint32_t wafer_version_minor_low: 3; - uint32_t pkg_version: 3; - uint32_t blk_version_minor:3; - uint32_t sys_data_part0_0: 5; - }; - uint32_t val; - } rd_mac_spi_sys_3; - union { - struct { - uint32_t reserved1: 7; - uint32_t k_rtc_ldo: 7; - uint32_t k_dig_ldo: 7; - uint32_t v_rtc_dbias20: 8; - uint32_t v_dig_dbias20_low: 3; - }; - uint32_t val; - } rd_mac_spi_sys_4; /*BLOCK1 data register $n.*/ - union { - struct { - uint32_t v_dig_dbias20_hi: 5; - uint32_t dig_dbias_hvt: 5; - uint32_t reserved1: 13; - uint32_t wafer_version_minor_high: 1; - uint32_t wafer_version_major: 2; - uint32_t reserved2: 6; - }; - uint32_t val; - } rd_mac_spi_sys_5; /*BLOCK1 data register $n.*/ - uint32_t rd_sys_part1_data0; /*Register $n of BLOCK2 (system).*/ - uint32_t rd_sys_part1_data1; /*Register $n of BLOCK2 (system).*/ - uint32_t rd_sys_part1_data2; /*Register $n of BLOCK2 (system).*/ - uint32_t rd_sys_part1_data3; /*Register $n of BLOCK2 (system).*/ - union { - struct { - uint32_t blk_version_major: 2; - uint32_t reserved1: 10; - uint32_t ocode: 8; - uint32_t reserved2: 12; - }; - uint32_t val; - } rd_sys_part1_data4; /*Register $n of BLOCK2 (system).*/ - uint32_t rd_sys_part1_data5; /*Register $n of BLOCK2 (system).*/ - uint32_t rd_sys_part1_data6; /*Register $n of BLOCK2 (system).*/ - uint32_t rd_sys_part1_data7; /*Register $n of BLOCK2 (system).*/ - uint32_t rd_usr_data0; /*Register $n of BLOCK3 (user).*/ - uint32_t rd_usr_data1; /*Register $n of BLOCK3 (user).*/ - uint32_t rd_usr_data2; /*Register $n of BLOCK3 (user).*/ - uint32_t rd_usr_data3; /*Register $n of BLOCK3 (user).*/ - uint32_t rd_usr_data4; /*Register $n of BLOCK3 (user).*/ - uint32_t rd_usr_data5; /*Register $n of BLOCK3 (user).*/ - uint32_t rd_usr_data6; /*Register $n of BLOCK3 (user).*/ - uint32_t rd_usr_data7; /*Register $n of BLOCK3 (user).*/ - uint32_t rd_key0_data0; /*Register $n of BLOCK4 (KEY0).*/ - uint32_t rd_key0_data1; /*Register $n of BLOCK4 (KEY0).*/ - uint32_t rd_key0_data2; /*Register $n of BLOCK4 (KEY0).*/ - uint32_t rd_key0_data3; /*Register $n of BLOCK4 (KEY0).*/ - uint32_t rd_key0_data4; /*Register $n of BLOCK4 (KEY0).*/ - uint32_t rd_key0_data5; /*Register $n of BLOCK4 (KEY0).*/ - uint32_t rd_key0_data6; /*Register $n of BLOCK4 (KEY0).*/ - uint32_t rd_key0_data7; /*Register $n of BLOCK4 (KEY0).*/ - uint32_t rd_key1_data0; /*Register $n of BLOCK5 (KEY1).*/ - uint32_t rd_key1_data1; /*Register $n of BLOCK5 (KEY1).*/ - uint32_t rd_key1_data2; /*Register $n of BLOCK5 (KEY1).*/ - uint32_t rd_key1_data3; /*Register $n of BLOCK5 (KEY1).*/ - uint32_t rd_key1_data4; /*Register $n of BLOCK5 (KEY1).*/ - uint32_t rd_key1_data5; /*Register $n of BLOCK5 (KEY1).*/ - uint32_t rd_key1_data6; /*Register $n of BLOCK5 (KEY1).*/ - uint32_t rd_key1_data7; /*Register $n of BLOCK5 (KEY1).*/ - uint32_t rd_key2_data0; /*Register $n of BLOCK6 (KEY2).*/ - uint32_t rd_key2_data1; /*Register $n of BLOCK6 (KEY2).*/ - uint32_t rd_key2_data2; /*Register $n of BLOCK6 (KEY2).*/ - uint32_t rd_key2_data3; /*Register $n of BLOCK6 (KEY2).*/ - uint32_t rd_key2_data4; /*Register $n of BLOCK6 (KEY2).*/ - uint32_t rd_key2_data5; /*Register $n of BLOCK6 (KEY2).*/ - uint32_t rd_key2_data6; /*Register $n of BLOCK6 (KEY2).*/ - uint32_t rd_key2_data7; /*Register $n of BLOCK6 (KEY2).*/ - uint32_t rd_key3_data0; /*Register $n of BLOCK7 (KEY3).*/ - uint32_t rd_key3_data1; /*Register $n of BLOCK7 (KEY3).*/ - uint32_t rd_key3_data2; /*Register $n of BLOCK7 (KEY3).*/ - uint32_t rd_key3_data3; /*Register $n of BLOCK7 (KEY3).*/ - uint32_t rd_key3_data4; /*Register $n of BLOCK7 (KEY3).*/ - uint32_t rd_key3_data5; /*Register $n of BLOCK7 (KEY3).*/ - uint32_t rd_key3_data6; /*Register $n of BLOCK7 (KEY3).*/ - uint32_t rd_key3_data7; /*Register $n of BLOCK7 (KEY3).*/ - uint32_t rd_key4_data0; /*Register $n of BLOCK8 (KEY4).*/ - uint32_t rd_key4_data1; /*Register $n of BLOCK8 (KEY4).*/ - uint32_t rd_key4_data2; /*Register $n of BLOCK8 (KEY4).*/ - uint32_t rd_key4_data3; /*Register $n of BLOCK8 (KEY4).*/ - uint32_t rd_key4_data4; /*Register $n of BLOCK8 (KEY4).*/ - uint32_t rd_key4_data5; /*Register $n of BLOCK8 (KEY4).*/ - uint32_t rd_key4_data6; /*Register $n of BLOCK8 (KEY4).*/ - uint32_t rd_key4_data7; /*Register $n of BLOCK8 (KEY4).*/ - uint32_t rd_key5_data0; /*Register $n of BLOCK9 (KEY5).*/ - uint32_t rd_key5_data1; /*Register $n of BLOCK9 (KEY5).*/ - uint32_t rd_key5_data2; /*Register $n of BLOCK9 (KEY5).*/ - uint32_t rd_key5_data3; /*Register $n of BLOCK9 (KEY5).*/ - uint32_t rd_key5_data4; /*Register $n of BLOCK9 (KEY5).*/ - uint32_t rd_key5_data5; /*Register $n of BLOCK9 (KEY5).*/ - uint32_t rd_key5_data6; /*Register $n of BLOCK9 (KEY5).*/ - uint32_t rd_key5_data7; /*Register $n of BLOCK9 (KEY5).*/ - uint32_t rd_sys_part2_data0; /*Register $n of BLOCK10 (system).*/ - uint32_t rd_sys_part2_data1; /*Register $n of BLOCK9 (KEY5).*/ - uint32_t rd_sys_part2_data2; /*Register $n of BLOCK10 (system).*/ - uint32_t rd_sys_part2_data3; /*Register $n of BLOCK10 (system).*/ - uint32_t rd_sys_part2_data4; /*Register $n of BLOCK10 (system).*/ - uint32_t rd_sys_part2_data5; /*Register $n of BLOCK10 (system).*/ - uint32_t rd_sys_part2_data6; /*Register $n of BLOCK10 (system).*/ - uint32_t rd_sys_part2_data7; /*Register $n of BLOCK10 (system).*/ - union { - struct { - uint32_t rd_dis_err: 7; /*If any bit in RD_DIS is 1 then it indicates a programming error.*/ - uint32_t rpt4_reserved5_err: 1; /*Reserved.*/ - uint32_t dis_icache_err: 1; /*If DIS_ICACHE is 1 then it indicates a programming error.*/ - uint32_t dis_usb_jtag_err: 1; /*If DIS_USB_JTAG is 1 then it indicates a programming error.*/ - uint32_t dis_download_icache: 1; /*If DIS_DOWNLOAD_ICACHE is 1 then it indicates a programming error.*/ - uint32_t dis_usb_device_err: 1; /*If DIS_USB_DEVICE is 1 then it indicates a programming error.*/ - uint32_t dis_force_download_err: 1; /*If DIS_FORCE_DOWNLOAD is 1 then it indicates a programming error.*/ - uint32_t dis_usb_err: 1; /*If DIS_USB is 1 then it indicates a programming error.*/ - uint32_t dis_can_err: 1; /*If DIS_CAN is 1 then it indicates a programming error.*/ - uint32_t jtag_sel_enable_err: 1; /*If JTAG_SEL_ENABLE is 1 then it indicates a programming error.*/ - uint32_t soft_dis_jtag_err: 3; /*If SOFT_DIS_JTAG is 1 then it indicates a programming error.*/ - uint32_t dis_pad_jtag_err: 1; /*If DIS_PAD_JTAG is 1 then it indicates a programming error.*/ - uint32_t dis_download_manual_encrypt_err: 1; /*If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1 then it indicates a programming error.*/ - uint32_t usb_drefh_err: 2; /*If any bit in USB_DREFH is 1 then it indicates a programming error.*/ - uint32_t usb_drefl_err: 2; /*If any bit in USB_DREFL is 1 then it indicates a programming error.*/ - uint32_t usb_exchg_pins_err: 1; /*If USB_EXCHG_PINS is 1 then it indicates a programming error.*/ - uint32_t vdd_spi_as_gpio_err: 1; /*If VDD_SPI_AS_GPIO is 1 then it indicates a programming error.*/ - uint32_t btlc_gpio_enable_err: 2; /*If any bit in BTLC_GPIO_ENABLE is 1 then it indicates a programming error.*/ - uint32_t powerglitch_en_err: 1; /*If POWERGLITCH_EN is 1 then it indicates a programming error.*/ - uint32_t power_glitch_dsense_err: 2; /*If any bit in POWER_GLITCH_DSENSE is 1 then it indicates a programming error.*/ - }; - uint32_t val; - } rd_repeat_err0; - union { - struct { - uint32_t rpt4_reserved2_err: 16; /*Reserved.*/ - uint32_t wdt_delay_sel_err: 2; /*If any bit in WDT_DELAY_SEL is 1 then it indicates a programming error.*/ - uint32_t spi_boot_crypt_cnt_err: 3; /*If any bit in SPI_BOOT_CRYPT_CNT is 1 then it indicates a programming error.*/ - uint32_t secure_boot_key_revoke0_err: 1; /*If SECURE_BOOT_KEY_REVOKE0 is 1 then it indicates a programming error.*/ - uint32_t secure_boot_key_revoke1_err: 1; /*If SECURE_BOOT_KEY_REVOKE1 is 1 then it indicates a programming error.*/ - uint32_t secure_boot_key_revoke2_err: 1; /*If SECURE_BOOT_KEY_REVOKE2 is 1 then it indicates a programming error.*/ - uint32_t key_purpose_0_err: 4; /*If any bit in KEY_PURPOSE_0 is 1 then it indicates a programming error.*/ - uint32_t key_purpose_1_err: 4; /*If any bit in KEY_PURPOSE_1 is 1 then it indicates a programming error.*/ - }; - uint32_t val; - } rd_repeat_err1; - union { - struct { - uint32_t key_purpose_2_err: 4; /*If any bit in KEY_PURPOSE_2 is 1 then it indicates a programming error.*/ - uint32_t key_purpose_3_err: 4; /*If any bit in KEY_PURPOSE_3 is 1 then it indicates a programming error.*/ - uint32_t key_purpose_4_err: 4; /*If any bit in KEY_PURPOSE_4 is 1 then it indicates a programming error.*/ - uint32_t key_purpose_5_err: 4; /*If any bit in KEY_PURPOSE_5 is 1 then it indicates a programming error.*/ - uint32_t rpt4_reserved3_err: 4; /*Reserved.*/ - uint32_t secure_boot_en_err: 1; /*If SECURE_BOOT_EN is 1 then it indicates a programming error.*/ - uint32_t secure_boot_aggressive_revoke_err: 1; /*If SECURE_BOOT_AGGRESSIVE_REVOKE is 1 then it indicates a programming error.*/ - uint32_t rpt4_reserved0_err: 6; /*Reserved.*/ - uint32_t flash_tpuw_err: 4; /*If any bit in FLASH_TPUM is 1 then it indicates a programming error.*/ - }; - uint32_t val; - } rd_repeat_err2; - union { - struct { - uint32_t dis_download_mode_err: 1; /*If the value is not zero then it indicates a programming error on DIS_DOWNLOAD_MODE.*/ - uint32_t dis_direct_boot_err: 1; /*If the value is not zero then it indicates a programming error on DIS_DIRECT_BOOT.*/ - uint32_t dis_usb_serial_jtag_rom_print_err:1; /*If the value is not zero then it indicates a programming error on DIS_USB_SERIAL_JTAG_ROM_PRINT.*/ - uint32_t rpt4_reserved8_err: 1; /*Reserved.*/ - uint32_t dis_usb_serial_jtag_download_mode_err: 1; /*If the value is not zero then it indicates a programming error on DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.*/ - uint32_t enable_security_download_err: 1; /*If the value is not zero then it indicates a programming error on ENABLE_SECURITY_DOWNLOAD.*/ - uint32_t uart_print_control_err: 2; /*If the value is not zero then it indicates a programming error on UART_PRINT_CONTROL.*/ - uint32_t rpt4_reserved7_err: 5; /*Reserved*/ - uint32_t force_send_resume_err: 1; /*If the value is not zero then it indicates a programming error on FORCE_SEND_RESUME.*/ - uint32_t secure_version_err: 16; /*If the value is not zero then it indicates a programming error on SECURE_VERSION.*/ - uint32_t rpt4_reserved1_err: 1; /*Reserved.*/ - uint32_t err_rst_enable_err: 1; /*Use BLOCK0 to check error record registers, 0 - without check.*/ - }; - uint32_t val; - } rd_repeat_err3; - union { - struct { - uint32_t rpt4_reserved4_err:24; /*Reserved.*/ - uint32_t reserved24: 8; /*Reserved.*/ - }; - uint32_t val; - } rd_repeat_err4; - uint32_t reserved_190; - uint32_t reserved_194; - uint32_t reserved_198; - uint32_t reserved_19c; - uint32_t reserved_1a0; - uint32_t reserved_1a4; - uint32_t reserved_1a8; - uint32_t reserved_1ac; - uint32_t reserved_1b0; - uint32_t reserved_1b4; - uint32_t reserved_1b8; - uint32_t reserved_1bc; - union { - struct { - uint32_t mac_spi_8m_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t reserved3: 1; /*Reserved.*/ - uint32_t sys_part1_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t mac_spi_8m_fail: 1; /*0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming MAC_SPI_8M failed and the number of error bytes is over 6.*/ - uint32_t usr_data_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t sys_part1_fail: 1; /*0: Means no failure and that the data of system part1 is reliable 1: Means that programming the data of system part1 failed and the number of error bytes is over 6.*/ - uint32_t key0_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t usr_data_fail: 1; /*0: Means no failure and that the data of user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ - uint32_t key1_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t key0_fail: 1; /*0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6.*/ - uint32_t key2_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t key1_fail: 1; /*0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6.*/ - uint32_t key3_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t key2_fail: 1; /*0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6.*/ - uint32_t key4_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t key3_fail: 1; /*0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6.*/ - }; - uint32_t val; - } rd_rs_err0; - union { - struct { - uint32_t key5_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t key4_fail: 1; /*0: Means no failure and that the data of KEY4 is reliable 1: Means that programming KEY4 failed and the number of error bytes is over 6.*/ - uint32_t sys_part2_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t key5_fail: 1; /*0: Means no failure and that the data of KEY5 is reliable 1: Means that programming KEY5 failed and the number of error bytes is over 6.*/ - uint32_t reserved8: 24; /*Reserved.*/ - }; - uint32_t val; - } rd_rs_err1; - union { - struct { - uint32_t mem_force_pd: 1; /*Set this bit to force eFuse SRAM into power-saving mode.*/ - uint32_t mem_clk_force_on: 1; /*Set this bit and force to activate clock signal of eFuse SRAM.*/ - uint32_t mem_force_pu: 1; /*Set this bit to force eFuse SRAM into working mode.*/ - uint32_t reserved3: 13; /*Reserved.*/ - uint32_t clk_en: 1; /*Set this bit and force to enable clock signal of eFuse memory.*/ - uint32_t reserved17: 15; /*Reserved.*/ - }; - uint32_t val; - } clk; - union { - struct { - uint32_t op_code: 16; /*0x5A5A: Operate programming command 0x5AA5: Operate read command.*/ - uint32_t reserved16:16; /*Reserved.*/ - }; - uint32_t val; - } conf; - union { - struct { - uint32_t state: 4; /*Indicates the state of the eFuse state machine.*/ - uint32_t otp_load_sw: 1; /*The value of OTP_LOAD_SW.*/ - uint32_t otp_vddq_c_sync2: 1; /*The value of OTP_VDDQ_C_SYNC2.*/ - uint32_t otp_strobe_sw: 1; /*The value of OTP_STROBE_SW.*/ - uint32_t otp_csb_sw: 1; /*The value of OTP_CSB_SW.*/ - uint32_t otp_pgenb_sw: 1; /*The value of OTP_PGENB_SW.*/ - uint32_t otp_vddq_is_sw: 1; /*The value of OTP_VDDQ_IS_SW.*/ - uint32_t repeat_err_cnt: 8; /*Indicates the number of error bits during programming BLOCK0.*/ - uint32_t reserved18: 14; /*Reserved.*/ - }; - uint32_t val; - } status; - union { - struct { - uint32_t read_cmd: 1; /*Set this bit to send read command.*/ - uint32_t pgm_cmd: 1; /*Set this bit to send programming command.*/ - uint32_t blk_num: 4; /*The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10 respectively.*/ - uint32_t reserved6: 26; /*Reserved.*/ - }; - uint32_t val; - } cmd; - union { - struct { - uint32_t read_done: 1; /*The raw bit signal for read_done interrupt.*/ - uint32_t pgm_done: 1; /*The raw bit signal for pgm_done interrupt.*/ - uint32_t reserved2: 30; /*Reserved.*/ - }; - uint32_t val; - } int_raw; - union { - struct { - uint32_t read_done: 1; /*The status signal for read_done interrupt.*/ - uint32_t pgm_done: 1; /*The status signal for pgm_done interrupt.*/ - uint32_t reserved2: 30; /*Reserved.*/ - }; - uint32_t val; - } int_st; - union { - struct { - uint32_t read_done: 1; /*The enable signal for read_done interrupt.*/ - uint32_t pgm_done: 1; /*The enable signal for pgm_done interrupt.*/ - uint32_t reserved2: 30; /*Reserved.*/ - }; - uint32_t val; - } int_ena; - union { - struct { - uint32_t read_done: 1; /*The clear signal for read_done interrupt.*/ - uint32_t pgm_done: 1; /*The clear signal for pgm_done interrupt.*/ - uint32_t reserved2: 30; /*Reserved.*/ - }; - uint32_t val; - } int_clr; - union { - struct { - uint32_t dac_clk_div: 8; /*Controls the division factor of the rising clock of the programming voltage.*/ - uint32_t dac_clk_pad_sel: 1; /*Don't care.*/ - uint32_t dac_num: 8; /*Controls the rising period of the programming voltage.*/ - uint32_t oe_clr: 1; /*Reduces the power supply of the programming voltage.*/ - uint32_t reserved18: 14; /*Reserved.*/ - }; - uint32_t val; - } dac_conf; - union { - struct { - uint32_t reserved0: 24; /*Configures the setup time of read operation.*/ - uint32_t read_init_num: 8; /*Configures the initial read time of eFuse.*/ - }; - uint32_t val; - } rd_tim_conf; - union { - struct { - uint32_t reserved0: 8; /*Configures the setup time of programming operation.*/ - uint32_t pwr_on_num:16; /*Configures the power up time for VDDQ.*/ - uint32_t reserved24: 8; /*Reserved.*/ - }; - uint32_t val; - } wr_tim_conf1; - union { - struct { - uint32_t pwr_off_num:16; /*Configures the power outage time for VDDQ.*/ - uint32_t reserved16: 16; /*Reserved.*/ - }; - uint32_t val; - } wr_tim_conf2; +/** Group: PGM Data Register */ +/** Type of pgm_data0 register + * Register 0 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit data to be programmed. + */ + uint32_t pgm_data_0:32; + }; + uint32_t val; +} efuse_pgm_data0_reg_t; + +/** Type of pgm_data1 register + * Register 1 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1st 32-bit data to be programmed. + */ + uint32_t pgm_data_1:32; + }; + uint32_t val; +} efuse_pgm_data1_reg_t; + +/** Type of pgm_data2 register + * Register 2 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2nd 32-bit data to be programmed. + */ + uint32_t pgm_data_2:32; + }; + uint32_t val; +} efuse_pgm_data2_reg_t; + +/** Type of pgm_data3 register + * Register 3 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0; + * The content of the 3rd 32-bit data to be programmed. + */ + uint32_t pgm_data_3:32; + }; + uint32_t val; +} efuse_pgm_data3_reg_t; + +/** Type of pgm_data4 register + * Register 4 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0; + * The content of the 4th 32-bit data to be programmed. + */ + uint32_t pgm_data_4:32; + }; + uint32_t val; +} efuse_pgm_data4_reg_t; + +/** Type of pgm_data5 register + * Register 5 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0; + * The content of the 5th 32-bit data to be programmed. + */ + uint32_t pgm_data_5:32; + }; + uint32_t val; +} efuse_pgm_data5_reg_t; + +/** Type of pgm_data6 register + * Register 6 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0; + * The content of the 6th 32-bit data to be programmed. + */ + uint32_t pgm_data_6:32; + }; + uint32_t val; +} efuse_pgm_data6_reg_t; + +/** Type of pgm_data7 register + * Register 7 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0; + * The content of the 7th 32-bit data to be programmed. + */ + uint32_t pgm_data_7:32; + }; + uint32_t val; +} efuse_pgm_data7_reg_t; + +/** Type of pgm_check_value0 register + * Register 0 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_0:32; + }; + uint32_t val; +} efuse_pgm_check_value0_reg_t; + +/** Type of pgm_check_value1 register + * Register 1 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1st 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_1:32; + }; + uint32_t val; +} efuse_pgm_check_value1_reg_t; + +/** Type of pgm_check_value2 register + * Register 2 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2nd 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_2:32; + }; + uint32_t val; +} efuse_pgm_check_value2_reg_t; + + +/** Group: Read Data Register */ +/** Type of rd_wr_dis register + * BLOCK0 data register 0. + */ +typedef union { + struct { + /** wr_dis : RO; bitpos: [31:0]; default: 0; + * Disable programming of individual eFuses. + */ + uint32_t wr_dis:32; + }; + uint32_t val; +} efuse_rd_wr_dis_reg_t; + +/** Type of rd_repeat_data0 register + * BLOCK0 data register 1. + */ +typedef union { + struct { + /** rd_dis : RO; bitpos: [6:0]; default: 0; + * Set this bit to disable reading from BlOCK4-10. + */ + uint32_t rd_dis:7; + /** dis_rtc_ram_boot : RO; bitpos: [7]; default: 0; + * Set this bit to disable boot from RTC RAM. + */ + uint32_t dis_rtc_ram_boot:1; + /** dis_icache : RO; bitpos: [8]; default: 0; + * Set this bit to disable Icache. + */ + uint32_t dis_icache:1; + /** dis_usb_jtag : RO; bitpos: [9]; default: 0; + * Set this bit to disable function of usb switch to jtag in module of usb device. + */ + uint32_t dis_usb_jtag:1; + /** dis_download_icache : RO; bitpos: [10]; default: 0; + * Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, + * 7). + */ + uint32_t dis_download_icache:1; + /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0; + * Represents whether USB-Serial-JTAG is disabled. 1: Disabled. 0: Enabled + */ + uint32_t dis_usb_serial_jtag:1; + /** dis_force_download : RO; bitpos: [12]; default: 0; + * Set this bit to disable the function that forces chip into download mode. + */ + uint32_t dis_force_download:1; + /** rpt4_reserved6 : RO; bitpos: [13]; default: 0; + * Reserved (used for four backups method). + */ + uint32_t rpt4_reserved6:1; + /** dis_twai : RO; bitpos: [14]; default: 0; + * Set this bit to disable CAN function. + */ + uint32_t dis_twai:1; + /** jtag_sel_enable : RO; bitpos: [15]; default: 0; + * Set this bit to enable selection between usb_to_jtag and pad_to_jtag through + * strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0. + */ + uint32_t jtag_sel_enable:1; + /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0; + * Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG + * can be enabled in HMAC module. + */ + uint32_t soft_dis_jtag:3; + /** dis_pad_jtag : RO; bitpos: [19]; default: 0; + * Set this bit to disable JTAG in the hard way. JTAG is disabled permanently. + */ + uint32_t dis_pad_jtag:1; + /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0; + * Set this bit to disable flash encryption when in download boot modes. + */ + uint32_t dis_download_manual_encrypt:1; + /** usb_drefh : RO; bitpos: [22:21]; default: 0; + * Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored + * in eFuse. + */ + uint32_t usb_drefh:2; + /** usb_drefl : RO; bitpos: [24:23]; default: 0; + * Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, + * stored in eFuse. + */ + uint32_t usb_drefl:2; + /** usb_exchg_pins : RO; bitpos: [25]; default: 0; + * Set this bit to exchange USB D+ and D- pins. + */ + uint32_t usb_exchg_pins:1; + /** vdd_spi_as_gpio : RO; bitpos: [26]; default: 0; + * Set this bit to vdd spi pin function as gpio. + */ + uint32_t vdd_spi_as_gpio:1; + /** btlc_gpio_enable : RO; bitpos: [28:27]; default: 0; + * Enable btlc gpio. + */ + uint32_t btlc_gpio_enable:2; + /** powerglitch_en : RO; bitpos: [29]; default: 0; + * Set this bit to enable power glitch function. + */ + uint32_t powerglitch_en:1; + /** power_glitch_dsense : RO; bitpos: [31:30]; default: 0; + * Sample delay configuration of power glitch. + */ + uint32_t power_glitch_dsense:2; + }; + uint32_t val; +} efuse_rd_repeat_data0_reg_t; + +/** Type of rd_repeat_data1 register + * BLOCK0 data register 2. + */ +typedef union { + struct { + /** rpt4_reserved2 : RO; bitpos: [15:0]; default: 0; + * Reserved (used for four backups method). + */ + uint32_t rpt4_reserved2:16; + /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0; + * Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: + * 80000. 2: 160000. 3:320000. + */ + uint32_t wdt_delay_sel:2; + /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0; + * Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even + * number of 1: disable. + */ + uint32_t spi_boot_crypt_cnt:3; + /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0; + * Set this bit to enable revoking first secure boot key. + */ + uint32_t secure_boot_key_revoke0:1; + /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0; + * Set this bit to enable revoking second secure boot key. + */ + uint32_t secure_boot_key_revoke1:1; + /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0; + * Set this bit to enable revoking third secure boot key. + */ + uint32_t secure_boot_key_revoke2:1; + /** key_purpose_0 : RO; bitpos: [27:24]; default: 0; + * Purpose of Key0. + */ + uint32_t key_purpose_0:4; + /** key_purpose_1 : RO; bitpos: [31:28]; default: 0; + * Purpose of Key1. + */ + uint32_t key_purpose_1:4; + }; + uint32_t val; +} efuse_rd_repeat_data1_reg_t; + +/** Type of rd_repeat_data2 register + * BLOCK0 data register 3. + */ +typedef union { + struct { + /** key_purpose_2 : RO; bitpos: [3:0]; default: 0; + * Purpose of Key2. + */ + uint32_t key_purpose_2:4; + /** key_purpose_3 : RO; bitpos: [7:4]; default: 0; + * Purpose of Key3. + */ + uint32_t key_purpose_3:4; + /** key_purpose_4 : RO; bitpos: [11:8]; default: 0; + * Purpose of Key4. + */ + uint32_t key_purpose_4:4; + /** key_purpose_5 : RO; bitpos: [15:12]; default: 0; + * Purpose of Key5. + */ + uint32_t key_purpose_5:4; + /** rpt4_reserved3 : RO; bitpos: [19:16]; default: 0; + * Reserved (used for four backups method). + */ + uint32_t rpt4_reserved3:4; + /** secure_boot_en : RO; bitpos: [20]; default: 0; + * Set this bit to enable secure boot. + */ + uint32_t secure_boot_en:1; + /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0; + * Set this bit to enable revoking aggressive secure boot. + */ + uint32_t secure_boot_aggressive_revoke:1; + /** rpt4_reserved0 : RO; bitpos: [27:22]; default: 0; + * Reserved (used for four backups method). + */ + uint32_t rpt4_reserved0:6; + /** flash_tpuw : RO; bitpos: [31:28]; default: 0; + * Configures flash waiting time after power-up, in unit of ms. If the value is less + * than 15, the waiting time is the configurable value; Otherwise, the waiting time is + * twice the configurable value. + */ + uint32_t flash_tpuw:4; + }; + uint32_t val; +} efuse_rd_repeat_data2_reg_t; + +/** Type of rd_repeat_data3 register + * BLOCK0 data register 4. + */ +typedef union { + struct { + /** dis_download_mode : RO; bitpos: [0]; default: 0; + * Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7). + */ + uint32_t dis_download_mode:1; + /** dis_direct_boot : RO; bitpos: [1]; default: 0; + * Disable direct boot mode + */ + uint32_t dis_direct_boot:1; + /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0; + * Represents whether USB printing is disabled or enabled. 1: Disabled. 0: Enabled + */ + uint32_t dis_usb_serial_jtag_rom_print:1; + /** flash_ecc_mode : RO; bitpos: [3]; default: 0; + * Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would + * use 16to17 byte mode. + */ + uint32_t flash_ecc_mode:1; + /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0; + * Disable UART download mode through USB-Serial-JTAG + */ + uint32_t dis_usb_serial_jtag_download_mode:1; + /** enable_security_download : RO; bitpos: [5]; default: 0; + * Set this bit to enable secure UART download mode. + */ + uint32_t enable_security_download:1; + /** uart_print_control : RO; bitpos: [7:6]; default: 0; + * Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 + * is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled. + */ + uint32_t uart_print_control:2; + /** pin_power_selection : RO; bitpos: [8]; default: 0; + * GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI. + */ + uint32_t pin_power_selection:1; + /** flash_type : RO; bitpos: [9]; default: 0; + * Set the maximum lines of SPI flash. 0: four lines. 1: eight lines. + */ + uint32_t flash_type:1; + /** flash_page_size : RO; bitpos: [11:10]; default: 0; + * Set Flash page size. + */ + uint32_t flash_page_size:2; + /** flash_ecc_en : RO; bitpos: [12]; default: 0; + * Set 1 to enable ECC for flash boot. + */ + uint32_t flash_ecc_en:1; + /** force_send_resume : RO; bitpos: [13]; default: 0; + * Set this bit to force ROM code to send a resume command during SPI boot. + */ + uint32_t force_send_resume:1; + /** secure_version : RO; bitpos: [29:14]; default: 0; + * Secure version (used by ESP-IDF anti-rollback feature). + */ + uint32_t secure_version:16; + /** reserved_0_158 : R; bitpos: [30]; default: 0; + * reserved + */ + uint32_t reserved_0_158:1; + /** err_rst_enable : R; bitpos: [31]; default: 0; + * Use BLOCK0 to check error record registers + */ + uint32_t err_rst_enable:1; + }; + uint32_t val; +} efuse_rd_repeat_data3_reg_t; + +/** Type of rd_repeat_data4 register + * BLOCK0 data register 5. + */ +typedef union { + struct { + /** disable_wafer_version_major : R; bitpos: [0]; default: 0; + * Disables check of wafer version major + */ + uint32_t disable_wafer_version_major:1; + /** disable_blk_version_major : R; bitpos: [1]; default: 0; + * Disables check of blk version major + */ + uint32_t disable_blk_version_major:1; + /** reserved_0_162 : R; bitpos: [23:2]; default: 0; + * reserved + */ + uint32_t reserved_0_162:22; + uint32_t reserved_24:8; + }; + uint32_t val; +} efuse_rd_repeat_data4_reg_t; + +/** Type of rd_mac_spi_sys_0 register + * BLOCK1 data register 0. + */ +typedef union { + struct { + /** mac_0 : RO; bitpos: [31:0]; default: 0; + * Stores the low 32 bits of MAC address. + */ + uint32_t mac_0:32; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_0_reg_t; + +/** Type of rd_mac_spi_sys_1 register + * BLOCK1 data register 1. + */ +typedef union { + struct { + /** mac_1 : RO; bitpos: [15:0]; default: 0; + * Stores the high 16 bits of MAC address. + */ + uint32_t mac_1:16; + /** spi_pad_config_clk : R; bitpos: [21:16]; default: 0; + * SPI PAD CLK + */ + uint32_t spi_pad_config_clk:6; + /** spi_pad_config_q : R; bitpos: [27:22]; default: 0; + * SPI PAD Q(D1) + */ + uint32_t spi_pad_config_q:6; + /** spi_pad_config_d : R; bitpos: [31:28]; default: 0; + * SPI PAD D(D0) + */ + uint32_t spi_pad_config_d:4; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_1_reg_t; + +/** Type of rd_mac_spi_sys_2 register + * BLOCK1 data register 2. + */ +typedef union { + struct { + /** spi_pad_config_d_1 : R; bitpos: [1:0]; default: 0; + * SPI PAD D(D0) + */ + uint32_t spi_pad_config_d_1:2; + /** spi_pad_config_cs : R; bitpos: [7:2]; default: 0; + * SPI PAD CS + */ + uint32_t spi_pad_config_cs:6; + /** spi_pad_config_hd : R; bitpos: [13:8]; default: 0; + * SPI PAD HD(D3) + */ + uint32_t spi_pad_config_hd:6; + /** spi_pad_config_wp : R; bitpos: [19:14]; default: 0; + * SPI PAD WP(D2) + */ + uint32_t spi_pad_config_wp:6; + /** spi_pad_config_dqs : R; bitpos: [25:20]; default: 0; + * SPI PAD DQS + */ + uint32_t spi_pad_config_dqs:6; + /** spi_pad_config_d4 : R; bitpos: [31:26]; default: 0; + * SPI PAD D4 + */ + uint32_t spi_pad_config_d4:6; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_2_reg_t; + +/** Type of rd_mac_spi_sys_3 register + * BLOCK1 data register 3. + */ +typedef union { + struct { + /** spi_pad_config_d5 : R; bitpos: [5:0]; default: 0; + * SPI PAD D5 + */ + uint32_t spi_pad_config_d5:6; + /** spi_pad_config_d6 : R; bitpos: [11:6]; default: 0; + * SPI PAD D6 + */ + uint32_t spi_pad_config_d6:6; + /** spi_pad_config_d7 : R; bitpos: [17:12]; default: 0; + * SPI PAD D7 + */ + uint32_t spi_pad_config_d7:6; + /** wafer_version_minor_lo : R; bitpos: [20:18]; default: 0; + * WAFER_VERSION_MINOR least significant bits + */ + uint32_t wafer_version_minor_lo:3; + /** pkg_version : R; bitpos: [23:21]; default: 0; + * Package version + */ + uint32_t pkg_version:3; + /** blk_version_minor : R; bitpos: [26:24]; default: 0; + * BLK_VERSION_MINOR + */ + uint32_t blk_version_minor:3; + /** reserved_1_123 : R; bitpos: [31:27]; default: 0; + * reserved + */ + uint32_t reserved_1_123:5; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_3_reg_t; + +/** Type of rd_mac_spi_sys_4 register + * BLOCK1 data register 4. + */ +typedef union { + struct { + /** reserved_1_128 : R; bitpos: [6:0]; default: 0; + * reserved + */ + uint32_t reserved_1_128:7; + /** k_rtc_ldo : R; bitpos: [13:7]; default: 0; + * BLOCK1 K_RTC_LDO + */ + uint32_t k_rtc_ldo:7; + /** k_dig_ldo : R; bitpos: [20:14]; default: 0; + * BLOCK1 K_DIG_LDO + */ + uint32_t k_dig_ldo:7; + /** v_rtc_dbias20 : R; bitpos: [28:21]; default: 0; + * BLOCK1 voltage of rtc dbias20 + */ + uint32_t v_rtc_dbias20:8; + /** v_dig_dbias20 : R; bitpos: [31:29]; default: 0; + * BLOCK1 voltage of digital dbias20 + */ + uint32_t v_dig_dbias20:3; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_4_reg_t; + +/** Type of rd_mac_spi_sys_5 register + * BLOCK1 data register 5. + */ +typedef union { + struct { + /** v_dig_dbias20_1 : R; bitpos: [4:0]; default: 0; + * BLOCK1 voltage of digital dbias20 + */ + uint32_t v_dig_dbias20_1:5; + /** dig_dbias_hvt : R; bitpos: [9:5]; default: 0; + * BLOCK1 digital dbias when hvt + */ + uint32_t dig_dbias_hvt:5; + /** thres_hvt : R; bitpos: [19:10]; default: 0; + * BLOCK1 pvt threshold when hvt + */ + uint32_t thres_hvt:10; + /** reserved_1_180 : R; bitpos: [22:20]; default: 0; + * reserved + */ + uint32_t reserved_1_180:3; + /** wafer_version_minor_hi : R; bitpos: [23]; default: 0; + * WAFER_VERSION_MINOR most significant bit + */ + uint32_t wafer_version_minor_hi:1; + /** wafer_version_major : R; bitpos: [25:24]; default: 0; + * WAFER_VERSION_MAJOR + */ + uint32_t wafer_version_major:2; + /** reserved_1_186 : R; bitpos: [31:26]; default: 0; + * reserved + */ + uint32_t reserved_1_186:6; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_5_reg_t; + +/** Type of rd_sys_part1_data0 register + * Register 0 of BLOCK2 (system). + */ +typedef union { + struct { + /** optional_unique_id : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data0_reg_t; + +/** Type of rd_sys_part1_data1 register + * Register 1 of BLOCK2 (system). + */ +typedef union { + struct { + /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id_1:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data1_reg_t; + +/** Type of rd_sys_part1_data2 register + * Register 2 of BLOCK2 (system). + */ +typedef union { + struct { + /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id_2:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data2_reg_t; + +/** Type of rd_sys_part1_data3 register + * Register 3 of BLOCK2 (system). + */ +typedef union { + struct { + /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id_3:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data3_reg_t; + +/** Type of rd_sys_part1_data4 register + * Register 4 of BLOCK2 (system). + */ +typedef union { + struct { + /** blk_version_major : R; bitpos: [1:0]; default: 0; + * BLK_VERSION_MAJOR of BLOCK2 + */ + uint32_t blk_version_major:2; + /** reserved_2_130 : R; bitpos: [2]; default: 0; + * reserved + */ + uint32_t reserved_2_130:1; + /** temp_calib : R; bitpos: [11:3]; default: 0; + * Temperature calibration data + */ + uint32_t temp_calib:9; + /** ocode : R; bitpos: [19:12]; default: 0; + * ADC OCode + */ + uint32_t ocode:8; + /** adc1_init_code_atten0 : R; bitpos: [29:20]; default: 0; + * ADC1 init code at atten0 + */ + uint32_t adc1_init_code_atten0:10; + /** adc1_init_code_atten1 : R; bitpos: [31:30]; default: 0; + * ADC1 init code at atten1 + */ + uint32_t adc1_init_code_atten1:2; + }; + uint32_t val; +} efuse_rd_sys_part1_data4_reg_t; + +/** Type of rd_sys_part1_data5 register + * Register 5 of BLOCK2 (system). + */ +typedef union { + struct { + /** adc1_init_code_atten1_1 : R; bitpos: [7:0]; default: 0; + * ADC1 init code at atten1 + */ + uint32_t adc1_init_code_atten1_1:8; + /** adc1_init_code_atten2 : R; bitpos: [17:8]; default: 0; + * ADC1 init code at atten2 + */ + uint32_t adc1_init_code_atten2:10; + /** adc1_init_code_atten3 : R; bitpos: [27:18]; default: 0; + * ADC1 init code at atten3 + */ + uint32_t adc1_init_code_atten3:10; + /** adc1_cal_vol_atten0 : R; bitpos: [31:28]; default: 0; + * ADC1 calibration voltage at atten0 + */ + uint32_t adc1_cal_vol_atten0:4; + }; + uint32_t val; +} efuse_rd_sys_part1_data5_reg_t; + +/** Type of rd_sys_part1_data6 register + * Register 6 of BLOCK2 (system). + */ +typedef union { + struct { + /** adc1_cal_vol_atten0_1 : R; bitpos: [5:0]; default: 0; + * ADC1 calibration voltage at atten0 + */ + uint32_t adc1_cal_vol_atten0_1:6; + /** adc1_cal_vol_atten1 : R; bitpos: [15:6]; default: 0; + * ADC1 calibration voltage at atten1 + */ + uint32_t adc1_cal_vol_atten1:10; + /** adc1_cal_vol_atten2 : R; bitpos: [25:16]; default: 0; + * ADC1 calibration voltage at atten2 + */ + uint32_t adc1_cal_vol_atten2:10; + /** adc1_cal_vol_atten3 : R; bitpos: [31:26]; default: 0; + * ADC1 calibration voltage at atten3 + */ + uint32_t adc1_cal_vol_atten3:6; + }; + uint32_t val; +} efuse_rd_sys_part1_data6_reg_t; + +/** Type of rd_sys_part1_data7 register + * Register 7 of BLOCK2 (system). + */ +typedef union { + struct { + /** adc1_cal_vol_atten3_1 : R; bitpos: [3:0]; default: 0; + * ADC1 calibration voltage at atten3 + */ + uint32_t adc1_cal_vol_atten3_1:4; + /** reserved_2_228 : R; bitpos: [31:4]; default: 0; + * reserved + */ + uint32_t reserved_2_228:28; + }; + uint32_t val; +} efuse_rd_sys_part1_data7_reg_t; + +/** Type of rd_usr_data0 register + * Register 0 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data0:32; + }; + uint32_t val; +} efuse_rd_usr_data0_reg_t; + +/** Type of rd_usr_data1 register + * Register 1 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of BLOCK3 (user). + */ + uint32_t usr_data1:32; + }; + uint32_t val; +} efuse_rd_usr_data1_reg_t; + +/** Type of rd_usr_data2 register + * Register 2 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of BLOCK3 (user). + */ + uint32_t usr_data2:32; + }; + uint32_t val; +} efuse_rd_usr_data2_reg_t; + +/** Type of rd_usr_data3 register + * Register 3 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of BLOCK3 (user). + */ + uint32_t usr_data3:32; + }; + uint32_t val; +} efuse_rd_usr_data3_reg_t; + +/** Type of rd_usr_data4 register + * Register 4 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data4:32; + }; + uint32_t val; +} efuse_rd_usr_data4_reg_t; + +/** Type of rd_usr_data5 register + * Register 5 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data5:32; + }; + uint32_t val; +} efuse_rd_usr_data5_reg_t; + +/** Type of rd_usr_data6 register + * Register 6 of BLOCK3 (user). + */ +typedef union { + struct { + /** reserved_3_192 : R; bitpos: [7:0]; default: 0; + * reserved + */ + uint32_t reserved_3_192:8; + /** custom_mac : R; bitpos: [31:8]; default: 0; + * Custom MAC address + */ + uint32_t custom_mac:24; + }; + uint32_t val; +} efuse_rd_usr_data6_reg_t; + +/** Type of rd_usr_data7 register + * Register 7 of BLOCK3 (user). + */ +typedef union { + struct { + /** custom_mac_1 : R; bitpos: [23:0]; default: 0; + * Custom MAC address + */ + uint32_t custom_mac_1:24; + /** reserved_3_248 : R; bitpos: [31:24]; default: 0; + * reserved + */ + uint32_t reserved_3_248:8; + }; + uint32_t val; +} efuse_rd_usr_data7_reg_t; + +/** Type of rd_key0_data0 register + * Register 0 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY0. + */ + uint32_t key0_data0:32; + }; + uint32_t val; +} efuse_rd_key0_data0_reg_t; + +/** Type of rd_key0_data1 register + * Register 1 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY0. + */ + uint32_t key0_data1:32; + }; + uint32_t val; +} efuse_rd_key0_data1_reg_t; + +/** Type of rd_key0_data2 register + * Register 2 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY0. + */ + uint32_t key0_data2:32; + }; + uint32_t val; +} efuse_rd_key0_data2_reg_t; + +/** Type of rd_key0_data3 register + * Register 3 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY0. + */ + uint32_t key0_data3:32; + }; + uint32_t val; +} efuse_rd_key0_data3_reg_t; + +/** Type of rd_key0_data4 register + * Register 4 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY0. + */ + uint32_t key0_data4:32; + }; + uint32_t val; +} efuse_rd_key0_data4_reg_t; + +/** Type of rd_key0_data5 register + * Register 5 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY0. + */ + uint32_t key0_data5:32; + }; + uint32_t val; +} efuse_rd_key0_data5_reg_t; + +/** Type of rd_key0_data6 register + * Register 6 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY0. + */ + uint32_t key0_data6:32; + }; + uint32_t val; +} efuse_rd_key0_data6_reg_t; + +/** Type of rd_key0_data7 register + * Register 7 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY0. + */ + uint32_t key0_data7:32; + }; + uint32_t val; +} efuse_rd_key0_data7_reg_t; + +/** Type of rd_key1_data0 register + * Register 0 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY1. + */ + uint32_t key1_data0:32; + }; + uint32_t val; +} efuse_rd_key1_data0_reg_t; + +/** Type of rd_key1_data1 register + * Register 1 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY1. + */ + uint32_t key1_data1:32; + }; + uint32_t val; +} efuse_rd_key1_data1_reg_t; + +/** Type of rd_key1_data2 register + * Register 2 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY1. + */ + uint32_t key1_data2:32; + }; + uint32_t val; +} efuse_rd_key1_data2_reg_t; + +/** Type of rd_key1_data3 register + * Register 3 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY1. + */ + uint32_t key1_data3:32; + }; + uint32_t val; +} efuse_rd_key1_data3_reg_t; + +/** Type of rd_key1_data4 register + * Register 4 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY1. + */ + uint32_t key1_data4:32; + }; + uint32_t val; +} efuse_rd_key1_data4_reg_t; + +/** Type of rd_key1_data5 register + * Register 5 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY1. + */ + uint32_t key1_data5:32; + }; + uint32_t val; +} efuse_rd_key1_data5_reg_t; + +/** Type of rd_key1_data6 register + * Register 6 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY1. + */ + uint32_t key1_data6:32; + }; + uint32_t val; +} efuse_rd_key1_data6_reg_t; + +/** Type of rd_key1_data7 register + * Register 7 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY1. + */ + uint32_t key1_data7:32; + }; + uint32_t val; +} efuse_rd_key1_data7_reg_t; + +/** Type of rd_key2_data0 register + * Register 0 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY2. + */ + uint32_t key2_data0:32; + }; + uint32_t val; +} efuse_rd_key2_data0_reg_t; + +/** Type of rd_key2_data1 register + * Register 1 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY2. + */ + uint32_t key2_data1:32; + }; + uint32_t val; +} efuse_rd_key2_data1_reg_t; + +/** Type of rd_key2_data2 register + * Register 2 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY2. + */ + uint32_t key2_data2:32; + }; + uint32_t val; +} efuse_rd_key2_data2_reg_t; + +/** Type of rd_key2_data3 register + * Register 3 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY2. + */ + uint32_t key2_data3:32; + }; + uint32_t val; +} efuse_rd_key2_data3_reg_t; + +/** Type of rd_key2_data4 register + * Register 4 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY2. + */ + uint32_t key2_data4:32; + }; + uint32_t val; +} efuse_rd_key2_data4_reg_t; + +/** Type of rd_key2_data5 register + * Register 5 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY2. + */ + uint32_t key2_data5:32; + }; + uint32_t val; +} efuse_rd_key2_data5_reg_t; + +/** Type of rd_key2_data6 register + * Register 6 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY2. + */ + uint32_t key2_data6:32; + }; + uint32_t val; +} efuse_rd_key2_data6_reg_t; + +/** Type of rd_key2_data7 register + * Register 7 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY2. + */ + uint32_t key2_data7:32; + }; + uint32_t val; +} efuse_rd_key2_data7_reg_t; + +/** Type of rd_key3_data0 register + * Register 0 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY3. + */ + uint32_t key3_data0:32; + }; + uint32_t val; +} efuse_rd_key3_data0_reg_t; + +/** Type of rd_key3_data1 register + * Register 1 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY3. + */ + uint32_t key3_data1:32; + }; + uint32_t val; +} efuse_rd_key3_data1_reg_t; + +/** Type of rd_key3_data2 register + * Register 2 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY3. + */ + uint32_t key3_data2:32; + }; + uint32_t val; +} efuse_rd_key3_data2_reg_t; + +/** Type of rd_key3_data3 register + * Register 3 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY3. + */ + uint32_t key3_data3:32; + }; + uint32_t val; +} efuse_rd_key3_data3_reg_t; + +/** Type of rd_key3_data4 register + * Register 4 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY3. + */ + uint32_t key3_data4:32; + }; + uint32_t val; +} efuse_rd_key3_data4_reg_t; + +/** Type of rd_key3_data5 register + * Register 5 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY3. + */ + uint32_t key3_data5:32; + }; + uint32_t val; +} efuse_rd_key3_data5_reg_t; + +/** Type of rd_key3_data6 register + * Register 6 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY3. + */ + uint32_t key3_data6:32; + }; + uint32_t val; +} efuse_rd_key3_data6_reg_t; + +/** Type of rd_key3_data7 register + * Register 7 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY3. + */ + uint32_t key3_data7:32; + }; + uint32_t val; +} efuse_rd_key3_data7_reg_t; + +/** Type of rd_key4_data0 register + * Register 0 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY4. + */ + uint32_t key4_data0:32; + }; + uint32_t val; +} efuse_rd_key4_data0_reg_t; + +/** Type of rd_key4_data1 register + * Register 1 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY4. + */ + uint32_t key4_data1:32; + }; + uint32_t val; +} efuse_rd_key4_data1_reg_t; + +/** Type of rd_key4_data2 register + * Register 2 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY4. + */ + uint32_t key4_data2:32; + }; + uint32_t val; +} efuse_rd_key4_data2_reg_t; + +/** Type of rd_key4_data3 register + * Register 3 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY4. + */ + uint32_t key4_data3:32; + }; + uint32_t val; +} efuse_rd_key4_data3_reg_t; + +/** Type of rd_key4_data4 register + * Register 4 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY4. + */ + uint32_t key4_data4:32; + }; + uint32_t val; +} efuse_rd_key4_data4_reg_t; + +/** Type of rd_key4_data5 register + * Register 5 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY4. + */ + uint32_t key4_data5:32; + }; + uint32_t val; +} efuse_rd_key4_data5_reg_t; + +/** Type of rd_key4_data6 register + * Register 6 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY4. + */ + uint32_t key4_data6:32; + }; + uint32_t val; +} efuse_rd_key4_data6_reg_t; + +/** Type of rd_key4_data7 register + * Register 7 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY4. + */ + uint32_t key4_data7:32; + }; + uint32_t val; +} efuse_rd_key4_data7_reg_t; + +/** Type of rd_key5_data0 register + * Register 0 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY5. + */ + uint32_t key5_data0:32; + }; + uint32_t val; +} efuse_rd_key5_data0_reg_t; + +/** Type of rd_key5_data1 register + * Register 1 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY5. + */ + uint32_t key5_data1:32; + }; + uint32_t val; +} efuse_rd_key5_data1_reg_t; + +/** Type of rd_key5_data2 register + * Register 2 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY5. + */ + uint32_t key5_data2:32; + }; + uint32_t val; +} efuse_rd_key5_data2_reg_t; + +/** Type of rd_key5_data3 register + * Register 3 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY5. + */ + uint32_t key5_data3:32; + }; + uint32_t val; +} efuse_rd_key5_data3_reg_t; + +/** Type of rd_key5_data4 register + * Register 4 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY5. + */ + uint32_t key5_data4:32; + }; + uint32_t val; +} efuse_rd_key5_data4_reg_t; + +/** Type of rd_key5_data5 register + * Register 5 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY5. + */ + uint32_t key5_data5:32; + }; + uint32_t val; +} efuse_rd_key5_data5_reg_t; + +/** Type of rd_key5_data6 register + * Register 6 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY5. + */ + uint32_t key5_data6:32; + }; + uint32_t val; +} efuse_rd_key5_data6_reg_t; + +/** Type of rd_key5_data7 register + * Register 7 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY5. + */ + uint32_t key5_data7:32; + }; + uint32_t val; +} efuse_rd_key5_data7_reg_t; + +/** Type of rd_sys_part2_data0 register + * Register 0 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_0:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data0_reg_t; + +/** Type of rd_sys_part2_data1 register + * Register 1 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1st 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_1:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data1_reg_t; + +/** Type of rd_sys_part2_data2 register + * Register 2 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2nd 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_2:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data2_reg_t; + +/** Type of rd_sys_part2_data3 register + * Register 3 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3rd 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_3:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data3_reg_t; + +/** Type of rd_sys_part2_data4 register + * Register 4 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_4:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data4_reg_t; + +/** Type of rd_sys_part2_data5 register + * Register 5 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_5:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data5_reg_t; + +/** Type of rd_sys_part2_data6 register + * Register 6 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_6:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data6_reg_t; + +/** Type of rd_sys_part2_data7 register + * Register 7 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_7:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data7_reg_t; + + +/** Group: Report Register */ +/** Type of rd_repeat_err0 register + * Programming error record register 0 of BLOCK0. + */ +typedef union { + struct { + /** rd_dis_err : RO; bitpos: [6:0]; default: 0; + * If any bit in RD_DIS is 1, then it indicates a programming error. + */ + uint32_t rd_dis_err:7; + /** dis_rtc_ram_boot_err : RO; bitpos: [7]; default: 0; + * If DIS_RTC_RAM_BOOT is 1, then it indicates a programming error. + */ + uint32_t dis_rtc_ram_boot_err:1; + /** dis_icache_err : RO; bitpos: [8]; default: 0; + * If DIS_ICACHE is 1, then it indicates a programming error. + */ + uint32_t dis_icache_err:1; + /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0; + * If DIS_USB_JTAG is 1, then it indicates a programming error. + */ + uint32_t dis_usb_jtag_err:1; + /** dis_download_icache_err : RO; bitpos: [10]; default: 0; + * If DIS_DOWNLOAD_ICACHE is 1, then it indicates a programming error. + */ + uint32_t dis_download_icache_err:1; + /** dis_usb_device_err : RO; bitpos: [11]; default: 0; + * If DIS_USB_DEVICE is 1, then it indicates a programming error. + */ + uint32_t dis_usb_device_err:1; + /** dis_force_download_err : RO; bitpos: [12]; default: 0; + * If DIS_FORCE_DOWNLOAD is 1, then it indicates a programming error. + */ + uint32_t dis_force_download_err:1; + /** rpt4_reserved6_err : RO; bitpos: [13]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved6_err:1; + /** dis_can_err : RO; bitpos: [14]; default: 0; + * If DIS_CAN is 1, then it indicates a programming error. + */ + uint32_t dis_can_err:1; + /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0; + * If JTAG_SEL_ENABLE is 1, then it indicates a programming error. + */ + uint32_t jtag_sel_enable_err:1; + /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0; + * If SOFT_DIS_JTAG is 1, then it indicates a programming error. + */ + uint32_t soft_dis_jtag_err:3; + /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0; + * If DIS_PAD_JTAG is 1, then it indicates a programming error. + */ + uint32_t dis_pad_jtag_err:1; + /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0; + * If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error. + */ + uint32_t dis_download_manual_encrypt_err:1; + /** usb_drefh_err : RO; bitpos: [22:21]; default: 0; + * If any bit in USB_DREFH is 1, then it indicates a programming error. + */ + uint32_t usb_drefh_err:2; + /** usb_drefl_err : RO; bitpos: [24:23]; default: 0; + * If any bit in USB_DREFL is 1, then it indicates a programming error. + */ + uint32_t usb_drefl_err:2; + /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0; + * If USB_EXCHG_PINS is 1, then it indicates a programming error. + */ + uint32_t usb_exchg_pins_err:1; + /** vdd_spi_as_gpio_err : RO; bitpos: [26]; default: 0; + * If VDD_SPI_AS_GPIO is 1, then it indicates a programming error. + */ + uint32_t vdd_spi_as_gpio_err:1; + /** btlc_gpio_enable_err : RO; bitpos: [28:27]; default: 0; + * If any bit in BTLC_GPIO_ENABLE is 1, then it indicates a programming error. + */ + uint32_t btlc_gpio_enable_err:2; + /** powerglitch_en_err : RO; bitpos: [29]; default: 0; + * If POWERGLITCH_EN is 1, then it indicates a programming error. + */ + uint32_t powerglitch_en_err:1; + /** power_glitch_dsense_err : RO; bitpos: [31:30]; default: 0; + * If any bit in POWER_GLITCH_DSENSE is 1, then it indicates a programming error. + */ + uint32_t power_glitch_dsense_err:2; + }; + uint32_t val; +} efuse_rd_repeat_err0_reg_t; + +/** Type of rd_repeat_err1 register + * Programming error record register 1 of BLOCK0. + */ +typedef union { + struct { + /** rpt4_reserved2_err : RO; bitpos: [15:0]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved2_err:16; + /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0; + * If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error. + */ + uint32_t wdt_delay_sel_err:2; + /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0; + * If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a programming error. + */ + uint32_t spi_boot_crypt_cnt_err:3; + /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0; + * If SECURE_BOOT_KEY_REVOKE0 is 1, then it indicates a programming error. + */ + uint32_t secure_boot_key_revoke0_err:1; + /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0; + * If SECURE_BOOT_KEY_REVOKE1 is 1, then it indicates a programming error. + */ + uint32_t secure_boot_key_revoke1_err:1; + /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0; + * If SECURE_BOOT_KEY_REVOKE2 is 1, then it indicates a programming error. + */ + uint32_t secure_boot_key_revoke2_err:1; + /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0; + * If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming error. + */ + uint32_t key_purpose_0_err:4; + /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0; + * If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming error. + */ + uint32_t key_purpose_1_err:4; + }; + uint32_t val; +} efuse_rd_repeat_err1_reg_t; + +/** Type of rd_repeat_err2 register + * Programming error record register 2 of BLOCK0. + */ +typedef union { + struct { + /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0; + * If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming error. + */ + uint32_t key_purpose_2_err:4; + /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0; + * If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming error. + */ + uint32_t key_purpose_3_err:4; + /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0; + * If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming error. + */ + uint32_t key_purpose_4_err:4; + /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0; + * If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming error. + */ + uint32_t key_purpose_5_err:4; + /** rpt4_reserved3_err : RO; bitpos: [19:16]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved3_err:4; + /** secure_boot_en_err : RO; bitpos: [20]; default: 0; + * If SECURE_BOOT_EN is 1, then it indicates a programming error. + */ + uint32_t secure_boot_en_err:1; + /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0; + * If SECURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error. + */ + uint32_t secure_boot_aggressive_revoke_err:1; + /** rpt4_reserved0_err : RO; bitpos: [27:22]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved0_err:6; + /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0; + * If any bit in FLASH_TPUM is 1, then it indicates a programming error. + */ + uint32_t flash_tpuw_err:4; + }; + uint32_t val; +} efuse_rd_repeat_err2_reg_t; + +/** Type of rd_repeat_err3 register + * Programming error record register 3 of BLOCK0. + */ +typedef union { + struct { + /** dis_download_mode_err : RO; bitpos: [0]; default: 0; + * If DIS_DOWNLOAD_MODE is 1, then it indicates a programming error. + */ + uint32_t dis_download_mode_err:1; + /** dis_legacy_spi_boot_err : RO; bitpos: [1]; default: 0; + * If DIS_LEGACY_SPI_BOOT is 1, then it indicates a programming error. + */ + uint32_t dis_legacy_spi_boot_err:1; + /** uart_print_channel_err : RO; bitpos: [2]; default: 0; + * If UART_PRINT_CHANNEL is 1, then it indicates a programming error. + */ + uint32_t uart_print_channel_err:1; + /** flash_ecc_mode_err : RO; bitpos: [3]; default: 0; + * If FLASH_ECC_MODE is 1, then it indicates a programming error. + */ + uint32_t flash_ecc_mode_err:1; + /** dis_usb_download_mode_err : RO; bitpos: [4]; default: 0; + * If DIS_USB_DOWNLOAD_MODE is 1, then it indicates a programming error. + */ + uint32_t dis_usb_download_mode_err:1; + /** enable_security_download_err : RO; bitpos: [5]; default: 0; + * If ENABLE_SECURITY_DOWNLOAD is 1, then it indicates a programming error. + */ + uint32_t enable_security_download_err:1; + /** uart_print_control_err : RO; bitpos: [7:6]; default: 0; + * If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error. + */ + uint32_t uart_print_control_err:2; + /** pin_power_selection_err : RO; bitpos: [8]; default: 0; + * If PIN_POWER_SELECTION is 1, then it indicates a programming error. + */ + uint32_t pin_power_selection_err:1; + /** flash_type_err : RO; bitpos: [9]; default: 0; + * If FLASH_TYPE is 1, then it indicates a programming error. + */ + uint32_t flash_type_err:1; + /** flash_page_size_err : RO; bitpos: [11:10]; default: 0; + * If any bits in FLASH_PAGE_SIZE is 1, then it indicates a programming error. + */ + uint32_t flash_page_size_err:2; + /** flash_ecc_en_err : RO; bitpos: [12]; default: 0; + * If FLASH_ECC_EN_ERR is 1, then it indicates a programming error. + */ + uint32_t flash_ecc_en_err:1; + /** force_send_resume_err : RO; bitpos: [13]; default: 0; + * If FORCE_SEND_RESUME is 1, then it indicates a programming error. + */ + uint32_t force_send_resume_err:1; + /** secure_version_err : RO; bitpos: [29:14]; default: 0; + * If any bit in SECURE_VERSION is 1, then it indicates a programming error. + */ + uint32_t secure_version_err:16; + /** rpt4_reserved1_err : RO; bitpos: [31:30]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved1_err:2; + }; + uint32_t val; +} efuse_rd_repeat_err3_reg_t; + +/** Type of rd_repeat_err4 register + * Programming error record register 4 of BLOCK0. + */ +typedef union { + struct { + /** rpt4_reserved4_err : RO; bitpos: [23:0]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved4_err:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} efuse_rd_repeat_err4_reg_t; + +/** Type of rd_rs_err0 register + * Programming error record register 0 of BLOCK1-10. + */ +typedef union { + struct { + /** mac_spi_8m_err_num : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t mac_spi_8m_err_num:3; + /** reserved_fail : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t reserved_fail:1; + /** sys_part1_num : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t sys_part1_num:3; + /** mac_spi_8m_fail : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part1 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t mac_spi_8m_fail:1; + /** usr_data_err_num : RO; bitpos: [10:8]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t usr_data_err_num:3; + /** sys_part1_fail : RO; bitpos: [11]; default: 0; + * 0: Means no failure and that the user data is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. + */ + uint32_t sys_part1_fail:1; + /** key0_err_num : RO; bitpos: [14:12]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key0_err_num:3; + /** usr_data_fail : RO; bitpos: [15]; default: 0; + * 0: Means no failure and that the data of key0 is reliable 1: Means that programming + * key0 failed and the number of error bytes is over 6. + */ + uint32_t usr_data_fail:1; + /** key1_err_num : RO; bitpos: [18:16]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key1_err_num:3; + /** key0_fail : RO; bitpos: [19]; default: 0; + * 0: Means no failure and that the data of key1 is reliable 1: Means that programming + * key1 failed and the number of error bytes is over 6. + */ + uint32_t key0_fail:1; + /** key2_err_num : RO; bitpos: [22:20]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key2_err_num:3; + /** key1_fail : RO; bitpos: [23]; default: 0; + * 0: Means no failure and that the data of key2 is reliable 1: Means that programming + * key2 failed and the number of error bytes is over 6. + */ + uint32_t key1_fail:1; + /** key3_err_num : RO; bitpos: [26:24]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key3_err_num:3; + /** key2_fail : RO; bitpos: [27]; default: 0; + * 0: Means no failure and that the data of key3 is reliable 1: Means that programming + * key3 failed and the number of error bytes is over 6. + */ + uint32_t key2_fail:1; + /** key4_err_num : RO; bitpos: [30:28]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key4_err_num:3; + /** key3_fail : RO; bitpos: [31]; default: 0; + * 0: Means no failure and that the data of key4 is reliable 1: Means that programming + * key4 failed and the number of error bytes is over 6. + */ + uint32_t key3_fail:1; + }; + uint32_t val; +} efuse_rd_rs_err0_reg_t; + +/** Type of rd_rs_err1 register + * Programming error record register 1 of BLOCK1-10. + */ +typedef union { + struct { + /** key5_err_num : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key5_err_num:3; + /** key4_fail : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of KEY5 is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. + */ + uint32_t key4_fail:1; + /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t sys_part2_err_num:3; + /** key5_fail : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part2 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t key5_fail:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} efuse_rd_rs_err1_reg_t; + + +/** Group: Configuration Register */ +/** Type of clk register + * eFuse clcok configuration register. + */ +typedef union { + struct { + /** efuse_mem_force_pd : R/W; bitpos: [0]; default: 0; + * Set this bit to force eFuse SRAM into power-saving mode. + */ + uint32_t efuse_mem_force_pd:1; + /** mem_clk_force_on : R/W; bitpos: [1]; default: 1; + * Set this bit and force to activate clock signal of eFuse SRAM. + */ + uint32_t mem_clk_force_on:1; + /** efuse_mem_force_pu : R/W; bitpos: [2]; default: 0; + * Set this bit to force eFuse SRAM into working mode. + */ + uint32_t efuse_mem_force_pu:1; + uint32_t reserved_3:13; + /** clk_en : R/W; bitpos: [16]; default: 0; + * Set this bit and force to enable clock signal of eFuse memory. + */ + uint32_t clk_en:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} efuse_clk_reg_t; + +/** Type of conf register + * eFuse operation mode configuraiton register; + */ +typedef union { + struct { + /** op_code : R/W; bitpos: [15:0]; default: 0; + * 0x5A5A: Operate programming command 0x5AA5: Operate read command. + */ + uint32_t op_code:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} efuse_conf_reg_t; + +/** Type of cmd register + * eFuse command register. + */ +typedef union { + struct { + /** read_cmd : R/WS/SC; bitpos: [0]; default: 0; + * Set this bit to send read command. + */ + uint32_t read_cmd:1; + /** pgm_cmd : R/WS/SC; bitpos: [1]; default: 0; + * Set this bit to send programming command. + */ + uint32_t pgm_cmd:1; + /** blk_num : R/W; bitpos: [5:2]; default: 0; + * The serial number of the block to be programmed. Value 0-10 corresponds to block + * number 0-10, respectively. + */ + uint32_t blk_num:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} efuse_cmd_reg_t; + +/** Type of dac_conf register + * Controls the eFuse programming voltage. + */ +typedef union { + struct { + /** dac_clk_div : R/W; bitpos: [7:0]; default: 28; + * Controls the division factor of the rising clock of the programming voltage. + */ + uint32_t dac_clk_div:8; + /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; + * Don't care. + */ + uint32_t dac_clk_pad_sel:1; + /** dac_num : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ + uint32_t dac_num:8; + /** oe_clr : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ + uint32_t oe_clr:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} efuse_dac_conf_reg_t; + +/** Type of rd_tim_conf register + * Configures read timing parameters. + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** read_init_num : R/W; bitpos: [31:24]; default: 18; + * Configures the initial read time of eFuse. + */ + uint32_t read_init_num:8; + }; + uint32_t val; +} efuse_rd_tim_conf_reg_t; + +/** Type of wr_tim_conf1 register + * Configurarion register 1 of eFuse programming timing parameters. + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** pwr_on_num : R/W; bitpos: [23:8]; default: 10368; + * Configures the power up time for VDDQ. + */ + uint32_t pwr_on_num:16; + uint32_t reserved_24:8; + }; + uint32_t val; +} efuse_wr_tim_conf1_reg_t; + +/** Type of wr_tim_conf2 register + * Configurarion register 2 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** pwr_off_num : R/W; bitpos: [15:0]; default: 400; + * Configures the power outage time for VDDQ. + */ + uint32_t pwr_off_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} efuse_wr_tim_conf2_reg_t; + + +/** Group: Status Register */ +/** Type of status register + * eFuse status register. + */ +typedef union { + struct { + /** state : RO; bitpos: [3:0]; default: 0; + * Indicates the state of the eFuse state machine. + */ + uint32_t state:4; + /** otp_load_sw : RO; bitpos: [4]; default: 0; + * The value of OTP_LOAD_SW. + */ + uint32_t otp_load_sw:1; + /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0; + * The value of OTP_VDDQ_C_SYNC2. + */ + uint32_t otp_vddq_c_sync2:1; + /** otp_strobe_sw : RO; bitpos: [6]; default: 0; + * The value of OTP_STROBE_SW. + */ + uint32_t otp_strobe_sw:1; + /** otp_csb_sw : RO; bitpos: [7]; default: 0; + * The value of OTP_CSB_SW. + */ + uint32_t otp_csb_sw:1; + /** otp_pgenb_sw : RO; bitpos: [8]; default: 0; + * The value of OTP_PGENB_SW. + */ + uint32_t otp_pgenb_sw:1; + /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0; + * The value of OTP_VDDQ_IS_SW. + */ + uint32_t otp_vddq_is_sw:1; + /** repeat_err_cnt : RO; bitpos: [17:10]; default: 0; + * Indicates the number of error bits during programming BLOCK0. + */ + uint32_t repeat_err_cnt:8; + uint32_t reserved_18:14; + }; + uint32_t val; +} efuse_status_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * eFuse raw interrupt register. + */ +typedef union { + struct { + /** read_done_int_raw : R/WC/SS; bitpos: [0]; default: 0; + * The raw bit signal for read_done interrupt. + */ + uint32_t read_done_int_raw:1; + /** pgm_done_int_raw : R/WC/SS; bitpos: [1]; default: 0; + * The raw bit signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_raw_reg_t; + +/** Type of int_st register + * eFuse interrupt status register. + */ +typedef union { + struct { + /** read_done_int_st : RO; bitpos: [0]; default: 0; + * The status signal for read_done interrupt. + */ + uint32_t read_done_int_st:1; + /** pgm_done_int_st : RO; bitpos: [1]; default: 0; + * The status signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_st:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_st_reg_t; + +/** Type of int_ena register + * eFuse interrupt enable register. + */ +typedef union { + struct { + /** read_done_int_ena : R/W; bitpos: [0]; default: 0; + * The enable signal for read_done interrupt. + */ + uint32_t read_done_int_ena:1; + /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0; + * The enable signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_ena_reg_t; + +/** Type of int_clr register + * eFuse interrupt clear register. + */ +typedef union { + struct { + /** read_done_int_clr : WO; bitpos: [0]; default: 0; + * The clear signal for read_done interrupt. + */ + uint32_t read_done_int_clr:1; + /** pgm_done_int_clr : WO; bitpos: [1]; default: 0; + * The clear signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_clr_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * eFuse version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 33583616; + * Stores eFuse version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} efuse_date_reg_t; + + +typedef struct { + volatile efuse_pgm_data0_reg_t pgm_data0; + volatile efuse_pgm_data1_reg_t pgm_data1; + volatile efuse_pgm_data2_reg_t pgm_data2; + volatile efuse_pgm_data3_reg_t pgm_data3; + volatile efuse_pgm_data4_reg_t pgm_data4; + volatile efuse_pgm_data5_reg_t pgm_data5; + volatile efuse_pgm_data6_reg_t pgm_data6; + volatile efuse_pgm_data7_reg_t pgm_data7; + volatile efuse_pgm_check_value0_reg_t pgm_check_value0; + volatile efuse_pgm_check_value1_reg_t pgm_check_value1; + volatile efuse_pgm_check_value2_reg_t pgm_check_value2; + volatile efuse_rd_wr_dis_reg_t rd_wr_dis; + volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; + volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1; + volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2; + volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3; + volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4; + volatile efuse_rd_mac_spi_sys_0_reg_t rd_mac_spi_sys_0; + volatile efuse_rd_mac_spi_sys_1_reg_t rd_mac_spi_sys_1; + volatile efuse_rd_mac_spi_sys_2_reg_t rd_mac_spi_sys_2; + volatile efuse_rd_mac_spi_sys_3_reg_t rd_mac_spi_sys_3; + volatile efuse_rd_mac_spi_sys_4_reg_t rd_mac_spi_sys_4; + volatile efuse_rd_mac_spi_sys_5_reg_t rd_mac_spi_sys_5; + volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0; + volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1; + volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2; + volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3; + volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4; + volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5; + volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6; + volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7; + volatile efuse_rd_usr_data0_reg_t rd_usr_data0; + volatile efuse_rd_usr_data1_reg_t rd_usr_data1; + volatile efuse_rd_usr_data2_reg_t rd_usr_data2; + volatile efuse_rd_usr_data3_reg_t rd_usr_data3; + volatile efuse_rd_usr_data4_reg_t rd_usr_data4; + volatile efuse_rd_usr_data5_reg_t rd_usr_data5; + volatile efuse_rd_usr_data6_reg_t rd_usr_data6; + volatile efuse_rd_usr_data7_reg_t rd_usr_data7; + volatile efuse_rd_key0_data0_reg_t rd_key0_data0; + volatile efuse_rd_key0_data1_reg_t rd_key0_data1; + volatile efuse_rd_key0_data2_reg_t rd_key0_data2; + volatile efuse_rd_key0_data3_reg_t rd_key0_data3; + volatile efuse_rd_key0_data4_reg_t rd_key0_data4; + volatile efuse_rd_key0_data5_reg_t rd_key0_data5; + volatile efuse_rd_key0_data6_reg_t rd_key0_data6; + volatile efuse_rd_key0_data7_reg_t rd_key0_data7; + volatile efuse_rd_key1_data0_reg_t rd_key1_data0; + volatile efuse_rd_key1_data1_reg_t rd_key1_data1; + volatile efuse_rd_key1_data2_reg_t rd_key1_data2; + volatile efuse_rd_key1_data3_reg_t rd_key1_data3; + volatile efuse_rd_key1_data4_reg_t rd_key1_data4; + volatile efuse_rd_key1_data5_reg_t rd_key1_data5; + volatile efuse_rd_key1_data6_reg_t rd_key1_data6; + volatile efuse_rd_key1_data7_reg_t rd_key1_data7; + volatile efuse_rd_key2_data0_reg_t rd_key2_data0; + volatile efuse_rd_key2_data1_reg_t rd_key2_data1; + volatile efuse_rd_key2_data2_reg_t rd_key2_data2; + volatile efuse_rd_key2_data3_reg_t rd_key2_data3; + volatile efuse_rd_key2_data4_reg_t rd_key2_data4; + volatile efuse_rd_key2_data5_reg_t rd_key2_data5; + volatile efuse_rd_key2_data6_reg_t rd_key2_data6; + volatile efuse_rd_key2_data7_reg_t rd_key2_data7; + volatile efuse_rd_key3_data0_reg_t rd_key3_data0; + volatile efuse_rd_key3_data1_reg_t rd_key3_data1; + volatile efuse_rd_key3_data2_reg_t rd_key3_data2; + volatile efuse_rd_key3_data3_reg_t rd_key3_data3; + volatile efuse_rd_key3_data4_reg_t rd_key3_data4; + volatile efuse_rd_key3_data5_reg_t rd_key3_data5; + volatile efuse_rd_key3_data6_reg_t rd_key3_data6; + volatile efuse_rd_key3_data7_reg_t rd_key3_data7; + volatile efuse_rd_key4_data0_reg_t rd_key4_data0; + volatile efuse_rd_key4_data1_reg_t rd_key4_data1; + volatile efuse_rd_key4_data2_reg_t rd_key4_data2; + volatile efuse_rd_key4_data3_reg_t rd_key4_data3; + volatile efuse_rd_key4_data4_reg_t rd_key4_data4; + volatile efuse_rd_key4_data5_reg_t rd_key4_data5; + volatile efuse_rd_key4_data6_reg_t rd_key4_data6; + volatile efuse_rd_key4_data7_reg_t rd_key4_data7; + volatile efuse_rd_key5_data0_reg_t rd_key5_data0; + volatile efuse_rd_key5_data1_reg_t rd_key5_data1; + volatile efuse_rd_key5_data2_reg_t rd_key5_data2; + volatile efuse_rd_key5_data3_reg_t rd_key5_data3; + volatile efuse_rd_key5_data4_reg_t rd_key5_data4; + volatile efuse_rd_key5_data5_reg_t rd_key5_data5; + volatile efuse_rd_key5_data6_reg_t rd_key5_data6; + volatile efuse_rd_key5_data7_reg_t rd_key5_data7; + volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0; + volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1; + volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2; + volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3; + volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4; + volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5; + volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6; + volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7; + volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0; + volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1; + volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2; + volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3; + uint32_t reserved_18c; + volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4; + uint32_t reserved_194[11]; + volatile efuse_rd_rs_err0_reg_t rd_rs_err0; + volatile efuse_rd_rs_err1_reg_t rd_rs_err1; + volatile efuse_clk_reg_t clk; + volatile efuse_conf_reg_t conf; + volatile efuse_status_reg_t status; + volatile efuse_cmd_reg_t cmd; + volatile efuse_int_raw_reg_t int_raw; + volatile efuse_int_st_reg_t int_st; + volatile efuse_int_ena_reg_t int_ena; + volatile efuse_int_clr_reg_t int_clr; + volatile efuse_dac_conf_reg_t dac_conf; + volatile efuse_rd_tim_conf_reg_t rd_tim_conf; + volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1; + volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2; uint32_t reserved_1f8; - union { - struct { - uint32_t date: 28; /*Stores eFuse version.*/ - uint32_t reserved28: 4; /*Reserved.*/ - }; - uint32_t val; - } date; + volatile efuse_date_reg_t date; } efuse_dev_t; extern efuse_dev_t EFUSE; + +#ifndef __cplusplus +_Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure"); +#endif + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32c3/include/soc/esp32c3/include/soc/soc_caps.h b/tools/sdk/esp32c3/include/soc/esp32c3/include/soc/soc_caps.h index c7abe37fad5..298907c34c7 100644 --- a/tools/sdk/esp32c3/include/soc/esp32c3/include/soc/soc_caps.h +++ b/tools/sdk/esp32c3/include/soc/esp32c3/include/soc/soc_caps.h @@ -339,6 +339,8 @@ #define SOC_EFUSE_DIS_USB_JTAG 1 #define SOC_EFUSE_DIS_DIRECT_BOOT 1 #define SOC_EFUSE_SOFT_DIS_JTAG 1 +#define SOC_EFUSE_DIS_ICACHE 1 +#define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // AES-XTS key purpose not supported for this block /*-------------------------- Secure Boot CAPS----------------------------*/ #define SOC_SECURE_BOOT_V2_RSA 1 @@ -417,3 +419,4 @@ #define SOC_BLE_SUPPORTED (1) /*!< Support Bluetooth Low Energy hardware */ #define SOC_BLE_MESH_SUPPORTED (1) /*!< Support BLE MESH */ #define SOC_BLE_50_SUPPORTED (1) /*!< Support Bluetooth 5.0 */ +#define SOC_BLE_DEVICE_PRIVACY_SUPPORTED (1) /*!< Support BLE device privacy mode */ diff --git a/tools/sdk/esp32c3/include/spi_flash/include/esp_spi_flash_counters.h b/tools/sdk/esp32c3/include/spi_flash/include/esp_spi_flash_counters.h index ab8157c256d..3355ee16bc2 100644 --- a/tools/sdk/esp32c3/include/spi_flash/include/esp_spi_flash_counters.h +++ b/tools/sdk/esp32c3/include/spi_flash/include/esp_spi_flash_counters.h @@ -1,16 +1,8 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -32,31 +24,38 @@ typedef struct { uint32_t count; // number of times operation was executed uint32_t time; // total time taken, in microseconds uint32_t bytes; // total number of bytes -} spi_flash_counter_t; +} esp_flash_counter_t; typedef struct { - spi_flash_counter_t read; - spi_flash_counter_t write; - spi_flash_counter_t erase; -} spi_flash_counters_t; + esp_flash_counter_t read; + esp_flash_counter_t write; + esp_flash_counter_t erase; +} esp_flash_counters_t; + +// for deprecate old api +typedef esp_flash_counter_t spi_flash_counter_t; +typedef esp_flash_counters_t spi_flash_counters_t; /** * @brief Reset SPI flash operation counters */ -void spi_flash_reset_counters(void); +void esp_flash_reset_counters(void); +void spi_flash_reset_counters(void) __attribute__((deprecated("Please use 'esp_flash_reset_counters' instead"))); /** * @brief Print SPI flash operation counters */ -void spi_flash_dump_counters(void); +void esp_flash_dump_counters(FILE* stream); +void spi_flash_dump_counters(void) __attribute__((deprecated("Please use 'esp_flash_dump_counters' instead"))); /** * @brief Return current SPI flash operation counters * - * @return pointer to the spi_flash_counters_t structure holding values + * @return pointer to the esp_flash_counters_t structure holding values * of the operation counters */ -const spi_flash_counters_t* spi_flash_get_counters(void); +const esp_flash_counters_t* esp_flash_get_counters(void); +const spi_flash_counters_t* spi_flash_get_counters(void) __attribute__((deprecated("Please use 'esp_flash_get_counters' instead"))); #ifdef __cplusplus } diff --git a/tools/sdk/esp32c3/include/tcp_transport/include/esp_transport_socks_proxy.h b/tools/sdk/esp32c3/include/tcp_transport/include/esp_transport_socks_proxy.h new file mode 100644 index 00000000000..566ed9a6de6 --- /dev/null +++ b/tools/sdk/esp32c3/include/tcp_transport/include/esp_transport_socks_proxy.h @@ -0,0 +1,61 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "esp_transport.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum socks_version_t {SOCKS4 = 4} socks_version_t; + +typedef enum socks_transport_response_t { + // The following values correspond to transport operation + SOCKS_RESPONSE_TARGET_NOT_FOUND = 0xF0, + SOCKS_RESPONSE_PROXY_UNREACHABLE = 0xF1, + SOCKS_TIMEOUT = 0xF2, + // The following values are defined by the SOCKS4 protocol + SOCKS_RESPONSE_SUCCESS = 0x5a, + SOCKS_RESPONSE_REQUEST_REJECTED = 0x5B, + SOCKS_RESPONSE_NOT_RUNNING_IDENTD = 0x5c, + SOCKS_RESPONSE_COULD_NOT_CONFIRM_ID = 0x5d, +} socks_transport_error_t; + +/* + * Socks configuration structure + */ +typedef struct esp_transport_socks_proxy_config_t { + const socks_version_t version; /*!< Socks protocol version.*/ + const char *address;/*!< Proxy address*/ + const int port; /*< Proxy port*/ +} esp_transport_socks_proxy_config_t; + +/** +* @brief Create a proxy transport +* @param parent_handle Handle for the parent transport +* @param config Pointer to the configuration structure to use +* +* @return +* - transport Handler for the created transport. +* - NULL in case of failure +*/ +esp_transport_handle_t esp_transport_socks_proxy_init(esp_transport_handle_t parent_handle, const esp_transport_socks_proxy_config_t *config); + +/** +* @brief Changes the configuration of the proxy +* @param socks_transport Handle for the transport +* @param config Pointer to the configuration structure to use +* +* @return +* - ESP_OK on success +*/ +esp_err_t esp_transport_socks_proxy_set_config(esp_transport_handle_t socks_transport, const esp_transport_socks_proxy_config_t *config); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32c3/ld/esp32c3.rom.ld b/tools/sdk/esp32c3/ld/esp32c3.rom.ld index df98b64643e..067243d1517 100644 --- a/tools/sdk/esp32c3/ld/esp32c3.rom.ld +++ b/tools/sdk/esp32c3/ld/esp32c3.rom.ld @@ -1686,7 +1686,7 @@ rcClearCurSched = 0x4000175c; rcClearCurStat = 0x40001760; rcLowerSched = 0x40001768; rcSetTxAmpduLimit = 0x4000176c; -rcTxUpdatePer = 0x40001770; +/* rcTxUpdatePer = 0x40001770;*/ rcUpdateAckSnr = 0x40001774; rcUpdateRate = 0x40001778; /* rcUpdateTxDone = 0x4000177c; */ diff --git a/tools/sdk/esp32c3/ld/libbtbb.a b/tools/sdk/esp32c3/ld/libbtbb.a index 2cac83941ae..51b90e07801 100644 Binary files a/tools/sdk/esp32c3/ld/libbtbb.a and b/tools/sdk/esp32c3/ld/libbtbb.a differ diff --git a/tools/sdk/esp32c3/ld/libbtdm_app.a b/tools/sdk/esp32c3/ld/libbtdm_app.a index 729e47ae564..3b444919276 100644 Binary files a/tools/sdk/esp32c3/ld/libbtdm_app.a and b/tools/sdk/esp32c3/ld/libbtdm_app.a differ diff --git a/tools/sdk/esp32c3/ld/libphy.a b/tools/sdk/esp32c3/ld/libphy.a index d5be1b5dbec..a8611617b2a 100644 Binary files a/tools/sdk/esp32c3/ld/libphy.a and b/tools/sdk/esp32c3/ld/libphy.a differ diff --git a/tools/sdk/esp32c3/ld/sections.ld b/tools/sdk/esp32c3/ld/sections.ld index 22d0a7a538b..4318e7497d0 100644 --- a/tools/sdk/esp32c3/ld/sections.ld +++ b/tools/sdk/esp32c3/ld/sections.ld @@ -1,6 +1,6 @@ /* Automatically generated file; DO NOT EDIT */ /* Espressif IoT Development Framework Linker Script */ -/* Generated from: /Users/ficeto/Desktop/ESP32/ESP-IDF-5/esp32-arduino-lib-builder/esp-idf/components/esp_system/ld/esp32c3/sections.ld.in */ +/* Generated from: /home/runner/work/esp32-arduino-lib-builder/esp32-arduino-lib-builder/esp-idf/components/esp_system/ld/esp32c3/sections.ld.in */ /* * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD @@ -230,6 +230,7 @@ SECTIONS *libnewlib.a:abort.*(.literal .literal.* .text .text.*) *libnewlib.a:assert.*(.literal .literal.* .text .text.*) *libnewlib.a:heap.*(.literal .literal.* .text .text.*) + *libnewlib.a:port_stdatomic.*(.literal .literal.* .text .text.*) *libnewlib.a:stdatomic.*(.literal .literal.* .text .text.*) *libriscv.a:interrupt.*(.literal .literal.* .text .text.*) *libriscv.a:vectors.*(.literal .literal.* .text .text.*) @@ -318,6 +319,7 @@ SECTIONS *libnewlib.a:abort.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) *libnewlib.a:assert.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) *libnewlib.a:heap.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libnewlib.a:port_stdatomic.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) *libnewlib.a:stdatomic.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) . = ALIGN(4); _nimble_data_start = ABSOLUTE(.); @@ -431,7 +433,7 @@ SECTIONS _instruction_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.text start, this can be used for mmu driver to maintain virtual address */ _text_start = ABSOLUTE(.); - *(EXCLUDE_FILE(*libesp_ringbuf.a *libfreertos.a *libgcov.a *librtc.a *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libapp_trace.a:port_uart.* *libesp_event.a:default_event_loop.* *libesp_event.a:esp_event.* *libesp_hw_support.a:cpu.* *libesp_hw_support.a:esp_gpio_reserve.* *libesp_hw_support.a:esp_memory_utils.* *libesp_hw_support.a:rtc_clk.* *libesp_hw_support.a:rtc_sleep.* *libesp_hw_support.a:rtc_time.* *libesp_hw_support.a:systimer.* *libesp_mm.a:esp_cache.* *libesp_rom.a:esp_rom_spiflash.* *libesp_rom.a:esp_rom_systimer.* *libesp_system.a:esp_err.* *libesp_system.a:esp_system_chip.* *libesp_system.a:ubsan.* *libgcc.a:_divsf3.* *libgcc.a:lib2funcs.* *libgcc.a:save-restore.* *libhal.a:cache_hal.* *libhal.a:i2c_hal_iram.* *libhal.a:ledc_hal_iram.* *libhal.a:mmu_hal.* *libhal.a:spi_flash_encrypt_hal_iram.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:spi_flash_hal_iram.* *libhal.a:spi_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libheap.a:tlsf.* *liblog.a:log.* *liblog.a:log_freertos.* *libnewlib.a:abort.* *libnewlib.a:assert.* *libnewlib.a:heap.* *libnewlib.a:stdatomic.* *libriscv.a:interrupt.* *libriscv.a:vectors.* *libsoc.a:lldesc.* *libspi_flash.a:flash_brownout_hook.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_boya.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:spi_flash_chip_generic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_th.* *libspi_flash.a:spi_flash_chip_winbond.* *libspi_flash.a:spi_flash_wrap.*) .literal EXCLUDE_FILE(*libesp_ringbuf.a *libfreertos.a *libgcov.a *librtc.a *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libapp_trace.a:port_uart.* *libesp_event.a:default_event_loop.* *libesp_event.a:esp_event.* *libesp_hw_support.a:cpu.* *libesp_hw_support.a:esp_gpio_reserve.* *libesp_hw_support.a:esp_memory_utils.* *libesp_hw_support.a:rtc_clk.* *libesp_hw_support.a:rtc_sleep.* *libesp_hw_support.a:rtc_time.* *libesp_hw_support.a:systimer.* *libesp_mm.a:esp_cache.* *libesp_rom.a:esp_rom_spiflash.* *libesp_rom.a:esp_rom_systimer.* *libesp_system.a:esp_err.* *libesp_system.a:esp_system_chip.* *libesp_system.a:ubsan.* *libgcc.a:_divsf3.* *libgcc.a:lib2funcs.* *libgcc.a:save-restore.* *libhal.a:cache_hal.* *libhal.a:i2c_hal_iram.* *libhal.a:ledc_hal_iram.* *libhal.a:mmu_hal.* *libhal.a:spi_flash_encrypt_hal_iram.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:spi_flash_hal_iram.* *libhal.a:spi_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libheap.a:tlsf.* *liblog.a:log.* *liblog.a:log_freertos.* *libnewlib.a:abort.* *libnewlib.a:assert.* *libnewlib.a:heap.* *libnewlib.a:stdatomic.* *libriscv.a:interrupt.* *libriscv.a:vectors.* *libsoc.a:lldesc.* *libspi_flash.a:flash_brownout_hook.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_boya.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:spi_flash_chip_generic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_th.* *libspi_flash.a:spi_flash_chip_winbond.* *libspi_flash.a:spi_flash_wrap.*) .literal.* EXCLUDE_FILE(*libesp_ringbuf.a *libfreertos.a *libgcov.a *librtc.a *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libapp_trace.a:port_uart.* *libesp_event.a:default_event_loop.* *libesp_event.a:esp_event.* *libesp_hw_support.a:cpu.* *libesp_hw_support.a:esp_gpio_reserve.* *libesp_hw_support.a:esp_memory_utils.* *libesp_hw_support.a:rtc_clk.* *libesp_hw_support.a:rtc_sleep.* *libesp_hw_support.a:rtc_time.* *libesp_hw_support.a:systimer.* *libesp_mm.a:esp_cache.* *libesp_rom.a:esp_rom_spiflash.* *libesp_rom.a:esp_rom_systimer.* *libesp_system.a:esp_err.* *libesp_system.a:esp_system_chip.* *libesp_system.a:ubsan.* *libgcc.a:_divsf3.* *libgcc.a:lib2funcs.* *libgcc.a:save-restore.* *libhal.a:cache_hal.* *libhal.a:i2c_hal_iram.* *libhal.a:ledc_hal_iram.* *libhal.a:mmu_hal.* *libhal.a:spi_flash_encrypt_hal_iram.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:spi_flash_hal_iram.* *libhal.a:spi_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libheap.a:tlsf.* *liblog.a:log.* *liblog.a:log_freertos.* *libnewlib.a:abort.* *libnewlib.a:assert.* *libnewlib.a:heap.* *libnewlib.a:stdatomic.* *libriscv.a:interrupt.* *libriscv.a:vectors.* *libsoc.a:lldesc.* *libspi_flash.a:flash_brownout_hook.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_boya.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:spi_flash_chip_generic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_th.* *libspi_flash.a:spi_flash_chip_winbond.* *libspi_flash.a:spi_flash_wrap.*) .text EXCLUDE_FILE(*libesp_ringbuf.a *libfreertos.a *libgcov.a *librtc.a *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libapp_trace.a:port_uart.* *libesp_event.a:default_event_loop.* *libesp_event.a:esp_event.* *libesp_hw_support.a:cpu.* *libesp_hw_support.a:esp_gpio_reserve.* *libesp_hw_support.a:esp_memory_utils.* *libesp_hw_support.a:rtc_clk.* *libesp_hw_support.a:rtc_sleep.* *libesp_hw_support.a:rtc_time.* *libesp_hw_support.a:systimer.* *libesp_mm.a:esp_cache.* *libesp_rom.a:esp_rom_spiflash.* *libesp_rom.a:esp_rom_systimer.* *libesp_system.a:esp_err.* *libesp_system.a:esp_system_chip.* *libesp_system.a:ubsan.* *libgcc.a:_divsf3.* *libgcc.a:lib2funcs.* *libgcc.a:save-restore.* *libhal.a:cache_hal.* *libhal.a:i2c_hal_iram.* *libhal.a:ledc_hal_iram.* *libhal.a:mmu_hal.* *libhal.a:spi_flash_encrypt_hal_iram.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:spi_flash_hal_iram.* *libhal.a:spi_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libheap.a:tlsf.* *liblog.a:log.* *liblog.a:log_freertos.* *libnewlib.a:abort.* *libnewlib.a:assert.* *libnewlib.a:heap.* *libnewlib.a:stdatomic.* *libriscv.a:interrupt.* *libriscv.a:vectors.* *libsoc.a:lldesc.* *libspi_flash.a:flash_brownout_hook.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_boya.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:spi_flash_chip_generic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_th.* *libspi_flash.a:spi_flash_chip_winbond.* *libspi_flash.a:spi_flash_wrap.*) .text.*) + *(EXCLUDE_FILE(*libesp_ringbuf.a *libfreertos.a *libgcov.a *librtc.a *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libapp_trace.a:port_uart.* *libesp_event.a:default_event_loop.* *libesp_event.a:esp_event.* *libesp_hw_support.a:cpu.* *libesp_hw_support.a:esp_gpio_reserve.* *libesp_hw_support.a:esp_memory_utils.* *libesp_hw_support.a:rtc_clk.* *libesp_hw_support.a:rtc_sleep.* *libesp_hw_support.a:rtc_time.* *libesp_hw_support.a:systimer.* *libesp_mm.a:esp_cache.* *libesp_rom.a:esp_rom_spiflash.* *libesp_rom.a:esp_rom_systimer.* *libesp_system.a:esp_err.* *libesp_system.a:esp_system_chip.* *libesp_system.a:ubsan.* *libgcc.a:_divsf3.* *libgcc.a:lib2funcs.* *libgcc.a:save-restore.* *libhal.a:cache_hal.* *libhal.a:i2c_hal_iram.* *libhal.a:ledc_hal_iram.* *libhal.a:mmu_hal.* *libhal.a:spi_flash_encrypt_hal_iram.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:spi_flash_hal_iram.* *libhal.a:spi_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libheap.a:tlsf.* *liblog.a:log.* *liblog.a:log_freertos.* *libnewlib.a:abort.* *libnewlib.a:assert.* *libnewlib.a:heap.* *libnewlib.a:port_stdatomic.* *libnewlib.a:stdatomic.* *libriscv.a:interrupt.* *libriscv.a:vectors.* *libsoc.a:lldesc.* *libspi_flash.a:flash_brownout_hook.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_boya.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:spi_flash_chip_generic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_th.* *libspi_flash.a:spi_flash_chip_winbond.* *libspi_flash.a:spi_flash_wrap.*) .literal EXCLUDE_FILE(*libesp_ringbuf.a *libfreertos.a *libgcov.a *librtc.a *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libapp_trace.a:port_uart.* *libesp_event.a:default_event_loop.* *libesp_event.a:esp_event.* *libesp_hw_support.a:cpu.* *libesp_hw_support.a:esp_gpio_reserve.* *libesp_hw_support.a:esp_memory_utils.* *libesp_hw_support.a:rtc_clk.* *libesp_hw_support.a:rtc_sleep.* *libesp_hw_support.a:rtc_time.* *libesp_hw_support.a:systimer.* *libesp_mm.a:esp_cache.* *libesp_rom.a:esp_rom_spiflash.* *libesp_rom.a:esp_rom_systimer.* *libesp_system.a:esp_err.* *libesp_system.a:esp_system_chip.* *libesp_system.a:ubsan.* *libgcc.a:_divsf3.* *libgcc.a:lib2funcs.* *libgcc.a:save-restore.* *libhal.a:cache_hal.* *libhal.a:i2c_hal_iram.* *libhal.a:ledc_hal_iram.* *libhal.a:mmu_hal.* *libhal.a:spi_flash_encrypt_hal_iram.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:spi_flash_hal_iram.* *libhal.a:spi_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libheap.a:tlsf.* *liblog.a:log.* *liblog.a:log_freertos.* *libnewlib.a:abort.* *libnewlib.a:assert.* *libnewlib.a:heap.* *libnewlib.a:port_stdatomic.* *libnewlib.a:stdatomic.* *libriscv.a:interrupt.* *libriscv.a:vectors.* *libsoc.a:lldesc.* *libspi_flash.a:flash_brownout_hook.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_boya.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:spi_flash_chip_generic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_th.* *libspi_flash.a:spi_flash_chip_winbond.* *libspi_flash.a:spi_flash_wrap.*) .literal.* EXCLUDE_FILE(*libesp_ringbuf.a *libfreertos.a *libgcov.a *librtc.a *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libapp_trace.a:port_uart.* *libesp_event.a:default_event_loop.* *libesp_event.a:esp_event.* *libesp_hw_support.a:cpu.* *libesp_hw_support.a:esp_gpio_reserve.* *libesp_hw_support.a:esp_memory_utils.* *libesp_hw_support.a:rtc_clk.* *libesp_hw_support.a:rtc_sleep.* *libesp_hw_support.a:rtc_time.* *libesp_hw_support.a:systimer.* *libesp_mm.a:esp_cache.* *libesp_rom.a:esp_rom_spiflash.* *libesp_rom.a:esp_rom_systimer.* *libesp_system.a:esp_err.* *libesp_system.a:esp_system_chip.* *libesp_system.a:ubsan.* *libgcc.a:_divsf3.* *libgcc.a:lib2funcs.* *libgcc.a:save-restore.* *libhal.a:cache_hal.* *libhal.a:i2c_hal_iram.* *libhal.a:ledc_hal_iram.* *libhal.a:mmu_hal.* *libhal.a:spi_flash_encrypt_hal_iram.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:spi_flash_hal_iram.* *libhal.a:spi_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libheap.a:tlsf.* *liblog.a:log.* *liblog.a:log_freertos.* *libnewlib.a:abort.* *libnewlib.a:assert.* *libnewlib.a:heap.* *libnewlib.a:port_stdatomic.* *libnewlib.a:stdatomic.* *libriscv.a:interrupt.* *libriscv.a:vectors.* *libsoc.a:lldesc.* *libspi_flash.a:flash_brownout_hook.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_boya.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:spi_flash_chip_generic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_th.* *libspi_flash.a:spi_flash_chip_winbond.* *libspi_flash.a:spi_flash_wrap.*) .text EXCLUDE_FILE(*libesp_ringbuf.a *libfreertos.a *libgcov.a *librtc.a *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libapp_trace.a:port_uart.* *libesp_event.a:default_event_loop.* *libesp_event.a:esp_event.* *libesp_hw_support.a:cpu.* *libesp_hw_support.a:esp_gpio_reserve.* *libesp_hw_support.a:esp_memory_utils.* *libesp_hw_support.a:rtc_clk.* *libesp_hw_support.a:rtc_sleep.* *libesp_hw_support.a:rtc_time.* *libesp_hw_support.a:systimer.* *libesp_mm.a:esp_cache.* *libesp_rom.a:esp_rom_spiflash.* *libesp_rom.a:esp_rom_systimer.* *libesp_system.a:esp_err.* *libesp_system.a:esp_system_chip.* *libesp_system.a:ubsan.* *libgcc.a:_divsf3.* *libgcc.a:lib2funcs.* *libgcc.a:save-restore.* *libhal.a:cache_hal.* *libhal.a:i2c_hal_iram.* *libhal.a:ledc_hal_iram.* *libhal.a:mmu_hal.* *libhal.a:spi_flash_encrypt_hal_iram.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:spi_flash_hal_iram.* *libhal.a:spi_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libheap.a:tlsf.* *liblog.a:log.* *liblog.a:log_freertos.* *libnewlib.a:abort.* *libnewlib.a:assert.* *libnewlib.a:heap.* *libnewlib.a:port_stdatomic.* *libnewlib.a:stdatomic.* *libriscv.a:interrupt.* *libriscv.a:vectors.* *libsoc.a:lldesc.* *libspi_flash.a:flash_brownout_hook.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_boya.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:spi_flash_chip_generic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_th.* *libspi_flash.a:spi_flash_chip_winbond.* *libspi_flash.a:spi_flash_wrap.*) .text.*) *(.wifi0iram .wifi0iram.*) *(.wifiorslpiram .wifiorslpiram.*) *(.wifirxiram .wifirxiram.*) @@ -444,7 +446,7 @@ SECTIONS *libesp_system.a:esp_system_chip.*(.text .text.esp_get_free_heap_size .text.esp_get_free_internal_heap_size .text.esp_get_idf_version .text.esp_get_minimum_free_heap_size) *libfreertos.a:app_startup.*(.literal .literal.* .text .text.*) *libheap.a:multi_heap.*(.text .text.multi_heap_check .text.multi_heap_dump .text.multi_heap_dump_tlsf .text.multi_heap_free_size_impl .text.multi_heap_get_info_impl .text.multi_heap_get_info_tlsf .text.multi_heap_minimum_free_size_impl .text.multi_heap_register_impl .text.tlsf_check_hook) - *libheap.a:multi_heap_poisoning.*(.text .text.multi_heap_free_size .text.multi_heap_get_info .text.multi_heap_minimum_free_size .text.multi_heap_register .text.subtract_poison_overhead) + *libheap.a:multi_heap_poisoning.*(.text .text.multi_heap_free_size .text.multi_heap_get_info .text.multi_heap_minimum_free_size .text.multi_heap_register) *libheap.a:tlsf.*(.text .text.default_walker .text.integrity_walker .text.tlsf_add_pool .text.tlsf_check .text.tlsf_check_pool .text.tlsf_create .text.tlsf_create_with_pool .text.tlsf_destroy .text.tlsf_fit_size .text.tlsf_pool_overhead .text.tlsf_remove_pool .text.tlsf_walk_pool) *liblog.a:log.*(.text .text.esp_log_level_get .text.esp_log_level_set .text.esp_log_set_vprintf .text.esp_log_writev .text.heap_bubble_down .text.s_log_level_get_and_unlock) *liblog.a:log_freertos.*(.text .text.esp_log_system_timestamp) @@ -508,7 +510,7 @@ SECTIONS { _flash_rodata_start = ABSOLUTE(.); - *(EXCLUDE_FILE(*libgcov.a *libphy.a *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libapp_trace.a:port_uart.* *libesp_hw_support.a:esp_memory_utils.* *libesp_hw_support.a:rtc_clk.* *libesp_hw_support.a:systimer.* *libesp_mm.a:esp_cache.* *libesp_rom.a:esp_rom_spiflash.* *libesp_rom.a:esp_rom_systimer.* *libesp_system.a:esp_err.* *libesp_system.a:ubsan.* *libfreertos.a:FreeRTOS-openocd.* *libgcc.a:_divsf3.* *libgcc.a:save-restore.* *libhal.a:cache_hal.* *libhal.a:i2c_hal_iram.* *libhal.a:ledc_hal_iram.* *libhal.a:mmu_hal.* *libhal.a:spi_flash_encrypt_hal_iram.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:spi_flash_hal_iram.* *libhal.a:spi_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libnewlib.a:abort.* *libnewlib.a:assert.* *libnewlib.a:heap.* *libnewlib.a:stdatomic.* *libsoc.a:lldesc.* *libspi_flash.a:flash_brownout_hook.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_boya.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:spi_flash_chip_generic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_th.* *libspi_flash.a:spi_flash_chip_winbond.* *libspi_flash.a:spi_flash_wrap.*) .rodata EXCLUDE_FILE(*libgcov.a *libphy.a *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libapp_trace.a:port_uart.* *libesp_hw_support.a:esp_memory_utils.* *libesp_hw_support.a:rtc_clk.* *libesp_hw_support.a:systimer.* *libesp_mm.a:esp_cache.* *libesp_rom.a:esp_rom_spiflash.* *libesp_rom.a:esp_rom_systimer.* *libesp_system.a:esp_err.* *libesp_system.a:ubsan.* *libfreertos.a:FreeRTOS-openocd.* *libgcc.a:_divsf3.* *libgcc.a:save-restore.* *libhal.a:cache_hal.* *libhal.a:i2c_hal_iram.* *libhal.a:ledc_hal_iram.* *libhal.a:mmu_hal.* *libhal.a:spi_flash_encrypt_hal_iram.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:spi_flash_hal_iram.* *libhal.a:spi_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libnewlib.a:abort.* *libnewlib.a:assert.* *libnewlib.a:heap.* *libnewlib.a:stdatomic.* *libsoc.a:lldesc.* *libspi_flash.a:flash_brownout_hook.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_boya.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:spi_flash_chip_generic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_th.* *libspi_flash.a:spi_flash_chip_winbond.* *libspi_flash.a:spi_flash_wrap.*) .rodata.* EXCLUDE_FILE(*libgcov.a *libphy.a *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libapp_trace.a:port_uart.* *libesp_hw_support.a:esp_memory_utils.* *libesp_hw_support.a:rtc_clk.* *libesp_hw_support.a:systimer.* *libesp_mm.a:esp_cache.* *libesp_rom.a:esp_rom_spiflash.* *libesp_rom.a:esp_rom_systimer.* *libesp_system.a:esp_err.* *libesp_system.a:ubsan.* *libfreertos.a:FreeRTOS-openocd.* *libgcc.a:_divsf3.* *libgcc.a:save-restore.* *libhal.a:cache_hal.* *libhal.a:i2c_hal_iram.* *libhal.a:ledc_hal_iram.* *libhal.a:mmu_hal.* *libhal.a:spi_flash_encrypt_hal_iram.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:spi_flash_hal_iram.* *libhal.a:spi_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libnewlib.a:abort.* *libnewlib.a:assert.* *libnewlib.a:heap.* *libnewlib.a:stdatomic.* *libsoc.a:lldesc.* *libspi_flash.a:flash_brownout_hook.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_boya.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:spi_flash_chip_generic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_th.* *libspi_flash.a:spi_flash_chip_winbond.* *libspi_flash.a:spi_flash_wrap.*) .sdata2 EXCLUDE_FILE(*libgcov.a *libphy.a *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libapp_trace.a:port_uart.* *libesp_hw_support.a:esp_memory_utils.* *libesp_hw_support.a:rtc_clk.* *libesp_hw_support.a:systimer.* *libesp_mm.a:esp_cache.* *libesp_rom.a:esp_rom_spiflash.* *libesp_rom.a:esp_rom_systimer.* *libesp_system.a:esp_err.* *libesp_system.a:ubsan.* *libfreertos.a:FreeRTOS-openocd.* *libgcc.a:_divsf3.* *libgcc.a:save-restore.* *libhal.a:cache_hal.* *libhal.a:i2c_hal_iram.* *libhal.a:ledc_hal_iram.* *libhal.a:mmu_hal.* *libhal.a:spi_flash_encrypt_hal_iram.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:spi_flash_hal_iram.* *libhal.a:spi_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libnewlib.a:abort.* *libnewlib.a:assert.* *libnewlib.a:heap.* *libnewlib.a:stdatomic.* *libsoc.a:lldesc.* *libspi_flash.a:flash_brownout_hook.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_boya.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:spi_flash_chip_generic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_th.* *libspi_flash.a:spi_flash_chip_winbond.* *libspi_flash.a:spi_flash_wrap.*) .sdata2.* EXCLUDE_FILE(*libgcov.a *libphy.a *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libapp_trace.a:port_uart.* *libesp_hw_support.a:esp_memory_utils.* *libesp_hw_support.a:rtc_clk.* *libesp_hw_support.a:systimer.* *libesp_mm.a:esp_cache.* *libesp_rom.a:esp_rom_spiflash.* *libesp_rom.a:esp_rom_systimer.* *libesp_system.a:esp_err.* *libesp_system.a:ubsan.* *libfreertos.a:FreeRTOS-openocd.* *libgcc.a:_divsf3.* *libgcc.a:save-restore.* *libhal.a:cache_hal.* *libhal.a:i2c_hal_iram.* *libhal.a:ledc_hal_iram.* *libhal.a:mmu_hal.* *libhal.a:spi_flash_encrypt_hal_iram.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:spi_flash_hal_iram.* *libhal.a:spi_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libnewlib.a:abort.* *libnewlib.a:assert.* *libnewlib.a:heap.* *libnewlib.a:stdatomic.* *libsoc.a:lldesc.* *libspi_flash.a:flash_brownout_hook.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_boya.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:spi_flash_chip_generic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_th.* *libspi_flash.a:spi_flash_chip_winbond.* *libspi_flash.a:spi_flash_wrap.*) .srodata EXCLUDE_FILE(*libgcov.a *libphy.a *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libapp_trace.a:port_uart.* *libesp_hw_support.a:esp_memory_utils.* *libesp_hw_support.a:rtc_clk.* *libesp_hw_support.a:systimer.* *libesp_mm.a:esp_cache.* *libesp_rom.a:esp_rom_spiflash.* *libesp_rom.a:esp_rom_systimer.* *libesp_system.a:esp_err.* *libesp_system.a:ubsan.* *libfreertos.a:FreeRTOS-openocd.* *libgcc.a:_divsf3.* *libgcc.a:save-restore.* *libhal.a:cache_hal.* *libhal.a:i2c_hal_iram.* *libhal.a:ledc_hal_iram.* *libhal.a:mmu_hal.* *libhal.a:spi_flash_encrypt_hal_iram.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:spi_flash_hal_iram.* *libhal.a:spi_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libnewlib.a:abort.* *libnewlib.a:assert.* *libnewlib.a:heap.* *libnewlib.a:stdatomic.* *libsoc.a:lldesc.* *libspi_flash.a:flash_brownout_hook.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_boya.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:spi_flash_chip_generic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_th.* *libspi_flash.a:spi_flash_chip_winbond.* *libspi_flash.a:spi_flash_wrap.*) .srodata.*) + *(EXCLUDE_FILE(*libgcov.a *libphy.a *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libapp_trace.a:port_uart.* *libesp_hw_support.a:esp_memory_utils.* *libesp_hw_support.a:rtc_clk.* *libesp_hw_support.a:systimer.* *libesp_mm.a:esp_cache.* *libesp_rom.a:esp_rom_spiflash.* *libesp_rom.a:esp_rom_systimer.* *libesp_system.a:esp_err.* *libesp_system.a:ubsan.* *libfreertos.a:FreeRTOS-openocd.* *libgcc.a:_divsf3.* *libgcc.a:save-restore.* *libhal.a:cache_hal.* *libhal.a:i2c_hal_iram.* *libhal.a:ledc_hal_iram.* *libhal.a:mmu_hal.* *libhal.a:spi_flash_encrypt_hal_iram.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:spi_flash_hal_iram.* *libhal.a:spi_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libnewlib.a:abort.* *libnewlib.a:assert.* *libnewlib.a:heap.* *libnewlib.a:port_stdatomic.* *libnewlib.a:stdatomic.* *libsoc.a:lldesc.* *libspi_flash.a:flash_brownout_hook.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_boya.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:spi_flash_chip_generic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_th.* *libspi_flash.a:spi_flash_chip_winbond.* *libspi_flash.a:spi_flash_wrap.*) .rodata EXCLUDE_FILE(*libgcov.a *libphy.a *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libapp_trace.a:port_uart.* *libesp_hw_support.a:esp_memory_utils.* *libesp_hw_support.a:rtc_clk.* *libesp_hw_support.a:systimer.* *libesp_mm.a:esp_cache.* *libesp_rom.a:esp_rom_spiflash.* *libesp_rom.a:esp_rom_systimer.* *libesp_system.a:esp_err.* *libesp_system.a:ubsan.* *libfreertos.a:FreeRTOS-openocd.* *libgcc.a:_divsf3.* *libgcc.a:save-restore.* *libhal.a:cache_hal.* *libhal.a:i2c_hal_iram.* *libhal.a:ledc_hal_iram.* *libhal.a:mmu_hal.* *libhal.a:spi_flash_encrypt_hal_iram.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:spi_flash_hal_iram.* *libhal.a:spi_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libnewlib.a:abort.* *libnewlib.a:assert.* *libnewlib.a:heap.* *libnewlib.a:port_stdatomic.* *libnewlib.a:stdatomic.* *libsoc.a:lldesc.* *libspi_flash.a:flash_brownout_hook.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_boya.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:spi_flash_chip_generic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_th.* *libspi_flash.a:spi_flash_chip_winbond.* *libspi_flash.a:spi_flash_wrap.*) .rodata.* EXCLUDE_FILE(*libgcov.a *libphy.a *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libapp_trace.a:port_uart.* *libesp_hw_support.a:esp_memory_utils.* *libesp_hw_support.a:rtc_clk.* *libesp_hw_support.a:systimer.* *libesp_mm.a:esp_cache.* *libesp_rom.a:esp_rom_spiflash.* *libesp_rom.a:esp_rom_systimer.* *libesp_system.a:esp_err.* *libesp_system.a:ubsan.* *libfreertos.a:FreeRTOS-openocd.* *libgcc.a:_divsf3.* *libgcc.a:save-restore.* *libhal.a:cache_hal.* *libhal.a:i2c_hal_iram.* *libhal.a:ledc_hal_iram.* *libhal.a:mmu_hal.* *libhal.a:spi_flash_encrypt_hal_iram.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:spi_flash_hal_iram.* *libhal.a:spi_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libnewlib.a:abort.* *libnewlib.a:assert.* *libnewlib.a:heap.* *libnewlib.a:port_stdatomic.* *libnewlib.a:stdatomic.* *libsoc.a:lldesc.* *libspi_flash.a:flash_brownout_hook.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_boya.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:spi_flash_chip_generic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_th.* *libspi_flash.a:spi_flash_chip_winbond.* *libspi_flash.a:spi_flash_wrap.*) .sdata2 EXCLUDE_FILE(*libgcov.a *libphy.a *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libapp_trace.a:port_uart.* *libesp_hw_support.a:esp_memory_utils.* *libesp_hw_support.a:rtc_clk.* *libesp_hw_support.a:systimer.* *libesp_mm.a:esp_cache.* *libesp_rom.a:esp_rom_spiflash.* *libesp_rom.a:esp_rom_systimer.* *libesp_system.a:esp_err.* *libesp_system.a:ubsan.* *libfreertos.a:FreeRTOS-openocd.* *libgcc.a:_divsf3.* *libgcc.a:save-restore.* *libhal.a:cache_hal.* *libhal.a:i2c_hal_iram.* *libhal.a:ledc_hal_iram.* *libhal.a:mmu_hal.* *libhal.a:spi_flash_encrypt_hal_iram.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:spi_flash_hal_iram.* *libhal.a:spi_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libnewlib.a:abort.* *libnewlib.a:assert.* *libnewlib.a:heap.* *libnewlib.a:port_stdatomic.* *libnewlib.a:stdatomic.* *libsoc.a:lldesc.* *libspi_flash.a:flash_brownout_hook.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_boya.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:spi_flash_chip_generic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_th.* *libspi_flash.a:spi_flash_chip_winbond.* *libspi_flash.a:spi_flash_wrap.*) .sdata2.* EXCLUDE_FILE(*libgcov.a *libphy.a *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libapp_trace.a:port_uart.* *libesp_hw_support.a:esp_memory_utils.* *libesp_hw_support.a:rtc_clk.* *libesp_hw_support.a:systimer.* *libesp_mm.a:esp_cache.* *libesp_rom.a:esp_rom_spiflash.* *libesp_rom.a:esp_rom_systimer.* *libesp_system.a:esp_err.* *libesp_system.a:ubsan.* *libfreertos.a:FreeRTOS-openocd.* *libgcc.a:_divsf3.* *libgcc.a:save-restore.* *libhal.a:cache_hal.* *libhal.a:i2c_hal_iram.* *libhal.a:ledc_hal_iram.* *libhal.a:mmu_hal.* *libhal.a:spi_flash_encrypt_hal_iram.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:spi_flash_hal_iram.* *libhal.a:spi_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libnewlib.a:abort.* *libnewlib.a:assert.* *libnewlib.a:heap.* *libnewlib.a:port_stdatomic.* *libnewlib.a:stdatomic.* *libsoc.a:lldesc.* *libspi_flash.a:flash_brownout_hook.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_boya.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:spi_flash_chip_generic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_th.* *libspi_flash.a:spi_flash_chip_winbond.* *libspi_flash.a:spi_flash_wrap.*) .srodata EXCLUDE_FILE(*libgcov.a *libphy.a *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libapp_trace.a:port_uart.* *libesp_hw_support.a:esp_memory_utils.* *libesp_hw_support.a:rtc_clk.* *libesp_hw_support.a:systimer.* *libesp_mm.a:esp_cache.* *libesp_rom.a:esp_rom_spiflash.* *libesp_rom.a:esp_rom_systimer.* *libesp_system.a:esp_err.* *libesp_system.a:ubsan.* *libfreertos.a:FreeRTOS-openocd.* *libgcc.a:_divsf3.* *libgcc.a:save-restore.* *libhal.a:cache_hal.* *libhal.a:i2c_hal_iram.* *libhal.a:ledc_hal_iram.* *libhal.a:mmu_hal.* *libhal.a:spi_flash_encrypt_hal_iram.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:spi_flash_hal_iram.* *libhal.a:spi_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libnewlib.a:abort.* *libnewlib.a:assert.* *libnewlib.a:heap.* *libnewlib.a:port_stdatomic.* *libnewlib.a:stdatomic.* *libsoc.a:lldesc.* *libspi_flash.a:flash_brownout_hook.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_boya.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:spi_flash_chip_generic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_th.* *libspi_flash.a:spi_flash_chip_winbond.* *libspi_flash.a:spi_flash_wrap.*) .srodata.*) *(.rodata_wlog_error .rodata_wlog_error.*) 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a/tools/sdk/esp32c3/lib/libwear_levelling.a b/tools/sdk/esp32c3/lib/libwear_levelling.a index 189fbda4710..8497dfcad0f 100644 Binary files a/tools/sdk/esp32c3/lib/libwear_levelling.a and b/tools/sdk/esp32c3/lib/libwear_levelling.a differ diff --git a/tools/sdk/esp32c3/lib/libwifi_provisioning.a b/tools/sdk/esp32c3/lib/libwifi_provisioning.a index 25d00ff9c7d..f441ee0f927 100644 Binary files a/tools/sdk/esp32c3/lib/libwifi_provisioning.a and b/tools/sdk/esp32c3/lib/libwifi_provisioning.a differ diff --git a/tools/sdk/esp32c3/lib/libwpa_supplicant.a b/tools/sdk/esp32c3/lib/libwpa_supplicant.a index 007f2684e7e..1c124f79b91 100644 Binary files a/tools/sdk/esp32c3/lib/libwpa_supplicant.a and b/tools/sdk/esp32c3/lib/libwpa_supplicant.a differ diff --git a/tools/sdk/esp32c3/lib/libws2812_led.a b/tools/sdk/esp32c3/lib/libws2812_led.a index 55d1c6052f8..2bf78c2b7ee 100644 Binary files a/tools/sdk/esp32c3/lib/libws2812_led.a and b/tools/sdk/esp32c3/lib/libws2812_led.a differ diff --git a/tools/sdk/esp32c3/platformio-build.py b/tools/sdk/esp32c3/platformio-build.py index a83c034718e..7001419435c 100644 --- a/tools/sdk/esp32c3/platformio-build.py +++ b/tools/sdk/esp32c3/platformio-build.py @@ -109,6 +109,7 @@ "-u", "pthread_include_pthread_cond_impl", "-u", "pthread_include_pthread_local_storage_impl", "-u", "pthread_include_pthread_rwlock_impl", + "-u", "pthread_include_pthread_semaphore_impl", "-u", "start_app", "-u", "__ubsan_include", "-u", "__assert_func", @@ -129,6 +130,7 @@ join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "freertos", "FreeRTOS-Kernel", "portable", "riscv", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "freertos", "esp_additions", "include", "freertos"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "freertos", "esp_additions", "include"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "freertos", "esp_additions", "arch", "riscv", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "esp_hw_support", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "esp_hw_support", "include", "soc"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "esp_hw_support", "include", "soc", "esp32c3"), @@ -251,6 +253,7 @@ join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "esp_http_server", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "esp_https_ota", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "esp_https_server", "include"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "esp_psram", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "esp_lcd", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "esp_lcd", "interface"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "protobuf-c", "protobuf-c"), @@ -258,7 +261,6 @@ join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "protocomm", "include", "security"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "protocomm", "include", "transports"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "esp_local_ctrl", "include"), - join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "esp_psram", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "espcoredump", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "espcoredump", "include", "port", "riscv"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "wear_levelling", "include"), @@ -297,9 +299,6 @@ join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "esp-dl", "include", "layer"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "esp-dl", "include", "detect"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "esp-dl", "include", "model_zoo"), - join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "esp-sr", "esp-tts", "esp_tts_chinese", "include"), - join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "esp32-camera", "driver", "include"), - join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "esp32-camera", "conversions", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "espressif__esp-dsp", "modules", "dotprod", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "espressif__esp-dsp", "modules", "support", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "espressif__esp-dsp", "modules", "windows", "include"), @@ -325,6 +324,9 @@ join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "espressif__esp-dsp", "modules", "common", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "espressif__esp-dsp", "modules", "kalman", "ekf", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "espressif__esp-dsp", "modules", "kalman", "ekf_imu13states", "include"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "esp-sr", "esp-tts", "esp_tts_chinese", "include"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "esp32-camera", "driver", "include"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "esp32-camera", "conversions", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", "include", "fb_gfx", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32c3", env.BoardConfig().get("build.arduino.memory_type", (env.BoardConfig().get("build.flash_mode", "dio") + "_qspi")), "include"), join(FRAMEWORK_DIR, "cores", env.BoardConfig().get("build.core")) @@ -337,12 +339,12 @@ ], LIBS=[ - "-lriscv", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lapp_trace", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lbt", "-lunity", "-lcmock", "-lconsole", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-lesp_hid", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_https_server", "-lesp_lcd", "-lprotobuf-c", "-lprotocomm", "-lesp_local_ctrl", "-lespcoredump", "-lwear_levelling", "-lsdmmc", "-lfatfs", "-ljson", "-lmqtt", "-lspiffs", "-lwifi_provisioning", "-lespressif__mdns", "-lcbor", "-lrmaker_common", "-lesp_diagnostics", "-lrtc_store", "-lesp_insights", "-ljson_parser", "-ljson_generator", "-lesp_schedule", "-lespressif__esp_secure_cert_mgr", "-lesp_rainmaker", "-lgpio_button", "-lqrcode", "-lws2812_led", "-lesp32-camera", "-lesp_littlefs", "-lespressif__esp-dsp", "-lfb_gfx", "-lapp_trace", "-lapp_trace", "-lcmock", "-lunity", "-lesp_lcd", "-lesp_hid", "-lfatfs", "-lwear_levelling", "-lsdmmc", "-lesp_insights", "-lcbor", "-lesp_diagnostics", "-lrtc_store", "-lesp_rainmaker", "-lesp_local_ctrl", "-lesp_https_server", "-lwifi_provisioning", "-lprotocomm", "-lbt", "-lbtdm_app", "-lprotobuf-c", "-ljson", "-lespressif__mdns", "-ljson_parser", "-ljson_generator", "-lesp_schedule", "-lespressif__esp_secure_cert_mgr", "-lqrcode", "-lrmaker_common", "-lconsole", "-lmqtt", "-lcat_face_detect", "-lhuman_face_detect", "-lcolor_detect", "-lmfn", "-ldl", "-lspiffs", "-lesp_tts_chinese", "-lvoice_set_xiaole", "-lriscv", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lespcoredump", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lriscv", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lespcoredump", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lriscv", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lespcoredump", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lriscv", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lespcoredump", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lriscv", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lespcoredump", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lriscv", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lespcoredump", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lc", "-lm", "-lnewlib", "-lstdc++", "-lpthread", "-lgcc", "-lcxx", "-lphy", "-lbtbb", "-lesp_phy", "-lphy", "-lbtbb", "-lesp_phy", "-lphy", "-lbtbb" + "-lriscv", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lapp_trace", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lbt", "-lunity", "-lcmock", "-lconsole", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-lesp_hid", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_https_server", "-lesp_lcd", "-lprotobuf-c", "-lprotocomm", "-lesp_local_ctrl", "-lespcoredump", "-lwear_levelling", "-lsdmmc", "-lfatfs", "-ljson", "-lmqtt", "-lspiffs", "-lwifi_provisioning", "-lespressif__mdns", "-lcbor", "-lrmaker_common", "-lesp_diagnostics", "-lrtc_store", "-lesp_insights", "-ljson_parser", "-ljson_generator", "-lesp_schedule", "-lespressif__esp_secure_cert_mgr", "-lesp_rainmaker", "-lgpio_button", "-lqrcode", "-lws2812_led", "-lespressif__esp-dsp", "-lesp32-camera", "-lesp_littlefs", "-lfb_gfx", "-lapp_trace", "-lapp_trace", "-lcmock", "-lunity", "-lesp_lcd", "-lesp_hid", "-lfatfs", "-lwear_levelling", "-lsdmmc", "-lesp_insights", "-lcbor", "-lesp_diagnostics", "-lrtc_store", "-lesp_rainmaker", "-lesp_local_ctrl", "-lesp_https_server", "-lwifi_provisioning", "-lprotocomm", "-lbt", "-lbtdm_app", "-lprotobuf-c", "-ljson", "-lespressif__mdns", "-ljson_parser", "-ljson_generator", "-lesp_schedule", "-lespressif__esp_secure_cert_mgr", "-lqrcode", "-lrmaker_common", "-lconsole", "-lmqtt", "-lcat_face_detect", "-lhuman_face_detect", "-lcolor_detect", "-lmfn", "-ldl", "-lspiffs", "-lespressif__esp-dsp", "-lesp_tts_chinese", "-lvoice_set_xiaole", "-lriscv", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lespcoredump", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lriscv", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lespcoredump", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lriscv", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lespcoredump", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lriscv", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lespcoredump", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lriscv", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lespcoredump", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lriscv", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lespcoredump", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lc", "-lm", "-lnewlib", "-lstdc++", "-lpthread", "-lgcc", "-lcxx", "-lphy", "-lbtbb", "-lesp_phy", "-lphy", "-lbtbb", "-lesp_phy", "-lphy", "-lbtbb" ], CPPDEFINES=[ "ESP_PLATFORM", - ("IDF_VER", '\\"v5.1-dev-4124-gbb9200acec\\"'), + ("IDF_VER", '\\"v5.1-dev-4528-g420ebd208a\\"'), ("MBEDTLS_CONFIG_FILE", '\\"mbedtls/esp_config.h\\"'), ("SOC_MMU_PAGE_SIZE", 'CONFIG_MMU_PAGE_SIZE'), "UNITY_INCLUDE_CONFIG_H", diff --git a/tools/sdk/esp32c3/qio_qspi/include/sdkconfig.h b/tools/sdk/esp32c3/qio_qspi/include/sdkconfig.h index cd6e92f13e4..db9e471979d 100644 --- a/tools/sdk/esp32c3/qio_qspi/include/sdkconfig.h +++ b/tools/sdk/esp32c3/qio_qspi/include/sdkconfig.h @@ -191,6 +191,8 @@ #define CONFIG_SOC_EFUSE_DIS_USB_JTAG 1 #define CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT 1 #define CONFIG_SOC_EFUSE_SOFT_DIS_JTAG 1 +#define CONFIG_SOC_EFUSE_DIS_ICACHE 1 +#define CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 #define CONFIG_SOC_SECURE_BOOT_V2_RSA 1 #define CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 #define CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 @@ -239,6 +241,7 @@ #define CONFIG_SOC_BLE_SUPPORTED 1 #define CONFIG_SOC_BLE_MESH_SUPPORTED 1 #define CONFIG_SOC_BLE_50_SUPPORTED 1 +#define CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED 1 #define CONFIG_IDF_CMAKE 1 #define CONFIG_IDF_TARGET_ARCH_RISCV 1 #define CONFIG_IDF_TARGET_ARCH "riscv" @@ -259,6 +262,7 @@ #define CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE 1 #define CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP 1 #define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x10 +#define CONFIG_BOOTLOADER_RESERVE_RTC_MEM 1 #define CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT 1 #define CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED 1 #define CONFIG_SECURE_BOOT_V2_PREFERRED 1 @@ -432,13 +436,12 @@ #define CONFIG_BT_SMP_ENABLE 1 #define CONFIG_BT_BLE_ESTAB_LINK_CONN_TOUT 30 #define CONFIG_BT_MAX_DEVICE_NAME_LEN 32 -#define CONFIG_BT_BLE_RPA_SUPPORTED 1 #define CONFIG_BT_BLE_RPA_TIMEOUT 900 #define CONFIG_BT_BLE_50_FEATURES_SUPPORTED 1 #define CONFIG_BT_BLE_42_FEATURES_SUPPORTED 1 #define CONFIG_BT_CTRL_MODE_EFF 1 -#define CONFIG_BT_CTRL_BLE_MAX_ACT 10 -#define CONFIG_BT_CTRL_BLE_MAX_ACT_EFF 10 +#define CONFIG_BT_CTRL_BLE_MAX_ACT 6 +#define CONFIG_BT_CTRL_BLE_MAX_ACT_EFF 6 #define CONFIG_BT_CTRL_BLE_STATIC_ACL_TX_BUF_NB 0 #define CONFIG_BT_CTRL_PINNED_TO_CORE 0 #define CONFIG_BT_CTRL_HCI_MODE_VHCI 1 @@ -1110,5 +1113,5 @@ #define CONFIG_WARN_WRITE_STRINGS CONFIG_COMPILER_WARN_WRITE_STRINGS #define CONFIG_WPA_MBEDTLS_CRYPTO CONFIG_ESP_WIFI_MBEDTLS_CRYPTO #define CONFIG_WPA_MBEDTLS_TLS_CLIENT CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT -#define CONFIG_ARDUINO_IDF_COMMIT "" +#define CONFIG_ARDUINO_IDF_COMMIT "420ebd208a" #define CONFIG_ARDUINO_IDF_BRANCH "release/v5.1" diff --git a/tools/sdk/esp32c3/qio_qspi/libspi_flash.a b/tools/sdk/esp32c3/qio_qspi/libspi_flash.a index 7551d4e03ce..b9b30075687 100644 Binary files a/tools/sdk/esp32c3/qio_qspi/libspi_flash.a and b/tools/sdk/esp32c3/qio_qspi/libspi_flash.a differ diff --git a/tools/sdk/esp32c3/qout_qspi/include/sdkconfig.h b/tools/sdk/esp32c3/qout_qspi/include/sdkconfig.h index 012c62e8227..e0cdb3fd979 100644 --- a/tools/sdk/esp32c3/qout_qspi/include/sdkconfig.h +++ b/tools/sdk/esp32c3/qout_qspi/include/sdkconfig.h @@ -191,6 +191,8 @@ #define CONFIG_SOC_EFUSE_DIS_USB_JTAG 1 #define CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT 1 #define CONFIG_SOC_EFUSE_SOFT_DIS_JTAG 1 +#define CONFIG_SOC_EFUSE_DIS_ICACHE 1 +#define CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 #define CONFIG_SOC_SECURE_BOOT_V2_RSA 1 #define CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 #define CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 @@ -239,6 +241,7 @@ #define CONFIG_SOC_BLE_SUPPORTED 1 #define CONFIG_SOC_BLE_MESH_SUPPORTED 1 #define CONFIG_SOC_BLE_50_SUPPORTED 1 +#define CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED 1 #define CONFIG_IDF_CMAKE 1 #define CONFIG_IDF_TARGET_ARCH_RISCV 1 #define CONFIG_IDF_TARGET_ARCH "riscv" @@ -259,6 +262,7 @@ #define CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE 1 #define CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP 1 #define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x10 +#define CONFIG_BOOTLOADER_RESERVE_RTC_MEM 1 #define CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT 1 #define CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED 1 #define CONFIG_SECURE_BOOT_V2_PREFERRED 1 @@ -432,13 +436,12 @@ #define CONFIG_BT_SMP_ENABLE 1 #define CONFIG_BT_BLE_ESTAB_LINK_CONN_TOUT 30 #define CONFIG_BT_MAX_DEVICE_NAME_LEN 32 -#define CONFIG_BT_BLE_RPA_SUPPORTED 1 #define CONFIG_BT_BLE_RPA_TIMEOUT 900 #define CONFIG_BT_BLE_50_FEATURES_SUPPORTED 1 #define CONFIG_BT_BLE_42_FEATURES_SUPPORTED 1 #define CONFIG_BT_CTRL_MODE_EFF 1 -#define CONFIG_BT_CTRL_BLE_MAX_ACT 10 -#define CONFIG_BT_CTRL_BLE_MAX_ACT_EFF 10 +#define CONFIG_BT_CTRL_BLE_MAX_ACT 6 +#define CONFIG_BT_CTRL_BLE_MAX_ACT_EFF 6 #define CONFIG_BT_CTRL_BLE_STATIC_ACL_TX_BUF_NB 0 #define CONFIG_BT_CTRL_PINNED_TO_CORE 0 #define CONFIG_BT_CTRL_HCI_MODE_VHCI 1 @@ -1110,5 +1113,5 @@ #define CONFIG_WARN_WRITE_STRINGS CONFIG_COMPILER_WARN_WRITE_STRINGS #define CONFIG_WPA_MBEDTLS_CRYPTO CONFIG_ESP_WIFI_MBEDTLS_CRYPTO #define CONFIG_WPA_MBEDTLS_TLS_CLIENT CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT -#define CONFIG_ARDUINO_IDF_COMMIT "" +#define CONFIG_ARDUINO_IDF_COMMIT "420ebd208a" #define CONFIG_ARDUINO_IDF_BRANCH "release/v5.1" diff --git a/tools/sdk/esp32c3/qout_qspi/libspi_flash.a b/tools/sdk/esp32c3/qout_qspi/libspi_flash.a index 2e4edcbf80c..3c5090974a5 100644 Binary files a/tools/sdk/esp32c3/qout_qspi/libspi_flash.a and b/tools/sdk/esp32c3/qout_qspi/libspi_flash.a differ diff --git a/tools/sdk/esp32c3/sdkconfig b/tools/sdk/esp32c3/sdkconfig index 974341c623e..6bef60cd54e 100644 --- a/tools/sdk/esp32c3/sdkconfig +++ b/tools/sdk/esp32c3/sdkconfig @@ -190,6 +190,8 @@ CONFIG_SOC_EFUSE_DIS_PAD_JTAG=y CONFIG_SOC_EFUSE_DIS_USB_JTAG=y CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT=y CONFIG_SOC_EFUSE_SOFT_DIS_JTAG=y +CONFIG_SOC_EFUSE_DIS_ICACHE=y +CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK=y CONFIG_SOC_SECURE_BOOT_V2_RSA=y CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS=3 CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS=y @@ -238,6 +240,7 @@ CONFIG_SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW=y CONFIG_SOC_BLE_SUPPORTED=y CONFIG_SOC_BLE_MESH_SUPPORTED=y CONFIG_SOC_BLE_50_SUPPORTED=y +CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED=y CONFIG_IDF_CMAKE=y CONFIG_IDF_TARGET_ARCH_RISCV=y CONFIG_IDF_TARGET_ARCH="riscv" @@ -285,6 +288,7 @@ CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP=y # CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS is not set CONFIG_BOOTLOADER_RESERVE_RTC_SIZE=0x10 # CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC is not set +CONFIG_BOOTLOADER_RESERVE_RTC_MEM=y CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT=y # end of Bootloader config @@ -773,7 +777,6 @@ CONFIG_BT_SMP_ENABLE=y # CONFIG_BT_BLE_ACT_SCAN_REP_ADV_SCAN is not set CONFIG_BT_BLE_ESTAB_LINK_CONN_TOUT=30 CONFIG_BT_MAX_DEVICE_NAME_LEN=32 -CONFIG_BT_BLE_RPA_SUPPORTED=y CONFIG_BT_BLE_RPA_TIMEOUT=900 CONFIG_BT_BLE_50_FEATURES_SUPPORTED=y CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y @@ -783,8 +786,8 @@ CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y # Controller Options # CONFIG_BT_CTRL_MODE_EFF=1 -CONFIG_BT_CTRL_BLE_MAX_ACT=10 -CONFIG_BT_CTRL_BLE_MAX_ACT_EFF=10 +CONFIG_BT_CTRL_BLE_MAX_ACT=6 +CONFIG_BT_CTRL_BLE_MAX_ACT_EFF=6 CONFIG_BT_CTRL_BLE_STATIC_ACL_TX_BUF_NB=0 CONFIG_BT_CTRL_PINNED_TO_CORE=0 CONFIG_BT_CTRL_HCI_MODE_VHCI=y @@ -957,6 +960,7 @@ CONFIG_BLE_MESH_DISCARD_OLD_SEQ_AUTH=y # BLE Mesh specific test option # # CONFIG_BLE_MESH_SELF_TEST is not set +# CONFIG_BLE_MESH_BQB_TEST is not set # CONFIG_BLE_MESH_SHELL is not set # CONFIG_BLE_MESH_DEBUG is not set # end of BLE Mesh specific test option @@ -1301,7 +1305,6 @@ CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP=y # ESP Ringbuf # # CONFIG_RINGBUF_PLACE_FUNCTIONS_INTO_FLASH is not set -# CONFIG_RINGBUF_PLACE_ISR_FUNCTIONS_INTO_FLASH is not set # end of ESP Ringbuf # @@ -1434,12 +1437,19 @@ CONFIG_ESP_WIFI_MBEDTLS_CRYPTO=y CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT=y # CONFIG_ESP_WIFI_WAPI_PSK is not set # CONFIG_ESP_WIFI_SUITE_B_192 is not set -# CONFIG_ESP_WIFI_WPS_STRICT is not set # CONFIG_ESP_WIFI_11KV_SUPPORT is not set # CONFIG_ESP_WIFI_MBO_SUPPORT is not set # CONFIG_ESP_WIFI_DPP_SUPPORT is not set # CONFIG_ESP_WIFI_11R_SUPPORT is not set # CONFIG_ESP_WIFI_WPS_SOFTAP_REGISTRAR is not set + +# +# WPS Configuration Options +# +# CONFIG_ESP_WIFI_WPS_STRICT is not set +# CONFIG_ESP_WIFI_WPS_PASSPHRASE is not set +# end of WPS Configuration Options + # CONFIG_ESP_WIFI_DEBUG_PRINT is not set # CONFIG_ESP_WIFI_TESTING_OPTIONS is not set # end of Wi-Fi @@ -1575,6 +1585,7 @@ CONFIG_HEAP_POISONING_LIGHT=y CONFIG_HEAP_TRACING_OFF=y # CONFIG_HEAP_TRACING_STANDALONE is not set # CONFIG_HEAP_TRACING_TOHOST is not set +# CONFIG_HEAP_USE_HOOKS is not set # CONFIG_HEAP_TASK_TRACKING is not set # CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS is not set # end of Heap memory debugging @@ -2284,6 +2295,8 @@ CONFIG_MDNS_PREDEF_NETIF_ETH=y # end of mDNS # end of Component config +# CONFIG_IDF_EXPERIMENTAL_FEATURES is not set + # Deprecated options for backward compatibility # CONFIG_APP_BUILD_TYPE_ELF_RAM is not set # CONFIG_NO_BLOBS is not set @@ -2589,12 +2602,12 @@ CONFIG_WPA_MBEDTLS_CRYPTO=y CONFIG_WPA_MBEDTLS_TLS_CLIENT=y # CONFIG_WPA_WAPI_PSK is not set # CONFIG_WPA_SUITE_B_192 is not set -# CONFIG_WPA_WPS_STRICT is not set # CONFIG_WPA_11KV_SUPPORT is not set # CONFIG_WPA_MBO_SUPPORT is not set # CONFIG_WPA_DPP_SUPPORT is not set # CONFIG_WPA_11R_SUPPORT is not set # CONFIG_WPA_WPS_SOFTAP_REGISTRAR is not set +# CONFIG_WPA_WPS_STRICT is not set # CONFIG_WPA_DEBUG_PRINT is not set # CONFIG_WPA_TESTING_OPTIONS is not set CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH=y diff --git a/tools/sdk/esp32s2/bin/bootloader_dio_40m.elf b/tools/sdk/esp32s2/bin/bootloader_dio_40m.elf index 172cd152f27..2b66606358c 100755 Binary files a/tools/sdk/esp32s2/bin/bootloader_dio_40m.elf and b/tools/sdk/esp32s2/bin/bootloader_dio_40m.elf differ diff --git a/tools/sdk/esp32s2/bin/bootloader_dio_80m.elf b/tools/sdk/esp32s2/bin/bootloader_dio_80m.elf index 527bb85eadf..be18d04525b 100755 Binary files a/tools/sdk/esp32s2/bin/bootloader_dio_80m.elf and b/tools/sdk/esp32s2/bin/bootloader_dio_80m.elf differ diff --git a/tools/sdk/esp32s2/bin/bootloader_dout_40m.elf b/tools/sdk/esp32s2/bin/bootloader_dout_40m.elf index 172cd152f27..2b66606358c 100755 Binary files a/tools/sdk/esp32s2/bin/bootloader_dout_40m.elf and b/tools/sdk/esp32s2/bin/bootloader_dout_40m.elf differ diff --git a/tools/sdk/esp32s2/bin/bootloader_dout_80m.elf b/tools/sdk/esp32s2/bin/bootloader_dout_80m.elf index 527bb85eadf..be18d04525b 100755 Binary files a/tools/sdk/esp32s2/bin/bootloader_dout_80m.elf and b/tools/sdk/esp32s2/bin/bootloader_dout_80m.elf differ diff --git a/tools/sdk/esp32s2/bin/bootloader_qio_40m.elf b/tools/sdk/esp32s2/bin/bootloader_qio_40m.elf index 5f9985eb007..8d4882ca81c 100755 Binary files a/tools/sdk/esp32s2/bin/bootloader_qio_40m.elf and b/tools/sdk/esp32s2/bin/bootloader_qio_40m.elf differ diff --git a/tools/sdk/esp32s2/bin/bootloader_qio_80m.elf b/tools/sdk/esp32s2/bin/bootloader_qio_80m.elf index c20116ded39..240c1eb601c 100755 Binary files a/tools/sdk/esp32s2/bin/bootloader_qio_80m.elf and b/tools/sdk/esp32s2/bin/bootloader_qio_80m.elf differ diff --git a/tools/sdk/esp32s2/bin/bootloader_qout_40m.elf b/tools/sdk/esp32s2/bin/bootloader_qout_40m.elf index 68a8ac71882..e88646f1ccb 100755 Binary files a/tools/sdk/esp32s2/bin/bootloader_qout_40m.elf and b/tools/sdk/esp32s2/bin/bootloader_qout_40m.elf differ diff --git a/tools/sdk/esp32s2/bin/bootloader_qout_80m.elf b/tools/sdk/esp32s2/bin/bootloader_qout_80m.elf index 4f601430b10..6fd9bceb2ff 100755 Binary files a/tools/sdk/esp32s2/bin/bootloader_qout_80m.elf and b/tools/sdk/esp32s2/bin/bootloader_qout_80m.elf differ diff --git a/tools/sdk/esp32s2/dio_qspi/include/sdkconfig.h b/tools/sdk/esp32s2/dio_qspi/include/sdkconfig.h index e5934cf2034..ddde0d4b160 100644 --- a/tools/sdk/esp32s2/dio_qspi/include/sdkconfig.h +++ b/tools/sdk/esp32s2/dio_qspi/include/sdkconfig.h @@ -214,6 +214,7 @@ #define CONFIG_SOC_EFUSE_SOFT_DIS_JTAG 1 #define CONFIG_SOC_EFUSE_DIS_BOOT_REMAP 1 #define CONFIG_SOC_EFUSE_DIS_LEGACY_SPI_BOOT 1 +#define CONFIG_SOC_EFUSE_DIS_ICACHE 1 #define CONFIG_SOC_SECURE_BOOT_V2_RSA 1 #define CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 #define CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 @@ -287,6 +288,7 @@ #define CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE 1 #define CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP 1 #define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x10 +#define CONFIG_BOOTLOADER_RESERVE_RTC_MEM 1 #define CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT 1 #define CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED 1 #define CONFIG_SECURE_BOOT_V2_PREFERRED 1 @@ -992,5 +994,5 @@ #define CONFIG_WARN_WRITE_STRINGS CONFIG_COMPILER_WARN_WRITE_STRINGS #define CONFIG_WPA_MBEDTLS_CRYPTO CONFIG_ESP_WIFI_MBEDTLS_CRYPTO #define CONFIG_WPA_MBEDTLS_TLS_CLIENT CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT -#define CONFIG_ARDUINO_IDF_COMMIT "" +#define CONFIG_ARDUINO_IDF_COMMIT "420ebd208a" #define CONFIG_ARDUINO_IDF_BRANCH "release/v5.1" diff --git a/tools/sdk/esp32s2/dio_qspi/libspi_flash.a b/tools/sdk/esp32s2/dio_qspi/libspi_flash.a index 2df2dde231f..a1a004d25b1 100644 Binary files a/tools/sdk/esp32s2/dio_qspi/libspi_flash.a and b/tools/sdk/esp32s2/dio_qspi/libspi_flash.a differ diff --git a/tools/sdk/esp32s2/dout_qspi/include/sdkconfig.h b/tools/sdk/esp32s2/dout_qspi/include/sdkconfig.h index 3c43caf1c5f..717ea65c1ee 100644 --- a/tools/sdk/esp32s2/dout_qspi/include/sdkconfig.h +++ b/tools/sdk/esp32s2/dout_qspi/include/sdkconfig.h @@ -214,6 +214,7 @@ #define CONFIG_SOC_EFUSE_SOFT_DIS_JTAG 1 #define CONFIG_SOC_EFUSE_DIS_BOOT_REMAP 1 #define CONFIG_SOC_EFUSE_DIS_LEGACY_SPI_BOOT 1 +#define CONFIG_SOC_EFUSE_DIS_ICACHE 1 #define CONFIG_SOC_SECURE_BOOT_V2_RSA 1 #define CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 #define CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 @@ -287,6 +288,7 @@ #define CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE 1 #define CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP 1 #define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x10 +#define CONFIG_BOOTLOADER_RESERVE_RTC_MEM 1 #define CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT 1 #define CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED 1 #define CONFIG_SECURE_BOOT_V2_PREFERRED 1 @@ -992,5 +994,5 @@ #define CONFIG_WARN_WRITE_STRINGS CONFIG_COMPILER_WARN_WRITE_STRINGS #define CONFIG_WPA_MBEDTLS_CRYPTO CONFIG_ESP_WIFI_MBEDTLS_CRYPTO #define CONFIG_WPA_MBEDTLS_TLS_CLIENT CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT -#define CONFIG_ARDUINO_IDF_COMMIT "" +#define CONFIG_ARDUINO_IDF_COMMIT "420ebd208a" #define CONFIG_ARDUINO_IDF_BRANCH "release/v5.1" diff --git a/tools/sdk/esp32s2/dout_qspi/libspi_flash.a b/tools/sdk/esp32s2/dout_qspi/libspi_flash.a index ce92771cf60..61cb590a47f 100644 Binary files a/tools/sdk/esp32s2/dout_qspi/libspi_flash.a and b/tools/sdk/esp32s2/dout_qspi/libspi_flash.a differ diff --git a/tools/sdk/esp32s2/flags/defines b/tools/sdk/esp32s2/flags/defines index 5847d2162fb..2c8b36ae704 100644 --- a/tools/sdk/esp32s2/flags/defines +++ b/tools/sdk/esp32s2/flags/defines @@ -1 +1 @@ --DESP_PLATFORM -DIDF_VER=\"v5.1-dev-4124-gbb9200acec\" -DMBEDTLS_CONFIG_FILE=\"mbedtls/esp_config.h\" -DSOC_MMU_PAGE_SIZE=CONFIG_MMU_PAGE_SIZE -DUNITY_INCLUDE_CONFIG_H -D_GNU_SOURCE -D_POSIX_READER_WRITER_LOCKS -DconfigENABLE_FREERTOS_DEBUG_OCDAWARE=1 \ No newline at end of file +-DESP_PLATFORM -DIDF_VER=\"v5.1-dev-4528-g420ebd208a\" -DMBEDTLS_CONFIG_FILE=\"mbedtls/esp_config.h\" -DSOC_MMU_PAGE_SIZE=CONFIG_MMU_PAGE_SIZE -DUNITY_INCLUDE_CONFIG_H -D_GNU_SOURCE -D_POSIX_READER_WRITER_LOCKS -DconfigENABLE_FREERTOS_DEBUG_OCDAWARE=1 \ No newline at end of file diff --git a/tools/sdk/esp32s2/flags/includes b/tools/sdk/esp32s2/flags/includes index f150d44540f..f47604e5461 100644 --- a/tools/sdk/esp32s2/flags/includes +++ b/tools/sdk/esp32s2/flags/includes @@ -1 +1 @@ --iwithprefixbefore newlib/platform_include -iwithprefixbefore freertos/FreeRTOS-Kernel/include -iwithprefixbefore freertos/FreeRTOS-Kernel/portable/xtensa/include -iwithprefixbefore freertos/esp_additions/include/freertos -iwithprefixbefore freertos/esp_additions/include -iwithprefixbefore esp_hw_support/include -iwithprefixbefore esp_hw_support/include/soc -iwithprefixbefore esp_hw_support/include/soc/esp32s2 -iwithprefixbefore esp_hw_support/port/esp32s2 -iwithprefixbefore heap/include -iwithprefixbefore log/include -iwithprefixbefore soc/include -iwithprefixbefore soc/esp32s2 -iwithprefixbefore soc/esp32s2/include -iwithprefixbefore hal/esp32s2/include -iwithprefixbefore hal/include -iwithprefixbefore hal/platform_port/include -iwithprefixbefore esp_rom/include -iwithprefixbefore esp_rom/include/esp32s2 -iwithprefixbefore esp_rom/esp32s2 -iwithprefixbefore esp_common/include -iwithprefixbefore esp_system/include -iwithprefixbefore esp_system/port/soc -iwithprefixbefore esp_system/port/include/private -iwithprefixbefore xtensa/include -iwithprefixbefore xtensa/esp32s2/include -iwithprefixbefore lwip/include -iwithprefixbefore lwip/include/apps -iwithprefixbefore lwip/include/apps/sntp -iwithprefixbefore lwip/lwip/src/include -iwithprefixbefore lwip/port/include -iwithprefixbefore lwip/port/freertos/include -iwithprefixbefore lwip/port/esp32xx/include -iwithprefixbefore lwip/port/esp32xx/include/arch -iwithprefixbefore espressif__mdns/include -iwithprefixbefore console -iwithprefixbefore vfs/include -iwithprefixbefore esp_netif/include -iwithprefixbefore esp_event/include -iwithprefixbefore esp_ringbuf/include -iwithprefixbefore efuse/include -iwithprefixbefore efuse/esp32s2/include -iwithprefixbefore driver/include -iwithprefixbefore driver/deprecated -iwithprefixbefore driver/analog_comparator/include -iwithprefixbefore driver/dac/include -iwithprefixbefore driver/gpio/include -iwithprefixbefore driver/gptimer/include -iwithprefixbefore driver/i2c/include -iwithprefixbefore driver/i2s/include -iwithprefixbefore driver/ledc/include -iwithprefixbefore driver/mcpwm/include -iwithprefixbefore driver/parlio/include -iwithprefixbefore driver/pcnt/include -iwithprefixbefore driver/rmt/include -iwithprefixbefore driver/sdio_slave/include -iwithprefixbefore driver/sdmmc/include -iwithprefixbefore driver/sigma_delta/include -iwithprefixbefore driver/spi/include -iwithprefixbefore driver/temperature_sensor/include -iwithprefixbefore driver/touch_sensor/include -iwithprefixbefore driver/twai/include -iwithprefixbefore driver/uart/include -iwithprefixbefore driver/usb_serial_jtag/include -iwithprefixbefore driver/touch_sensor/esp32s2/include -iwithprefixbefore esp_pm/include -iwithprefixbefore mbedtls/port/include -iwithprefixbefore mbedtls/mbedtls/include -iwithprefixbefore mbedtls/mbedtls/library -iwithprefixbefore mbedtls/esp_crt_bundle/include -iwithprefixbefore esp_app_format/include -iwithprefixbefore bootloader_support/include -iwithprefixbefore bootloader_support/bootloader_flash/include -iwithprefixbefore esp_partition/include -iwithprefixbefore app_update/include -iwithprefixbefore esp_mm/include -iwithprefixbefore spi_flash/include -iwithprefixbefore pthread/include -iwithprefixbefore esp_timer/include -iwithprefixbefore app_trace/include -iwithprefixbefore nvs_flash/include -iwithprefixbefore esp_phy/include -iwithprefixbefore esp_phy/esp32s2/include -iwithprefixbefore wpa_supplicant/include -iwithprefixbefore wpa_supplicant/port/include -iwithprefixbefore wpa_supplicant/esp_supplicant/include -iwithprefixbefore esp_coex/include -iwithprefixbefore esp_wifi/include -iwithprefixbefore esp_wifi/wifi_apps/include -iwithprefixbefore unity/include -iwithprefixbefore unity/unity/src -iwithprefixbefore cmock/CMock/src -iwithprefixbefore http_parser -iwithprefixbefore esp-tls -iwithprefixbefore esp-tls/esp-tls-crypto -iwithprefixbefore esp_adc/include -iwithprefixbefore esp_adc/interface -iwithprefixbefore esp_adc/esp32s2/include -iwithprefixbefore esp_adc/deprecated/include -iwithprefixbefore esp_eth/include -iwithprefixbefore esp_gdbstub/include -iwithprefixbefore esp_gdbstub/xtensa -iwithprefixbefore esp_gdbstub/esp32s2 -iwithprefixbefore esp_hid/include -iwithprefixbefore tcp_transport/include -iwithprefixbefore esp_http_client/include -iwithprefixbefore esp_http_server/include -iwithprefixbefore esp_https_ota/include -iwithprefixbefore esp_https_server/include -iwithprefixbefore esp_lcd/include -iwithprefixbefore esp_lcd/interface -iwithprefixbefore protobuf-c/protobuf-c -iwithprefixbefore protocomm/include/common -iwithprefixbefore protocomm/include/security -iwithprefixbefore protocomm/include/transports -iwithprefixbefore esp_local_ctrl/include -iwithprefixbefore esp_psram/include -iwithprefixbefore espcoredump/include -iwithprefixbefore espcoredump/include/port/xtensa -iwithprefixbefore wear_levelling/include -iwithprefixbefore sdmmc/include -iwithprefixbefore fatfs/diskio -iwithprefixbefore fatfs/vfs -iwithprefixbefore fatfs/src -iwithprefixbefore idf_test/include -iwithprefixbefore idf_test/include/esp32s2 -iwithprefixbefore ieee802154/include -iwithprefixbefore json/cJSON -iwithprefixbefore mqtt/esp-mqtt/include -iwithprefixbefore perfmon/include -iwithprefixbefore spiffs/include -iwithprefixbefore touch_element/include -iwithprefixbefore ulp/ulp_common/include -iwithprefixbefore ulp/ulp_common/include/esp32s2 -iwithprefixbefore usb/include -iwithprefixbefore wifi_provisioning/include -iwithprefixbefore cbor/port/include -iwithprefixbefore rmaker_common/include -iwithprefixbefore esp_diagnostics/include -iwithprefixbefore rtc_store/include -iwithprefixbefore esp_insights/include -iwithprefixbefore json_parser/upstream/include -iwithprefixbefore json_parser/upstream -iwithprefixbefore json_generator/upstream -iwithprefixbefore esp_schedule/include -iwithprefixbefore espressif__esp_secure_cert_mgr/include -iwithprefixbefore esp_rainmaker/include -iwithprefixbefore gpio_button/button/include -iwithprefixbefore qrcode/include -iwithprefixbefore ws2812_led -iwithprefixbefore freertos/FreeRTOS-Kernel/include/freertos -iwithprefixbefore arduino_tinyusb/tinyusb/src -iwithprefixbefore arduino_tinyusb/include -iwithprefixbefore esp_littlefs/include -iwithprefixbefore esp-dl/include -iwithprefixbefore esp-dl/include/tool -iwithprefixbefore esp-dl/include/typedef -iwithprefixbefore esp-dl/include/image -iwithprefixbefore esp-dl/include/math -iwithprefixbefore esp-dl/include/nn -iwithprefixbefore esp-dl/include/layer -iwithprefixbefore esp-dl/include/detect -iwithprefixbefore esp-dl/include/model_zoo -iwithprefixbefore esp-sr/esp-tts/esp_tts_chinese/include -iwithprefixbefore esp32-camera/driver/include -iwithprefixbefore esp32-camera/conversions/include -iwithprefixbefore espressif__esp-dsp/modules/dotprod/include -iwithprefixbefore espressif__esp-dsp/modules/support/include -iwithprefixbefore espressif__esp-dsp/modules/windows/include -iwithprefixbefore espressif__esp-dsp/modules/windows/hann/include -iwithprefixbefore espressif__esp-dsp/modules/windows/blackman/include -iwithprefixbefore espressif__esp-dsp/modules/windows/blackman_harris/include -iwithprefixbefore espressif__esp-dsp/modules/windows/blackman_nuttall/include -iwithprefixbefore espressif__esp-dsp/modules/windows/nuttall/include -iwithprefixbefore espressif__esp-dsp/modules/windows/flat_top/include -iwithprefixbefore espressif__esp-dsp/modules/iir/include -iwithprefixbefore espressif__esp-dsp/modules/fir/include -iwithprefixbefore espressif__esp-dsp/modules/math/include -iwithprefixbefore espressif__esp-dsp/modules/math/add/include -iwithprefixbefore espressif__esp-dsp/modules/math/sub/include -iwithprefixbefore espressif__esp-dsp/modules/math/mul/include -iwithprefixbefore espressif__esp-dsp/modules/math/addc/include -iwithprefixbefore espressif__esp-dsp/modules/math/mulc/include -iwithprefixbefore espressif__esp-dsp/modules/math/sqrt/include -iwithprefixbefore espressif__esp-dsp/modules/matrix/include -iwithprefixbefore espressif__esp-dsp/modules/fft/include -iwithprefixbefore espressif__esp-dsp/modules/dct/include -iwithprefixbefore espressif__esp-dsp/modules/conv/include -iwithprefixbefore espressif__esp-dsp/modules/common/include -iwithprefixbefore espressif__esp-dsp/modules/kalman/ekf/include -iwithprefixbefore espressif__esp-dsp/modules/kalman/ekf_imu13states/include -iwithprefixbefore fb_gfx/include \ No newline at end of file +-iwithprefixbefore newlib/platform_include -iwithprefixbefore freertos/FreeRTOS-Kernel/include -iwithprefixbefore freertos/FreeRTOS-Kernel/portable/xtensa/include -iwithprefixbefore freertos/esp_additions/include/freertos -iwithprefixbefore freertos/esp_additions/include -iwithprefixbefore freertos/esp_additions/arch/xtensa/include -iwithprefixbefore esp_hw_support/include -iwithprefixbefore esp_hw_support/include/soc -iwithprefixbefore esp_hw_support/include/soc/esp32s2 -iwithprefixbefore esp_hw_support/port/esp32s2 -iwithprefixbefore heap/include -iwithprefixbefore log/include -iwithprefixbefore soc/include -iwithprefixbefore soc/esp32s2 -iwithprefixbefore soc/esp32s2/include -iwithprefixbefore hal/esp32s2/include -iwithprefixbefore hal/include -iwithprefixbefore hal/platform_port/include -iwithprefixbefore esp_rom/include -iwithprefixbefore esp_rom/include/esp32s2 -iwithprefixbefore esp_rom/esp32s2 -iwithprefixbefore esp_common/include -iwithprefixbefore esp_system/include -iwithprefixbefore esp_system/port/soc -iwithprefixbefore esp_system/port/include/private -iwithprefixbefore xtensa/include -iwithprefixbefore xtensa/esp32s2/include -iwithprefixbefore lwip/include -iwithprefixbefore lwip/include/apps -iwithprefixbefore lwip/include/apps/sntp -iwithprefixbefore lwip/lwip/src/include -iwithprefixbefore lwip/port/include -iwithprefixbefore lwip/port/freertos/include -iwithprefixbefore lwip/port/esp32xx/include -iwithprefixbefore lwip/port/esp32xx/include/arch -iwithprefixbefore espressif__mdns/include -iwithprefixbefore console -iwithprefixbefore vfs/include -iwithprefixbefore esp_netif/include -iwithprefixbefore esp_event/include -iwithprefixbefore esp_ringbuf/include -iwithprefixbefore efuse/include -iwithprefixbefore efuse/esp32s2/include -iwithprefixbefore driver/include -iwithprefixbefore driver/deprecated -iwithprefixbefore driver/analog_comparator/include -iwithprefixbefore driver/dac/include -iwithprefixbefore driver/gpio/include -iwithprefixbefore driver/gptimer/include -iwithprefixbefore driver/i2c/include -iwithprefixbefore driver/i2s/include -iwithprefixbefore driver/ledc/include -iwithprefixbefore driver/mcpwm/include -iwithprefixbefore driver/parlio/include -iwithprefixbefore driver/pcnt/include -iwithprefixbefore driver/rmt/include -iwithprefixbefore driver/sdio_slave/include -iwithprefixbefore driver/sdmmc/include -iwithprefixbefore driver/sigma_delta/include -iwithprefixbefore driver/spi/include -iwithprefixbefore driver/temperature_sensor/include -iwithprefixbefore driver/touch_sensor/include -iwithprefixbefore driver/twai/include -iwithprefixbefore driver/uart/include -iwithprefixbefore driver/usb_serial_jtag/include -iwithprefixbefore driver/touch_sensor/esp32s2/include -iwithprefixbefore esp_pm/include -iwithprefixbefore mbedtls/port/include -iwithprefixbefore mbedtls/mbedtls/include -iwithprefixbefore mbedtls/mbedtls/library -iwithprefixbefore mbedtls/esp_crt_bundle/include -iwithprefixbefore esp_app_format/include -iwithprefixbefore bootloader_support/include -iwithprefixbefore bootloader_support/bootloader_flash/include -iwithprefixbefore esp_partition/include -iwithprefixbefore app_update/include -iwithprefixbefore esp_mm/include -iwithprefixbefore spi_flash/include -iwithprefixbefore pthread/include -iwithprefixbefore esp_timer/include -iwithprefixbefore app_trace/include -iwithprefixbefore nvs_flash/include -iwithprefixbefore esp_phy/include -iwithprefixbefore esp_phy/esp32s2/include -iwithprefixbefore wpa_supplicant/include -iwithprefixbefore wpa_supplicant/port/include -iwithprefixbefore wpa_supplicant/esp_supplicant/include -iwithprefixbefore esp_coex/include -iwithprefixbefore esp_wifi/include -iwithprefixbefore esp_wifi/wifi_apps/include -iwithprefixbefore unity/include -iwithprefixbefore unity/unity/src -iwithprefixbefore cmock/CMock/src -iwithprefixbefore http_parser -iwithprefixbefore esp-tls -iwithprefixbefore esp-tls/esp-tls-crypto -iwithprefixbefore esp_adc/include -iwithprefixbefore esp_adc/interface -iwithprefixbefore esp_adc/esp32s2/include -iwithprefixbefore esp_adc/deprecated/include -iwithprefixbefore esp_eth/include -iwithprefixbefore esp_gdbstub/include -iwithprefixbefore esp_gdbstub/xtensa -iwithprefixbefore esp_gdbstub/esp32s2 -iwithprefixbefore esp_hid/include -iwithprefixbefore tcp_transport/include -iwithprefixbefore esp_http_client/include -iwithprefixbefore esp_http_server/include -iwithprefixbefore esp_https_ota/include -iwithprefixbefore esp_https_server/include -iwithprefixbefore esp_psram/include -iwithprefixbefore esp_lcd/include -iwithprefixbefore esp_lcd/interface -iwithprefixbefore protobuf-c/protobuf-c -iwithprefixbefore protocomm/include/common -iwithprefixbefore protocomm/include/security -iwithprefixbefore protocomm/include/transports -iwithprefixbefore esp_local_ctrl/include -iwithprefixbefore espcoredump/include -iwithprefixbefore espcoredump/include/port/xtensa -iwithprefixbefore wear_levelling/include -iwithprefixbefore sdmmc/include -iwithprefixbefore fatfs/diskio -iwithprefixbefore fatfs/vfs -iwithprefixbefore fatfs/src -iwithprefixbefore idf_test/include -iwithprefixbefore idf_test/include/esp32s2 -iwithprefixbefore ieee802154/include -iwithprefixbefore json/cJSON -iwithprefixbefore mqtt/esp-mqtt/include -iwithprefixbefore perfmon/include -iwithprefixbefore spiffs/include -iwithprefixbefore touch_element/include -iwithprefixbefore ulp/ulp_common/include -iwithprefixbefore ulp/ulp_common/include/esp32s2 -iwithprefixbefore usb/include -iwithprefixbefore wifi_provisioning/include -iwithprefixbefore cbor/port/include -iwithprefixbefore rmaker_common/include -iwithprefixbefore esp_diagnostics/include -iwithprefixbefore rtc_store/include -iwithprefixbefore esp_insights/include -iwithprefixbefore json_parser/upstream/include -iwithprefixbefore json_parser/upstream -iwithprefixbefore json_generator/upstream -iwithprefixbefore esp_schedule/include -iwithprefixbefore espressif__esp_secure_cert_mgr/include -iwithprefixbefore esp_rainmaker/include -iwithprefixbefore gpio_button/button/include -iwithprefixbefore qrcode/include -iwithprefixbefore ws2812_led -iwithprefixbefore freertos/FreeRTOS-Kernel/include/freertos -iwithprefixbefore arduino_tinyusb/tinyusb/src -iwithprefixbefore arduino_tinyusb/include -iwithprefixbefore esp_littlefs/include -iwithprefixbefore esp-dl/include -iwithprefixbefore esp-dl/include/tool -iwithprefixbefore esp-dl/include/typedef -iwithprefixbefore esp-dl/include/image -iwithprefixbefore esp-dl/include/math -iwithprefixbefore esp-dl/include/nn -iwithprefixbefore esp-dl/include/layer -iwithprefixbefore esp-dl/include/detect -iwithprefixbefore esp-dl/include/model_zoo -iwithprefixbefore espressif__esp-dsp/modules/dotprod/include -iwithprefixbefore espressif__esp-dsp/modules/support/include -iwithprefixbefore espressif__esp-dsp/modules/windows/include -iwithprefixbefore espressif__esp-dsp/modules/windows/hann/include -iwithprefixbefore espressif__esp-dsp/modules/windows/blackman/include -iwithprefixbefore espressif__esp-dsp/modules/windows/blackman_harris/include -iwithprefixbefore espressif__esp-dsp/modules/windows/blackman_nuttall/include -iwithprefixbefore espressif__esp-dsp/modules/windows/nuttall/include -iwithprefixbefore espressif__esp-dsp/modules/windows/flat_top/include -iwithprefixbefore espressif__esp-dsp/modules/iir/include -iwithprefixbefore espressif__esp-dsp/modules/fir/include -iwithprefixbefore espressif__esp-dsp/modules/math/include -iwithprefixbefore espressif__esp-dsp/modules/math/add/include -iwithprefixbefore espressif__esp-dsp/modules/math/sub/include -iwithprefixbefore espressif__esp-dsp/modules/math/mul/include -iwithprefixbefore espressif__esp-dsp/modules/math/addc/include -iwithprefixbefore espressif__esp-dsp/modules/math/mulc/include -iwithprefixbefore espressif__esp-dsp/modules/math/sqrt/include -iwithprefixbefore espressif__esp-dsp/modules/matrix/include -iwithprefixbefore espressif__esp-dsp/modules/fft/include -iwithprefixbefore espressif__esp-dsp/modules/dct/include -iwithprefixbefore espressif__esp-dsp/modules/conv/include -iwithprefixbefore espressif__esp-dsp/modules/common/include -iwithprefixbefore espressif__esp-dsp/modules/kalman/ekf/include -iwithprefixbefore espressif__esp-dsp/modules/kalman/ekf_imu13states/include -iwithprefixbefore esp-sr/esp-tts/esp_tts_chinese/include -iwithprefixbefore esp32-camera/driver/include -iwithprefixbefore esp32-camera/conversions/include -iwithprefixbefore fb_gfx/include \ No newline at end of file diff --git a/tools/sdk/esp32s2/flags/ld_flags b/tools/sdk/esp32s2/flags/ld_flags index 15209b0a93c..8ecf3991d2e 100644 --- a/tools/sdk/esp32s2/flags/ld_flags +++ b/tools/sdk/esp32s2/flags/ld_flags @@ -1 +1 @@ --mlongcalls -Wl,--cref -Wl,--defsym=IDF_TARGET_ESP32S2=0 -Wl,--no-warn-rwx-segments -fno-rtti -fno-lto -Wl,--gc-sections -Wl,--warn-common -Wl,--wrap=esp_log_write -Wl,--wrap=esp_log_writev -Wl,--wrap=log_printf -u _Z5setupv -u _Z4loopv -u esp_app_desc -u pthread_include_pthread_impl -u pthread_include_pthread_cond_impl -u pthread_include_pthread_local_storage_impl -u pthread_include_pthread_rwlock_impl -u ld_include_highint_hdl -u start_app -u __ubsan_include -Wl,--wrap=longjmp -u __assert_func -Wl,--undefined=uxTopUsedPriority -Wl,--undefined=FreeRTOS_openocd_params -u app_main -u newlib_include_heap_impl -u newlib_include_syscalls_impl -u newlib_include_pthread_impl -u newlib_include_assert_impl -u __cxa_guard_dummy -u include_esp_phy_override -u vfs_include_syscalls_impl \ No newline at end of file +-mlongcalls -Wl,--cref -Wl,--defsym=IDF_TARGET_ESP32S2=0 -Wl,--no-warn-rwx-segments -fno-rtti -fno-lto -Wl,--gc-sections -Wl,--warn-common -Wl,--wrap=esp_log_write -Wl,--wrap=esp_log_writev -Wl,--wrap=log_printf -u _Z5setupv -u _Z4loopv -u esp_app_desc -u pthread_include_pthread_impl -u pthread_include_pthread_cond_impl -u pthread_include_pthread_local_storage_impl -u pthread_include_pthread_rwlock_impl -u pthread_include_pthread_semaphore_impl -u ld_include_highint_hdl -u start_app -u __ubsan_include -Wl,--wrap=longjmp -u __assert_func -Wl,--undefined=uxTopUsedPriority -Wl,--undefined=FreeRTOS_openocd_params -u app_main -u newlib_include_heap_impl -u newlib_include_syscalls_impl -u newlib_include_pthread_impl -u newlib_include_assert_impl -u __cxa_guard_dummy -u include_esp_phy_override -u vfs_include_syscalls_impl \ No newline at end of file diff --git a/tools/sdk/esp32s2/flags/ld_libs b/tools/sdk/esp32s2/flags/ld_libs index ddad795aadc..81a60cc43e8 100644 --- a/tools/sdk/esp32s2/flags/ld_libs +++ b/tools/sdk/esp32s2/flags/ld_libs @@ -1 +1 @@ --lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lapp_trace -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lunity -lcmock -lconsole -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -lesp_hid -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_https_server -lesp_lcd -lprotobuf-c -lprotocomm -lesp_local_ctrl -lesp_psram -lespcoredump -lwear_levelling -lsdmmc -lfatfs -ljson -lmqtt -lperfmon -lspiffs -ltouch_element -lulp -lusb -lwifi_provisioning -lespressif__mdns -lcbor -lrmaker_common -lesp_diagnostics -lrtc_store -lesp_insights -ljson_parser -ljson_generator -lesp_schedule -lespressif__esp_secure_cert_mgr -lesp_rainmaker -lgpio_button -lqrcode -lws2812_led -larduino_tinyusb -lesp32-camera -lesp_littlefs -lespressif__esp-dsp -lfb_gfx -lapp_trace -lapp_trace -lcmock -lunity -lesp_lcd -lperfmon -ltouch_element -lusb -lesp_hid -lfatfs -lwear_levelling -lsdmmc -lesp_insights -lcbor -lesp_diagnostics -lrtc_store -lesp_rainmaker -lesp_local_ctrl -lesp_https_server -lwifi_provisioning -lprotocomm -lprotobuf-c -ljson -lespressif__mdns -ljson_parser -ljson_generator -lesp_schedule -lespressif__esp_secure_cert_mgr -lqrcode -lrmaker_common -lconsole -lmqtt -lcat_face_detect -lhuman_face_detect -lcolor_detect -lmfn -ldl -lspiffs -lesp_tts_chinese -lvoice_set_xiaole -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxt_hal -lc -lm -lnewlib -lstdc++ -lpthread -lgcc -lcxx -lphy -lesp_phy -lphy -lesp_phy -lphy \ No newline at end of file +-lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lapp_trace -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lunity -lcmock -lconsole -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -lesp_hid -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_https_server -lesp_psram -lesp_lcd -lprotobuf-c -lprotocomm -lesp_local_ctrl -lespcoredump -lwear_levelling -lsdmmc -lfatfs -ljson -lmqtt -lperfmon -lspiffs -ltouch_element -lulp -lusb -lwifi_provisioning -lespressif__mdns -lcbor -lrmaker_common -lesp_diagnostics -lrtc_store -lesp_insights -ljson_parser -ljson_generator -lesp_schedule -lespressif__esp_secure_cert_mgr -lesp_rainmaker -lgpio_button -lqrcode -lws2812_led -larduino_tinyusb -lespressif__esp-dsp -lesp32-camera -lesp_littlefs -lfb_gfx -lapp_trace -lapp_trace -lcmock -lunity -lesp_lcd -lperfmon -ltouch_element -lusb -lesp_hid -lfatfs -lwear_levelling -lsdmmc -lesp_insights -lcbor -lesp_diagnostics -lrtc_store -lesp_rainmaker -lesp_local_ctrl -lesp_https_server -lwifi_provisioning -lprotocomm -lprotobuf-c -ljson -lespressif__mdns -ljson_parser -ljson_generator -lesp_schedule -lespressif__esp_secure_cert_mgr -lqrcode -lrmaker_common -lconsole -lmqtt -lcat_face_detect -lhuman_face_detect -lcolor_detect -lmfn -ldl -lspiffs -lespressif__esp-dsp -lesp_tts_chinese -lvoice_set_xiaole -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxt_hal -lc -lm -lnewlib -lstdc++ -lpthread -lgcc -lcxx -lphy -lesp_phy -lphy -lesp_phy -lphy \ No newline at end of file diff --git a/tools/sdk/esp32s2/include/bootloader_support/include/bootloader_common.h b/tools/sdk/esp32s2/include/bootloader_support/include/bootloader_common.h index 6145a72ef8e..b74acf560c7 100644 --- a/tools/sdk/esp32s2/include/bootloader_support/include/bootloader_common.h +++ b/tools/sdk/esp32s2/include/bootloader_support/include/bootloader_common.h @@ -173,7 +173,7 @@ esp_err_t bootloader_common_check_chip_validity(const esp_image_header_t* img_hd */ void bootloader_common_vddsdio_configure(void); -#if defined( CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP ) || defined( CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC ) +#if CONFIG_BOOTLOADER_RESERVE_RTC_MEM /** * @brief Returns partition from rtc_retain_mem * @@ -223,6 +223,21 @@ void bootloader_common_reset_rtc_retain_mem(void); */ uint16_t bootloader_common_get_rtc_retain_mem_reboot_counter(void); +/** + * @brief Returns True if Factory reset has happened + * + * Reset the status after reading it. + * + * @return True: Factory reset has happened + * False: No Factory reset + */ +bool bootloader_common_get_rtc_retain_mem_factory_reset_state(void); + +/** + * @brief Sets Factory reset status + */ +void bootloader_common_set_rtc_retain_mem_factory_reset_state(void); + /** * @brief Returns rtc_retain_mem * @@ -233,7 +248,7 @@ uint16_t bootloader_common_get_rtc_retain_mem_reboot_counter(void); */ rtc_retain_mem_t* bootloader_common_get_rtc_retain_mem(void); -#endif +#endif // CONFIG_BOOTLOADER_RESERVE_RTC_MEM #ifdef __cplusplus } diff --git a/tools/sdk/esp32s2/include/bootloader_support/include/esp_image_format.h b/tools/sdk/esp32s2/include/bootloader_support/include/esp_image_format.h index 20545f5d7f6..5ec2ff0282f 100644 --- a/tools/sdk/esp32s2/include/bootloader_support/include/esp_image_format.h +++ b/tools/sdk/esp32s2/include/bootloader_support/include/esp_image_format.h @@ -47,7 +47,14 @@ typedef enum { typedef struct { esp_partition_pos_t partition; /*!< Partition of application which worked before goes to the deep sleep. */ uint16_t reboot_counter; /*!< Reboot counter. Reset only when power is off. */ - uint16_t reserve; /*!< Reserve */ + union { + struct { + uint8_t factory_reset_state : 1; /* True when Factory reset has occurred */ + uint8_t reserve : 7; /* Reserve */ + }; + uint8_t val; + } flags; + uint8_t reserve; /*!< Reserve */ #ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC uint8_t custom[CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE]; /*!< Reserve for custom propose */ #endif @@ -57,6 +64,8 @@ typedef struct { ESP_STATIC_ASSERT(offsetof(rtc_retain_mem_t, crc) == sizeof(rtc_retain_mem_t) - sizeof(uint32_t), "CRC field must be the last field of rtc_retain_mem_t structure"); +#ifdef CONFIG_BOOTLOADER_RESERVE_RTC_MEM + #ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC ESP_STATIC_ASSERT(CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE % 4 == 0, "CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE must be a multiple of 4 bytes"); /* The custom field must be the penultimate field */ @@ -64,19 +73,16 @@ ESP_STATIC_ASSERT(offsetof(rtc_retain_mem_t, custom) == sizeof(rtc_retain_mem_t) "custom field in rtc_retain_mem_t structure must be the field before the CRC one"); #endif -#if defined(CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP) || defined(CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC) ESP_STATIC_ASSERT(CONFIG_BOOTLOADER_RESERVE_RTC_SIZE % 4 == 0, "CONFIG_BOOTLOADER_RESERVE_RTC_SIZE must be a multiple of 4 bytes"); -#endif #ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC #define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE + CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE) -#elif defined(CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP) +#else #define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE) #endif -#if defined(CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP) || defined(CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC) ESP_STATIC_ASSERT(sizeof(rtc_retain_mem_t) <= ESP_BOOTLOADER_RESERVE_RTC, "Reserved RTC area must exceed size of rtc_retain_mem_t"); -#endif +#endif // CONFIG_BOOTLOADER_RESERVE_RTC_MEM /** * @brief Verify an app image. diff --git a/tools/sdk/esp32s2/include/driver/include/esp_private/spi_common_internal.h b/tools/sdk/esp32s2/include/driver/include/esp_private/spi_common_internal.h index 83b9c1ad6b3..6cc711b5224 100644 --- a/tools/sdk/esp32s2/include/driver/include/esp_private/spi_common_internal.h +++ b/tools/sdk/esp32s2/include/driver/include/esp_private/spi_common_internal.h @@ -13,6 +13,10 @@ #include "freertos/FreeRTOS.h" #include "hal/spi_types.h" #include "esp_pm.h" +#if SOC_GDMA_SUPPORTED +#include "esp_private/gdma.h" +#endif + #ifdef __cplusplus extern "C" @@ -130,6 +134,22 @@ esp_err_t spicommon_dma_chan_alloc(spi_host_device_t host_id, spi_dma_chan_t dma */ esp_err_t spicommon_dma_chan_free(spi_host_device_t host_id); +#if SOC_GDMA_SUPPORTED +/** + * @brief Get SPI GDMA Handle for GMDA Supported Chip + * + * @param host_id SPI host ID + * @param gdma_handle GDMA Handle to Return + * @param gdma_direction GDMA Channel Direction in Enum + * - GDMA_CHANNEL_DIRECTION_TX + * - GDMA_CHANNEL_DIRECTION_RX + * + * @return + * - ESP_OK: On success + */ +esp_err_t spicommon_gdma_get_handle(spi_host_device_t host_id, gdma_channel_handle_t *gdma_handle, gdma_channel_direction_t gdma_direction); +#endif + /** * @brief Connect a SPI peripheral to GPIO pins * diff --git a/tools/sdk/esp32s2/include/driver/ledc/include/driver/ledc.h b/tools/sdk/esp32s2/include/driver/ledc/include/driver/ledc.h index 509b81634d3..c0e2f14530f 100644 --- a/tools/sdk/esp32s2/include/driver/ledc/include/driver/ledc.h +++ b/tools/sdk/esp32s2/include/driver/ledc/include/driver/ledc.h @@ -450,10 +450,10 @@ esp_err_t ledc_fade_start(ledc_mode_t speed_mode, ledc_channel_t channel, ledc_f #if SOC_LEDC_SUPPORT_FADE_STOP /** - * @brief Stop LEDC fading. Duty of the channel will stay at its present vlaue. + * @brief Stop LEDC fading. The duty of the channel is garanteed to be fixed at most one PWM cycle after the function returns. * @note This API can be called if a new fixed duty or a new fade want to be set while the last fade operation is still running in progress. * @note Call this API will abort the fading operation only if it was started by calling ledc_fade_start with LEDC_FADE_NO_WAIT mode. - * @note If a fade was started with LEDC_FADE_WAIT_DONE mode, calling this API afterwards is no use in stopping the fade. Fade will continue until it reachs the target duty. + * @note If a fade was started with LEDC_FADE_WAIT_DONE mode, calling this API afterwards HAS no use in stopping the fade. Fade will continue until it reachs the target duty. * @param speed_mode Select the LEDC channel group with specified speed mode. Note that not all targets support high speed mode. * @param channel LEDC channel number * diff --git a/tools/sdk/esp32s2/include/driver/rmt/include/driver/rmt_rx.h b/tools/sdk/esp32s2/include/driver/rmt/include/driver/rmt_rx.h index c750a59a734..ddb409d94a7 100644 --- a/tools/sdk/esp32s2/include/driver/rmt/include/driver/rmt_rx.h +++ b/tools/sdk/esp32s2/include/driver/rmt/include/driver/rmt_rx.h @@ -29,10 +29,12 @@ typedef struct { * @brief RMT RX channel specific configuration */ typedef struct { - int gpio_num; /*!< GPIO number used by RMT RX channel. Set to -1 if unused */ + gpio_num_t gpio_num; /*!< GPIO number used by RMT RX channel. Set to -1 if unused */ rmt_clock_source_t clk_src; /*!< Clock source of RMT RX channel, channels in the same group must use the same clock source */ uint32_t resolution_hz; /*!< Channel clock resolution, in Hz */ - size_t mem_block_symbols; /*!< Size of memory block, in number of `rmt_symbol_word_t`, must be an even */ + size_t mem_block_symbols; /*!< Size of memory block, in number of `rmt_symbol_word_t`, must be an even. + In the DMA mode, this field controls the DMA buffer size, it can be set to a large value (e.g. 1024); + In the normal mode, this field controls the number of RMT memory block that will be used by the channel. */ struct { uint32_t invert_in: 1; /*!< Whether to invert the incoming RMT channel signal */ uint32_t with_dma: 1; /*!< If set, the driver will allocate an RMT channel with DMA capability */ diff --git a/tools/sdk/esp32s2/include/driver/rmt/include/driver/rmt_tx.h b/tools/sdk/esp32s2/include/driver/rmt/include/driver/rmt_tx.h index 83b1cef392e..9444ae3aabc 100644 --- a/tools/sdk/esp32s2/include/driver/rmt/include/driver/rmt_tx.h +++ b/tools/sdk/esp32s2/include/driver/rmt/include/driver/rmt_tx.h @@ -30,10 +30,12 @@ typedef struct { * @brief RMT TX channel specific configuration */ typedef struct { - int gpio_num; /*!< GPIO number used by RMT TX channel. Set to -1 if unused */ + gpio_num_t gpio_num; /*!< GPIO number used by RMT TX channel. Set to -1 if unused */ rmt_clock_source_t clk_src; /*!< Clock source of RMT TX channel, channels in the same group must use the same clock source */ uint32_t resolution_hz; /*!< Channel clock resolution, in Hz */ - size_t mem_block_symbols; /*!< Size of memory block, in number of `rmt_symbol_word_t`, must be an even */ + size_t mem_block_symbols; /*!< Size of memory block, in number of `rmt_symbol_word_t`, must be an even. + In the DMA mode, this field controls the DMA buffer size, it can be set to a large value; + In the normal mode, this field controls the number of RMT memory block that will be used by the channel. */ size_t trans_queue_depth; /*!< Depth of internal transfer queue, increase this value can support more transfers pending in the background */ struct { uint32_t invert_out: 1; /*!< Whether to invert the RMT channel signal before output to GPIO pad */ diff --git a/tools/sdk/esp32s2/include/driver/rmt/include/driver/rmt_types.h b/tools/sdk/esp32s2/include/driver/rmt/include/driver/rmt_types.h index 2dea896ea67..63032d4d994 100644 --- a/tools/sdk/esp32s2/include/driver/rmt/include/driver/rmt_types.h +++ b/tools/sdk/esp32s2/include/driver/rmt/include/driver/rmt_types.h @@ -10,6 +10,7 @@ #include #include #include "hal/rmt_types.h" +#include "hal/gpio_types.h" // for gpio_num_t #ifdef __cplusplus extern "C" { diff --git a/tools/sdk/esp32s2/include/driver/sdmmc/include/driver/sdmmc_host.h b/tools/sdk/esp32s2/include/driver/sdmmc/include/driver/sdmmc_host.h index 1a4beb892a4..46b6f6af366 100644 --- a/tools/sdk/esp32s2/include/driver/sdmmc/include/driver/sdmmc_host.h +++ b/tools/sdk/esp32s2/include/driver/sdmmc/include/driver/sdmmc_host.h @@ -40,6 +40,7 @@ extern "C" { .get_bus_width = &sdmmc_host_get_slot_width, \ .set_bus_ddr_mode = &sdmmc_host_set_bus_ddr_mode, \ .set_card_clk = &sdmmc_host_set_card_clk, \ + .set_cclk_always_on = &sdmmc_host_set_cclk_always_on, \ .do_transaction = &sdmmc_host_do_transaction, \ .deinit = &sdmmc_host_deinit, \ .io_int_enable = sdmmc_host_io_int_enable, \ @@ -204,6 +205,19 @@ esp_err_t sdmmc_host_set_card_clk(int slot, uint32_t freq_khz); */ esp_err_t sdmmc_host_set_bus_ddr_mode(int slot, bool ddr_enabled); +/** + * @brief Enable or disable always-on card clock + * When cclk_always_on is false, the host controller is allowed to shut down + * the card clock between the commands. When cclk_always_on is true, the clock + * is generated even if no command is in progress. + * @param slot slot number + * @param cclk_always_on enable or disable always-on clock + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_ARG if the slot number is invalid + */ +esp_err_t sdmmc_host_set_cclk_always_on(int slot, bool cclk_always_on); + /** * @brief Send command to the card and get response * diff --git a/tools/sdk/esp32s2/include/driver/sdmmc/include/driver/sdmmc_types.h b/tools/sdk/esp32s2/include/driver/sdmmc/include/driver/sdmmc_types.h index 8a38d792e3a..bc74a38c1d5 100644 --- a/tools/sdk/esp32s2/include/driver/sdmmc/include/driver/sdmmc_types.h +++ b/tools/sdk/esp32s2/include/driver/sdmmc/include/driver/sdmmc_types.h @@ -175,6 +175,7 @@ typedef struct { size_t (*get_bus_width)(int slot); /*!< host function to get bus width */ esp_err_t (*set_bus_ddr_mode)(int slot, bool ddr_enable); /*!< host function to set DDR mode */ esp_err_t (*set_card_clk)(int slot, uint32_t freq_khz); /*!< host function to set card clock frequency */ + esp_err_t (*set_cclk_always_on)(int slot, bool cclk_always_on); /*!< host function to set whether the clock is always enabled */ esp_err_t (*do_transaction)(int slot, sdmmc_command_t* cmdinfo); /*!< host function to do a transaction */ union { esp_err_t (*deinit)(void); /*!< host function to deinitialize the driver */ diff --git a/tools/sdk/esp32s2/include/driver/spi/include/driver/sdspi_host.h b/tools/sdk/esp32s2/include/driver/spi/include/driver/sdspi_host.h index 3b127fbfefb..146cff69cd3 100644 --- a/tools/sdk/esp32s2/include/driver/spi/include/driver/sdspi_host.h +++ b/tools/sdk/esp32s2/include/driver/spi/include/driver/sdspi_host.h @@ -45,6 +45,7 @@ typedef int sdspi_dev_handle_t; .get_bus_width = NULL, \ .set_bus_ddr_mode = NULL, \ .set_card_clk = &sdspi_host_set_card_clk, \ + .set_cclk_always_on = NULL, \ .do_transaction = &sdspi_host_do_transaction, \ .deinit_p = &sdspi_host_remove_device, \ .io_int_enable = &sdspi_host_io_int_enable, \ diff --git a/tools/sdk/esp32s2/include/driver/uart/include/driver/uart.h b/tools/sdk/esp32s2/include/driver/uart/include/driver/uart.h index ba5f49306ea..314adf172dd 100644 --- a/tools/sdk/esp32s2/include/driver/uart/include/driver/uart.h +++ b/tools/sdk/esp32s2/include/driver/uart/include/driver/uart.h @@ -766,8 +766,10 @@ esp_err_t uart_get_collision_flag(uart_port_t uart_num, bool* collision_flag); * The character that triggers wakeup is not received by UART (i.e. it can not * be obtained from UART FIFO). Depending on the baud rate, a few characters * after that will also not be received. Note that when the chip enters and exits - * light sleep mode, APB frequency will be changing. To make sure that UART has - * correct baud rate all the time, select UART_SCLK_REF_TICK or UART_SCLK_XTAL as UART clock source in uart_config_t::source_clk. + * light sleep mode, APB frequency will be changing. To ensure that UART has + * correct Baud rate all the time, it is necessary to select a source clock which has + * a fixed frequency and remains active during sleep. For the supported clock sources + * of the chips, please refer to `uart_sclk_t` or `soc_periph_uart_clk_src_legacy_t` * * @note in ESP32, the wakeup signal can only be input via IO_MUX (i.e. * GPIO3 should be configured as function_1 to wake up UART0, diff --git a/tools/sdk/esp32s2/include/efuse/esp32s2/include/esp_efuse_table.h b/tools/sdk/esp32s2/include/efuse/esp32s2/include/esp_efuse_table.h index 6e0404f31f9..957e041d741 100644 --- a/tools/sdk/esp32s2/include/efuse/esp32s2/include/esp_efuse_table.h +++ b/tools/sdk/esp32s2/include/efuse/esp32s2/include/esp_efuse_table.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,7 +10,7 @@ extern "C" { #include "esp_efuse.h" -// md5_digest_table 3ac9188bf7eb0a27f3f636085a260743 +// md5_digest_table 42c79ddff54c8f03645a832a69f60af2 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -19,55 +19,148 @@ extern "C" { extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_RTC_RAM_BOOT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DCACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_ICACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_DCACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[]; +#define ESP_EFUSE_WR_DIS_DIS_CAN ESP_EFUSE_WR_DIS_DIS_TWAI +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_BOOT_REMAP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HARD_DIS_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_XPD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_TIEH[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_FORCE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[]; +#define ESP_EFUSE_WR_DIS_KEY0_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_0 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[]; +#define ESP_EFUSE_WR_DIS_KEY1_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_1 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[]; +#define ESP_EFUSE_WR_DIS_KEY2_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_2 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[]; +#define ESP_EFUSE_WR_DIS_KEY3_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_3 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[]; +#define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[]; +#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_LEGACY_SPI_BOOT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CHANNEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PIN_POWER_SELECTION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TYPE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[]; +#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CLK[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_Q[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_HD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_WP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_DQS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D4[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D5[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D6[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D7[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_HI[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_LO[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC_CALIB[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A10H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A11H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A12H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A13H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A20H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A21H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A22H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A23H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A10L[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A11L[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A12L[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A13L[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A20L[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A21L[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A22L[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A23L[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[]; +#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[]; +#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC +#define ESP_EFUSE_WR_DIS_USER_DATA_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[]; +#define ESP_EFUSE_WR_DIS_KEY0 ESP_EFUSE_WR_DIS_BLOCK_KEY0 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[]; +#define ESP_EFUSE_WR_DIS_KEY1 ESP_EFUSE_WR_DIS_BLOCK_KEY1 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[]; +#define ESP_EFUSE_WR_DIS_KEY2 ESP_EFUSE_WR_DIS_BLOCK_KEY2 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[]; +#define ESP_EFUSE_WR_DIS_KEY3 ESP_EFUSE_WR_DIS_BLOCK_KEY3 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[]; +#define ESP_EFUSE_WR_DIS_KEY4 ESP_EFUSE_WR_DIS_BLOCK_KEY4 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[]; +#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[]; +#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXT_PHY_ENABLE[]; +#define ESP_EFUSE_WR_DIS_EXT_PHY_ENABLE ESP_EFUSE_WR_DIS_USB_EXT_PHY_ENABLE +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_FORCE_NOPERSIST[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK0_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_RTC_RAM_BOOT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[]; +#define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[]; +#define ESP_EFUSE_RD_DIS_KEY1 ESP_EFUSE_RD_DIS_BLOCK_KEY1 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[]; +#define ESP_EFUSE_RD_DIS_KEY2 ESP_EFUSE_RD_DIS_BLOCK_KEY2 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[]; +#define ESP_EFUSE_RD_DIS_KEY3 ESP_EFUSE_RD_DIS_BLOCK_KEY3 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[]; +#define ESP_EFUSE_RD_DIS_KEY4 ESP_EFUSE_RD_DIS_BLOCK_KEY4 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[]; +#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[]; +#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DCACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_DCACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[]; +#define ESP_EFUSE_DIS_CAN ESP_EFUSE_DIS_TWAI extern const esp_efuse_desc_t* ESP_EFUSE_DIS_BOOT_REMAP[]; extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_HARD_DIS_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[]; extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXT_PHY_ENABLE[]; +#define ESP_EFUSE_EXT_PHY_ENABLE ESP_EFUSE_USB_EXT_PHY_ENABLE +extern const esp_efuse_desc_t* ESP_EFUSE_USB_FORCE_NOPERSIST[]; extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK0_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_XPD[]; extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_TIEH[]; @@ -78,11 +171,17 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[]; extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[]; +#define ESP_EFUSE_KEY0_PURPOSE ESP_EFUSE_KEY_PURPOSE_0 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[]; +#define ESP_EFUSE_KEY1_PURPOSE ESP_EFUSE_KEY_PURPOSE_1 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[]; +#define ESP_EFUSE_KEY2_PURPOSE ESP_EFUSE_KEY_PURPOSE_2 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[]; +#define ESP_EFUSE_KEY3_PURPOSE ESP_EFUSE_KEY_PURPOSE_3 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[]; +#define ESP_EFUSE_KEY4_PURPOSE ESP_EFUSE_KEY_PURPOSE_4 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[]; +#define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5 extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[]; extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[]; @@ -98,35 +197,65 @@ extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[]; +extern const esp_efuse_desc_t* ESP_EFUSE_MAC[]; +#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[]; extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_HI[]; extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_LO[]; extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC_CALIB[]; extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A10H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A11H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A12H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A13H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A20H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A21H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A22H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A23H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A10L[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A11L[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A12L[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A13L[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A20L[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A21L[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A22L[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A23L[]; extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[]; +#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[]; +#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_USER_DATA_MAC_CUSTOM +#define ESP_EFUSE_CUSTOM_MAC ESP_EFUSE_USER_DATA_MAC_CUSTOM extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[]; +#define ESP_EFUSE_BLOCK_KEY0 ESP_EFUSE_KEY0 extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[]; +#define ESP_EFUSE_BLOCK_KEY1 ESP_EFUSE_KEY1 extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[]; +#define ESP_EFUSE_BLOCK_KEY2 ESP_EFUSE_KEY2 extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[]; +#define ESP_EFUSE_BLOCK_KEY3 ESP_EFUSE_KEY3 extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[]; +#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4 extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[]; +#define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5 extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[]; +#define ESP_EFUSE_BLOCK_SYS_DATA2 ESP_EFUSE_SYS_DATA_PART2 #ifdef __cplusplus } diff --git a/tools/sdk/esp32s2/include/esp-tls/esp_tls.h b/tools/sdk/esp32s2/include/esp-tls/esp_tls.h index 3ada350379e..0efe587b53b 100644 --- a/tools/sdk/esp32s2/include/esp-tls/esp_tls.h +++ b/tools/sdk/esp32s2/include/esp-tls/esp_tls.h @@ -71,6 +71,15 @@ typedef struct tls_keep_alive_cfg { int keep_alive_count; /*!< Keep-alive packet retry send count */ } tls_keep_alive_cfg_t; +/* +* @brief ESP-TLS Address families +*/ +typedef enum esp_tls_addr_family { + ESP_TLS_AF_UNSPEC = 0, /**< Unspecified address family. */ + ESP_TLS_AF_INET, /**< IPv4 address family. */ + ESP_TLS_AF_INET6, /**< IPv6 address family. */ +} esp_tls_addr_family_t; + /** * @brief ESP-TLS configuration parameters * @@ -182,6 +191,8 @@ typedef struct esp_tls_cfg { #ifdef CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS esp_tls_client_session_t *client_session; /*! Pointer for the client session ticket context. */ #endif /* CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS */ + + esp_tls_addr_family_t addr_family; /*!< The address family to use when connecting to a host. */ } esp_tls_cfg_t; #ifdef CONFIG_ESP_TLS_SERVER diff --git a/tools/sdk/esp32s2/include/esp_coex/include/esp_coexist.h b/tools/sdk/esp32s2/include/esp_coex/include/esp_coexist.h index e3fb019d420..9ed897c28a7 100644 --- a/tools/sdk/esp32s2/include/esp_coex/include/esp_coexist.h +++ b/tools/sdk/esp32s2/include/esp_coex/include/esp_coexist.h @@ -201,6 +201,14 @@ esp_err_t esp_external_coex_set_validate_high(bool is_high_valid); #endif #endif +#if CONFIG_ESP_COEX_SW_COEXIST_ENABLE && CONFIG_SOC_IEEE802154_SUPPORTED +/** + * @brief Enable Wi-Fi and 802.15.4 coexistence. + * @return : ESP_OK - success, other - failed + */ +esp_err_t esp_coex_wifi_i154_enable(void); +#endif + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32s2/include/esp_coex/include/esp_coexist_adapter.h b/tools/sdk/esp32s2/include/esp_coex/include/esp_coexist_adapter.h index 11bf54d9b5e..fde83d1111d 100644 --- a/tools/sdk/esp32s2/include/esp_coex/include/esp_coexist_adapter.h +++ b/tools/sdk/esp32s2/include/esp_coex/include/esp_coexist_adapter.h @@ -38,7 +38,10 @@ typedef struct { void (* _free)(void *p); int64_t (* _esp_timer_get_time)(void); bool (* _env_is_chip)(void); +#if CONFIG_IDF_TARGET_ESP32C2 + // this function is only used on esp32c2 uint32_t (* _slowclk_cal_get)(void); +#endif void (* _timer_disarm)(void *timer); void (* _timer_done)(void *ptimer); void (* _timer_setfn)(void *ptimer, void *pfunction, void *parg); diff --git a/tools/sdk/esp32s2/include/esp_http_client/include/esp_http_client.h b/tools/sdk/esp32s2/include/esp_http_client/include/esp_http_client.h index 5638b7c6817..e1dbd5c8f1c 100644 --- a/tools/sdk/esp32s2/include/esp_http_client/include/esp_http_client.h +++ b/tools/sdk/esp32s2/include/esp_http_client/include/esp_http_client.h @@ -382,6 +382,34 @@ esp_err_t esp_http_client_set_password(esp_http_client_handle_t client, const ch */ esp_err_t esp_http_client_set_authtype(esp_http_client_handle_t client, esp_http_client_auth_type_t auth_type); +/** + * @brief Get http request user_data. + * The value stored from the esp_http_client_config_t will be written + * to the address passed into data. + * + * @param[in] client The esp_http_client handle + * @param[out] data A pointer to the pointer that will be set to user_data. + * + * @return + * - ESP_OK + * - ESP_ERR_INVALID_ARG + */ +esp_err_t esp_http_client_get_user_data(esp_http_client_handle_t client, void **data); + +/** + * @brief Set http request user_data. + * The value passed in +data+ will be available during event callbacks. + * No memory management will be performed on the user's behalf. + * + * @param[in] client The esp_http_client handle + * @param[in] data The pointer to the user data + * + * @return + * - ESP_OK + * - ESP_ERR_INVALID_ARG + */ +esp_err_t esp_http_client_set_user_data(esp_http_client_handle_t client, void *data); + /** * @brief Get HTTP client session errno * diff --git a/tools/sdk/esp32s2/include/esp_http_server/include/esp_http_server.h b/tools/sdk/esp32s2/include/esp_http_server/include/esp_http_server.h index 3826a40c9a3..39c2a82a31f 100644 --- a/tools/sdk/esp32s2/include/esp_http_server/include/esp_http_server.h +++ b/tools/sdk/esp32s2/include/esp_http_server/include/esp_http_server.h @@ -15,6 +15,7 @@ #include #include #include +#include #ifdef __cplusplus extern "C" { diff --git a/tools/sdk/esp32s2/include/esp_hw_support/include/esp_private/esp_modem_clock.h b/tools/sdk/esp32s2/include/esp_hw_support/include/esp_private/esp_modem_clock.h index 8b406550c66..bc678e039c3 100644 --- a/tools/sdk/esp32s2/include/esp_hw_support/include/esp_private/esp_modem_clock.h +++ b/tools/sdk/esp32s2/include/esp_hw_support/include/esp_private/esp_modem_clock.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,6 +10,7 @@ #include #include +#include "soc/soc_caps.h" #include "soc/periph_defs.h" #include "hal/modem_clock_types.h" diff --git a/tools/sdk/esp32s2/include/esp_hw_support/include/esp_private/gdma.h b/tools/sdk/esp32s2/include/esp_hw_support/include/esp_private/gdma.h index d71f3c6fc8a..bf5d97dd324 100644 --- a/tools/sdk/esp32s2/include/esp_hw_support/include/esp_private/gdma.h +++ b/tools/sdk/esp32s2/include/esp_hw_support/include/esp_private/gdma.h @@ -177,14 +177,28 @@ esp_err_t gdma_set_transfer_ability(gdma_channel_handle_t dma_chan, const gdma_t /** * @brief Apply channel strategy for GDMA channel * - * @param dma_chan GDMA channel handle, allocated by `gdma_new_channel` - * @param config Configuration of GDMA channel strategy + * @param[in] dma_chan GDMA channel handle, allocated by `gdma_new_channel` + * @param[in] config Configuration of GDMA channel strategy * - ESP_OK: Apply channel strategy successfully * - ESP_ERR_INVALID_ARG: Apply channel strategy failed because of invalid argument * - ESP_FAIL: Apply channel strategy failed because of other error */ esp_err_t gdma_apply_strategy(gdma_channel_handle_t dma_chan, const gdma_strategy_config_t *config); +/** + * @brief Set GDMA channel priority + * + * @note By default, all GDMA channels are with the same priority: 0. Channels with the same priority are served in round-robin manner. + * + * @param[in] dma_chan GDMA channel handle, allocated by `gdma_new_channel` + * @param[in] priority Priority of GDMA channel, higher value means higher priority + * @return + * - ESP_OK: Set GDMA channel priority successfully + * - ESP_ERR_INVALID_ARG: Set GDMA channel priority failed because of invalid argument, e.g. priority out of range [0,GDMA_LL_CHANNEL_MAX_PRIORITY] + * - ESP_FAIL: Set GDMA channel priority failed because of other error + */ +esp_err_t gdma_set_priority(gdma_channel_handle_t dma_chan, uint32_t priority); + /** * @brief Delete GDMA channel * @note If you call `gdma_new_channel` several times for a same peripheral, make sure you call this API the same times. @@ -251,6 +265,7 @@ esp_err_t gdma_register_rx_event_callbacks(gdma_channel_handle_t dma_chan, gdma_ * @return * - ESP_OK: Start DMA engine successfully * - ESP_ERR_INVALID_ARG: Start DMA engine failed because of invalid argument + * - ESP_ERR_INVALID_STATE: Start DMA engine failed because of invalid state, e.g. the channel is controlled by ETM, so can't start it manually * - ESP_FAIL: Start DMA engine failed because of other error */ esp_err_t gdma_start(gdma_channel_handle_t dma_chan, intptr_t desc_base_addr); @@ -265,6 +280,7 @@ esp_err_t gdma_start(gdma_channel_handle_t dma_chan, intptr_t desc_base_addr); * @return * - ESP_OK: Stop DMA engine successfully * - ESP_ERR_INVALID_ARG: Stop DMA engine failed because of invalid argument + * - ESP_ERR_INVALID_STATE: Stop DMA engine failed because of invalid state, e.g. the channel is controlled by ETM, so can't stop it manually * - ESP_FAIL: Stop DMA engine failed because of other error */ esp_err_t gdma_stop(gdma_channel_handle_t dma_chan); @@ -333,6 +349,7 @@ typedef struct { * @brief Get the ETM task for GDMA channel * * @note The created ETM task object can be deleted later by calling `esp_etm_del_task` + * @note If the GDMA task (e.g. start/stop) is controlled by ETM, then you can't use `gdma_start`/`gdma_stop` to control it. * * @param[in] dma_chan GDMA channel handle, allocated by `gdma_new_channel` * @param[in] config GDMA ETM task configuration diff --git a/tools/sdk/esp32s2/include/esp_hw_support/include/esp_private/sleep_modem.h b/tools/sdk/esp32s2/include/esp_hw_support/include/esp_private/sleep_modem.h index 7e11d88a9e6..7601aeebd82 100644 --- a/tools/sdk/esp32s2/include/esp_hw_support/include/esp_private/sleep_modem.h +++ b/tools/sdk/esp32s2/include/esp_hw_support/include/esp_private/sleep_modem.h @@ -42,6 +42,13 @@ void mac_bb_power_up_cb_execute(void); #if SOC_PM_SUPPORT_PMU_MODEM_STATE +/** + * @brief The retention action in the modem state of WiFi PHY module + * + * @param restore true for restore the PHY context, false for backup the PHY context + */ +void sleep_modem_wifi_do_phy_retention(bool restore); + /** * @brief Get WiFi modem state * diff --git a/tools/sdk/esp32s2/include/esp_hw_support/include/soc/esp32c2/memprot.h b/tools/sdk/esp32s2/include/esp_hw_support/include/soc/esp32c2/memprot.h deleted file mode 100644 index c7b1ad461e8..00000000000 --- a/tools/sdk/esp32s2/include/esp_hw_support/include/soc/esp32c2/memprot.h +++ /dev/null @@ -1,440 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - - -/* INTERNAL API - * generic interface to PMS memory protection features - */ - -#pragma once - -#include -#include -#include "esp_attr.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef IRAM_SRAM_START -#define IRAM_SRAM_START 0x4037C000 -#endif - -#ifndef DRAM_SRAM_START -#define DRAM_SRAM_START 0x3FC7C000 -#endif - -typedef enum { - MEMPROT_NONE = 0x00000000, - MEMPROT_IRAM0_SRAM = 0x00000001, - MEMPROT_DRAM0_SRAM = 0x00000002, - MEMPROT_ALL = 0xFFFFFFFF -} mem_type_prot_t; - -typedef enum { - MEMPROT_SPLITLINE_NONE = 0, - MEMPROT_IRAM0_DRAM0_SPLITLINE, - MEMPROT_IRAM0_LINE_0_SPLITLINE, - MEMPROT_IRAM0_LINE_1_SPLITLINE, - MEMPROT_DRAM0_DMA_LINE_0_SPLITLINE, - MEMPROT_DRAM0_DMA_LINE_1_SPLITLINE -} split_line_t; - -typedef enum { - MEMPROT_PMS_AREA_NONE = 0, - MEMPROT_IRAM0_PMS_AREA_0, - MEMPROT_IRAM0_PMS_AREA_1, - MEMPROT_IRAM0_PMS_AREA_2, - MEMPROT_IRAM0_PMS_AREA_3, - MEMPROT_DRAM0_PMS_AREA_0, - MEMPROT_DRAM0_PMS_AREA_1, - MEMPROT_DRAM0_PMS_AREA_2, - MEMPROT_DRAM0_PMS_AREA_3 -} pms_area_t; - -typedef enum -{ - MEMPROT_PMS_WORLD_0 = 0, - MEMPROT_PMS_WORLD_1, - MEMPROT_PMS_WORLD_2, - MEMPROT_PMS_WORLD_INVALID = 0xFFFFFFFF -} pms_world_t; - -typedef enum -{ - MEMPROT_PMS_OP_READ = 0, - MEMPROT_PMS_OP_WRITE, - MEMPROT_PMS_OP_FETCH, - MEMPROT_PMS_OP_INVALID = 0xFFFFFFFF -} pms_operation_type_t; - -/** - * @brief Converts Memory protection type to string - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - */ -const char *esp_memprot_mem_type_to_str(mem_type_prot_t mem_type); - -/** - * @brief Converts Split line type to string - * - * @param line_type Split line type (see split_line_t enum) - */ -const char *esp_memprot_split_line_to_str(split_line_t line_type); - -/** - * @brief Converts PMS Area type to string - * - * @param area_type PMS Area type (see pms_area_t enum) - */ -const char *esp_memprot_pms_to_str(pms_area_t area_type); - -/** - * @brief Returns PMS splitting address for given Split line type - * - * The value is taken from PMS configuration registers (IRam0 range) - * For details on split lines see 'esp_memprot_set_prot_int' function description - * - * @param line_type Split line type (see split_line_t enum) - * - * @return appropriate split line address - */ -uint32_t *esp_memprot_get_split_addr(split_line_t line_type); - -/** - * @brief Returns default main IRAM/DRAM splitting address - * - * The address value is given by _iram_text_end global (IRam0 range) - - * @return Main I/D split line (IRam0_DRam0_Split_Addr) - */ -void *esp_memprot_get_default_main_split_addr(void); - -/** - * @brief Sets a lock for the main IRAM/DRAM splitting address - * - * Locks can be unlocked only by digital system reset - */ -void esp_memprot_set_split_line_lock(void); - -/** - * @brief Gets a lock status for the main IRAM/DRAM splitting address - * - * @return true/false (locked/unlocked) - */ -bool esp_memprot_get_split_line_lock(void); - -/** - * @brief Sets required split line address - * - * @param line_type Split line type (see split_line_t enum) - * @param line_addr target address from a memory range relevant to given line_type (IRAM/DRAM) - */ -void esp_memprot_set_split_line(split_line_t line_type, const void *line_addr); - -/** - * @brief Sets a lock for PMS Area settings of required Memory type - * - * Locks can be unlocked only by digital system reset - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - */ -void esp_memprot_set_pms_lock(mem_type_prot_t mem_type); - -/** - * @brief Gets a lock status for PMS Area settings of required Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return true/false (locked/unlocked) - */ -bool esp_memprot_get_pms_lock(mem_type_prot_t mem_type); - -/** - * @brief Sets permissions for given PMS Area in IRam0 memory range (MEMPROT_IRAM0_SRAM) - * - * @param area_type IRam0 PMS Area type (see pms_area_t enum) - * @param r Read permission flag - * @param w Write permission flag - * @param x Execute permission flag - */ -void esp_memprot_iram_set_pms_area(pms_area_t area_type, bool r, bool w, bool x); - -/** - * @brief Gets current permissions for given PMS Area in IRam0 memory range (MEMPROT_IRAM0_SRAM) - * - * @param area_type IRam0 PMS Area type (see pms_area_t enum) - * @param r Read permission flag holder - * @param w Write permission flag holder - * @param x Execute permission flag holder - */ -void esp_memprot_iram_get_pms_area(pms_area_t area_type, bool *r, bool *w, bool *x); - -/** - * @brief Sets permissions for given PMS Area in DRam0 memory range (MEMPROT_DRAM0_SRAM) - * - * @param area_type DRam0 PMS Area type (see pms_area_t enum) - * @param r Read permission flag - * @param w Write permission flag - */ -void esp_memprot_dram_set_pms_area(pms_area_t area_type, bool r, bool w); - -/** - * @brief Gets current permissions for given PMS Area in DRam0 memory range (MEMPROT_DRAM0_SRAM) - * - * @param area_type DRam0 PMS Area type (see pms_area_t enum) - * @param r Read permission flag holder - * @param w Write permission flag holder - */ -void esp_memprot_dram_get_pms_area(pms_area_t area_type, bool *r, bool *w); - -/** - * @brief Sets a lock for PMS interrupt monitor settings of required Memory type - * - * Locks can be unlocked only by digital system reset - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - */ -void esp_memprot_set_monitor_lock(mem_type_prot_t mem_type); - -/** - * @brief Gets a lock status for PMS interrupt monitor settings of required Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return true/false (locked/unlocked) - */ -bool esp_memprot_get_monitor_lock(mem_type_prot_t mem_type); - -/** - * @brief Enable PMS violation interrupt monitoring of required Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * @param enable/disable - */ -void esp_memprot_set_monitor_en(mem_type_prot_t mem_type, bool enable); - -/** - * @brief Gets enable/disable status for PMS interrupt monitor settings of required Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return true/false (enabled/disabled) - */ -bool esp_memprot_get_monitor_en(mem_type_prot_t mem_type); - -/** - * @brief Gets CPU ID for currently active PMS violation interrupt - * - * @return CPU ID (CPU_PRO for ESP32-C2) - */ -int IRAM_ATTR esp_memprot_intr_get_cpuid(void); - -/** - * @brief Clears current interrupt ON flag for given Memory type - * - * Interrupt clearing happens in two steps: - * 1. Interrupt CLR flag is set (to clear the interrupt ON status) - * 2. Interrupt CLR flag is reset (to allow further monitoring) - * This operation is non-atomic by PMS module design - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - */ -void IRAM_ATTR esp_memprot_monitor_clear_intr(mem_type_prot_t mem_type); - -/** - * @brief Returns active PMS violation interrupt (if any) - * - * This function iterates through supported Memory type status registers - * and returns the first interrupt-on flag. If none is found active, - * MEMPROT_NONE is returned. - * Order of checking (in current version): - * 1. MEMPROT_IRAM0_SRAM - * 2. MEMPROT_DRAM0_SRAM - * - * @return mem_type Memory protection type related to active interrupt found (see mem_type_prot_t enum) - */ -mem_type_prot_t IRAM_ATTR esp_memprot_get_active_intr_memtype(void); - -/** - * @brief Checks whether any violation interrupt is active - * - * @return true/false (yes/no) - */ -bool IRAM_ATTR esp_memprot_is_locked_any(void); - -/** - * @brief Checks whether any violation interrupt is enabled - * - * @return true/false (yes/no) - */ -bool IRAM_ATTR esp_memprot_is_intr_ena_any(void); - -/** - * @brief Checks whether any violation interrupt is enabled - * - * @return true/false (yes/no) - */ -bool IRAM_ATTR esp_memprot_get_violate_intr_on(mem_type_prot_t mem_type); - -/** - * @brief Returns the address which caused the violation interrupt (if any) - * - * The address is taken from appropriate PMS violation status register, based given Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return faulting address - */ -uint32_t IRAM_ATTR esp_memprot_get_violate_addr(mem_type_prot_t mem_type); - -/** - * @brief Returns the World identifier of the code causing the violation interrupt (if any) - * - * The value is taken from appropriate PMS violation status register, based given Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return World identifier (see pms_world_t enum) - */ -pms_world_t IRAM_ATTR esp_memprot_get_violate_world(mem_type_prot_t mem_type); - -/** - * @brief Returns Read or Write operation type which caused the violation interrupt (if any) - * - * The value (bit) is taken from appropriate PMS violation status register, based given Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return PMS operation type relevant to mem_type parameter (se pms_operation_type_t) - */ -pms_operation_type_t IRAM_ATTR esp_memprot_get_violate_wr(mem_type_prot_t mem_type); - -/** - * @brief Returns LoadStore flag of the operation type which caused the violation interrupt (if any) - * - * The value (bit) is taken from appropriate PMS violation status register, based given Memory type - * Effective only on IRam0 access - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return true/false (LoadStore bit on/off) - */ -bool IRAM_ATTR esp_memprot_get_violate_loadstore(mem_type_prot_t mem_type); - -/** - * @brief Returns byte-enables for the address which caused the violation interrupt (if any) - * - * The value is taken from appropriate PMS violation status register, based given Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return byte-enables - */ -uint32_t IRAM_ATTR esp_memprot_get_violate_byte_en(mem_type_prot_t mem_type); - -/** - * @brief Returns raw contents of DRam0 status register 1 - * - * @return 32-bit register value - */ -uint32_t IRAM_ATTR esp_memprot_get_dram_status_reg_1(void); - -/** - * @brief Returns raw contents of DRam0 status register 2 - * - * @return 32-bit register value - */ -uint32_t IRAM_ATTR esp_memprot_get_dram_status_reg_2(void); - -/** - * @brief Returns raw contents of IRam0 status register - * - * @return 32-bit register value - */ -uint32_t IRAM_ATTR esp_memprot_get_iram_status_reg(void); - -/** - * @brief Register PMS violation interrupt in global interrupt matrix for given Memory type - * - * Memory protection components uses specific interrupt number, see ETS_MEMPROT_ERR_INUM - * The registration makes the panic-handler routine being called when the interrupt appears - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - */ -void esp_memprot_set_intr_matrix(mem_type_prot_t mem_type); - -/** - * @brief Convenient routine for setting the PMS defaults - * - * Called on application startup, depending on CONFIG_ESP_SYSTEM_MEMPROT_FEATURE Kconfig settings - * For implementation details see 'esp_memprot_set_prot_int' description - * - * @param invoke_panic_handler register all interrupts for panic handling (true/false) - * @param lock_feature lock the defaults to prevent further PMS settings changes (true/false) - * @param mem_type_mask 32-bit field of specific PMS parts to configure (see 'esp_memprot_set_prot_int') - */ -void esp_memprot_set_prot(bool invoke_panic_handler, bool lock_feature, uint32_t *mem_type_mask); - -/** - * @brief Internal routine for setting the PMS defaults - * - * Called on application startup from within 'esp_memprot_set_prot'. Allows setting a specific splitting address - * (main I/D split line) - see the parameter 'split_addr'. If the 'split_addr' equals to NULL, default I/D split line - * is used (&_iram_text_end) and all the remaining lines share the same address. - * The function sets all the split lines and PMS areas to the same space, - * ie there is a single instruction space and single data space at the end. - * The PMS split lines and permission areas scheme described below: - * - * DRam0/DMA IRam0 - * ----------------------------------------------- - * ... | IRam0_PMS_0 | - * DRam0_PMS_0 ----------------------------------------------- IRam0_line1_Split_addr - * ... | IRam0_PMS_1 | - * ... ----------------------------------------------- IRam0_line0_Split_addr - * | IRam0_PMS_2 | - * =============================================== IRam0_DRam0_Split_addr (main I/D) - * | DRam0_PMS_1 | - * DRam0_DMA_line0_Split_addr ----------------------------------------------- ... - * | DRam0_PMS_2 | ... - * DRam0_DMA_line1_Split_addr ----------------------------------------------- IRam0_PMS_3 - * | DRam0_PMS_3 | ... - * ----------------------------------------------- - * - * Default settings provided by 'esp_memprot_set_prot_int' are as follows: - * - * DRam0/DMA IRam0 - * ----------------------------------------------- - * | IRam0_PMS_0 = IRam0_PMS_1 = IRam0_PMS_2 | - * | DRam0_PMS_0 | IRam0_line1_Split_addr - * DRam0_DMA_line0_Split_addr | | = - * = =============================================== IRam0_line0_Split_addr - * DRam0_DMA_line1_Split_addr | | = - * | DRam0_PMS_1 = DRam0_PMS_2 = DRam0_PMS_3 | IRam0_DRam0_Split_addr (main I/D) - * | IRam0_PMS_3 | - * ----------------------------------------------- - * - * Once the memprot feature is locked, it can be unlocked only by digital system reset - * - * @param invoke_panic_handler register all the violation interrupts for panic handling (true/false) - * @param lock_feature lock the defaults to prevent further PMS settings changes (true/false) - * @param split_addr specific main I/D adrees or NULL to use default ($_iram_text_end) - * @param mem_type_mask 32-bit field of specific PMS parts to configure (members of mem_type_prot_t) - */ -void esp_memprot_set_prot_int(bool invoke_panic_handler, bool lock_feature, void *split_addr, uint32_t *mem_type_mask); - -/** - * @brief Returns raw contents of PMS interrupt monitor register for given Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return 32-bit register value - */ -uint32_t esp_memprot_get_monitor_enable_reg(mem_type_prot_t mem_type); - -#ifdef __cplusplus -} -#endif diff --git a/tools/sdk/esp32s2/include/esp_hw_support/include/soc/esp32s2/memprot.h b/tools/sdk/esp32s2/include/esp_hw_support/include/soc/esp32s2/memprot.h index 0ebd6474578..596633ac7f2 100644 --- a/tools/sdk/esp32s2/include/esp_hw_support/include/soc/esp32s2/memprot.h +++ b/tools/sdk/esp32s2/include/esp_hw_support/include/soc/esp32s2/memprot.h @@ -68,7 +68,7 @@ typedef enum { * The address is given by region-specific global symbol exported from linker script, * it is not read out from related configuration register. */ -uint32_t *IRAM_ATTR esp_memprot_get_split_addr(mem_type_prot_t mem_type); +uint32_t * esp_memprot_get_split_addr(mem_type_prot_t mem_type); /** * @brief Initializes illegal memory access control for required memory section. @@ -116,7 +116,7 @@ esp_err_t esp_memprot_clear_intr(mem_type_prot_t mem_type); * * @return Memory protection area type (see mem_type_prot_t enum) */ -mem_type_prot_t IRAM_ATTR esp_memprot_get_active_intr_memtype(void); +mem_type_prot_t esp_memprot_get_active_intr_memtype(void); /** * @brief Gets interrupt status register contents for specified memory region @@ -141,7 +141,7 @@ esp_err_t esp_memprot_get_fault_reg(mem_type_prot_t mem_type, uint32_t *fault_re * DRAM0: 0 - non-atomic operation, 1 - atomic operation * @return ESP_OK on success, ESP_ERR_INVALID_ARG on failure */ -esp_err_t IRAM_ATTR esp_memprot_get_fault_status(mem_type_prot_t mem_type, uint32_t **faulting_address, uint32_t *op_type, uint32_t *op_subtype); +esp_err_t esp_memprot_get_fault_status(mem_type_prot_t mem_type, uint32_t **faulting_address, uint32_t *op_type, uint32_t *op_subtype); /** * @brief Gets string representation of required memory region identifier @@ -150,7 +150,7 @@ esp_err_t IRAM_ATTR esp_memprot_get_fault_status(mem_type_prot_t mem_type, uint3 * * @return mem_type as string */ -const char *IRAM_ATTR esp_memprot_type_to_str(mem_type_prot_t mem_type); +const char * esp_memprot_type_to_str(mem_type_prot_t mem_type); /** * @brief Detects whether any of the interrupt locks is active (requires digital system reset to unlock) diff --git a/tools/sdk/esp32s2/include/esp_lcd/include/esp_lcd_panel_commands.h b/tools/sdk/esp32s2/include/esp_lcd/include/esp_lcd_panel_commands.h index 091ef1cffef..5917c3e8774 100644 --- a/tools/sdk/esp32s2/include/esp_lcd/include/esp_lcd_panel_commands.h +++ b/tools/sdk/esp32s2/include/esp_lcd/include/esp_lcd_panel_commands.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -31,7 +31,7 @@ #define LCD_CMD_RAMRD 0x2E // Read frame memory #define LCD_CMD_PTLAR 0x30 // Define the partial area #define LCD_CMD_VSCRDEF 0x33 // Vertical scrolling definition -#define LCD_CMD_TEOFF 0x34 // Turns of tearing effect +#define LCD_CMD_TEOFF 0x34 // Turns off tearing effect #define LCD_CMD_TEON 0x35 // Turns on tearing effect #define LCD_CMD_MADCTL 0x36 // Memory data access control @@ -48,7 +48,7 @@ #define LCD_CMD_COLMOD 0x3A // Defines the format of RGB picture data #define LCD_CMD_RAMWRC 0x3C // Memory write continue #define LCD_CMD_RAMRDC 0x3E // Memory read continue -#define LCD_CMD_STE 0x44 // Set tear scanline, tearing effect output signal when display module reaches line N -#define LCD_CMD_GDCAN 0x45 // Get scanline +#define LCD_CMD_STE 0x44 // Set tear scan line, tearing effect output signal when display module reaches line N +#define LCD_CMD_GDCAN 0x45 // Get scan line #define LCD_CMD_WRDISBV 0x51 // Write display brightness #define LCD_CMD_RDDISBV 0x52 // Read display brightness value diff --git a/tools/sdk/esp32s2/include/esp_lcd/include/esp_lcd_panel_io.h b/tools/sdk/esp32s2/include/esp_lcd/include/esp_lcd_panel_io.h index c01fe3e441f..de7b434b5f8 100644 --- a/tools/sdk/esp32s2/include/esp_lcd/include/esp_lcd_panel_io.h +++ b/tools/sdk/esp32s2/include/esp_lcd/include/esp_lcd_panel_io.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -71,7 +71,7 @@ esp_err_t esp_lcd_panel_io_rx_param(esp_lcd_panel_io_handle_t io, int lcd_cmd, v * this function will wait until they are finished and the queue is empty before sending the command(s). * * @param[in] io LCD panel IO handle, which is created by other factory API like `esp_lcd_new_panel_io_spi()` - * @param[in] lcd_cmd The specific LCD command (set to -1 if no command needed - only in SPI and I2C) + * @param[in] lcd_cmd The specific LCD command, set to -1 if no command needed * @param[in] param Buffer that holds the command specific parameters, set to NULL if no parameter is needed for the command * @param[in] param_size Size of `param` in memory, in bytes, set to zero if no parameter is needed for the command * @return diff --git a/tools/sdk/esp32s2/include/esp_mm/include/esp_cache.h b/tools/sdk/esp32s2/include/esp_mm/include/esp_cache.h index 800e8865695..af51a18ed72 100644 --- a/tools/sdk/esp32s2/include/esp_mm/include/esp_cache.h +++ b/tools/sdk/esp32s2/include/esp_mm/include/esp_cache.h @@ -41,9 +41,9 @@ extern "C" { * @note You should not call this during any Flash operations (e.g. esp_flash APIs, nvs and some other APIs that are based on esp_flash APIs) * @note If XIP_From_PSRAM is enabled (by enabling both CONFIG_SPIRAM_FETCH_INSTRUCTIONS and CONFIG_SPIRAM_RODATA), you can call this API during Flash operations * - * @param[in] Starting address to do the msync - * @param[in] Size to do the msync - * @param[in] Flags, see `ESP_CACHE_MSYNC_FLAG_x` + * @param[in] addr Starting address to do the msync + * @param[in] size Size to do the msync + * @param[in] flags Flags, see `ESP_CACHE_MSYNC_FLAG_x` * * @return * - ESP_OK: diff --git a/tools/sdk/esp32s2/include/esp_mm/include/esp_mmu_map.h b/tools/sdk/esp32s2/include/esp_mm/include/esp_mmu_map.h index 33d3396441d..355b0c97501 100644 --- a/tools/sdk/esp32s2/include/esp_mm/include/esp_mmu_map.h +++ b/tools/sdk/esp32s2/include/esp_mm/include/esp_mmu_map.h @@ -47,7 +47,7 @@ extern "C" { * - the to-be-mapped paddr block is overlapped with an already mapped paddr block. * - the to-be-mapped paddr block encloses an already mapped paddr block. * 2. If the to-be-mapped paddr block is enclosed by an already mapped paddr block, no new mapping will happen, return ESP_ERR_INVALID_STATE. The out pointer will be the already mapped paddr corresponding vaddr. - * 3. If the to-be-mapped paddr block is totally the same as an already mapped paddr block, no new mapping will happen, return ESP_ERR_INVALID_STATE. The out pointer will be the corresponding vaddr. + * 3. If the to-be-mapped paddr block is identical with an already mapped paddr block, no new mapping will happen, return ESP_ERR_INVALID_STATE. The out pointer will be the corresponding vaddr. * * - If this flag isn't set, overlapped, enclosed or same to-be-mapped paddr block will lead to ESP_ERR_INVALID_ARG. */ @@ -77,7 +77,7 @@ typedef uint32_t esp_paddr_t; * - ESP_ERR_NOT_FOUND: No enough size free block to use * - ESP_ERR_NO_MEM: Out of memory, this API will allocate some heap memory for internal usage * - ESP_ERR_INVALID_STATE: Paddr is mapped already, this API will return corresponding vaddr_start of the previously mapped block. - * Only to-be-mapped paddr block is totally enclosed by a previously mapped block will lead to this error: + * Only to-be-mapped paddr block is totally enclosed by a previously mapped block will lead to this error. (Identical scenario will behave similarly) * new_block_start new_block_end * |-------- New Block --------| * |--------------- Block ---------------| @@ -156,6 +156,20 @@ esp_err_t esp_mmu_vaddr_to_paddr(void *vaddr, esp_paddr_t *out_paddr, mmu_target */ esp_err_t esp_mmu_paddr_to_vaddr(esp_paddr_t paddr, mmu_target_t target, mmu_vaddr_t type, void **out_vaddr); +/** + * @brief If the physical address is mapped, this API will provide the capabilities of the virtual address where the physical address is mapped to. + * + * @note: Only return value is ESP_OK(which means physically address is successfully mapped), then caps you get make sense. + * @note This API only check one page (see CONFIG_MMU_PAGE_SIZE), starting from the `paddr` + * + * @param[in] paddr Physical address + * @param[out] out_caps Bitwise OR of MMU_MEM_CAP_* flags indicating the capabilities of a virtual address where the physical address is mapped to. + * @return + * - ESP_OK: Physical address successfully mapped. + * - ESP_ERR_INVALID_ARG: Null pointer + * - ESP_ERR_NOT_FOUND: Physical address is not mapped successfully. + */ +esp_err_t esp_mmu_paddr_find_caps(const esp_paddr_t paddr, mmu_mem_caps_t *out_caps); #ifdef __cplusplus } diff --git a/tools/sdk/esp32s2/include/esp_netif/include/esp_netif.h b/tools/sdk/esp32s2/include/esp_netif/include/esp_netif.h index 9372b6d1506..2510a1eefee 100644 --- a/tools/sdk/esp32s2/include/esp_netif/include/esp_netif.h +++ b/tools/sdk/esp32s2/include/esp_netif/include/esp_netif.h @@ -523,6 +523,34 @@ int esp_netif_get_netif_impl_index(esp_netif_t *esp_netif); */ esp_err_t esp_netif_get_netif_impl_name(esp_netif_t *esp_netif, char* name); +/** + * @brief Enable NAPT on an interface + * + * @note Enable operation can be performed only on one interface at a time. + * NAPT cannot be enabled on multiple interfaces according to this implementation. + * + * @param[in] esp_netif Handle to esp-netif instance + * + * @return + * - ESP_OK + * - ESP_FAIL + * - ESP_ERR_NOT_SUPPORTED +*/ + +esp_err_t esp_netif_napt_enable(esp_netif_t *esp_netif); + +/** + * @brief Disable NAPT on an interface. + * + * @param[in] esp_netif Handle to esp-netif instance + * + * @return + * - ESP_OK + * - ESP_FAIL + * - ESP_ERR_NOT_SUPPORTED +*/ +esp_err_t esp_netif_napt_disable(esp_netif_t *esp_netif); + /** * @} */ diff --git a/tools/sdk/esp32s2/include/esp_phy/include/esp_phy_init.h b/tools/sdk/esp32s2/include/esp_phy/include/esp_phy_init.h index 4f30c7795fc..4813e5bdee6 100644 --- a/tools/sdk/esp32s2/include/esp_phy/include/esp_phy_init.h +++ b/tools/sdk/esp32s2/include/esp_phy/include/esp_phy_init.h @@ -180,6 +180,15 @@ void esp_phy_disable(void); */ void esp_btbb_enable(void); +/** + * @brief Disable BTBB module + * + * Dsiable BTBB module, used by IEEE802154 or Bluetooth. + * Users should not call this API in their application. + * + */ +void esp_btbb_disable(void); + /** * @brief Load calibration data from NVS and initialize PHY and RF module */ diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32/rom/ets_sys.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32/rom/ets_sys.h index 6f9688fcf18..549db8ffc63 100644 --- a/tools/sdk/esp32s2/include/esp_rom/include/esp32/rom/ets_sys.h +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32/rom/ets_sys.h @@ -48,7 +48,10 @@ extern "C" { typedef enum { ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1 /**< return failed in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, } ETS_STATUS; typedef uint32_t ETSSignal; @@ -621,13 +624,16 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); #define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) typedef enum { OK = 0, FAIL, PENDING, BUSY, CANCEL, -} STATUS; +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif /** * @} diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32/rom/uart.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32/rom/uart.h index 3eb59f30f96..3bd0d38f484 100644 --- a/tools/sdk/esp32s2/include/esp_rom/include/esp32/rom/uart.h +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32/rom/uart.h @@ -227,7 +227,7 @@ void uart_buff_switch(uint8_t uart_no); * * @return OK. */ -STATUS uart_tx_one_char(uint8_t TxChar); +ETS_STATUS uart_tx_one_char(uint8_t TxChar); /** * @brief Output a char to message exchange channel, wait until fifo not full. @@ -237,7 +237,7 @@ STATUS uart_tx_one_char(uint8_t TxChar); * * @return OK. */ -STATUS uart_tx_one_char2(uint8_t TxChar); +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); /** * @brief Wait until uart tx full empty. @@ -273,7 +273,7 @@ static inline void IRAM_ATTR uart_tx_wait_idle(uint8_t uart_no) { * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_one_char(uint8_t *pRxChar); +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); /** * @brief Get an input char from message channel, wait until successful. @@ -295,7 +295,7 @@ char uart_rx_one_char_block(void); * * @return OK. */ -STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); /** * @brief Process uart received information in the interrupt handler. @@ -318,7 +318,7 @@ void uart_rx_intr_handler(void *para); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); /** * @brief Get all chars from receive buffer. @@ -329,7 +329,7 @@ STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); * @return OK for successful. * FAIL for failed. */ -STATUS UartGetCmdLn(uint8_t *pCmdLn); +ETS_STATUS UartGetCmdLn(uint8_t *pCmdLn); /** * @brief Get uart configuration struct. @@ -379,7 +379,7 @@ int recv_packet(uint8_t *p, int len, uint8_t is_sync); * @return OK for successful. * FAIL for failed. */ -STATUS SendMsg(uint8_t *pData, uint16_t DataLen); +ETS_STATUS SendMsg(uint8_t *pData, uint16_t DataLen); /** * @brief Receive an packet from download tool, with SLIP escaping. @@ -395,7 +395,7 @@ STATUS SendMsg(uint8_t *pData, uint16_t DataLen); * @return OK for successful. * FAIL for failed. */ -STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync); +ETS_STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync); extern UartDevice UartDev; diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32c2/rom/ets_sys.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32c2/rom/ets_sys.h index 6d2e3a4ef4e..ad642fcc460 100644 --- a/tools/sdk/esp32s2/include/esp_rom/include/esp32c2/rom/ets_sys.h +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32c2/rom/ets_sys.h @@ -43,7 +43,10 @@ extern "C" { typedef enum { ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1 /**< return failed in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, } ETS_STATUS; typedef ETS_STATUS ets_status_t; @@ -438,13 +441,16 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); #define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) typedef enum { OK = 0, FAIL, PENDING, BUSY, CANCEL, -} STATUS; +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif /** * @} diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32c2/rom/uart.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32c2/rom/uart.h index 8a4507e8108..454e0d83a11 100644 --- a/tools/sdk/esp32s2/include/esp_rom/include/esp32c2/rom/uart.h +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32c2/rom/uart.h @@ -205,7 +205,7 @@ void uart_tx_switch(uint8_t uart_no); * * @return OK. */ -STATUS uart_tx_one_char(uint8_t TxChar); +ETS_STATUS uart_tx_one_char(uint8_t TxChar); /** * @brief Output a char to message exchange channel, wait until fifo not full. @@ -215,7 +215,7 @@ STATUS uart_tx_one_char(uint8_t TxChar); * * @return OK. */ -STATUS uart_tx_one_char2(uint8_t TxChar); +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); /** * @brief Wait until uart tx full empty. @@ -245,7 +245,7 @@ void uart_tx_wait_idle(uint8_t uart_no); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_one_char(uint8_t *pRxChar); +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); /** * @brief Get an input char from message channel, wait until successful. @@ -267,7 +267,7 @@ char uart_rx_one_char_block(void); * * @return OK. */ -STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); /** * @brief Get an char from receive buffer. @@ -280,7 +280,7 @@ STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); /** * @brief Get all chars from receive buffer. @@ -291,7 +291,7 @@ STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); * @return OK for successful. * FAIL for failed. */ -STATUS UartGetCmdLn(uint8_t *pCmdLn); +ETS_STATUS UartGetCmdLn(uint8_t *pCmdLn); /** * @brief Get uart configuration struct. diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32c3/rom/ets_sys.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32c3/rom/ets_sys.h index d5489bd835d..06b3b47d8c2 100644 --- a/tools/sdk/esp32s2/include/esp_rom/include/esp32c3/rom/ets_sys.h +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32c3/rom/ets_sys.h @@ -43,7 +43,10 @@ extern "C" { typedef enum { ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1 /**< return failed in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, } ETS_STATUS; typedef ETS_STATUS ets_status_t; @@ -430,13 +433,16 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); #define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) typedef enum { OK = 0, FAIL, PENDING, BUSY, CANCEL, -} STATUS; +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif /** * @} diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32c3/rom/uart.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32c3/rom/uart.h index 0cd91b06d57..a4fbd52077f 100644 --- a/tools/sdk/esp32s2/include/esp_rom/include/esp32c3/rom/uart.h +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32c3/rom/uart.h @@ -195,7 +195,7 @@ void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue); * * @return OK. */ -STATUS uart_tx_one_char(uint8_t TxChar); +ETS_STATUS uart_tx_one_char(uint8_t TxChar); /** * @brief Output a char to message exchange channel, wait until fifo not full. @@ -205,7 +205,7 @@ STATUS uart_tx_one_char(uint8_t TxChar); * * @return OK. */ -STATUS uart_tx_one_char2(uint8_t TxChar); +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); /** * @brief Wait until uart tx full empty. @@ -235,7 +235,7 @@ void uart_tx_wait_idle(uint8_t uart_no); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_one_char(uint8_t *pRxChar); +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); /** * @brief Get an input char from message channel, wait until successful. @@ -257,7 +257,7 @@ char uart_rx_one_char_block(void); * * @return OK. */ -STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); /** * @brief Get an char from receive buffer. @@ -270,7 +270,7 @@ STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); /** * @brief Get uart configuration struct. diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32c6/rom/ets_sys.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32c6/rom/ets_sys.h index 48a724d54b8..7c04af3a54c 100644 --- a/tools/sdk/esp32s2/include/esp_rom/include/esp32c6/rom/ets_sys.h +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32c6/rom/ets_sys.h @@ -43,7 +43,10 @@ extern "C" { typedef enum { ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1 /**< return failed in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, } ETS_STATUS; typedef ETS_STATUS ets_status_t; @@ -407,13 +410,16 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); #define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) typedef enum { OK = 0, FAIL, PENDING, BUSY, CANCEL, -} STATUS; +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif /** * @} diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32c6/rom/uart.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32c6/rom/uart.h index 380f19a4e56..9045c42f6f6 100644 --- a/tools/sdk/esp32s2/include/esp_rom/include/esp32c6/rom/uart.h +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32c6/rom/uart.h @@ -205,7 +205,7 @@ void uart_tx_switch(uint8_t uart_no); * * @return OK. */ -STATUS uart_tx_one_char(uint8_t TxChar); +ETS_STATUS uart_tx_one_char(uint8_t TxChar); /** * @brief Output a char to message exchange channel, wait until fifo not full. @@ -215,7 +215,7 @@ STATUS uart_tx_one_char(uint8_t TxChar); * * @return OK. */ -STATUS uart_tx_one_char2(uint8_t TxChar); +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); /** * @brief Wait until uart tx full empty. @@ -245,7 +245,7 @@ void uart_tx_wait_idle(uint8_t uart_no); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_one_char(uint8_t *pRxChar); +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); /** * @brief Get an input char from message channel, wait until successful. @@ -267,7 +267,7 @@ char uart_rx_one_char_block(void); * * @return OK. */ -STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); /** * @brief Process uart recevied information in the interrupt handler. @@ -290,7 +290,7 @@ void uart_rx_intr_handler(void *para); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); /** * @brief Get all chars from receive buffer. @@ -301,7 +301,7 @@ STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); * @return OK for successful. * FAIL for failed. */ -STATUS UartGetCmdLn(uint8_t *pCmdLn); +ETS_STATUS UartGetCmdLn(uint8_t *pCmdLn); /** * @brief Get uart configuration struct. diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32h2/rom/efuse.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32h2/rom/efuse.h index 6cd9f4b377e..dc612dff4b8 100644 --- a/tools/sdk/esp32s2/include/esp_rom/include/esp32h2/rom/efuse.h +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32h2/rom/efuse.h @@ -27,7 +27,8 @@ extern "C" { typedef enum { ETS_EFUSE_KEY_PURPOSE_USER = 0, - ETS_EFUSE_KEY_PURPOSE_RESERVED = 1, + ETS_EFUSE_KEY_PURPOSE_ECDSA_KEY = 1, + ETS_EFUSE_KEY_PURPOSE_RESERVED = 2, ETS_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32h2/rom/ets_sys.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32h2/rom/ets_sys.h index b9ac5a13f41..b9247bc3bdf 100644 --- a/tools/sdk/esp32s2/include/esp_rom/include/esp32h2/rom/ets_sys.h +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32h2/rom/ets_sys.h @@ -43,7 +43,10 @@ extern "C" { typedef enum { ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1 /**< return failed in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, } ETS_STATUS; typedef ETS_STATUS ets_status_t; @@ -406,13 +409,16 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); #define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) typedef enum { OK = 0, FAIL, PENDING, BUSY, CANCEL, -} STATUS; +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif /** * @} diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32h2/rom/uart.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32h2/rom/uart.h index 380f19a4e56..9045c42f6f6 100644 --- a/tools/sdk/esp32s2/include/esp_rom/include/esp32h2/rom/uart.h +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32h2/rom/uart.h @@ -205,7 +205,7 @@ void uart_tx_switch(uint8_t uart_no); * * @return OK. */ -STATUS uart_tx_one_char(uint8_t TxChar); +ETS_STATUS uart_tx_one_char(uint8_t TxChar); /** * @brief Output a char to message exchange channel, wait until fifo not full. @@ -215,7 +215,7 @@ STATUS uart_tx_one_char(uint8_t TxChar); * * @return OK. */ -STATUS uart_tx_one_char2(uint8_t TxChar); +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); /** * @brief Wait until uart tx full empty. @@ -245,7 +245,7 @@ void uart_tx_wait_idle(uint8_t uart_no); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_one_char(uint8_t *pRxChar); +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); /** * @brief Get an input char from message channel, wait until successful. @@ -267,7 +267,7 @@ char uart_rx_one_char_block(void); * * @return OK. */ -STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); /** * @brief Process uart recevied information in the interrupt handler. @@ -290,7 +290,7 @@ void uart_rx_intr_handler(void *para); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); /** * @brief Get all chars from receive buffer. @@ -301,7 +301,7 @@ STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); * @return OK for successful. * FAIL for failed. */ -STATUS UartGetCmdLn(uint8_t *pCmdLn); +ETS_STATUS UartGetCmdLn(uint8_t *pCmdLn); /** * @brief Get uart configuration struct. diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32h4/rom/ets_sys.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32h4/rom/ets_sys.h index 902127abfbb..91544de628a 100644 --- a/tools/sdk/esp32s2/include/esp_rom/include/esp32h4/rom/ets_sys.h +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32h4/rom/ets_sys.h @@ -43,7 +43,10 @@ extern "C" { typedef enum { ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1 /**< return failed in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, } ETS_STATUS; typedef ETS_STATUS ets_status_t; @@ -441,13 +444,16 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); #define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) typedef enum { OK = 0, FAIL, PENDING, BUSY, CANCEL, -} STATUS; +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif /** * @} diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32h4/rom/uart.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32h4/rom/uart.h index d271893d761..28677ac4097 100644 --- a/tools/sdk/esp32s2/include/esp_rom/include/esp32h4/rom/uart.h +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32h4/rom/uart.h @@ -205,7 +205,7 @@ void uart_tx_switch(uint8_t uart_no); * * @return OK. */ -STATUS uart_tx_one_char(uint8_t TxChar); +ETS_STATUS uart_tx_one_char(uint8_t TxChar); /** * @brief Output a char to message exchange channel, wait until fifo not full. @@ -215,7 +215,7 @@ STATUS uart_tx_one_char(uint8_t TxChar); * * @return OK. */ -STATUS uart_tx_one_char2(uint8_t TxChar); +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); /** * @brief Wait until uart tx full empty. @@ -245,7 +245,7 @@ void uart_tx_wait_idle(uint8_t uart_no); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_one_char(uint8_t *pRxChar); +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); /** * @brief Get an input char from message channel, wait until successful. @@ -267,7 +267,7 @@ char uart_rx_one_char_block(void); * * @return OK. */ -STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); /** * @brief Get an char from receive buffer. @@ -280,7 +280,7 @@ STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); /** * @brief Get all chars from receive buffer. @@ -291,7 +291,7 @@ STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); * @return OK for successful. * FAIL for failed. */ -STATUS UartGetCmdLn(uint8_t *pCmdLn); +ETS_STATUS UartGetCmdLn(uint8_t *pCmdLn); /** * @brief Get uart configuration struct. diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/ets_sys.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/ets_sys.h index a2cf1adce34..19c1994de71 100644 --- a/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/ets_sys.h +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/ets_sys.h @@ -45,7 +45,10 @@ extern "C" { typedef enum { ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1 /**< return failed in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, } ETS_STATUS; typedef ETS_STATUS ets_status_t; @@ -556,13 +559,16 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); #define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) typedef enum { OK = 0, FAIL, PENDING, BUSY, CANCEL, -} STATUS; +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif /** * @} diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/uart.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/uart.h index 899413f3171..491d2c28fbe 100644 --- a/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/uart.h +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/uart.h @@ -1,16 +1,8 @@ -// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _ROM_UART_H_ #define _ROM_UART_H_ @@ -251,7 +243,7 @@ void uart_buff_switch(uint8_t uart_no); * * @return OK. */ -STATUS uart_tx_one_char(uint8_t TxChar); +ETS_STATUS uart_tx_one_char(uint8_t TxChar); /** * @brief Output a char to message exchange channel, wait until fifo not full. @@ -261,7 +253,7 @@ STATUS uart_tx_one_char(uint8_t TxChar); * * @return OK. */ -STATUS uart_tx_one_char2(uint8_t TxChar); +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); /** * @brief Wait until uart tx full empty. @@ -291,7 +283,7 @@ void uart_tx_wait_idle(uint8_t uart_no); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_one_char(uint8_t *pRxChar); +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); /** * @brief Get an input char from message channel, wait until successful. @@ -313,7 +305,7 @@ char uart_rx_one_char_block(void); * * @return OK. */ -STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); /** * @brief Process uart recevied information in the interrupt handler. @@ -336,7 +328,7 @@ void uart_rx_intr_handler(void *para); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); /** * @brief Get all chars from receive buffer. @@ -347,7 +339,7 @@ STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); * @return OK for successful. * FAIL for failed. */ -STATUS UartGetCmdLn(uint8_t *pCmdLn); +ETS_STATUS UartGetCmdLn(uint8_t *pCmdLn); /** * @brief Get uart configuration struct. @@ -397,7 +389,7 @@ int recv_packet(uint8_t *p, int len, uint8_t is_sync); * @return OK for successful. * FAIL for failed. */ -STATUS SendMsg(uint8_t *pData, uint16_t DataLen); +ETS_STATUS SendMsg(uint8_t *pData, uint16_t DataLen); /** * @brief Receive an packet from download tool, with SLIP escaping. @@ -413,7 +405,7 @@ STATUS SendMsg(uint8_t *pData, uint16_t DataLen); * @return OK for successful. * FAIL for failed. */ -STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync); +ETS_STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync); /** * @brief Check if this UART is in download connection. diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/ets_sys.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/ets_sys.h index 9047442c36e..83c93b2eb6a 100644 --- a/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/ets_sys.h +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/ets_sys.h @@ -43,7 +43,10 @@ extern "C" { typedef enum { ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1 /**< return failed in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, } ETS_STATUS; typedef ETS_STATUS ets_status_t; @@ -543,13 +546,16 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); #define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) typedef enum { OK = 0, FAIL, PENDING, BUSY, CANCEL, -} STATUS; +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif /** * @} diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/uart.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/uart.h index 3486886ad54..864563f7883 100644 --- a/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/uart.h +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/uart.h @@ -203,7 +203,7 @@ void uart_tx_switch(uint8_t uart_no); * * @return OK. */ -STATUS uart_tx_one_char(uint8_t TxChar); +ETS_STATUS uart_tx_one_char(uint8_t TxChar); /** * @brief Output a char to message exchange channel, wait until fifo not full. @@ -213,7 +213,7 @@ STATUS uart_tx_one_char(uint8_t TxChar); * * @return OK. */ -STATUS uart_tx_one_char2(uint8_t TxChar); +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); /** * @brief Wait until uart tx full empty. @@ -243,7 +243,7 @@ void uart_tx_wait_idle(uint8_t uart_no); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_one_char(uint8_t *pRxChar); +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); /** * @brief Get an input char from message channel, wait until successful. @@ -265,7 +265,7 @@ char uart_rx_one_char_block(void); * * @return OK. */ -STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); /** * @brief Get an char from receive buffer. @@ -278,7 +278,7 @@ STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); /** * @brief Get uart configuration struct. diff --git a/tools/sdk/esp32s2/include/esp_wifi/include/esp_mesh.h b/tools/sdk/esp32s2/include/esp_wifi/include/esp_mesh.h index 78f65945051..5ba707b527e 100644 --- a/tools/sdk/esp32s2/include/esp_wifi/include/esp_mesh.h +++ b/tools/sdk/esp32s2/include/esp_wifi/include/esp_mesh.h @@ -174,7 +174,8 @@ typedef enum { MESH_EVENT_PARENT_DISCONNECTED, /**< parent is disconnected on station interface */ MESH_EVENT_NO_PARENT_FOUND, /**< no parent found */ MESH_EVENT_LAYER_CHANGE, /**< layer changes over the mesh network */ - MESH_EVENT_TODS_STATE, /**< state represents whether the root is able to access external IP network */ + MESH_EVENT_TODS_STATE, /**< state represents whether the root is able to access external IP network. + This state is a manual event that needs to be triggered with esp_mesh_post_toDS_state(). */ MESH_EVENT_VOTE_STARTED, /**< the process of voting a new root is started either by children or by the root */ MESH_EVENT_VOTE_STOPPED, /**< the process of voting a new root is stopped */ MESH_EVENT_ROOT_ADDRESS, /**< the root address is obtained. It is posted by mesh stack automatically. */ @@ -1175,7 +1176,10 @@ esp_err_t esp_mesh_get_rx_pending(mesh_rx_pending_t *pending); int esp_mesh_available_txupQ_num(const mesh_addr_t *addr, uint32_t *xseqno_in); /** - * @brief Set the number of queue + * @brief Set the number of RX queue for the node, the average number of window allocated to one of + * its child node is: wnd = xon_qsize / (2 * max_connection + 1). + * However, the window of each child node is not strictly equal to the average value, + * it is affected by the traffic also. * * @attention This API shall be called before mesh is started. * diff --git a/tools/sdk/esp32s2/include/esp_wifi/include/esp_wifi.h b/tools/sdk/esp32s2/include/esp_wifi/include/esp_wifi.h index 863ebb7d702..3c0ade914b1 100644 --- a/tools/sdk/esp32s2/include/esp_wifi/include/esp_wifi.h +++ b/tools/sdk/esp32s2/include/esp_wifi/include/esp_wifi.h @@ -660,10 +660,10 @@ esp_err_t esp_wifi_get_country(wifi_country_t *country); /** - * @brief Set MAC address of WiFi station or the soft-AP interface. + * @brief Set MAC address of WiFi station, soft-AP or NAN interface. * * @attention 1. This API can only be called when the interface is disabled - * @attention 2. Soft-AP and station have different MAC addresses, do not set them to be the same. + * @attention 2. Above mentioned interfaces have different MAC addresses, do not set them to be the same. * @attention 3. The bit 0 of the first byte of MAC address can not be 1. For example, the MAC address * can set to be "1a:XX:XX:XX:XX:XX", but can not be "15:XX:XX:XX:XX:XX". * @@ -1151,6 +1151,7 @@ esp_err_t esp_wifi_set_inactive_time(wifi_interface_t ifx, uint16_t sec); * @return * - ESP_OK: succeed * - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init + * - ESP_ERR_WIFI_NOT_STARTED: WiFi is not started by esp_wifi_start * - ESP_ERR_WIFI_ARG: invalid argument */ esp_err_t esp_wifi_get_inactive_time(wifi_interface_t ifx, uint16_t *sec); @@ -1348,6 +1349,19 @@ esp_err_t esp_wifi_sta_get_aid(uint16_t *aid); */ esp_err_t esp_wifi_sta_get_negotiated_phymode(wifi_phy_mode_t *phymode); +/** + * @brief Config dynamic carrier sense + * + * @attention This API should be called after esp_wifi_start(). + * + * @param enabled Dynamic carrier sense is enabled or not. + * + * @return + * - ESP_OK: succeed + * - others: failed + */ +esp_err_t esp_wifi_set_dynamic_cs(bool enabled); + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32s2/include/esp_wifi/include/esp_wifi_types.h b/tools/sdk/esp32s2/include/esp_wifi/include/esp_wifi_types.h index ac12c34b497..614bcd2cb5b 100644 --- a/tools/sdk/esp32s2/include/esp_wifi/include/esp_wifi_types.h +++ b/tools/sdk/esp32s2/include/esp_wifi/include/esp_wifi_types.h @@ -129,6 +129,7 @@ typedef enum { WIFI_REASON_AP_TSF_RESET = 206, WIFI_REASON_ROAMING = 207, WIFI_REASON_ASSOC_COMEBACK_TIME_TOO_LONG = 208, + WIFI_REASON_SA_QUERY_TIMEOUT = 209, } wifi_err_reason_t; typedef enum { diff --git a/tools/sdk/esp32s2/include/esp_wifi/wifi_apps/include/esp_nan.h b/tools/sdk/esp32s2/include/esp_wifi/wifi_apps/include/esp_nan.h index 0fba2bf5f57..9be6bbb6659 100644 --- a/tools/sdk/esp32s2/include/esp_wifi/wifi_apps/include/esp_nan.h +++ b/tools/sdk/esp32s2/include/esp_wifi/wifi_apps/include/esp_nan.h @@ -120,8 +120,8 @@ esp_err_t esp_wifi_nan_cancel_service(uint8_t service_id); * @param req NAN Datapath Request parameters. * * @return - * - non-zero: NAN Datapath Identifier - * - zero: failed + * - non-zero NAN Datapath identifier: If NAN datapath req was accepted by publisher + * - zero: If NAN datapath req was rejected by publisher or a timeout occurs */ uint8_t esp_wifi_nan_datapath_req(wifi_nan_datapath_req_t *req); diff --git a/tools/sdk/esp32s2/include/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/portmacro.h b/tools/sdk/esp32s2/include/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/portmacro.h index a1adffbd4f3..660c48a950e 100644 --- a/tools/sdk/esp32s2/include/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/portmacro.h +++ b/tools/sdk/esp32s2/include/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/portmacro.h @@ -523,6 +523,14 @@ extern void _frxt_setup_switch( void ); //Defined in portasm.S #define portALT_GET_RUN_TIME_COUNTER_VALUE(x) do {x = (uint32_t)esp_timer_get_time();} while(0) #endif +// --------------------- TCB Cleanup ----------------------- + +#if CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP +/* If enabled, users must provide an implementation of vPortCleanUpTCB() */ +extern void vPortCleanUpTCB ( void *pxTCB ); +#define portCLEAN_UP_TCB( pxTCB ) vPortCleanUpTCB( pxTCB ) +#endif /* CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP */ + // -------------- Optimized Task Selection ----------------- #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 @@ -627,7 +635,7 @@ FORCE_INLINE_ATTR BaseType_t xPortGetCoreID(void) /* ------------------------------------------------------ Misc --------------------------------------------------------- * - Miscellaneous porting macros - * - These are not port of the FreeRTOS porting interface, but are used by other FreeRTOS dependent components + * - These are not part of the FreeRTOS porting interface, but are used by other FreeRTOS dependent components * ------------------------------------------------------------------------------------------------------------------ */ // -------------------- Co-Processor ----------------------- diff --git a/tools/sdk/esp32s2/include/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/FreeRTOSConfig_arch.h b/tools/sdk/esp32s2/include/freertos/esp_additions/arch/xtensa/include/freertos/FreeRTOSConfig_arch.h similarity index 50% rename from tools/sdk/esp32s2/include/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/FreeRTOSConfig_arch.h rename to tools/sdk/esp32s2/include/freertos/esp_additions/arch/xtensa/include/freertos/FreeRTOSConfig_arch.h index cb0c78ec1f8..a7ed6d5e4a3 100644 --- a/tools/sdk/esp32s2/include/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/FreeRTOSConfig_arch.h +++ b/tools/sdk/esp32s2/include/freertos/esp_additions/arch/xtensa/include/freertos/FreeRTOSConfig_arch.h @@ -1,18 +1,17 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef FREERTOS_CONFIG_XTENSA_H -#define FREERTOS_CONFIG_XTENSA_H +#pragma once -//Xtensa Archiecture specific configuration. This file is included in the common FreeRTOSConfig.h. +/* Xtensa Architecture specific configuration. This file is included in the common FreeRTOSConfig.h. */ #include "sdkconfig.h" /* Required for configuration-dependent settings. */ -#include "xtensa_config.h" +#include "freertos/xtensa_config.h" /* -------------------------------------------- Xtensa Additional Config ---------------------------------------------- * - Provide Xtensa definitions usually given by -D option when building with xt-make (see readme_xtensa.txt) @@ -27,29 +26,55 @@ * - XT_USE_SWPRI We don't define this (unused) * ------------------------------------------------------------------------------------------------------------------ */ -#define configXT_SIMULATOR 0 -#define configXT_BOARD 1 /* Board mode */ +#define configXT_SIMULATOR 0 +#define configXT_BOARD 1 /* Board mode */ #if CONFIG_FREERTOS_CORETIMER_0 -#define configXT_TIMER_INDEX 0 + #define configXT_TIMER_INDEX 0 #elif CONFIG_FREERTOS_CORETIMER_1 -#define configXT_TIMER_INDEX 1 + #define configXT_TIMER_INDEX 1 #endif -#define configXT_INTEXC_HOOKS 0 +#define configXT_INTEXC_HOOKS 0 -#define configBENCHMARK 0 +#define configBENCHMARK 0 /* ------------------------------------------------- FreeRTOS Config --------------------------------------------------- * - All Vanilla FreeRTOS configuration goes into this section * ------------------------------------------------------------------------------------------------------------------ */ -// ------------------ Scheduler Related -------------------- +/* ------------------ Scheduler Related -------------------- */ +#define configMAX_PRIORITIES ( 25 ) #ifdef CONFIG_FREERTOS_OPTIMIZED_SCHEDULER -#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #else -#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 -#endif -#define configMAX_API_CALL_INTERRUPT_PRIORITY XCHAL_EXCM_LEVEL + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#endif /* CONFIG_FREERTOS_OPTIMIZED_SCHEDULER */ +#define configMINIMAL_STACK_SIZE ( CONFIG_FREERTOS_IDLE_TASK_STACKSIZE + configSTACK_OVERHEAD_TOTAL ) +#define configMAX_API_CALL_INTERRUPT_PRIORITY XCHAL_EXCM_LEVEL + +/* ----------------------- System -------------------------- */ + +#define configUSE_NEWLIB_REENTRANT 1 +#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1 + +/* ----------------------- Memory ------------------------- */ + +/* This isn't used as FreeRTOS will only allocate from internal memory (see + * heap_idf.c). We simply define this macro to span all non-statically-allocated + * shared RAM. */ +#define configTOTAL_HEAP_SIZE ( &_heap_end - &_heap_start ) + +/* ------------------- Run-time Stats ---------------------- */ + +#if CONFIG_FREERTOS_USE_TRACE_FACILITY + /* Used by uxTaskGetSystemState(), and other trace facility functions */ + #define configUSE_TRACE_FACILITY 1 +#endif /* CONFIG_FREERTOS_USE_TRACE_FACILITY */ + +/* -------------------- API Includes ----------------------- */ + +#define INCLUDE_xTaskDelayUntil 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 /* ------------------------------------------------ ESP-IDF Additions -------------------------------------------------- * @@ -60,9 +85,7 @@ * Size needs to be aligned to the stack increment, since the location of * the stack for the 2nd CPU will be calculated using configISR_STACK_SIZE. */ -#define configSTACK_ALIGNMENT 16 +#define configSTACK_ALIGNMENT 16 #ifndef configISR_STACK_SIZE -#define configISR_STACK_SIZE ((CONFIG_FREERTOS_ISR_STACKSIZE + configSTACK_ALIGNMENT - 1) & (~(configSTACK_ALIGNMENT - 1))) + #define configISR_STACK_SIZE ( ( CONFIG_FREERTOS_ISR_STACKSIZE + configSTACK_ALIGNMENT - 1 ) & ( ~( configSTACK_ALIGNMENT - 1 ) ) ) #endif - -#endif // FREERTOS_CONFIG_XTENSA_H diff --git a/tools/sdk/esp32s2/include/freertos/esp_additions/include/esp_private/freertos_idf_additions_priv.h b/tools/sdk/esp32s2/include/freertos/esp_additions/include/esp_private/freertos_idf_additions_priv.h new file mode 100644 index 00000000000..c6e6ba81c08 --- /dev/null +++ b/tools/sdk/esp32s2/include/freertos/esp_additions/include/esp_private/freertos_idf_additions_priv.h @@ -0,0 +1,99 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/* + * This file is like "idf_additions.h" but for private API (i.e., only meant to + * be called by other internally by other + * ESP-IDF components. + */ + +#include "sdkconfig.h" +#include "freertos/FreeRTOS.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/* ----------------------------------------------------------------------------- + * Priority Raise/Restore + * - Special functions to forcefully raise and restore a task's priority + * - Used by cache_utils.c when disabling/enabling the cache + * -------------------------------------------------------------------------- */ + +#if ( INCLUDE_vTaskPrioritySet == 1 ) + + typedef struct + { + UBaseType_t uxPriority; + #if ( configUSE_MUTEXES == 1 ) + UBaseType_t uxBasePriority; + #endif + } prvTaskSavedPriority_t; + +/** + * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be + * available. See the configuration section for more information. + * + * Saves the current priority and current base priority of a task, then + * raises the task's current and base priority to uxNewPriority if + * uxNewPriority is of a higher priority. + * + * Once a task's priority has been raised with this function, the priority + * can be restored by calling prvTaskPriorityRestore() + * + * - Note that this function differs from vTaskPrioritySet() as the task's + * current priority will be modified even if the task has already + * inherited a priority. + * - This function is intended for special circumstance where a task must be + * forced immediately to a higher priority. + * + * For configUSE_MUTEXES == 0: A context switch will occur before the + * function returns if the priority being set is higher than the currently + * executing task. + * + * @note This functions is private and should only be called internally + * within various IDF components. Users should never call this function from + * their application. + * + * @note vTaskPrioritySet() should not be called while a task's priority is + * already raised via this function + * + * @param pxSavedPriority returns base and current priorities + * + * @param uxNewPriority The priority to which the task's priority will be + * set. + */ + void prvTaskPriorityRaise( prvTaskSavedPriority_t * pxSavedPriority, + UBaseType_t uxNewPriority ); + +/** + * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be + * available. + * See the configuration section for more information. + * + * Restore a task's priority that was previously raised by + * prvTaskPriorityRaise(). + * + * For configUSE_MUTEXES == 0: A context switch will occur before the function + * returns if the priority + * being set is higher than the currently executing task. + * + * @note This functions is private and should only be called internally within + * various IDF components. Users should never call this function from their + * application. + * + * @param pxSavedPriority previously saved base and current priorities that need + * to be restored + */ + void prvTaskPriorityRestore( prvTaskSavedPriority_t * pxSavedPriority ); + +#endif // ( INCLUDE_vTaskPrioritySet == 1) + +#ifdef __cplusplus + } +#endif diff --git a/tools/sdk/esp32s2/include/freertos/esp_additions/include/freertos/FreeRTOSConfig.h b/tools/sdk/esp32s2/include/freertos/esp_additions/include/freertos/FreeRTOSConfig.h index 182ca817180..3a3c10ea253 100644 --- a/tools/sdk/esp32s2/include/freertos/esp_additions/include/freertos/FreeRTOSConfig.h +++ b/tools/sdk/esp32s2/include/freertos/esp_additions/include/freertos/FreeRTOSConfig.h @@ -1,293 +1,285 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H +#pragma once #include "sdkconfig.h" -/* -This file gets pulled into assembly sources. Therefore, some includes need to be wrapped in #ifndef __ASSEMBLER__ -*/ +/* This file gets pulled into assembly sources. Therefore, some includes need to + * be wrapped in #ifndef __ASSEMBLER__ */ #ifndef __ASSEMBLER__ -#include //For configASSERT() + /* For configASSERT() */ + #include #endif /* def __ASSEMBLER__ */ -#ifdef CONFIG_FREERTOS_SMP - -// Pull in the SMP configuration -#include "freertos/FreeRTOSConfig_smp.h" - -#else // CONFIG_FREERTOS_SMP - -// The arch-specific FreeRTOSConfig_arch.h in port//include. -#include "freertos/FreeRTOSConfig_arch.h" - -#if !(defined(FREERTOS_CONFIG_XTENSA_H) \ - || defined(FREERTOS_CONFIG_RISCV_H) \ - || defined(FREERTOS_CONFIG_LINUX_H)) -#error "Needs architecture-speific FreeRTOSConfig.h!" -#endif - /* ----------------------------------------------------- Helpers ------------------------------------------------------- * - Macros that the FreeRTOS configuration macros depend on * ------------------------------------------------------------------------------------------------------------------ */ /* Higher stack checker modes cause overhead on each function call */ #if CONFIG_STACK_CHECK_ALL || CONFIG_STACK_CHECK_STRONG -#define STACK_OVERHEAD_CHECKER 256 + #define STACK_OVERHEAD_CHECKER 256 #else -#define STACK_OVERHEAD_CHECKER 0 + #define STACK_OVERHEAD_CHECKER 0 #endif /* with optimizations disabled, scheduler uses additional stack */ #if CONFIG_COMPILER_OPTIMIZATION_NONE -#define STACK_OVERHEAD_OPTIMIZATION 320 + #define STACK_OVERHEAD_OPTIMIZATION 320 #else -#define STACK_OVERHEAD_OPTIMIZATION 0 + #define STACK_OVERHEAD_OPTIMIZATION 0 #endif /* apptrace mdule increases minimum stack usage */ #if CONFIG_APPTRACE_ENABLE -#define STACK_OVERHEAD_APPTRACE 1280 + #define STACK_OVERHEAD_APPTRACE 1280 #else -#define STACK_OVERHEAD_APPTRACE 0 + #define STACK_OVERHEAD_APPTRACE 0 #endif /* Stack watchpoint decreases minimum usable stack size by up to 60 bytes. - See FreeRTOS FREERTOS_WATCHPOINT_END_OF_STACK option in Kconfig. */ + * See FreeRTOS FREERTOS_WATCHPOINT_END_OF_STACK option in Kconfig. */ #if CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK -#define STACK_OVERHEAD_WATCHPOINT 60 + #define STACK_OVERHEAD_WATCHPOINT 60 #else -#define STACK_OVERHEAD_WATCHPOINT 0 + #define STACK_OVERHEAD_WATCHPOINT 0 #endif -#define configSTACK_OVERHEAD_TOTAL ( \ - STACK_OVERHEAD_CHECKER + \ - STACK_OVERHEAD_OPTIMIZATION + \ - STACK_OVERHEAD_APPTRACE + \ - STACK_OVERHEAD_WATCHPOINT \ - ) +#define configSTACK_OVERHEAD_TOTAL \ + ( \ + STACK_OVERHEAD_CHECKER + \ + STACK_OVERHEAD_OPTIMIZATION + \ + STACK_OVERHEAD_APPTRACE + \ + STACK_OVERHEAD_WATCHPOINT \ + ) + +/* The arch-specific FreeRTOSConfig_arch.h in esp_additions/arch_include/. + * Placed here due to configSTACK_OVERHEAD_TOTAL. Todo: IDF-5712. */ +#include "freertos/FreeRTOSConfig_arch.h" /* ------------------------------------------------- FreeRTOS Config --------------------------------------------------- * - All Vanilla FreeRTOS configuration goes into this section * - Keep this section in-sync with the corresponding version of single-core upstream version of FreeRTOS - * - Don't put any SMP or ESP-IDF exclusive FreeRTOS configurations here. Those go into the next section + * - Don't put any Amazon SMP FreeRTOS or IDF FreeRTOS configurations here. Those go into the next section * - Not all FreeRTOS configuration are listed. Some configurations have default values set in FreeRTOS.h thus don't * need to be explicitly defined. * ------------------------------------------------------------------------------------------------------------------ */ /*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - * - * See http://www.freertos.org/a00110.html - *----------------------------------------------------------*/ - -// ------------------ Scheduler Related -------------------- - -#define configUSE_PREEMPTION 1 -#define configUSE_TICKLESS_IDLE CONFIG_FREERTOS_USE_TICKLESS_IDLE +* Application specific definitions. +* +* These definitions should be adjusted for your particular hardware and +* application requirements. +* +* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE +* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. +* +* See http://www.freertos.org/a00110.html +*----------------------------------------------------------*/ + +/* ------------------ Scheduler Related -------------------- */ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE CONFIG_FREERTOS_USE_TICKLESS_IDLE #if configUSE_TICKLESS_IDLE -#define configEXPECTED_IDLE_TIME_BEFORE_SLEEP CONFIG_FREERTOS_IDLE_TIME_BEFORE_SLEEP -#endif //configUSE_TICKLESS_IDLE -#define configCPU_CLOCK_HZ (CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ * 1000000) -#define configTICK_RATE_HZ CONFIG_FREERTOS_HZ -#ifdef CONFIG_IDF_TARGET_LINUX -#define configMAX_PRIORITIES ( 7 ) // Default in upstream simulator -/* The stack allocated by FreeRTOS will be passed to a pthread. - pthread has a minimal stack size which currently is 16KB. - The rest is for additional structures of the POSIX/Linux port. - This is a magic number since PTHREAD_STACK_MIN seems to not be a constant. */ -#define configMINIMAL_STACK_SIZE ( ( unsigned short ) (0x4000 + 40) / sizeof(portSTACK_TYPE) ) -#else -#define configMAX_PRIORITIES ( 25 ) //This has impact on speed of search for highest priority -#define configMINIMAL_STACK_SIZE ( CONFIG_FREERTOS_IDLE_TASK_STACKSIZE + configSTACK_OVERHEAD_TOTAL ) -#endif -#define configUSE_TIME_SLICING 1 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 0 -#define configKERNEL_INTERRUPT_PRIORITY 1 //Todo: This currently isn't used anywhere - -// ------------- Synchronization Primitives ---------------- - -#define configUSE_MUTEXES 1 -#define configUSE_RECURSIVE_MUTEXES 1 -#define configUSE_COUNTING_SEMAPHORES 1 -#define configUSE_QUEUE_SETS 1 -#define configQUEUE_REGISTRY_SIZE CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE -#define configUSE_TASK_NOTIFICATIONS 1 -#define configTASK_NOTIFICATION_ARRAY_ENTRIES CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES - -// ----------------------- System -------------------------- - -#define configMAX_TASK_NAME_LEN CONFIG_FREERTOS_MAX_TASK_NAME_LEN -#define configNUM_THREAD_LOCAL_STORAGE_POINTERS CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS -#define configSTACK_DEPTH_TYPE uint32_t -#ifndef CONFIG_IDF_TARGET_LINUX -#define configUSE_NEWLIB_REENTRANT 1 -#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1 -#else -#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0 // Default in upstream simulator -#endif + #define configEXPECTED_IDLE_TIME_BEFORE_SLEEP CONFIG_FREERTOS_IDLE_TIME_BEFORE_SLEEP +#endif /* configUSE_TICKLESS_IDLE */ +#define configCPU_CLOCK_HZ ( CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ * 1000000 ) +#define configTICK_RATE_HZ CONFIG_FREERTOS_HZ +#define configUSE_TIME_SLICING 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configKERNEL_INTERRUPT_PRIORITY 1 /*Todo: This currently isn't used anywhere */ + +/* ------------- Synchronization Primitives ---------------- */ + +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_QUEUE_SETS 1 +#define configQUEUE_REGISTRY_SIZE CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE +#define configUSE_TASK_NOTIFICATIONS 1 +#define configTASK_NOTIFICATION_ARRAY_ENTRIES CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES + +/* ----------------------- System -------------------------- */ + +#define configMAX_TASK_NAME_LEN CONFIG_FREERTOS_MAX_TASK_NAME_LEN +#if CONFIG_FREERTOS_SMP +/* Number of TLSP is doubled to store TLSP deletion callbacks */ + #define configNUM_THREAD_LOCAL_STORAGE_POINTERS ( CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS * 2 ) +#else /* CONFIG_FREERTOS_SMP */ + #define configNUM_THREAD_LOCAL_STORAGE_POINTERS CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS +#endif /* CONFIG_FREERTOS_SMP */ +#define configSTACK_DEPTH_TYPE uint32_t #if CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY -#define configENABLE_BACKWARD_COMPATIBILITY 1 -#else -#define configENABLE_BACKWARD_COMPATIBILITY 0 -#endif -#define configASSERT(a) assert(a) - -// ----------------------- Memory ------------------------- - -#define configSUPPORT_STATIC_ALLOCATION 1 -#define configSUPPORT_DYNAMIC_ALLOCATION 1 -#ifdef CONFIG_IDF_TARGET_LINUX -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 65 * 1024 ) ) // Default in upstream simulator -#else -//We define the heap to span all of the non-statically-allocated shared RAM. ToDo: Make sure there -//is some space left for the app and main cpu when running outside of a thread. -#define configTOTAL_HEAP_SIZE (&_heap_end - &_heap_start)//( ( size_t ) (64 * 1024) ) -#endif -#define configAPPLICATION_ALLOCATED_HEAP 1 -#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 - -// ------------------------ Hooks -------------------------- - -#define configUSE_IDLE_HOOK CONFIG_FREERTOS_USE_IDLE_HOOK -#define configUSE_TICK_HOOK CONFIG_FREERTOS_USE_TICK_HOOK + #define configENABLE_BACKWARD_COMPATIBILITY 1 +#else /* CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY */ + #define configENABLE_BACKWARD_COMPATIBILITY 0 +#endif /* CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY */ +#define configASSERT( a ) assert( a ) + +/* ----------------------- Memory ------------------------- */ + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configAPPLICATION_ALLOCATED_HEAP 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +/* ------------------------ Hooks -------------------------- */ + +#if CONFIG_FREERTOS_USE_IDLE_HOOK + #define configUSE_IDLE_HOOK 1 +#else /* CONFIG_FREERTOS_USE_IDLE_HOOK */ + #define configUSE_IDLE_HOOK 0 +#endif /* CONFIG_FREERTOS_USE_IDLE_HOOK */ +#if CONFIG_FREERTOS_USE_TICK_HOOK + #define configUSE_TICK_HOOK 1 +#else /* CONFIG_FREERTOS_USE_TICK_HOOK */ + #define configUSE_TICK_HOOK 0 +#endif /* CONFIG_FREERTOS_USE_TICK_HOOK */ #if CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE -#define configCHECK_FOR_STACK_OVERFLOW 0 + #define configCHECK_FOR_STACK_OVERFLOW 0 #elif CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL -#define configCHECK_FOR_STACK_OVERFLOW 1 + #define configCHECK_FOR_STACK_OVERFLOW 1 #elif CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY -#define configCHECK_FOR_STACK_OVERFLOW 2 -#endif -#define configRECORD_STACK_HIGH_ADDRESS 1 // This must be set as the port requires TCB.pxEndOfStack + #define configCHECK_FOR_STACK_OVERFLOW 2 +#endif /* CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE */ +#define configRECORD_STACK_HIGH_ADDRESS 1 /* This must be set as the port requires TCB.pxEndOfStack */ -// ------------------- Run-time Stats ---------------------- +/* ------------------- Run-time Stats ---------------------- */ #ifdef CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS -#define configGENERATE_RUN_TIME_STATS 1 /* Used by vTaskGetRunTimeStats() */ -#endif -#ifdef CONFIG_IDF_TARGET_LINUX -#define configUSE_TRACE_FACILITY 1 -#else -#ifdef CONFIG_FREERTOS_USE_TRACE_FACILITY -#define configUSE_TRACE_FACILITY 1 /* Used by uxTaskGetSystemState(), and other trace facility functions */ -#endif -#endif + #define configGENERATE_RUN_TIME_STATS 1 /* Used by vTaskGetRunTimeStats() */ +#endif /* CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS */ #ifdef CONFIG_FREERTOS_USE_STATS_FORMATTING_FUNCTIONS -#define configUSE_STATS_FORMATTING_FUNCTIONS 1 /* Used by vTaskList() */ -#endif + #define configUSE_STATS_FORMATTING_FUNCTIONS 1 /* Used by vTaskList() */ +#endif /* CONFIG_FREERTOS_USE_STATS_FORMATTING_FUNCTIONS */ -// -------------------- Co-routines ----------------------- +/* -------------------- Co-routines ----------------------- */ -#define configUSE_CO_ROUTINES 0 // CO_ROUTINES are not supported in ESP-IDF -#define configMAX_CO_ROUTINE_PRIORITIES 2 +#define configUSE_CO_ROUTINES 0 /* CO_ROUTINES are not supported in ESP-IDF */ +#define configMAX_CO_ROUTINE_PRIORITIES 2 -// ------------------- Software Timer ---------------------- +/* ------------------- Software Timer ---------------------- */ -#define configUSE_TIMERS 1 -#define configTIMER_TASK_PRIORITY CONFIG_FREERTOS_TIMER_TASK_PRIORITY -#define configTIMER_QUEUE_LENGTH CONFIG_FREERTOS_TIMER_QUEUE_LENGTH -#define configTIMER_TASK_STACK_DEPTH CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY CONFIG_FREERTOS_TIMER_TASK_PRIORITY +#define configTIMER_QUEUE_LENGTH CONFIG_FREERTOS_TIMER_QUEUE_LENGTH +#define configTIMER_TASK_STACK_DEPTH CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH -// -------------------- API Includes ----------------------- +/* -------------------- API Includes ----------------------- */ #if CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY -#define configENABLE_BACKWARD_COMPATIBILITY 1 -#else -#define configENABLE_BACKWARD_COMPATIBILITY 0 -#endif - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelay 1 -#define INCLUDE_xTaskGetIdleTaskHandle 1 -#define INCLUDE_xTaskAbortDelay 1 -#define INCLUDE_xSemaphoreGetMutexHolder 1 -#define INCLUDE_xTaskGetHandle 1 -#define INCLUDE_uxTaskGetStackHighWaterMark 1 -#define INCLUDE_uxTaskGetStackHighWaterMark2 1 -#define INCLUDE_eTaskGetState 1 -#define INCLUDE_xTaskResumeFromISR 1 -#define INCLUDE_xTimerPendFunctionCall 1 -#define INCLUDE_xTaskGetSchedulerState 1 -#ifdef CONFIG_IDF_TARGET_LINUX -#define INCLUDE_xTaskGetCurrentTaskHandle 0 // not defined in POSIX simulator -#define INCLUDE_vTaskDelayUntil 1 -#else -#define INCLUDE_xTaskDelayUntil 1 -#define INCLUDE_xTaskGetCurrentTaskHandle 1 -#endif -//Unlisted -#define INCLUDE_pxTaskGetStackStart 1 - -// -------------------- Trace Macros ----------------------- + #define configENABLE_BACKWARD_COMPATIBILITY 1 +#else /* CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY */ + #define configENABLE_BACKWARD_COMPATIBILITY 0 +#endif /* CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetIdleTaskHandle 1 +#define INCLUDE_xTaskAbortDelay 1 +#define INCLUDE_xSemaphoreGetMutexHolder 1 +#define INCLUDE_xTaskGetHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_uxTaskGetStackHighWaterMark2 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTaskResumeFromISR 1 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskGetSchedulerState 1 +/* Unlisted */ +#define INCLUDE_pxTaskGetStackStart 1 + +/* -------------------- Trace Macros ----------------------- */ /* -For trace macros. -Note: Include trace macros here and not above as trace macros are dependent on some of the FreeRTOS configs -*/ + * For trace macros. + * Note: Include trace macros here and not above as trace macros are dependent on some of the FreeRTOS configs + */ #ifndef __ASSEMBLER__ -#if CONFIG_SYSVIEW_ENABLE -#include "SEGGER_SYSVIEW_FreeRTOS.h" -#undef INLINE // to avoid redefinition -#endif //CONFIG_SYSVIEW_ENABLE + #if CONFIG_SYSVIEW_ENABLE + #include "SEGGER_SYSVIEW_FreeRTOS.h" + #undef INLINE /* to avoid redefinition */ + #endif /* CONFIG_SYSVIEW_ENABLE */ + + #if CONFIG_FREERTOS_SMP + +/* Default values for trace macros added to ESP-IDF implementation of SYSVIEW + * that is not part of Amazon SMP FreeRTOS. */ + #ifndef traceISR_EXIT + #define traceISR_EXIT() + #endif + #ifndef traceISR_ENTER + #define traceISR_ENTER( _n_ ) + #endif + + #ifndef traceQUEUE_GIVE_FROM_ISR + #define traceQUEUE_GIVE_FROM_ISR( pxQueue ) + #endif + + #ifndef traceQUEUE_GIVE_FROM_ISR_FAILED + #define traceQUEUE_GIVE_FROM_ISR_FAILED( pxQueue ) + #endif + + #ifndef traceQUEUE_SEMAPHORE_RECEIVE + #define traceQUEUE_SEMAPHORE_RECEIVE( pxQueue ) + #endif + #endif /* CONFIG_FREERTOS_SMP */ #endif /* def __ASSEMBLER__ */ -/* ------------------------------------------------ ESP-IDF Additions -------------------------------------------------- - * - All FreeRTOS related configurations no part of Vanilla FreeRTOS goes into this section - * - FreeRTOS configurations related to SMP and ESP-IDF additions go into this section +/* ----------------------------------------------- Amazon SMP FreeRTOS ------------------------------------------------- + * - All Amazon SMP FreeRTOS specific configurations * ------------------------------------------------------------------------------------------------------------------ */ -// ------------------------- SMP --------------------------- - -#ifndef CONFIG_FREERTOS_UNICORE -#define portNUM_PROCESSORS 2 -#else -#define portNUM_PROCESSORS 1 -#endif -#define configNUM_CORES portNUM_PROCESSORS -#ifdef CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID -#define configTASKLIST_INCLUDE_COREID 1 -#endif - -// ---------------------- Features ------------------------- - -#ifdef CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS -#define configTHREAD_LOCAL_STORAGE_DELETE_CALLBACKS 1 -#endif - -#if CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER -#define configCHECK_MUTEX_GIVEN_BY_OWNER 1 -#else -#define configCHECK_MUTEX_GIVEN_BY_OWNER 0 -#endif - -#ifndef __ASSEMBLER__ -#if CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP -extern void vPortCleanUpTCB ( void *pxTCB ); -#define portCLEAN_UP_TCB( pxTCB ) vPortCleanUpTCB( pxTCB ) -#endif -#endif - -// -------------------- Compatibility ---------------------- +#if CONFIG_FREERTOS_SMP + #ifdef CONFIG_FREERTOS_UNICORE + #define configNUM_CORES 1 + #else + #define configNUM_CORES 2 + #endif /* CONFIG_FREERTOS_UNICORE */ + #define configUSE_CORE_AFFINITY 1 + #define configRUN_MULTIPLE_PRIORITIES 1 + #define configUSE_TASK_PREEMPTION_DISABLE 1 + +/* This is always enabled to call IDF style idle hooks, by can be "--Wl,--wrap" + * if users enable CONFIG_FREERTOS_USE_MINIMAL_IDLE_HOOK. */ + #define configUSE_MINIMAL_IDLE_HOOK 1 + +/* IDF Newlib supports dynamic reentrancy. We provide our own __getreent() + * function. */ + #define configNEWLIB_REENTRANT_IS_DYNAMIC 1 +#endif /* CONFIG_FREERTOS_SMP */ + +/* -------------------------------------------------- IDF FreeRTOS ----------------------------------------------------- + * - All IDF FreeRTOS specific configurations + * ------------------------------------------------------------------------------------------------------------------ */ -// backward compatibility for 4.4 -#define xTaskRemoveFromUnorderedEventList vTaskRemoveFromUnorderedEventList +#if !CONFIG_FREERTOS_SMP + #ifdef CONFIG_FREERTOS_UNICORE + #define configNUM_CORES 1 + #else + #define configNUM_CORES 2 + #endif /* CONFIG_FREERTOS_UNICORE */ + #ifdef CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID + #define configTASKLIST_INCLUDE_COREID 1 + #endif /* CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID */ + #ifdef CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS + #define configTHREAD_LOCAL_STORAGE_DELETE_CALLBACKS 1 + #endif /* CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS */ + #if CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER + #define configCHECK_MUTEX_GIVEN_BY_OWNER 1 + #endif /* CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER */ +#endif /* !CONFIG_FREERTOS_SMP */ -#endif // CONFIG_FREERTOS_SMP +/* ------------------------------------------------ ESP-IDF Additions -------------------------------------------------- + * - Any other macros required by the rest of ESP-IDF + * ------------------------------------------------------------------------------------------------------------------ */ -#endif /* FREERTOS_CONFIG_H */ +#define portNUM_PROCESSORS configNUM_CORES diff --git a/tools/sdk/esp32s2/include/freertos/esp_additions/include/freertos/idf_additions.h b/tools/sdk/esp32s2/include/freertos/esp_additions/include/freertos/idf_additions.h index 6523575c8da..22aac424b74 100644 --- a/tools/sdk/esp32s2/include/freertos/esp_additions/include/freertos/idf_additions.h +++ b/tools/sdk/esp32s2/include/freertos/esp_additions/include/freertos/idf_additions.h @@ -1,45 +1,65 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ +#pragma once + +/* + * This file contains the function prototypes of ESP-IDF specific API additions + * to the FreeRTOS kernel. These API additions are not part of Vanilla (i.e., + * upstream) FreeRTOS and include things such as.... + * - Various helper functions + * - API for ESP-IDF feature additions to FreeRTOS (such as TSLP deletion + * call backs) + */ + #include "sdkconfig.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" -#include "idf_additions_inc.h" -#if CONFIG_FREERTOS_SMP || __DOXYGEN__ +#ifdef __cplusplus + extern "C" { +#endif -/* ------------------------------------------------ Helper Functions --------------------------------------------------- +/* ----------------------------------------------------------------------------- + * SMP related API additions to FreeRTOS * - * ------------------------------------------------------------------------------------------------------------------ */ + * Todo: Move IDF FreeRTOS SMP related additions to this header as well (see + * IDF-7201) + * -------------------------------------------------------------------------- */ + +#if CONFIG_FREERTOS_SMP || __DOXYGEN__ /** * @brief Create a new task that is pinned to a particular core * - * Helper function to create a task that is pinned to a particular core, or has no affinity. In other wrods, the created - * task will have an affinity mask of: + * Helper function to create a task that is pinned to a particular core, or has + * no affinity. In other wrods, the created task will have an affinity mask of: * - (1 << xCoreID) if it is pinned to a particular core * - Set to tskNO_AFFINITY if it has no affinity * * @param pxTaskCode Pointer to the task entry function. * @param pcName A descriptive name for the task. * @param usStackDepth The size of the task stack. - * @param pvParameters Pointer that will be used as the parameter for the task being created. + * @param pvParameters Pointer that will be used as the parameter for the task + * being created. * @param uxPriority The priority at which the task should run. - * @param pxCreatedTask Used to pass back a handle by which the created task can be referenced. - * @param xCoreID The core to which the task is pinned to, or tskNO_AFFINITY if the task has no core affinity - * @return pdPASS if the task was successfully created and added to a ready list, otherwise an error code defined in the - * file projdefs.h + * @param pxCreatedTask Used to pass back a handle by which the created task can + * be referenced. + * @param xCoreID The core to which the task is pinned to, or tskNO_AFFINITY if + * the task has no core affinity + * @return pdPASS if the task was successfully created and added to a ready + * list, otherwise an error code defined in the file projdefs.h */ -BaseType_t xTaskCreatePinnedToCore( TaskFunction_t pxTaskCode, - const char * const pcName, - const uint32_t usStackDepth, - void * const pvParameters, - UBaseType_t uxPriority, - TaskHandle_t * const pxCreatedTask, - const BaseType_t xCoreID); + BaseType_t xTaskCreatePinnedToCore( TaskFunction_t pxTaskCode, + const char * const pcName, + const uint32_t usStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask, + const BaseType_t xCoreID ); /** @@ -50,142 +70,118 @@ BaseType_t xTaskCreatePinnedToCore( TaskFunction_t pxTaskCode, * @param pxTaskCode Pointer to the task entry function. * @param pcName A descriptive name for the task. * @param ulStackDepth The size of the task stack. - * @param pvParameters Pointer that will be used as the parameter for the task being created. + * @param pvParameters Pointer that will be used as the parameter for the task + * being created. * @param uxPriority The priority at which the task should run. - * @param puxStackBuffer Must point to a StackType_t array that has at least ulStackDepth indexes - * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will then be used to hold the task's data structures, - * @param xCoreID The core to which the task is pinned to, or tskNO_AFFINITY if the task has no core affinity + * @param puxStackBuffer Must point to a StackType_t array that has at least + * ulStackDepth indexes + * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will + * then be used to hold the task's data structures, + * @param xCoreID The core to which the task is pinned to, or tskNO_AFFINITY if + * the task has no core affinity * @return The task handle if the task was created, NULL otherwise. */ -#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) -TaskHandle_t xTaskCreateStaticPinnedToCore( TaskFunction_t pxTaskCode, - const char * const pcName, - const uint32_t ulStackDepth, - void * const pvParameters, - UBaseType_t uxPriority, - StackType_t * const puxStackBuffer, - StaticTask_t * const pxTaskBuffer, - const BaseType_t xCoreID ); -#endif /* configSUPPORT_STATIC_ALLOCATION */ + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + TaskHandle_t xTaskCreateStaticPinnedToCore( TaskFunction_t pxTaskCode, + const char * const pcName, + const uint32_t ulStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer, + const BaseType_t xCoreID ); + #endif /* configSUPPORT_STATIC_ALLOCATION */ /** * @brief Get the handle of the task running on a certain core * - * Because of the nature of SMP processing, there is no guarantee that this value will still be valid on return and - * should only be used for debugging purposes. + * Because of the nature of SMP processing, there is no guarantee that this + * value will still be valid on return and should only be used for debugging + * purposes. * - * [refactor-todo] Mark this function as deprecated, call xTaskGetCurrentTaskHandleCPU() instead + * [refactor-todo] Mark this function as deprecated, call + * xTaskGetCurrentTaskHandleCPU() instead * * @param xCoreID The core to query * @return Handle of the current task running on the queried core */ -TaskHandle_t xTaskGetCurrentTaskHandleForCPU( BaseType_t xCoreID ); + TaskHandle_t xTaskGetCurrentTaskHandleForCPU( BaseType_t xCoreID ); /** * @brief Get the handle of idle task for the given CPU. * - * [refactor-todo] Mark this function as deprecated, call xTaskGetIdleTaskHandle() instead + * [refactor-todo] Mark this function as deprecated, call + * xTaskGetIdleTaskHandle() instead * * @param xCoreID The core to query * @return Handle of the idle task for the queried core */ -TaskHandle_t xTaskGetIdleTaskHandleForCPU( BaseType_t xCoreID ); + TaskHandle_t xTaskGetIdleTaskHandleForCPU( BaseType_t xCoreID ); /** * @brief Get the current core affintiy of a particular task * - * Helper function to get the core affinity of a particular task. If the task is pinned to a particular core, the core - * ID is returned. If the task is not pinned to a particular core, tskNO_AFFINITY is returned. + * Helper function to get the core affinity of a particular task. If the task is + * pinned to a particular core, the core ID is returned. If the task is not + * pinned to a particular core, tskNO_AFFINITY is returned. * - * [refactor-todo] Mark this function as deprecated, call vTaskCoreAffinityGet() instead + * [refactor-todo] Mark this function as deprecated, call vTaskCoreAffinityGet() + * instead * * @param xTask The task to query * @return The tasks coreID or tskNO_AFFINITY */ -BaseType_t xTaskGetAffinity( TaskHandle_t xTask ); - -#if ( CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS ) - - /** - * Prototype of local storage pointer deletion callback. - */ - typedef void (*TlsDeleteCallbackFunction_t)( int, void * ); - - /** - * Set local storage pointer and deletion callback. - * - * Each task contains an array of pointers that is dimensioned by the - * configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h. - * The kernel does not use the pointers itself, so the application writer - * can use the pointers for any purpose they wish. - * - * Local storage pointers set for a task can reference dynamically - * allocated resources. This function is similar to - * vTaskSetThreadLocalStoragePointer, but provides a way to release - * these resources when the task gets deleted. For each pointer, - * a callback function can be set. This function will be called - * when task is deleted, with the local storage pointer index - * and value as arguments. - * - * @param xTaskToSet Task to set thread local storage pointer for - * @param xIndex The index of the pointer to set, from 0 to - * configNUM_THREAD_LOCAL_STORAGE_POINTERS - 1. - * @param pvValue Pointer value to set. - * @param pvDelCallback Function to call to dispose of the local - * storage pointer when the task is deleted. - */ - void vTaskSetThreadLocalStoragePointerAndDelCallback( - TaskHandle_t xTaskToSet, - BaseType_t xIndex, - void *pvValue, - TlsDeleteCallbackFunction_t pvDelCallback); -#endif // CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS + BaseType_t xTaskGetAffinity( TaskHandle_t xTask ); #endif // CONFIG_FREERTOS_SMP || __DOXYGEN__ -#if ( INCLUDE_vTaskPrioritySet == 1 ) +/* ----------------------------------------------------------------------------- + * TLSP Deletion Callback related API additions + * + * Todo: Move IDF FreeRTOS TLSP Deletion Callback related additions to this + * header as well (see IDF-7201) + * -------------------------------------------------------------------------- */ + +#if CONFIG_FREERTOS_SMP || __DOXYGEN__ + + #if ( CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS ) /** - * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Saves the current priority and current base priority of a task, then raises the tasks - * current and base priority to uxNewPriority if uxNewPriority is of a higher priority. - * Once a task's priority has been raised with this function, the priority can be restored - * by calling prvTaskPriorityRestore() - * - Note that this function differs from vTaskPrioritySet() as the task's current priority - * will be modified even if the task has already inherited a priority. - * - This function is intended for special circumstance where a task must be forced immediately - * to a higher priority. - * - * For configUSE_MUTEXES == 0: A context switch will occur before the function returns if the priority - * being set is higher than the currently executing task. - * - * @note This functions is private is only be called internally within various IDF components. - * Users should never call this function from their application. - * - * @note vTaskPrioritySet() should not be called while a task's priority is already raised via this function - * - * @param pxSavedPriority returns base and current priorities - * - * @param uxNewPriority The priority to which the task will be set. + * Prototype of local storage pointer deletion callback. */ -void prvTaskPriorityRaise( prvTaskSavedPriority_t * pxSavedPriority, UBaseType_t uxNewPriority ); + typedef void (* TlsDeleteCallbackFunction_t)( int, + void * ); /** - * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Restore a task's priority that was previously raised by prvTaskPriorityRaise(). - * - * For configUSE_MUTEXES == 0: A context switch will occur before the function returns if the priority - * being set is higher than the currently executing task. - * - * @note This functions is private is only be called internally within various IDF components. - * Users should never call this function from their application. - * - * @param pxSavedPriority previously saved base and current priorities that need to be restored + * Set local storage pointer and deletion callback. + * + * Each task contains an array of pointers that is dimensioned by the + * configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h. The + * kernel does not use the pointers itself, so the application writer can use + * the pointers for any purpose they wish. + * + * Local storage pointers set for a task can reference dynamically allocated + * resources. This function is similar to vTaskSetThreadLocalStoragePointer, but + * provides a way to release these resources when the task gets deleted. For + * each pointer, a callback function can be set. This function will be called + * when task is deleted, with the local storage pointer index and value as + * arguments. + * + * @param xTaskToSet Task to set thread local storage pointer for + * @param xIndex The index of the pointer to set, from 0 to + * configNUM_THREAD_LOCAL_STORAGE_POINTERS - 1. + * @param pvValue Pointer value to set. + * @param pvDelCallback Function to call to dispose of the local storage + * pointer when the task is deleted. */ -void prvTaskPriorityRestore( prvTaskSavedPriority_t * pxSavedPriority ); + void vTaskSetThreadLocalStoragePointerAndDelCallback( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue, + TlsDeleteCallbackFunction_t pvDelCallback ); + #endif // CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS + +#endif // CONFIG_FREERTOS_SMP || __DOXYGEN__ -#endif // ( INCLUDE_vTaskPrioritySet == 1) +#ifdef __cplusplus + } +#endif diff --git a/tools/sdk/esp32s2/include/freertos/esp_additions/include/freertos/idf_additions_inc.h b/tools/sdk/esp32s2/include/freertos/esp_additions/include/freertos/idf_additions_inc.h deleted file mode 100644 index 25b0b6d9a4d..00000000000 --- a/tools/sdk/esp32s2/include/freertos/esp_additions/include/freertos/idf_additions_inc.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - - -#ifndef FREERTOS_ADDITITIONS_INC_H_ -#define FREERTOS_ADDITITIONS_INC_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "sdkconfig.h" -#include "freertos/FreeRTOS.h" - -#if ( INCLUDE_vTaskPrioritySet == 1 ) - -typedef struct { - UBaseType_t uxPriority; -#if ( configUSE_MUTEXES == 1 ) - UBaseType_t uxBasePriority; -#endif -} prvTaskSavedPriority_t; - -#endif // ( INCLUDE_vTaskPrioritySet == 1) - -#ifdef __cplusplus -} -#endif - -#endif //FREERTOS_ADDITITIONS_INC_H_ diff --git a/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/efuse_ll.h b/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/efuse_ll.h index 147bde79bf8..ccfb01fb032 100644 --- a/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/efuse_ll.h +++ b/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/efuse_ll.h @@ -32,12 +32,12 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void) { - return EFUSE.rd_mac_spi_8m_0; + return EFUSE.rd_mac_spi_sys_0.mac_0; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void) { - return EFUSE.rd_mac_spi_8m_1.mac_1; + return EFUSE.rd_mac_spi_sys_1.mac_1; } __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void) @@ -48,13 +48,13 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en // use efuse_hal_get_major_chip_version() to get major chip version __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void) { - return EFUSE.rd_mac_spi_8m_3.wafer_version_major; + return EFUSE.rd_mac_spi_sys_3.wafer_version_major; } // use efuse_hal_get_minor_chip_version() to get minor chip version __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void) { - return (EFUSE.rd_mac_spi_8m_3.wafer_version_minor_high << 3) + EFUSE.rd_mac_spi_8m_4.wafer_version_minor_low; + return (EFUSE.rd_mac_spi_sys_3.wafer_version_minor_hi << 3) + EFUSE.rd_mac_spi_sys_4.wafer_version_minor_lo; } __attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void) @@ -64,12 +64,12 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_ver __attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void) { - return EFUSE.rd_mac_spi_8m_3.blk_version_major; + return EFUSE.rd_mac_spi_sys_3.blk_version_major; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void) { - return EFUSE.rd_sys_data4.blk_version_minor; + return EFUSE.rd_sys_part1_data4.blk_version_minor; } __attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void) @@ -79,37 +79,37 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_versi __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void) { - return EFUSE.rd_mac_spi_8m_4.pkg_version; + return EFUSE.rd_mac_spi_sys_4.pkg_version; } __attribute__((always_inline)) static inline bool efuse_ll_get_sdio_force(void) { - return EFUSE.rd_repeat_data1.sdio_force; + return EFUSE.rd_repeat_data1.vdd_spi_force; } __attribute__((always_inline)) static inline bool efuse_ll_get_sdio_tieh(void) { - return EFUSE.rd_repeat_data1.sdio_tieh; + return EFUSE.rd_repeat_data1.vdd_spi_tieh; } __attribute__((always_inline)) static inline bool efuse_ll_get_sdio_xpd(void) { - return EFUSE.rd_repeat_data1.sdio_xpd; + return EFUSE.rd_repeat_data1.vdd_spi_xpd; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefl(void) { - return EFUSE.rd_repeat_data1.sdio_drefl; + return EFUSE.rd_repeat_data1.vdd_spi_drefl; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefm(void) { - return EFUSE.rd_repeat_data1.sdio_drefm; + return EFUSE.rd_repeat_data1.vdd_spi_drefm; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefh(void) { - return EFUSE.rd_repeat_data0.sdio_drefh; + return EFUSE.rd_repeat_data0.vdd_spi_drefh; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_ocode(void) @@ -117,7 +117,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_ocode(void) // OCODE1, BLOCK2, 128, 4, (#4 reg, pos 0) // OCODE2, BLOCK2, 144, 3, (#4 reg, pos 16) // OCODE = (ocode2 << 4) + ocode1 - return (EFUSE.rd_sys_data4.ocode_hi << 4) + EFUSE.rd_sys_data4.ocode_low; + return (((EFUSE.rd_sys_part1_data4.val >> 16) & 0x7) << 4) + (EFUSE.rd_sys_part1_data4.val & 0xF); } /******************* eFuse control functions *************************/ diff --git a/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/ledc_ll.h b/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/ledc_ll.h index 0f7e08e3d85..fbdd6cc2f11 100644 --- a/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/ledc_ll.h +++ b/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/ledc_ll.h @@ -38,6 +38,9 @@ extern "C" { #define LEDC_LL_IS_TIMER_SPECIFIC_CLOCK(SPEED, CLK) ((CLK) == LEDC_USE_REF_TICK) +#define LEDC_LL_GLOBAL_CLK_DEFAULT LEDC_SLOW_CLK_RC_FAST + + /** * @brief Set LEDC low speed timer clock * diff --git a/tools/sdk/esp32s2/include/hal/include/hal/ecdsa_hal.h b/tools/sdk/esp32s2/include/hal/include/hal/ecdsa_hal.h new file mode 100644 index 00000000000..d7244b3dc05 --- /dev/null +++ b/tools/sdk/esp32s2/include/hal/include/hal/ecdsa_hal.h @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/******************************************************************************* + * NOTICE + * The HAL is not public api, don't use in application code. + * See readme.md in soc/README.md + ******************************************************************************/ + +#pragma once + +#include +#include "hal/ecdsa_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * ECDSA peripheral config structure + */ +typedef struct { + ecdsa_mode_t mode; /* Mode of operation */ + ecdsa_curve_t curve; /* Curve to use for operation */ + ecdsa_k_mode_t k_mode; /* Source of K */ + ecdsa_sha_mode_t sha_mode; /* Source of SHA that needs to be signed */ +} ecdsa_hal_config_t; + +/** + * @brief Generate ECDSA signature + * + * @param conf Configuration for ECDSA operation, see ``ecdsa_hal_config_t`` + * @param k Value of K used internally. Set this to NULL if K is generated by hardware + * @param hash Hash that is to be signed + * @param r_out Buffer that will contain `R` component of ECDSA signature + * @param s_out Buffer that will contain `S` component of ECDSA signature + * @param len Length of the r_out and s_out buffer (32 bytes for SECP256R1, 24 for SECP192R1) + */ +void ecdsa_hal_gen_signature(ecdsa_hal_config_t *conf, const uint8_t *k, const uint8_t *hash, + uint8_t *r_out, uint8_t *s_out, uint16_t len); + +/** + * @brief Verify given ECDSA signature + * + * @param conf Configuration for ECDSA operation, see ``ecdsa_hal_config_t`` + * @param hash Hash that was signed + * @param r `R` component of ECDSA signature + * @param s `S` component of ECDSA signature + * @param pub_x X coordinate of public key + * @param pub_y Y coordinate of public key + * @param len Length of r and s buffer (32 bytes for SECP256R1, 24 for SECP192R1) + * + * @return - 0, if the signature matches + * - -1, if verification fails + */ +int ecdsa_hal_verify_signature(ecdsa_hal_config_t *conf, const uint8_t *hash, const uint8_t *r, const uint8_t *s, + const uint8_t *pub_x, const uint8_t *pub_y, uint16_t len); +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/hal/include/hal/ecdsa_types.h b/tools/sdk/esp32s2/include/hal/include/hal/ecdsa_types.h new file mode 100644 index 00000000000..fdb2f3d3cf0 --- /dev/null +++ b/tools/sdk/esp32s2/include/hal/include/hal/ecdsa_types.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief ECDSA peripheral work modes + */ +typedef enum { + ECDSA_MODE_SIGN_VERIFY, + ECDSA_MODE_SIGN_GEN, +} ecdsa_mode_t; + +/** + * @brief ECDSA curve options + */ +typedef enum { + ECDSA_CURVE_SECP192R1, + ECDSA_CURVE_SECP256R1, +} ecdsa_curve_t; + +/** + * @brief Source of 'K' used internally for generating signature + */ +typedef enum { + ECDSA_K_USE_TRNG, + ECDSA_K_USER_PROVIDED, +} ecdsa_k_mode_t; + +/** + * @brief Source of SHA message that is to be signed/verified + */ +typedef enum { + ECDSA_Z_USE_SHA_PERI, + ECDSA_Z_USER_PROVIDED, +} ecdsa_sha_mode_t; + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/hal/include/hal/efuse_hal.h b/tools/sdk/esp32s2/include/hal/include/hal/efuse_hal.h index 2f141b74404..bb11c9ae7b3 100644 --- a/tools/sdk/esp32s2/include/hal/include/hal/efuse_hal.h +++ b/tools/sdk/esp32s2/include/hal/include/hal/efuse_hal.h @@ -26,6 +26,15 @@ void efuse_hal_get_mac(uint8_t *mac); */ uint32_t efuse_hal_chip_revision(void); +/** + * @brief Is flash encryption currently enabled in hardware? + * + * Flash encryption is enabled if the FLASH_CRYPT_CNT efuse has an odd number of bits set. + * + * @return true if flash encryption is enabled. + */ +bool efuse_hal_flash_encryption_enabled(void); + /** * @brief Returns major chip version */ diff --git a/tools/sdk/esp32s2/include/hal/include/hal/modem_clock_hal.h b/tools/sdk/esp32s2/include/hal/include/hal/modem_clock_hal.h new file mode 100644 index 00000000000..9912308f5eb --- /dev/null +++ b/tools/sdk/esp32s2/include/hal/include/hal/modem_clock_hal.h @@ -0,0 +1,48 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The HAL layer for MODEM CLOCK + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc/soc_caps.h" +#include "hal/modem_syscon_ll.h" +#include "hal/modem_lpcon_ll.h" +#include "hal/modem_clock_types.h" + +typedef struct { + modem_syscon_dev_t *syscon_dev; + modem_lpcon_dev_t *lpcon_dev; +} modem_clock_hal_context_t; + +#if MAC_SUPPORT_PMU_MODEM_STATE +void modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain, uint32_t bitmap); +#endif + +void modem_clock_hal_enable_fe_clock(modem_clock_hal_context_t *hal, bool enable); + +#if SOC_BT_SUPPORTED +void modem_clock_hal_set_ble_rtc_timer_divisor_value(modem_clock_hal_context_t *hal, uint32_t divider); +void modem_clock_hal_enable_ble_rtc_timer_clock(modem_clock_hal_context_t *hal, bool enable); +void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src); +void modem_clock_hal_deselect_all_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t *hal); +#endif + +void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src); +void modem_clock_hal_deselect_all_coex_lpclk_source(modem_clock_hal_context_t *hal); + +#if SOC_WIFI_SUPPORTED +void modem_clock_hal_select_wifi_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src); +void modem_clock_hal_deselect_all_wifi_lpclk_source(modem_clock_hal_context_t *hal); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/hal/include/hal/rmt_types.h b/tools/sdk/esp32s2/include/hal/include/hal/rmt_types.h index 1082761d87a..7650c78bb70 100644 --- a/tools/sdk/esp32s2/include/hal/include/hal/rmt_types.h +++ b/tools/sdk/esp32s2/include/hal/include/hal/rmt_types.h @@ -1,11 +1,12 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once +#include #include "soc/clk_tree_defs.h" #include "soc/soc_caps.h" @@ -28,12 +29,12 @@ typedef int rmt_clock_source_t; */ typedef union { struct { - unsigned int duration0 : 15; /*!< Duration of level0 */ - unsigned int level0 : 1; /*!< Level of the first part */ - unsigned int duration1 : 15; /*!< Duration of level1 */ - unsigned int level1 : 1; /*!< Level of the second part */ + uint16_t duration0 : 15; /*!< Duration of level0 */ + uint16_t level0 : 1; /*!< Level of the first part */ + uint16_t duration1 : 15; /*!< Duration of level1 */ + uint16_t level1 : 1; /*!< Level of the second part */ }; - unsigned int val; /*!< Equivalent unsigned value for the RMT symbol */ + uint32_t val; /*!< Equivalent unsigned value for the RMT symbol */ } rmt_symbol_word_t; #ifdef __cplusplus diff --git a/tools/sdk/esp32s2/include/hal/include/hal/spi_slave_hd_hal.h b/tools/sdk/esp32s2/include/hal/include/hal/spi_slave_hd_hal.h index 099139cc015..d426f97e970 100644 --- a/tools/sdk/esp32s2/include/hal/include/hal/spi_slave_hd_hal.h +++ b/tools/sdk/esp32s2/include/hal/include/hal/spi_slave_hd_hal.h @@ -1,16 +1,8 @@ -// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ /******************************************************************************* * NOTICE @@ -258,8 +250,7 @@ int spi_slave_hd_hal_get_rxlen(spi_slave_hd_hal_context_t *hal); */ int spi_slave_hd_hal_get_last_addr(spi_slave_hd_hal_context_t *hal); -#if CONFIG_IDF_TARGET_ESP32S2 -//Append mode is only supported on ESP32S2 now + //////////////////////////////////////////////////////////////////////////////// // Append Mode //////////////////////////////////////////////////////////////////////////////// @@ -315,4 +306,3 @@ esp_err_t spi_slave_hd_hal_txdma_append(spi_slave_hd_hal_context_t *hal, uint8_t * - ESP_ERR_INVALID_STATE: Function called in invalid state. */ esp_err_t spi_slave_hd_hal_rxdma_append(spi_slave_hd_hal_context_t *hal, uint8_t *data, size_t len, void *arg); -#endif //#if CONFIG_IDF_TARGET_ESP32S2 diff --git a/tools/sdk/esp32s2/include/heap/include/esp_heap_caps.h b/tools/sdk/esp32s2/include/heap/include/esp_heap_caps.h index e5adf162b83..f3d1026c8b5 100644 --- a/tools/sdk/esp32s2/include/heap/include/esp_heap_caps.h +++ b/tools/sdk/esp32s2/include/heap/include/esp_heap_caps.h @@ -11,6 +11,7 @@ #include "multi_heap.h" #include #include "esp_err.h" +#include "esp_attr.h" #ifdef __cplusplus extern "C" { @@ -53,6 +54,26 @@ typedef void (*esp_alloc_failed_hook_t) (size_t size, uint32_t caps, const char */ esp_err_t heap_caps_register_failed_alloc_callback(esp_alloc_failed_hook_t callback); +#ifdef CONFIG_HEAP_USE_HOOKS +/** + * @brief callback called after every allocation + * @param ptr the allocated memory + * @param size in bytes of the allocation + * @param caps Bitwise OR of MALLOC_CAP_* flags indicating the type of memory allocated. + * @note this hook is called on the same thread as the allocation, which may be within a low level operation. + * You should refrain from doing heavy work, logging, flash writes, or any locking. + */ +__attribute__((weak)) IRAM_ATTR void esp_heap_trace_alloc_hook(void* ptr, size_t size, uint32_t caps); + +/** + * @brief callback called after every free + * @param ptr the memory that was freed + * @note this hook is called on the same thread as the allocation, which may be within a low level operation. + * You should refrain from doing heavy work, logging, flash writes, or any locking. + */ +__attribute__((weak)) IRAM_ATTR void esp_heap_trace_free_hook(void* ptr); +#endif + /** * @brief Allocate a chunk of memory which has the given capabilities * diff --git a/tools/sdk/esp32s2/include/heap/include/esp_heap_trace.h b/tools/sdk/esp32s2/include/heap/include/esp_heap_trace.h index b1c5d476e4c..2b0daa2e4c6 100644 --- a/tools/sdk/esp32s2/include/heap/include/esp_heap_trace.h +++ b/tools/sdk/esp32s2/include/heap/include/esp_heap_trace.h @@ -36,8 +36,11 @@ typedef struct heap_trace_record_t { size_t size; ///< Size of the allocation void *alloced_by[CONFIG_HEAP_TRACING_STACK_DEPTH]; ///< Call stack of the caller which allocated the memory. void *freed_by[CONFIG_HEAP_TRACING_STACK_DEPTH]; ///< Call stack of the caller which freed the memory (all zero if not freed.) -#ifdef CONFIG_HEAP_TRACING_STANDALONE - TAILQ_ENTRY(heap_trace_record_t) tailq; ///< Linked list: prev & next records +#if CONFIG_HEAP_TRACING_STANDALONE + TAILQ_ENTRY(heap_trace_record_t) tailq_list; ///< Linked list: prev & next records +#if CONFIG_HEAP_TRACE_HASH_MAP + TAILQ_ENTRY(heap_trace_record_t) tailq_hashmap; ///< Linked list: prev & next in hashmap entry list +#endif // CONFIG_HEAP_TRACE_HASH_MAP #endif // CONFIG_HEAP_TRACING_STANDALONE } heap_trace_record_t; @@ -52,6 +55,10 @@ typedef struct { size_t capacity; ///< The capacity of the internal buffer size_t high_water_mark; ///< The maximum value that 'count' got to size_t has_overflowed; ///< True if the internal buffer overflowed at some point +#if CONFIG_HEAP_TRACE_HASH_MAP + size_t total_hashmap_hits; ///< If hashmap is used, the total number of hits + size_t total_hashmap_miss; ///< If hashmap is used, the total number of misses (possibly due to overflow) +#endif } heap_trace_summary_t; /** diff --git a/tools/sdk/esp32s2/include/mbedtls/port/include/ecdsa/ecdsa_alt.h b/tools/sdk/esp32s2/include/mbedtls/port/include/ecdsa/ecdsa_alt.h new file mode 100644 index 00000000000..9e2620b3126 --- /dev/null +++ b/tools/sdk/esp32s2/include/mbedtls/port/include/ecdsa/ecdsa_alt.h @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "sdkconfig.h" +#include "mbedtls/pk.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef CONFIG_MBEDTLS_HARDWARE_ECDSA_SIGN + +/** + * @brief Initialize MPI to notify mbedtls_ecdsa_sign to use the private key in efuse + * We break the MPI struct of the private key in order to + * differentiate between hardware key and software key + * + * @note Currently, `efuse_blk` is not used internally. + * Hardware will choose the efuse block that has purpose set to ECDSA_KEY. + * In case of multiple ECDSA_KEY burnt in efuse, hardware will choose the + * greater efuse block number as the private key. + * + * @param key The MPI in which this functions stores the hardware context. + * This must be uninitialized + * @param efuse_blk The efuse key block that should be used as the private key. + * The key purpose of this block must be ECDSA_KEY + * + * @return - 0 if successful + * - -1 otherwise + * + */ +int esp_ecdsa_privkey_load_mpi(mbedtls_mpi *key, int efuse_blk); + +/** + * @brief Initialize PK context to notify mbedtls_ecdsa_sign to use the private key in efuse + * We break the MPI struct used to represent the private key `d` in ECP keypair + * in order to differentiate between hardware key and software key + * + * @note Currently, `efuse_blk` is not used internally. + * Hardware will choose the efuse block that has purpose set to ECDSA_KEY. + * In case of multiple ECDSA_KEY burnt in efuse, hardware will choose the + * greater efuse block number as the private key. + * + * @param key_ctx The context in which this functions stores the hardware context. + * This must be uninitialized + * @param efuse_blk The efuse key block that should be used as the private key. + * The key purpose of this block must be ECDSA_KEY + * + * @return - 0 if successful + * - -1 otherwise + */ +int esp_ecdsa_privkey_load_pk_context(mbedtls_pk_context *key_ctx, int efuse_blk); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/mbedtls/port/include/mbedtls/esp_config.h b/tools/sdk/esp32s2/include/mbedtls/port/include/mbedtls/esp_config.h index 71905d8cb3c..ea2efa243ad 100644 --- a/tools/sdk/esp32s2/include/mbedtls/port/include/mbedtls/esp_config.h +++ b/tools/sdk/esp32s2/include/mbedtls/port/include/mbedtls/esp_config.h @@ -224,6 +224,7 @@ #undef MBEDTLS_ECP_VERIFY_ALT #undef MBEDTLS_ECP_VERIFY_ALT_SOFT_FALLBACK #endif + /** * \def MBEDTLS_ENTROPY_HARDWARE_ALT * diff --git a/tools/sdk/esp32s2/include/pthread/include/semaphore.h b/tools/sdk/esp32s2/include/pthread/include/semaphore.h new file mode 100644 index 00000000000..5a7ef56b971 --- /dev/null +++ b/tools/sdk/esp32s2/include/pthread/include/semaphore.h @@ -0,0 +1,73 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef unsigned int sem_t; + +/** + * This is the maximum value to which any POSIX semaphore can count on ESP chips. + */ +#define SEM_VALUE_MAX 0x7FFF + +/** + * This is a POSIX function, please refer to the POSIX specification for a detailed description. + * + * Must NOT be called if threads are still blocked on semaphore! + */ +int sem_destroy(sem_t *sem); + +/** + * This is a POSIX function, please refer to the POSIX specification for a detailed description. + * + * Note that on ESP chips, pshared is ignored. Semaphores can always be shared between FreeRTOS tasks. + */ +int sem_init(sem_t *sem, int pshared, unsigned value); + +/** + * This is a POSIX function, please refer to the POSIX specification for a detailed description. + * + * Note that, unlike specified in POSIX, this implementation returns -1 and sets errno to + * EAGAIN if the semaphore can not be unlocked (posted) due to its value being SEM_VALUE_MAX. + */ +int sem_post(sem_t *sem); + +/** + * This is a POSIX function, please refer to the POSIX specification for a detailed description. + * + * Note the following three deviations/issues originating from the underlying FreeRTOS implementation: + * * The time value passed by abstime will be rounded up to the next FreeRTOS tick. + * * The actual timeout will happen after the tick the time was rounded to + * and before the following tick. + * * It is possible, though unlikely, that the task is preempted directly after the timeout calculation, + * delaying timeout of the following blocking operating system call by the duration of the preemption. + */ +int sem_timedwait(sem_t * restrict semaphore, const struct timespec *restrict abstime); + +/** + * This is a POSIX function, please refer to the POSIX specification for a detailed description. + */ +int sem_trywait(sem_t *sem); + +/** + * This is a POSIX function, please refer to the POSIX specification for a detailed description. + */ +int sem_wait(sem_t *sem); + +/** + * This is a POSIX function, please refer to the POSIX specification for a detailed description. + */ +int sem_getvalue(sem_t *restrict sem, int *restrict sval); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/soc/esp32s2/include/soc/efuse_defs.h b/tools/sdk/esp32s2/include/soc/esp32s2/include/soc/efuse_defs.h new file mode 100644 index 00000000000..55f3abff560 --- /dev/null +++ b/tools/sdk/esp32s2/include/soc/esp32s2/include/soc/efuse_defs.h @@ -0,0 +1,17 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define EFUSE_WRITE_OP_CODE 0x5a5a +#define EFUSE_READ_OP_CODE 0x5aa5 + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/soc/esp32s2/include/soc/efuse_reg.h b/tools/sdk/esp32s2/include/soc/esp32s2/include/soc/efuse_reg.h index bb369fa740e..b742bfc37c6 100644 --- a/tools/sdk/esp32s2/include/soc/esp32s2/include/soc/efuse_reg.h +++ b/tools/sdk/esp32s2/include/soc/esp32s2/include/soc/efuse_reg.h @@ -1,2313 +1,2749 @@ -/* - * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_EFUSE_REG_H_ -#define _SOC_EFUSE_REG_H_ - +#pragma once +#include +#include "soc/soc.h" +#include "efuse_defs.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" -#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x000) -/* EFUSE_WR_DIS : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Set this bit to disable eFuse programming.*/ -#define EFUSE_WR_DIS 0xFFFFFFFF -#define EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S)) -#define EFUSE_WR_DIS_V 0xFFFFFFFF -#define EFUSE_WR_DIS_S 0 -#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x004) -/* EFUSE_VDD_SPI_DREFH : R/W ;bitpos:[31:30] ;default: 2'h0 ; */ -/*description: SPI regulator high voltage reference.*/ -#define EFUSE_VDD_SPI_DREFH 0x00000003 -#define EFUSE_VDD_SPI_DREFH_M ((EFUSE_VDD_SPI_DREFH_V)<<(EFUSE_VDD_SPI_DREFH_S)) -#define EFUSE_VDD_SPI_DREFH_V 0x3 -#define EFUSE_VDD_SPI_DREFH_S 30 -/* EFUSE_VDD_SPI_MODECURLIM : R/W ;bitpos:[29] ;default: 1'h0 ; */ -/*description: SPI regulator switches current limit mode.*/ -#define EFUSE_VDD_SPI_MODECURLIM (BIT(29)) -#define EFUSE_VDD_SPI_MODECURLIM_M (BIT(29)) -#define EFUSE_VDD_SPI_MODECURLIM_V 0x1 -#define EFUSE_VDD_SPI_MODECURLIM_S 29 -/* EFUSE_RPT4_RESERVED0 : RO ;bitpos:[28:27] ;default: 2'h0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED0 0x00000003 -#define EFUSE_RPT4_RESERVED0_M ((EFUSE_RPT4_RESERVED0_V)<<(EFUSE_RPT4_RESERVED0_S)) -#define EFUSE_RPT4_RESERVED0_V 0x3 -#define EFUSE_RPT4_RESERVED0_S 27 -/* EFUSE_USB_FORCE_NOPERSIST : R/W ;bitpos:[26] ;default: 1'h0 ; */ -/*description: Force nopersist to 1.*/ -#define EFUSE_USB_FORCE_NOPERSIST (BIT(26)) -#define EFUSE_USB_FORCE_NOPERSIST_M (BIT(26)) -#define EFUSE_USB_FORCE_NOPERSIST_V 0x1 -#define EFUSE_USB_FORCE_NOPERSIST_S 26 -/* EFUSE_USB_EXT_PHY_ENABLE : R/W ;bitpos:[25] ;default: 1'h0 ; */ -/*description: Set this bit to enable external PHY.*/ -#define EFUSE_USB_EXT_PHY_ENABLE (BIT(25)) -#define EFUSE_USB_EXT_PHY_ENABLE_M (BIT(25)) -#define EFUSE_USB_EXT_PHY_ENABLE_V 0x1 -#define EFUSE_USB_EXT_PHY_ENABLE_S 25 -/* EFUSE_USB_EXCHG_PINS : R/W ;bitpos:[24] ;default: 1'h0 ; */ -/*description: Set this bit to exchange D+ and D- pins.*/ -#define EFUSE_USB_EXCHG_PINS (BIT(24)) -#define EFUSE_USB_EXCHG_PINS_M (BIT(24)) -#define EFUSE_USB_EXCHG_PINS_V 0x1 -#define EFUSE_USB_EXCHG_PINS_S 24 -/* EFUSE_USB_DREFL : R/W ;bitpos:[23:22] ;default: 2'h0 ; */ -/*description: Controls single-end input threshold vrefl 0.8 V to 1.04 V with - step of 80 mV stored in eFuse.*/ -#define EFUSE_USB_DREFL 0x00000003 -#define EFUSE_USB_DREFL_M ((EFUSE_USB_DREFL_V)<<(EFUSE_USB_DREFL_S)) -#define EFUSE_USB_DREFL_V 0x3 -#define EFUSE_USB_DREFL_S 22 -/* EFUSE_USB_DREFH : R/W ;bitpos:[21:20] ;default: 2'h0 ; */ -/*description: Controls single-end input threshold vrefh 1.76 V to 2 V with - step of 80 mV stored in eFuse.*/ -#define EFUSE_USB_DREFH 0x00000003 -#define EFUSE_USB_DREFH_M ((EFUSE_USB_DREFH_V)<<(EFUSE_USB_DREFH_S)) -#define EFUSE_USB_DREFH_V 0x3 -#define EFUSE_USB_DREFH_S 20 -/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[19] ;default: 1'h0 ; */ -/*description: Set this bit to disable flash encrypt function (except in SPI/HSPI/Legacy_SPI - boot mode).*/ -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(19)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(19)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 19 -/* EFUSE_HARD_DIS_JTAG : R/W ;bitpos:[18] ;default: 1'h0 ; */ -/*description: Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.*/ -#define EFUSE_HARD_DIS_JTAG (BIT(18)) -#define EFUSE_HARD_DIS_JTAG_M (BIT(18)) -#define EFUSE_HARD_DIS_JTAG_V 0x1 -#define EFUSE_HARD_DIS_JTAG_S 18 -/* EFUSE_SOFT_DIS_JTAG : R/W ;bitpos:[17] ;default: 1'h0 ; */ -/*description: Set this bit to disable JTAG in the soft way. JTAG can be enabled - in HMAC module.*/ -#define EFUSE_SOFT_DIS_JTAG (BIT(17)) -#define EFUSE_SOFT_DIS_JTAG_M (BIT(17)) -#define EFUSE_SOFT_DIS_JTAG_V 0x1 -#define EFUSE_SOFT_DIS_JTAG_S 17 -/* EFUSE_DIS_EFUSE_ATE_WR : R/W ;bitpos:[16] ;default: 1'h0 ; */ -/*description: Set this bit to disable programming eFuse through ATE mode.*/ -#define EFUSE_DIS_EFUSE_ATE_WR (BIT(16)) -#define EFUSE_DIS_EFUSE_ATE_WR_M (BIT(16)) -#define EFUSE_DIS_EFUSE_ATE_WR_V 0x1 -#define EFUSE_DIS_EFUSE_ATE_WR_S 16 -/* EFUSE_DIS_BOOT_REMAP : R/W ;bitpos:[15] ;default: 1'h0 ; */ -/*description: Set this bit to disable boot remap from RAM to ROM.*/ -#define EFUSE_DIS_BOOT_REMAP (BIT(15)) -#define EFUSE_DIS_BOOT_REMAP_M (BIT(15)) -#define EFUSE_DIS_BOOT_REMAP_V 0x1 -#define EFUSE_DIS_BOOT_REMAP_S 15 -/* EFUSE_DIS_CAN : R/W ;bitpos:[14] ;default: 1'h0 ; */ -/*description: Set this bit to disable CAN function.*/ -#define EFUSE_DIS_CAN (BIT(14)) -#define EFUSE_DIS_CAN_M (BIT(14)) -#define EFUSE_DIS_CAN_V 0x1 -#define EFUSE_DIS_CAN_S 14 -/* EFUSE_DIS_USB : R/W ;bitpos:[13] ;default: 1'h0 ; */ -/*description: Set this bit to disable USB function.*/ -#define EFUSE_DIS_USB (BIT(13)) -#define EFUSE_DIS_USB_M (BIT(13)) -#define EFUSE_DIS_USB_V 0x1 -#define EFUSE_DIS_USB_S 13 -/* EFUSE_DIS_FORCE_DOWNLOAD : R/W ;bitpos:[12] ;default: 1'h0 ; */ -/*description: Set this bit to disable the function that forces chip into download mode.*/ -#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_M (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x1 -#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 -/* EFUSE_DIS_DOWNLOAD_DCACHE : R/W ;bitpos:[11] ;default: 1'h0 ; */ -/*description: Set this bit to disable Dcache in download mode ( boot_mode[3:0] - is 0 1 2 3 6 7).*/ -#define EFUSE_DIS_DOWNLOAD_DCACHE (BIT(11)) -#define EFUSE_DIS_DOWNLOAD_DCACHE_M (BIT(11)) -#define EFUSE_DIS_DOWNLOAD_DCACHE_V 0x1 -#define EFUSE_DIS_DOWNLOAD_DCACHE_S 11 -/* EFUSE_DIS_DOWNLOAD_ICACHE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: Set this bit to disable Icache in download mode (boot_mode[3:0] - is 0 1 2 3 6 7).*/ -#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_M (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x1 -#define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 -/* EFUSE_DIS_DCACHE : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: Set this bit to disable Dcache.*/ -#define EFUSE_DIS_DCACHE (BIT(9)) -#define EFUSE_DIS_DCACHE_M (BIT(9)) -#define EFUSE_DIS_DCACHE_V 0x1 -#define EFUSE_DIS_DCACHE_S 9 -/* EFUSE_DIS_ICACHE : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: Set this bit to disable Icache.*/ -#define EFUSE_DIS_ICACHE (BIT(8)) -#define EFUSE_DIS_ICACHE_M (BIT(8)) -#define EFUSE_DIS_ICACHE_V 0x1 -#define EFUSE_DIS_ICACHE_S 8 -/* EFUSE_DIS_RTC_RAM_BOOT : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: Set this bit to disable boot from RTC RAM.*/ -#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_M (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_V 0x1 -#define EFUSE_DIS_RTC_RAM_BOOT_S 7 -/* EFUSE_RD_DIS : R/W ;bitpos:[6:0] ;default: 7'h0 ; */ -/*description: Set this bit to disable reading from BlOCK4-10.*/ -#define EFUSE_RD_DIS 0x0000007F -#define EFUSE_RD_DIS_M ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S)) -#define EFUSE_RD_DIS_V 0x7F -#define EFUSE_RD_DIS_S 0 +/** EFUSE_PGM_DATA0_REG register + * Register 0 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) +/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) +#define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_S 0 -#define EFUSE_RD_DIS_KEY0 (1<<0) -#define EFUSE_RD_DIS_KEY1 (1<<1) -#define EFUSE_RD_DIS_KEY2 (1<<2) -#define EFUSE_RD_DIS_KEY3 (1<<3) -#define EFUSE_RD_DIS_KEY4 (1<<4) -#define EFUSE_RD_DIS_KEY5 (1<<5) -#define EFUSE_RD_DIS_SYS_DATA_PART2 (1<<6) - -#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x008) -/* EFUSE_KEY_PURPOSE_1 : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: Purpose of Key1. Refer to Table KEY_PURPOSE Values.*/ -#define EFUSE_KEY_PURPOSE_1 0x0000000F -#define EFUSE_KEY_PURPOSE_1_M ((EFUSE_KEY_PURPOSE_1_V)<<(EFUSE_KEY_PURPOSE_1_S)) -#define EFUSE_KEY_PURPOSE_1_V 0xF -#define EFUSE_KEY_PURPOSE_1_S 28 -/* EFUSE_KEY_PURPOSE_0 : R/W ;bitpos:[27:24] ;default: 4'h0 ; */ -/*description: Purpose of Key0. Refer to Table KEY_PURPOSE Values.*/ -#define EFUSE_KEY_PURPOSE_0 0x0000000F -#define EFUSE_KEY_PURPOSE_0_M ((EFUSE_KEY_PURPOSE_0_V)<<(EFUSE_KEY_PURPOSE_0_S)) -#define EFUSE_KEY_PURPOSE_0_V 0xF -#define EFUSE_KEY_PURPOSE_0_S 24 -/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : R/W ;bitpos:[23] ;default: 1'h0 ; */ -/*description: Set this bit to enable revoking third secure boot key.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 -/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : R/W ;bitpos:[22] ;default: 1'h0 ; */ -/*description: Set this bit to enable revoking second secure boot key.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 -/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : R/W ;bitpos:[21] ;default: 1'h0 ; */ -/*description: Set this bit to enable revoking first secure boot key.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 -/* EFUSE_SPI_BOOT_CRYPT_CNT : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable*/ -#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_M ((EFUSE_SPI_BOOT_CRYPT_CNT_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_S)) -#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x7 -#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 -/* EFUSE_WAT_DELAY_SEL : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: Selects RTC watchdog timeout threshold.*/ -#define EFUSE_WAT_DELAY_SEL 0x00000003 -#define EFUSE_WAT_DELAY_SEL_M ((EFUSE_WAT_DELAY_SEL_V)<<(EFUSE_WAT_DELAY_SEL_S)) -#define EFUSE_WAT_DELAY_SEL_V 0x3 -#define EFUSE_WAT_DELAY_SEL_S 16 -/* EFUSE_VDD_SPI_DCAP : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ -/*description: Prevents SPI regulator from overshoot.*/ -#define EFUSE_VDD_SPI_DCAP 0x00000003 -#define EFUSE_VDD_SPI_DCAP_M ((EFUSE_VDD_SPI_DCAP_V)<<(EFUSE_VDD_SPI_DCAP_S)) -#define EFUSE_VDD_SPI_DCAP_V 0x3 -#define EFUSE_VDD_SPI_DCAP_S 14 -/* EFUSE_VDD_SPI_INIT : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ -/*description: Adds resistor from LDO output to ground. 0: no resistance*/ -#define EFUSE_VDD_SPI_INIT 0x00000003 -#define EFUSE_VDD_SPI_INIT_M ((EFUSE_VDD_SPI_INIT_V)<<(EFUSE_VDD_SPI_INIT_S)) -#define EFUSE_VDD_SPI_INIT_V 0x3 -#define EFUSE_VDD_SPI_INIT_S 12 -/* EFUSE_VDD_SPI_DCURLIM : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ -/*description: Tunes the current limit threshold of SPI regulator when tieh=0 - about 800 mA/(8+d).*/ -#define EFUSE_VDD_SPI_DCURLIM 0x00000007 -#define EFUSE_VDD_SPI_DCURLIM_M ((EFUSE_VDD_SPI_DCURLIM_V)<<(EFUSE_VDD_SPI_DCURLIM_S)) -#define EFUSE_VDD_SPI_DCURLIM_V 0x7 -#define EFUSE_VDD_SPI_DCURLIM_S 9 -/* EFUSE_VDD_SPI_ENCURLIM : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: Set SPI regulator to 1 to enable output current limit.*/ -#define EFUSE_VDD_SPI_ENCURLIM (BIT(8)) -#define EFUSE_VDD_SPI_ENCURLIM_M (BIT(8)) -#define EFUSE_VDD_SPI_ENCURLIM_V 0x1 -#define EFUSE_VDD_SPI_ENCURLIM_S 8 -/* EFUSE_VDD_SPI_EN_INIT : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: Set SPI regulator to 0 to configure init[1:0]=0.*/ -#define EFUSE_VDD_SPI_EN_INIT (BIT(7)) -#define EFUSE_VDD_SPI_EN_INIT_M (BIT(7)) -#define EFUSE_VDD_SPI_EN_INIT_V 0x1 -#define EFUSE_VDD_SPI_EN_INIT_S 7 -/* EFUSE_VDD_SPI_FORCE : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: Set this bit and force to use the configuration of eFuse to configure VDD_SPI.*/ -#define EFUSE_VDD_SPI_FORCE (BIT(6)) -#define EFUSE_VDD_SPI_FORCE_M (BIT(6)) -#define EFUSE_VDD_SPI_FORCE_V 0x1 -#define EFUSE_VDD_SPI_FORCE_S 6 -/* EFUSE_VDD_SPI_TIEH : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: SPI regulator output is short connected to VDD3P3_RTC_IO.*/ -#define EFUSE_VDD_SPI_TIEH (BIT(5)) -#define EFUSE_VDD_SPI_TIEH_M (BIT(5)) -#define EFUSE_VDD_SPI_TIEH_V 0x1 -#define EFUSE_VDD_SPI_TIEH_S 5 -/* EFUSE_VDD_SPI_XPD : R/W ;bitpos:[4] ;default: 1'h0 ; */ -/*description: SPI regulator power up signal.*/ -#define EFUSE_VDD_SPI_XPD (BIT(4)) -#define EFUSE_VDD_SPI_XPD_M (BIT(4)) -#define EFUSE_VDD_SPI_XPD_V 0x1 -#define EFUSE_VDD_SPI_XPD_S 4 -/* EFUSE_VDD_SPI_DREFL : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ -/*description: SPI regulator low voltage reference.*/ -#define EFUSE_VDD_SPI_DREFL 0x00000003 -#define EFUSE_VDD_SPI_DREFL_M ((EFUSE_VDD_SPI_DREFL_V)<<(EFUSE_VDD_SPI_DREFL_S)) -#define EFUSE_VDD_SPI_DREFL_V 0x3 -#define EFUSE_VDD_SPI_DREFL_S 2 -/* EFUSE_VDD_SPI_DREFM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: SPI regulator medium voltage reference.*/ -#define EFUSE_VDD_SPI_DREFM 0x00000003 -#define EFUSE_VDD_SPI_DREFM_M ((EFUSE_VDD_SPI_DREFM_V)<<(EFUSE_VDD_SPI_DREFM_S)) -#define EFUSE_VDD_SPI_DREFM_V 0x3 -#define EFUSE_VDD_SPI_DREFM_S 0 +/** EFUSE_PGM_DATA1_REG register + * Register 1 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) +/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) +#define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_S 0 -#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0x00c) -/* EFUSE_FLASH_TPUW : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: Configures flash waiting time after power-up in unit of ms. - When the value is 15 the waiting time is 30 ms.*/ -#define EFUSE_FLASH_TPUW 0x0000000F -#define EFUSE_FLASH_TPUW_M ((EFUSE_FLASH_TPUW_V)<<(EFUSE_FLASH_TPUW_S)) -#define EFUSE_FLASH_TPUW_V 0xF -#define EFUSE_FLASH_TPUW_S 28 -/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[27:22] ;default: 6'h0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED1 0x0000003F -#define EFUSE_RPT4_RESERVED1_M ((EFUSE_RPT4_RESERVED1_V)<<(EFUSE_RPT4_RESERVED1_S)) -#define EFUSE_RPT4_RESERVED1_V 0x3F -#define EFUSE_RPT4_RESERVED1_S 22 -/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : R/W ;bitpos:[21] ;default: 1'h0 ; */ -/*description: Set this bit to enable revoking aggressive secure boot.*/ -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x1 -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 -/* EFUSE_SECURE_BOOT_EN : R/W ;bitpos:[20] ;default: 1'h0 ; */ -/*description: Set this bit to enable secure boot.*/ -#define EFUSE_SECURE_BOOT_EN (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_M (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_V 0x1 -#define EFUSE_SECURE_BOOT_EN_S 20 -/* EFUSE_KEY_PURPOSE_6 : R/W ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: Purpose of Key6. Refer to Table KEY_PURPOSE Values.*/ -#define EFUSE_KEY_PURPOSE_6 0x0000000F -#define EFUSE_KEY_PURPOSE_6_M ((EFUSE_KEY_PURPOSE_6_V)<<(EFUSE_KEY_PURPOSE_6_S)) -#define EFUSE_KEY_PURPOSE_6_V 0xF -#define EFUSE_KEY_PURPOSE_6_S 16 -/* EFUSE_KEY_PURPOSE_5 : R/W ;bitpos:[15:12] ;default: 4'h0 ; */ -/*description: Purpose of Key5. Refer to Table KEY_PURPOSE Values.*/ -#define EFUSE_KEY_PURPOSE_5 0x0000000F -#define EFUSE_KEY_PURPOSE_5_M ((EFUSE_KEY_PURPOSE_5_V)<<(EFUSE_KEY_PURPOSE_5_S)) -#define EFUSE_KEY_PURPOSE_5_V 0xF -#define EFUSE_KEY_PURPOSE_5_S 12 -/* EFUSE_KEY_PURPOSE_4 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ -/*description: Purpose of Key4. Refer to Table KEY_PURPOSE Values.*/ -#define EFUSE_KEY_PURPOSE_4 0x0000000F -#define EFUSE_KEY_PURPOSE_4_M ((EFUSE_KEY_PURPOSE_4_V)<<(EFUSE_KEY_PURPOSE_4_S)) -#define EFUSE_KEY_PURPOSE_4_V 0xF -#define EFUSE_KEY_PURPOSE_4_S 8 -/* EFUSE_KEY_PURPOSE_3 : R/W ;bitpos:[7:4] ;default: 4'h0 ; */ -/*description: Purpose of Key3. Refer to Table KEY_PURPOSE Values.*/ -#define EFUSE_KEY_PURPOSE_3 0x0000000F -#define EFUSE_KEY_PURPOSE_3_M ((EFUSE_KEY_PURPOSE_3_V)<<(EFUSE_KEY_PURPOSE_3_S)) -#define EFUSE_KEY_PURPOSE_3_V 0xF -#define EFUSE_KEY_PURPOSE_3_S 4 -/* EFUSE_KEY_PURPOSE_2 : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: Purpose of Key2. Refer to Table KEY_PURPOSE Values.*/ -#define EFUSE_KEY_PURPOSE_2 0x0000000F -#define EFUSE_KEY_PURPOSE_2_M ((EFUSE_KEY_PURPOSE_2_V)<<(EFUSE_KEY_PURPOSE_2_S)) -#define EFUSE_KEY_PURPOSE_2_V 0xF -#define EFUSE_KEY_PURPOSE_2_S 0 +/** EFUSE_PGM_DATA2_REG register + * Register 2 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) +/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) +#define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_S 0 -#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x010) -/* EFUSE_RPT4_RESERVED2 : RO ;bitpos:[31:27] ;default: 5'h0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED2 0x0000001F -#define EFUSE_RPT4_RESERVED2_M ((EFUSE_RPT4_RESERVED2_V)<<(EFUSE_RPT4_RESERVED2_S)) -#define EFUSE_RPT4_RESERVED2_V 0x1F -#define EFUSE_RPT4_RESERVED2_S 27 -/* EFUSE_SECURE_VERSION : R/W ;bitpos:[26:11] ;default: 16'h0 ; */ -/*description: IDF secure version.*/ -#define EFUSE_SECURE_VERSION 0x0000FFFF -#define EFUSE_SECURE_VERSION_M ((EFUSE_SECURE_VERSION_V)<<(EFUSE_SECURE_VERSION_S)) -#define EFUSE_SECURE_VERSION_V 0xFFFF -#define EFUSE_SECURE_VERSION_S 11 -/* EFUSE_FORCE_SEND_RESUME : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: Set this bit to force ROM code to send a resume command during SPI boot.*/ -#define EFUSE_FORCE_SEND_RESUME (BIT(10)) -#define EFUSE_FORCE_SEND_RESUME_M (BIT(10)) -#define EFUSE_FORCE_SEND_RESUME_V 0x1 -#define EFUSE_FORCE_SEND_RESUME_S 10 -/* EFUSE_FLASH_TYPE : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: The type of the interfaced flash. 0: four data lines 1: eight data lines.*/ -#define EFUSE_FLASH_TYPE (BIT(9)) -#define EFUSE_FLASH_TYPE_M (BIT(9)) -#define EFUSE_FLASH_TYPE_V 0x1 -#define EFUSE_FLASH_TYPE_S 9 -/* EFUSE_PIN_POWER_SELECTION : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU*/ -#define EFUSE_PIN_POWER_SELECTION (BIT(8)) -#define EFUSE_PIN_POWER_SELECTION_M (BIT(8)) -#define EFUSE_PIN_POWER_SELECTION_V 0x1 -#define EFUSE_PIN_POWER_SELECTION_S 8 -/* EFUSE_UART_PRINT_CONTROL : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: The type of UART print control.00: Forces to print.01: Controlled - by GPIO46 print at low level.10: Controlled by GPIO46 print at high level.11: Forces to disable print.*/ -#define EFUSE_UART_PRINT_CONTROL 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_M ((EFUSE_UART_PRINT_CONTROL_V)<<(EFUSE_UART_PRINT_CONTROL_S)) -#define EFUSE_UART_PRINT_CONTROL_V 0x3 -#define EFUSE_UART_PRINT_CONTROL_S 6 -/* EFUSE_ENABLE_SECURITY_DOWNLOAD : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: Set this bit to enable security download mode.*/ -#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x1 -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 -/* EFUSE_DIS_USB_DOWNLOAD_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */ -/*description: Set this bit to disable download through USB.*/ -#define EFUSE_DIS_USB_DOWNLOAD_MODE (BIT(4)) -#define EFUSE_DIS_USB_DOWNLOAD_MODE_M (BIT(4)) -#define EFUSE_DIS_USB_DOWNLOAD_MODE_V 0x1 -#define EFUSE_DIS_USB_DOWNLOAD_MODE_S 4 -/* EFUSE_RPT4_RESERVED3 : R/W ;bitpos:[3] ;default: 1'h0 ; */ -/*description: Set this bit to disable tiny basic console in ROM.*/ -#define EFUSE_RPT4_RESERVED3 (BIT(3)) -#define EFUSE_RPT4_RESERVED3_M (BIT(3)) -#define EFUSE_RPT4_RESERVED3_V 0x1 -#define EFUSE_RPT4_RESERVED3_S 3 -/* EFUSE_UART_PRINT_CHANNEL : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: Selectes UART print channel. 0: UART0*/ -#define EFUSE_UART_PRINT_CHANNEL (BIT(2)) -#define EFUSE_UART_PRINT_CHANNEL_M (BIT(2)) -#define EFUSE_UART_PRINT_CHANNEL_V 0x1 -#define EFUSE_UART_PRINT_CHANNEL_S 2 -/* EFUSE_DIS_LEGACY_SPI_BOOT : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4).*/ -#define EFUSE_DIS_LEGACY_SPI_BOOT (BIT(1)) -#define EFUSE_DIS_LEGACY_SPI_BOOT_M (BIT(1)) -#define EFUSE_DIS_LEGACY_SPI_BOOT_V 0x1 -#define EFUSE_DIS_LEGACY_SPI_BOOT_S 1 -/* EFUSE_DIS_DOWNLOAD_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to disable download mode (boot_mode[3:0] = 0 1 2 3 6 7).*/ -#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_M (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MODE_S 0 +/** EFUSE_PGM_DATA3_REG register + * Register 3 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc) +/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 3th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) +#define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_S 0 + +/** EFUSE_PGM_DATA4_REG register + * Register 4 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) +/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 4th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) +#define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_S 0 -#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x014) -/* EFUSE_RPT1_RESERVED0 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT1_RESERVED0 0x000000FF -#define EFUSE_RPT1_RESERVED0_M ((EFUSE_RPT1_RESERVED0_V)<<(EFUSE_RPT1_RESERVED0_S)) -#define EFUSE_RPT1_RESERVED0_V 0xFF -#define EFUSE_RPT1_RESERVED0_S 24 -/* EFUSE_RPT4_RESERVED4 : RO ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED4 0x00FFFFFF -#define EFUSE_RPT4_RESERVED4_M ((EFUSE_RPT4_RESERVED4_V)<<(EFUSE_RPT4_RESERVED4_S)) -#define EFUSE_RPT4_RESERVED4_V 0xFFFFFF -#define EFUSE_RPT4_RESERVED4_S 0 - -#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x018) -/* EFUSE_PGM_DATA_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the sixth 32-bit data to be programmed.*/ -#define EFUSE_PGM_DATA_6 0xFFFFFFFF -#define EFUSE_PGM_DATA_6_M ((EFUSE_PGM_DATA_6_V)<<(EFUSE_PGM_DATA_6_S)) -#define EFUSE_PGM_DATA_6_V 0xFFFFFFFF -#define EFUSE_PGM_DATA_6_S 0 - -#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x01c) -/* EFUSE_PGM_DATA_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The value of pgm data 7.*/ -#define EFUSE_PGM_DATA_7 0xFFFFFFFF -#define EFUSE_PGM_DATA_7_M ((EFUSE_PGM_DATA_7_V)<<(EFUSE_PGM_DATA_7_S)) -#define EFUSE_PGM_DATA_7_V 0xFFFFFFFF -#define EFUSE_PGM_DATA_7_S 0 - -#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x020) -/* EFUSE_PGM_RS_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 0th 32-bit RS code to be programmed.*/ -#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_0_M ((EFUSE_PGM_RS_DATA_0_V)<<(EFUSE_PGM_RS_DATA_0_S)) -#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFF +/** EFUSE_PGM_DATA5_REG register + * Register 5 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) +/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 5th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) +#define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_S 0 + +/** EFUSE_PGM_DATA6_REG register + * Register 6 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) +/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 6th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) +#define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_S 0 + +/** EFUSE_PGM_DATA7_REG register + * Register 7 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c) +/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 7th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) +#define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_S 0 + +/** EFUSE_PGM_CHECK_VALUE0_REG register + * Register 0 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) +/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) +#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_0_S 0 -#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x024) -/* EFUSE_PGM_RS_DATA_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the first 32-bit RS code to be programmed.*/ -#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_1_M ((EFUSE_PGM_RS_DATA_1_V)<<(EFUSE_PGM_RS_DATA_1_S)) -#define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_1_S 0 - -#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x028) -/* EFUSE_PGM_RS_DATA_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the second 32-bit RS code to be programmed.*/ -#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_2_M ((EFUSE_PGM_RS_DATA_2_V)<<(EFUSE_PGM_RS_DATA_2_S)) -#define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_2_S 0 - -#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x02c) -/* EFUSE_WR_DIS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The value of WR_DIS.*/ -#define EFUSE_WR_DIS 0xFFFFFFFF -#define EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S)) -#define EFUSE_WR_DIS_V 0xFFFFFFFF +/** EFUSE_PGM_CHECK_VALUE1_REG register + * Register 1 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) +/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1th 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) +#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_0_S 0 + +/** EFUSE_PGM_CHECK_VALUE2_REG register + * Register 2 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) +/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2th 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) +#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_0_S 0 + +/** EFUSE_RD_WR_DIS_REG register + * Register 0 of BLOCK0. + */ +#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c) +/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; + * Disables programming of individual eFuses. + */ +#define EFUSE_WR_DIS 0xFFFFFFFFU +#define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) +#define EFUSE_WR_DIS_V 0xFFFFFFFFU #define EFUSE_WR_DIS_S 0 -#define EFUSE_WR_DIS_RD_DIS (1<<0) -#define EFUSE_WR_DIS_DIS_RTC_RAM_BOOT (1<<1) -#define EFUSE_WR_DIS_GROUP_1 (1<<2) -#define EFUSE_WR_DIS_GROUP_2 (1<<3) -#define EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT (1<<4) -#define EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0 (1<<5) -#define EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1 (1<<6) -#define EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2 (1<<7) -#define EFUSE_WR_DIS_KEY0_PURPOSE (1<<8) -#define EFUSE_WR_DIS_KEY1_PURPOSE (1<<9) -#define EFUSE_WR_DIS_KEY2_PURPOSE (1<<10) -#define EFUSE_WR_DIS_KEY3_PURPOSE (1<<11) -#define EFUSE_WR_DIS_KEY4_PURPOSE (1<<12) -#define EFUSE_WR_DIS_KEY5_PURPOSE (1<<13) -#define EFUSE_WR_DIS_SECURE_BOOT_EN (1<<15) -#define EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE (1<<16) -#define EFUSE_WR_DIS_GROUP_3 (1<<18) -#define EFUSE_WR_DIS_BLK1 (1<<20) -#define EFUSE_WR_DIS_SYS_DATA_PART1 (1<<21) -#define EFUSE_WR_DIS_USER_DATA (1<<22) -#define EFUSE_WR_DIS_KEY0 (1<<23) -#define EFUSE_WR_DIS_KEY1 (1<<24) -#define EFUSE_WR_DIS_KEY2 (1<<25) -#define EFUSE_WR_DIS_KEY3 (1<<26) -#define EFUSE_WR_DIS_KEY4 (1<<27) -#define EFUSE_WR_DIS_KEY5 (1<<28) -#define EFUSE_WR_DIS_SYS_DATA_PART2 (1<<29) -#define EFUSE_WR_DIS_USB_EXCHG_PINS (1<<30) - - -#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x030) -/* EFUSE_VDD_SPI_DREFH : RO ;bitpos:[31:30] ;default: 2'h0 ; */ -/*description: The value of VDD_SPI_DREFH.*/ -#define EFUSE_VDD_SPI_DREFH 0x00000003 -#define EFUSE_VDD_SPI_DREFH_M ((EFUSE_VDD_SPI_DREFH_V)<<(EFUSE_VDD_SPI_DREFH_S)) -#define EFUSE_VDD_SPI_DREFH_V 0x3 -#define EFUSE_VDD_SPI_DREFH_S 30 -/* EFUSE_VDD_SPI_MODECURLIM : RO ;bitpos:[29] ;default: 1'h0 ; */ -/*description: The value of VDD_SPI_MODECURLIM.*/ -#define EFUSE_VDD_SPI_MODECURLIM (BIT(29)) -#define EFUSE_VDD_SPI_MODECURLIM_M (BIT(29)) -#define EFUSE_VDD_SPI_MODECURLIM_V 0x1 -#define EFUSE_VDD_SPI_MODECURLIM_S 29 -/* EFUSE_RPT4_RESERVED0 : RO ;bitpos:[28:27] ;default: 2'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED0 0x00000003 -#define EFUSE_RPT4_RESERVED0_M ((EFUSE_RPT4_RESERVED0_V)<<(EFUSE_RPT4_RESERVED0_S)) -#define EFUSE_RPT4_RESERVED0_V 0x3 -#define EFUSE_RPT4_RESERVED0_S 27 -/* EFUSE_USB_FORCE_NOPERSIST : RO ;bitpos:[26] ;default: 1'h0 ; */ -/*description: The value of usb_force_nopersist*/ -#define EFUSE_USB_FORCE_NOPERSIST (BIT(26)) -#define EFUSE_USB_FORCE_NOPERSIST_M (BIT(26)) -#define EFUSE_USB_FORCE_NOPERSIST_V 0x1 -#define EFUSE_USB_FORCE_NOPERSIST_S 26 -/* EFUSE_USB_EXT_PHY_ENABLE : RO ;bitpos:[25] ;default: 1'h0 ; */ -/*description: The value of EXT_PHY_ENABLE.*/ -#define EFUSE_USB_EXT_PHY_ENABLE (BIT(25)) -#define EFUSE_USB_EXT_PHY_ENABLE_M (BIT(25)) -#define EFUSE_USB_EXT_PHY_ENABLE_V 0x1 -#define EFUSE_USB_EXT_PHY_ENABLE_S 25 -/* EFUSE_USB_EXCHG_PINS : RO ;bitpos:[24] ;default: 1'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_USB_EXCHG_PINS (BIT(24)) -#define EFUSE_USB_EXCHG_PINS_M (BIT(24)) -#define EFUSE_USB_EXCHG_PINS_V 0x1 -#define EFUSE_USB_EXCHG_PINS_S 24 -/* EFUSE_USB_DREFL : RO ;bitpos:[23:22] ;default: 2'h0 ; */ -/*description: The value of USB_DREFL.*/ -#define EFUSE_USB_DREFL 0x00000003 -#define EFUSE_USB_DREFL_M ((EFUSE_USB_DREFL_V)<<(EFUSE_USB_DREFL_S)) -#define EFUSE_USB_DREFL_V 0x3 -#define EFUSE_USB_DREFL_S 22 -/* EFUSE_USB_DREFH : RO ;bitpos:[21:20] ;default: 2'h0 ; */ -/*description: The value of USB_DREFH.*/ -#define EFUSE_USB_DREFH 0x00000003 -#define EFUSE_USB_DREFH_M ((EFUSE_USB_DREFH_V)<<(EFUSE_USB_DREFH_S)) -#define EFUSE_USB_DREFH_V 0x3 -#define EFUSE_USB_DREFH_S 20 -/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO ;bitpos:[19] ;default: 1'h0 ; */ -/*description: The value of DIS_DOWNLOAD_MANUAL_ENCRYPT.*/ -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(19)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(19)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 19 -/* EFUSE_HARD_DIS_JTAG : RO ;bitpos:[18] ;default: 1'h0 ; */ -/*description: The value of HARD_DIS_JTAG.*/ -#define EFUSE_HARD_DIS_JTAG (BIT(18)) -#define EFUSE_HARD_DIS_JTAG_M (BIT(18)) -#define EFUSE_HARD_DIS_JTAG_V 0x1 -#define EFUSE_HARD_DIS_JTAG_S 18 -/* EFUSE_SOFT_DIS_JTAG : RO ;bitpos:[17] ;default: 1'h0 ; */ -/*description: The value of SOFT_DIS_JTAG.*/ -#define EFUSE_SOFT_DIS_JTAG (BIT(17)) -#define EFUSE_SOFT_DIS_JTAG_M (BIT(17)) -#define EFUSE_SOFT_DIS_JTAG_V 0x1 -#define EFUSE_SOFT_DIS_JTAG_S 17 -/* EFUSE_DIS_EFUSE_ATE_WR : RO ;bitpos:[16] ;default: 1'h0 ; */ -/*description: The value of DIS_EFUSE_ATE_WR.*/ -#define EFUSE_DIS_EFUSE_ATE_WR (BIT(16)) -#define EFUSE_DIS_EFUSE_ATE_WR_M (BIT(16)) -#define EFUSE_DIS_EFUSE_ATE_WR_V 0x1 -#define EFUSE_DIS_EFUSE_ATE_WR_S 16 -/* EFUSE_DIS_BOOT_REMAP : RO ;bitpos:[15] ;default: 1'h0 ; */ -/*description: The value of DIS_BOOT_REMAP.*/ -#define EFUSE_DIS_BOOT_REMAP (BIT(15)) -#define EFUSE_DIS_BOOT_REMAP_M (BIT(15)) -#define EFUSE_DIS_BOOT_REMAP_V 0x1 -#define EFUSE_DIS_BOOT_REMAP_S 15 -/* EFUSE_DIS_CAN : RO ;bitpos:[14] ;default: 1'h0 ; */ -/*description: The value of DIS_CAN.*/ -#define EFUSE_DIS_CAN (BIT(14)) -#define EFUSE_DIS_CAN_M (BIT(14)) -#define EFUSE_DIS_CAN_V 0x1 -#define EFUSE_DIS_CAN_S 14 -/* EFUSE_DIS_USB : RO ;bitpos:[13] ;default: 1'h0 ; */ -/*description: The value of DIS_USB.*/ -#define EFUSE_DIS_USB (BIT(13)) -#define EFUSE_DIS_USB_M (BIT(13)) -#define EFUSE_DIS_USB_V 0x1 -#define EFUSE_DIS_USB_S 13 -/* EFUSE_DIS_FORCE_DOWNLOAD : RO ;bitpos:[12] ;default: 1'h0 ; */ -/*description: The value of DIS_FORCE_DOWNLOAD.*/ -#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_M (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x1 -#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 -/* EFUSE_DIS_DOWNLOAD_DCACHE : RO ;bitpos:[11] ;default: 1'h0 ; */ -/*description: The value of DIS_DOWNLOAD_DCACHE.*/ -#define EFUSE_DIS_DOWNLOAD_DCACHE (BIT(11)) -#define EFUSE_DIS_DOWNLOAD_DCACHE_M (BIT(11)) -#define EFUSE_DIS_DOWNLOAD_DCACHE_V 0x1 -#define EFUSE_DIS_DOWNLOAD_DCACHE_S 11 -/* EFUSE_DIS_DOWNLOAD_ICACHE : RO ;bitpos:[10] ;default: 1'h0 ; */ -/*description: The value of DIS_DOWNLOAD_ICACHE.*/ -#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_M (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x1 -#define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 -/* EFUSE_DIS_DCACHE : RO ;bitpos:[9] ;default: 1'h0 ; */ -/*description: The value of DIS_DCACHE.*/ -#define EFUSE_DIS_DCACHE (BIT(9)) -#define EFUSE_DIS_DCACHE_M (BIT(9)) -#define EFUSE_DIS_DCACHE_V 0x1 -#define EFUSE_DIS_DCACHE_S 9 -/* EFUSE_DIS_ICACHE : RO ;bitpos:[8] ;default: 1'h0 ; */ -/*description: The value of DIS_ICACHE.*/ -#define EFUSE_DIS_ICACHE (BIT(8)) -#define EFUSE_DIS_ICACHE_M (BIT(8)) -#define EFUSE_DIS_ICACHE_V 0x1 -#define EFUSE_DIS_ICACHE_S 8 -/* EFUSE_DIS_RTC_RAM_BOOT : RO ;bitpos:[7] ;default: 1'h0 ; */ -/*description: The value of DIS_RTC_RAM_BOOT.*/ -#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_M (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_V 0x1 -#define EFUSE_DIS_RTC_RAM_BOOT_S 7 -/* EFUSE_RD_DIS : RO ;bitpos:[6:0] ;default: 7'h0 ; */ -/*description: The value of RD_DIS.*/ -#define EFUSE_RD_DIS 0x0000007F -#define EFUSE_RD_DIS_M ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S)) -#define EFUSE_RD_DIS_V 0x7F +/** EFUSE_RD_REPEAT_DATA0_REG register + * Register 1 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) +/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; + * Disables software reading from individual eFuse blocks (BLOCK4-10). + */ +#define EFUSE_RD_DIS 0x0000007FU +#define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) +#define EFUSE_RD_DIS_V 0x0000007FU #define EFUSE_RD_DIS_S 0 +/** EFUSE_DIS_RTC_RAM_BOOT : RO; bitpos: [7]; default: 0; + * Reserved. + */ +#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) +#define EFUSE_DIS_RTC_RAM_BOOT_M (EFUSE_DIS_RTC_RAM_BOOT_V << EFUSE_DIS_RTC_RAM_BOOT_S) +#define EFUSE_DIS_RTC_RAM_BOOT_V 0x00000001U +#define EFUSE_DIS_RTC_RAM_BOOT_S 7 +/** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0; + * Set this bit to disable Icache. + */ +#define EFUSE_DIS_ICACHE (BIT(8)) +#define EFUSE_DIS_ICACHE_M (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S) +#define EFUSE_DIS_ICACHE_V 0x00000001U +#define EFUSE_DIS_ICACHE_S 8 +/** EFUSE_DIS_DCACHE : RO; bitpos: [9]; default: 0; + * Set this bit to disable Dcache. + */ +#define EFUSE_DIS_DCACHE (BIT(9)) +#define EFUSE_DIS_DCACHE_M (EFUSE_DIS_DCACHE_V << EFUSE_DIS_DCACHE_S) +#define EFUSE_DIS_DCACHE_V 0x00000001U +#define EFUSE_DIS_DCACHE_S 9 +/** EFUSE_DIS_DOWNLOAD_ICACHE : RO; bitpos: [10]; default: 0; + * Disables Icache when SoC is in Download mode. + */ +#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) +#define EFUSE_DIS_DOWNLOAD_ICACHE_M (EFUSE_DIS_DOWNLOAD_ICACHE_V << EFUSE_DIS_DOWNLOAD_ICACHE_S) +#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 +/** EFUSE_DIS_DOWNLOAD_DCACHE : RO; bitpos: [11]; default: 0; + * Disables Dcache when SoC is in Download mode. + */ +#define EFUSE_DIS_DOWNLOAD_DCACHE (BIT(11)) +#define EFUSE_DIS_DOWNLOAD_DCACHE_M (EFUSE_DIS_DOWNLOAD_DCACHE_V << EFUSE_DIS_DOWNLOAD_DCACHE_S) +#define EFUSE_DIS_DOWNLOAD_DCACHE_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_DCACHE_S 11 +/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0; + * Set this bit to disable the function that forces chip into download mode. + */ +#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x00000001U +#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 +/** EFUSE_DIS_USB : RO; bitpos: [13]; default: 0; + * Set this bit to disable USB OTG function. + */ +#define EFUSE_DIS_USB (BIT(13)) +#define EFUSE_DIS_USB_M (EFUSE_DIS_USB_V << EFUSE_DIS_USB_S) +#define EFUSE_DIS_USB_V 0x00000001U +#define EFUSE_DIS_USB_S 13 +/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0; + * Set this bit to disable the TWAI Controller function. + */ +#define EFUSE_DIS_TWAI (BIT(14)) +#define EFUSE_DIS_TWAI_M (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S) +#define EFUSE_DIS_TWAI_V 0x00000001U +#define EFUSE_DIS_TWAI_S 14 +/** EFUSE_DIS_BOOT_REMAP : RO; bitpos: [15]; default: 0; + * Disables capability to Remap RAM to ROM address space. + */ +#define EFUSE_DIS_BOOT_REMAP (BIT(15)) +#define EFUSE_DIS_BOOT_REMAP_M (EFUSE_DIS_BOOT_REMAP_V << EFUSE_DIS_BOOT_REMAP_S) +#define EFUSE_DIS_BOOT_REMAP_V 0x00000001U +#define EFUSE_DIS_BOOT_REMAP_S 15 +/** EFUSE_RPT4_RESERVED5 : RO; bitpos: [16]; default: 0; + * Reserved (used for four backups method). + */ +#define EFUSE_RPT4_RESERVED5 (BIT(16)) +#define EFUSE_RPT4_RESERVED5_M (EFUSE_RPT4_RESERVED5_V << EFUSE_RPT4_RESERVED5_S) +#define EFUSE_RPT4_RESERVED5_V 0x00000001U +#define EFUSE_RPT4_RESERVED5_S 16 +/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [17]; default: 0; + * Software disables JTAG. When software disabled, JTAG can be activated temporarily + * by HMAC peripheral. + */ +#define EFUSE_SOFT_DIS_JTAG (BIT(17)) +#define EFUSE_SOFT_DIS_JTAG_M (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S) +#define EFUSE_SOFT_DIS_JTAG_V 0x00000001U +#define EFUSE_SOFT_DIS_JTAG_S 17 +/** EFUSE_HARD_DIS_JTAG : RO; bitpos: [18]; default: 0; + * Hardware disables JTAG permanently. + */ +#define EFUSE_HARD_DIS_JTAG (BIT(18)) +#define EFUSE_HARD_DIS_JTAG_M (EFUSE_HARD_DIS_JTAG_V << EFUSE_HARD_DIS_JTAG_S) +#define EFUSE_HARD_DIS_JTAG_V 0x00000001U +#define EFUSE_HARD_DIS_JTAG_S 18 +/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [19]; default: 0; + * Disables flash encryption when in download boot modes. + */ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(19)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 19 +/** EFUSE_USB_DREFH : RO; bitpos: [21:20]; default: 0; + * Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored + * in eFuse. + */ +#define EFUSE_USB_DREFH 0x00000003U +#define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S) +#define EFUSE_USB_DREFH_V 0x00000003U +#define EFUSE_USB_DREFH_S 20 +/** EFUSE_USB_DREFL : RO; bitpos: [23:22]; default: 0; + * Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, + * stored in eFuse. + */ +#define EFUSE_USB_DREFL 0x00000003U +#define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S) +#define EFUSE_USB_DREFL_V 0x00000003U +#define EFUSE_USB_DREFL_S 22 +/** EFUSE_USB_EXCHG_PINS : RO; bitpos: [24]; default: 0; + * Set this bit to exchange USB D+ and D- pins. + */ +#define EFUSE_USB_EXCHG_PINS (BIT(24)) +#define EFUSE_USB_EXCHG_PINS_M (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S) +#define EFUSE_USB_EXCHG_PINS_V 0x00000001U +#define EFUSE_USB_EXCHG_PINS_S 24 +/** EFUSE_USB_EXT_PHY_ENABLE : RO; bitpos: [25]; default: 0; + * Set this bit to enable external USB PHY. + */ +#define EFUSE_USB_EXT_PHY_ENABLE (BIT(25)) +#define EFUSE_USB_EXT_PHY_ENABLE_M (EFUSE_USB_EXT_PHY_ENABLE_V << EFUSE_USB_EXT_PHY_ENABLE_S) +#define EFUSE_USB_EXT_PHY_ENABLE_V 0x00000001U +#define EFUSE_USB_EXT_PHY_ENABLE_S 25 +/** EFUSE_USB_FORCE_NOPERSIST : RO; bitpos: [26]; default: 0; + * If set, forces USB BVALID to 1. + */ +#define EFUSE_USB_FORCE_NOPERSIST (BIT(26)) +#define EFUSE_USB_FORCE_NOPERSIST_M (EFUSE_USB_FORCE_NOPERSIST_V << EFUSE_USB_FORCE_NOPERSIST_S) +#define EFUSE_USB_FORCE_NOPERSIST_V 0x00000001U +#define EFUSE_USB_FORCE_NOPERSIST_S 26 +/** EFUSE_BLOCK0_VERSION : R; bitpos: [28:27]; default: 0; + * BLOCK0 efuse version + */ +#define EFUSE_BLOCK0_VERSION 0x00000003U +#define EFUSE_BLOCK0_VERSION_M (EFUSE_BLOCK0_VERSION_V << EFUSE_BLOCK0_VERSION_S) +#define EFUSE_BLOCK0_VERSION_V 0x00000003U +#define EFUSE_BLOCK0_VERSION_S 27 +/** EFUSE_VDD_SPI_MODECURLIM : RO; bitpos: [29]; default: 0; + * SPI regulator switches current limit mode. + */ +#define EFUSE_VDD_SPI_MODECURLIM (BIT(29)) +#define EFUSE_VDD_SPI_MODECURLIM_M (EFUSE_VDD_SPI_MODECURLIM_V << EFUSE_VDD_SPI_MODECURLIM_S) +#define EFUSE_VDD_SPI_MODECURLIM_V 0x00000001U +#define EFUSE_VDD_SPI_MODECURLIM_S 29 +/** EFUSE_VDD_SPI_DREFH : RO; bitpos: [31:30]; default: 0; + * SPI regulator high voltage reference. + */ +#define EFUSE_VDD_SPI_DREFH 0x00000003U +#define EFUSE_VDD_SPI_DREFH_M (EFUSE_VDD_SPI_DREFH_V << EFUSE_VDD_SPI_DREFH_S) +#define EFUSE_VDD_SPI_DREFH_V 0x00000003U +#define EFUSE_VDD_SPI_DREFH_S 30 -#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x034) -/* EFUSE_KEY_PURPOSE_1 : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_1.*/ -#define EFUSE_KEY_PURPOSE_1 0x0000000F -#define EFUSE_KEY_PURPOSE_1_M ((EFUSE_KEY_PURPOSE_1_V)<<(EFUSE_KEY_PURPOSE_1_S)) -#define EFUSE_KEY_PURPOSE_1_V 0xF -#define EFUSE_KEY_PURPOSE_1_S 28 -/* EFUSE_KEY_PURPOSE_0 : RO ;bitpos:[27:24] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_0.*/ -#define EFUSE_KEY_PURPOSE_0 0x0000000F -#define EFUSE_KEY_PURPOSE_0_M ((EFUSE_KEY_PURPOSE_0_V)<<(EFUSE_KEY_PURPOSE_0_S)) -#define EFUSE_KEY_PURPOSE_0_V 0xF -#define EFUSE_KEY_PURPOSE_0_S 24 -/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO ;bitpos:[23] ;default: 1'h0 ; */ -/*description: The value of SECURE_BOOT_KEY_REVOKE2.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 -/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO ;bitpos:[22] ;default: 1'h0 ; */ -/*description: The value of SECURE_BOOT_KEY_REVOKE1.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 -/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO ;bitpos:[21] ;default: 1'h0 ; */ -/*description: The value of SECURE_BOOT_KEY_REVOKE0.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 -/* EFUSE_SPI_BOOT_CRYPT_CNT : RO ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: The value of SPI_BOOT_CRYPT_CNT.*/ -#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_M ((EFUSE_SPI_BOOT_CRYPT_CNT_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_S)) -#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x7 -#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 -/* EFUSE_WDT_DELAY_SEL : RO ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: The value of WDT_DELAY_SEL.*/ -#define EFUSE_WDT_DELAY_SEL 0x00000003 -#define EFUSE_WDT_DELAY_SEL_M ((EFUSE_WDT_DELAY_SEL_V)<<(EFUSE_WDT_DELAY_SEL_S)) -#define EFUSE_WDT_DELAY_SEL_V 0x3 -#define EFUSE_WDT_DELAY_SEL_S 16 -/* EFUSE_VDD_SPI_DCAP : RO ;bitpos:[15:14] ;default: 2'h0 ; */ -/*description: The value of REG_VDD_SPI_DCAP.*/ -#define EFUSE_VDD_SPI_DCAP 0x00000003 -#define EFUSE_VDD_SPI_DCAP_M ((EFUSE_VDD_SPI_DCAP_V)<<(EFUSE_VDD_SPI_DCAP_S)) -#define EFUSE_VDD_SPI_DCAP_V 0x3 -#define EFUSE_VDD_SPI_DCAP_S 14 -/* EFUSE_VDD_SPI_INIT : RO ;bitpos:[13:12] ;default: 2'h0 ; */ -/*description: The value of VDD_SPI_INIT.*/ -#define EFUSE_VDD_SPI_INIT 0x00000003 -#define EFUSE_VDD_SPI_INIT_M ((EFUSE_VDD_SPI_INIT_V)<<(EFUSE_VDD_SPI_INIT_S)) -#define EFUSE_VDD_SPI_INIT_V 0x3 -#define EFUSE_VDD_SPI_INIT_S 12 -/* EFUSE_VDD_SPI_DCURLIM : RO ;bitpos:[11:9] ;default: 3'h0 ; */ -/*description: The value of VDD_SPI_DCURLIM.*/ -#define EFUSE_VDD_SPI_DCURLIM 0x00000007 -#define EFUSE_VDD_SPI_DCURLIM_M ((EFUSE_VDD_SPI_DCURLIM_V)<<(EFUSE_VDD_SPI_DCURLIM_S)) -#define EFUSE_VDD_SPI_DCURLIM_V 0x7 -#define EFUSE_VDD_SPI_DCURLIM_S 9 -/* EFUSE_VDD_SPI_ENCURLIM : RO ;bitpos:[8] ;default: 1'h0 ; */ -/*description: The value of VDD_SPI_ENCURLIM.*/ -#define EFUSE_VDD_SPI_ENCURLIM (BIT(8)) -#define EFUSE_VDD_SPI_ENCURLIM_M (BIT(8)) -#define EFUSE_VDD_SPI_ENCURLIM_V 0x1 -#define EFUSE_VDD_SPI_ENCURLIM_S 8 -/* EFUSE_VDD_SPI_EN_INIT : RO ;bitpos:[7] ;default: 1'h0 ; */ -/*description: The value of VDD_SPI_EN_INIT.*/ -#define EFUSE_VDD_SPI_EN_INIT (BIT(7)) -#define EFUSE_VDD_SPI_EN_INIT_M (BIT(7)) -#define EFUSE_VDD_SPI_EN_INIT_V 0x1 -#define EFUSE_VDD_SPI_EN_INIT_S 7 -/* EFUSE_VDD_SPI_FORCE : RO ;bitpos:[6] ;default: 1'h0 ; */ -/*description: The value of VDD_SPI_FORCE.*/ -#define EFUSE_VDD_SPI_FORCE (BIT(6)) -#define EFUSE_VDD_SPI_FORCE_M (BIT(6)) -#define EFUSE_VDD_SPI_FORCE_V 0x1 -#define EFUSE_VDD_SPI_FORCE_S 6 -/* EFUSE_VDD_SPI_TIEH : RO ;bitpos:[5] ;default: 1'h0 ; */ -/*description: The value of VDD_SPI_TIEH.*/ -#define EFUSE_VDD_SPI_TIEH (BIT(5)) -#define EFUSE_VDD_SPI_TIEH_M (BIT(5)) -#define EFUSE_VDD_SPI_TIEH_V 0x1 -#define EFUSE_VDD_SPI_TIEH_S 5 -/* EFUSE_VDD_SPI_XPD : RO ;bitpos:[4] ;default: 1'h0 ; */ -/*description: The value of VDD_SPI_XPD.*/ -#define EFUSE_VDD_SPI_XPD (BIT(4)) -#define EFUSE_VDD_SPI_XPD_M (BIT(4)) -#define EFUSE_VDD_SPI_XPD_V 0x1 -#define EFUSE_VDD_SPI_XPD_S 4 -/* EFUSE_VDD_SPI_DREFL : RO ;bitpos:[3:2] ;default: 2'h0 ; */ -/*description: The value of VDD_SPI_DREFL.*/ -#define EFUSE_VDD_SPI_DREFL 0x00000003 -#define EFUSE_VDD_SPI_DREFL_M ((EFUSE_VDD_SPI_DREFL_V)<<(EFUSE_VDD_SPI_DREFL_S)) -#define EFUSE_VDD_SPI_DREFL_V 0x3 -#define EFUSE_VDD_SPI_DREFL_S 2 -/* EFUSE_VDD_SPI_DREFM : RO ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: The value of VDD_SPI_DREFM.*/ -#define EFUSE_VDD_SPI_DREFM 0x00000003 -#define EFUSE_VDD_SPI_DREFM_M ((EFUSE_VDD_SPI_DREFM_V)<<(EFUSE_VDD_SPI_DREFM_S)) -#define EFUSE_VDD_SPI_DREFM_V 0x3 +/** EFUSE_RD_REPEAT_DATA1_REG register + * Register 2 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) +/** EFUSE_VDD_SPI_DREFM : RO; bitpos: [1:0]; default: 0; + * SPI regulator medium voltage reference. + */ +#define EFUSE_VDD_SPI_DREFM 0x00000003U +#define EFUSE_VDD_SPI_DREFM_M (EFUSE_VDD_SPI_DREFM_V << EFUSE_VDD_SPI_DREFM_S) +#define EFUSE_VDD_SPI_DREFM_V 0x00000003U #define EFUSE_VDD_SPI_DREFM_S 0 +/** EFUSE_VDD_SPI_DREFL : RO; bitpos: [3:2]; default: 0; + * SPI regulator low voltage reference. + */ +#define EFUSE_VDD_SPI_DREFL 0x00000003U +#define EFUSE_VDD_SPI_DREFL_M (EFUSE_VDD_SPI_DREFL_V << EFUSE_VDD_SPI_DREFL_S) +#define EFUSE_VDD_SPI_DREFL_V 0x00000003U +#define EFUSE_VDD_SPI_DREFL_S 2 +/** EFUSE_VDD_SPI_XPD : RO; bitpos: [4]; default: 0; + * If VDD_SPI_FORCE is 1, this value determines if the VDD_SPI regulator is powered on. + */ +#define EFUSE_VDD_SPI_XPD (BIT(4)) +#define EFUSE_VDD_SPI_XPD_M (EFUSE_VDD_SPI_XPD_V << EFUSE_VDD_SPI_XPD_S) +#define EFUSE_VDD_SPI_XPD_V 0x00000001U +#define EFUSE_VDD_SPI_XPD_S 4 +/** EFUSE_VDD_SPI_TIEH : RO; bitpos: [5]; default: 0; + * If VDD_SPI_FORCE is 1, determines VDD_SPI voltage. 0: VDD_SPI connects to 1.8 V + * LDO. 1: VDD_SPI connects to VDD_RTC_IO. + */ +#define EFUSE_VDD_SPI_TIEH (BIT(5)) +#define EFUSE_VDD_SPI_TIEH_M (EFUSE_VDD_SPI_TIEH_V << EFUSE_VDD_SPI_TIEH_S) +#define EFUSE_VDD_SPI_TIEH_V 0x00000001U +#define EFUSE_VDD_SPI_TIEH_S 5 +/** EFUSE_VDD_SPI_FORCE : RO; bitpos: [6]; default: 0; + * Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TIEH to configure VDD_SPI LDO. + */ +#define EFUSE_VDD_SPI_FORCE (BIT(6)) +#define EFUSE_VDD_SPI_FORCE_M (EFUSE_VDD_SPI_FORCE_V << EFUSE_VDD_SPI_FORCE_S) +#define EFUSE_VDD_SPI_FORCE_V 0x00000001U +#define EFUSE_VDD_SPI_FORCE_S 6 +/** EFUSE_VDD_SPI_EN_INIT : RO; bitpos: [7]; default: 0; + * Set SPI regulator to 0 to configure init[1:0]=0. + */ +#define EFUSE_VDD_SPI_EN_INIT (BIT(7)) +#define EFUSE_VDD_SPI_EN_INIT_M (EFUSE_VDD_SPI_EN_INIT_V << EFUSE_VDD_SPI_EN_INIT_S) +#define EFUSE_VDD_SPI_EN_INIT_V 0x00000001U +#define EFUSE_VDD_SPI_EN_INIT_S 7 +/** EFUSE_VDD_SPI_ENCURLIM : RO; bitpos: [8]; default: 0; + * Set SPI regulator to 1 to enable output current limit. + */ +#define EFUSE_VDD_SPI_ENCURLIM (BIT(8)) +#define EFUSE_VDD_SPI_ENCURLIM_M (EFUSE_VDD_SPI_ENCURLIM_V << EFUSE_VDD_SPI_ENCURLIM_S) +#define EFUSE_VDD_SPI_ENCURLIM_V 0x00000001U +#define EFUSE_VDD_SPI_ENCURLIM_S 8 +/** EFUSE_VDD_SPI_DCURLIM : RO; bitpos: [11:9]; default: 0; + * Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d). + */ +#define EFUSE_VDD_SPI_DCURLIM 0x00000007U +#define EFUSE_VDD_SPI_DCURLIM_M (EFUSE_VDD_SPI_DCURLIM_V << EFUSE_VDD_SPI_DCURLIM_S) +#define EFUSE_VDD_SPI_DCURLIM_V 0x00000007U +#define EFUSE_VDD_SPI_DCURLIM_S 9 +/** EFUSE_VDD_SPI_INIT : RO; bitpos: [13:12]; default: 0; + * Adds resistor from LDO output to ground. 0: no resistance. 1: 6 K. 2: 4 K. 3: 2 K. + */ +#define EFUSE_VDD_SPI_INIT 0x00000003U +#define EFUSE_VDD_SPI_INIT_M (EFUSE_VDD_SPI_INIT_V << EFUSE_VDD_SPI_INIT_S) +#define EFUSE_VDD_SPI_INIT_V 0x00000003U +#define EFUSE_VDD_SPI_INIT_S 12 +/** EFUSE_VDD_SPI_DCAP : RO; bitpos: [15:14]; default: 0; + * Prevents SPI regulator from overshoot. + */ +#define EFUSE_VDD_SPI_DCAP 0x00000003U +#define EFUSE_VDD_SPI_DCAP_M (EFUSE_VDD_SPI_DCAP_V << EFUSE_VDD_SPI_DCAP_S) +#define EFUSE_VDD_SPI_DCAP_V 0x00000003U +#define EFUSE_VDD_SPI_DCAP_S 14 +/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0; + * Selects RTC watchdog timeout threshold at startup. 0: 40,000 slow clock cycles. 1: + * 80,000 slow clock cycles. 2: 160,000 slow clock cycles. 3: 320,000 slow clock + * cycles. + */ +#define EFUSE_WDT_DELAY_SEL 0x00000003U +#define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) +#define EFUSE_WDT_DELAY_SEL_V 0x00000003U +#define EFUSE_WDT_DELAY_SEL_S 16 +/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0; + * Enables encryption and decryption, when an SPI boot mode is set. Feature is enabled + * 1 or 3 bits are set in the eFuse, disabled otherwise. + */ +#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 +/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0; + * If set, revokes use of secure boot key digest 0. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 +/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0; + * If set, revokes use of secure boot key digest 1. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 +/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0; + * If set, revokes use of secure boot key digest 2. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 +/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0; + * Purpose of KEY0. Refer to Table Key Purpose Values. + */ +#define EFUSE_KEY_PURPOSE_0 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_M (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S) +#define EFUSE_KEY_PURPOSE_0_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_S 24 +/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0; + * Purpose of KEY1. Refer to Table Key Purpose Values. + */ +#define EFUSE_KEY_PURPOSE_1 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_M (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S) +#define EFUSE_KEY_PURPOSE_1_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_S 28 -#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x038) -/* EFUSE_FLASH_TPUW : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: The value of FLASH_TPUW.*/ -#define EFUSE_FLASH_TPUW 0x0000000F -#define EFUSE_FLASH_TPUW_M ((EFUSE_FLASH_TPUW_V)<<(EFUSE_FLASH_TPUW_S)) -#define EFUSE_FLASH_TPUW_V 0xF -#define EFUSE_FLASH_TPUW_S 28 -/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[27:22] ;default: 6'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED1 0x0000003F -#define EFUSE_RPT4_RESERVED1_M ((EFUSE_RPT4_RESERVED1_V)<<(EFUSE_RPT4_RESERVED1_S)) -#define EFUSE_RPT4_RESERVED1_V 0x3F -#define EFUSE_RPT4_RESERVED1_S 22 -/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO ;bitpos:[21] ;default: 1'h0 ; */ -/*description: The value of SECURE_BOOT_AGGRESSIVE_REVOKE.*/ -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x1 -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 -/* EFUSE_SECURE_BOOT_EN : RO ;bitpos:[20] ;default: 1'h0 ; */ -/*description: The value of SECURE_BOOT_EN.*/ -#define EFUSE_SECURE_BOOT_EN (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_M (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_V 0x1 -#define EFUSE_SECURE_BOOT_EN_S 20 -/* EFUSE_KEY_PURPOSE_6 : RO ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_6.*/ -#define EFUSE_KEY_PURPOSE_6 0x0000000F -#define EFUSE_KEY_PURPOSE_6_M ((EFUSE_KEY_PURPOSE_6_V)<<(EFUSE_KEY_PURPOSE_6_S)) -#define EFUSE_KEY_PURPOSE_6_V 0xF -#define EFUSE_KEY_PURPOSE_6_S 16 -/* EFUSE_KEY_PURPOSE_5 : RO ;bitpos:[15:12] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_5.*/ -#define EFUSE_KEY_PURPOSE_5 0x0000000F -#define EFUSE_KEY_PURPOSE_5_M ((EFUSE_KEY_PURPOSE_5_V)<<(EFUSE_KEY_PURPOSE_5_S)) -#define EFUSE_KEY_PURPOSE_5_V 0xF -#define EFUSE_KEY_PURPOSE_5_S 12 -/* EFUSE_KEY_PURPOSE_4 : RO ;bitpos:[11:8] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_4.*/ -#define EFUSE_KEY_PURPOSE_4 0x0000000F -#define EFUSE_KEY_PURPOSE_4_M ((EFUSE_KEY_PURPOSE_4_V)<<(EFUSE_KEY_PURPOSE_4_S)) -#define EFUSE_KEY_PURPOSE_4_V 0xF -#define EFUSE_KEY_PURPOSE_4_S 8 -/* EFUSE_KEY_PURPOSE_3 : RO ;bitpos:[7:4] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_3.*/ -#define EFUSE_KEY_PURPOSE_3 0x0000000F -#define EFUSE_KEY_PURPOSE_3_M ((EFUSE_KEY_PURPOSE_3_V)<<(EFUSE_KEY_PURPOSE_3_S)) -#define EFUSE_KEY_PURPOSE_3_V 0xF -#define EFUSE_KEY_PURPOSE_3_S 4 -/* EFUSE_KEY_PURPOSE_2 : RO ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_2.*/ -#define EFUSE_KEY_PURPOSE_2 0x0000000F -#define EFUSE_KEY_PURPOSE_2_M ((EFUSE_KEY_PURPOSE_2_V)<<(EFUSE_KEY_PURPOSE_2_S)) -#define EFUSE_KEY_PURPOSE_2_V 0xF +/** EFUSE_RD_REPEAT_DATA2_REG register + * Register 3 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) +/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0; + * Purpose of KEY2. Refer to Table Key Purpose Values. + */ +#define EFUSE_KEY_PURPOSE_2 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_M (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S) +#define EFUSE_KEY_PURPOSE_2_V 0x0000000FU #define EFUSE_KEY_PURPOSE_2_S 0 +/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0; + * Purpose of KEY3. Refer to Table Key Purpose Values. + */ +#define EFUSE_KEY_PURPOSE_3 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_M (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S) +#define EFUSE_KEY_PURPOSE_3_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_S 4 +/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0; + * Purpose of KEY4. Refer to Table Key Purpose Values. + */ +#define EFUSE_KEY_PURPOSE_4 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_M (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S) +#define EFUSE_KEY_PURPOSE_4_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_S 8 +/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0; + * Purpose of KEY5. Refer to Table Key Purpose Values. + */ +#define EFUSE_KEY_PURPOSE_5 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S) +#define EFUSE_KEY_PURPOSE_5_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_S 12 +/** EFUSE_KEY_PURPOSE_6 : RO; bitpos: [19:16]; default: 0; + * Purpose of KEY6. Refer to Table Key Purpose Values. + */ +#define EFUSE_KEY_PURPOSE_6 0x0000000FU +#define EFUSE_KEY_PURPOSE_6_M (EFUSE_KEY_PURPOSE_6_V << EFUSE_KEY_PURPOSE_6_S) +#define EFUSE_KEY_PURPOSE_6_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_6_S 16 +/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0; + * Set this bit to enable secure boot. + */ +#define EFUSE_SECURE_BOOT_EN (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) +#define EFUSE_SECURE_BOOT_EN_V 0x00000001U +#define EFUSE_SECURE_BOOT_EN_S 20 +/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0; + * Set this bit to enable aggressive secure boot key revocation mode. + */ +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001U +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 +/** EFUSE_RPT4_RESERVED1 : RO; bitpos: [27:22]; default: 0; + * Reserved (used for four backups method). + */ +#define EFUSE_RPT4_RESERVED1 0x0000003FU +#define EFUSE_RPT4_RESERVED1_M (EFUSE_RPT4_RESERVED1_V << EFUSE_RPT4_RESERVED1_S) +#define EFUSE_RPT4_RESERVED1_V 0x0000003FU +#define EFUSE_RPT4_RESERVED1_S 22 +/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0; + * Configures flash startup delay after SoC power-up, in unit of (ms/2). When the + * value is 15, delay is 7.5 ms. + */ +#define EFUSE_FLASH_TPUW 0x0000000FU +#define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S) +#define EFUSE_FLASH_TPUW_V 0x0000000FU +#define EFUSE_FLASH_TPUW_S 28 -#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x03c) -/* EFUSE_RPT4_RESERVED2 : RO ;bitpos:[31:27] ;default: 5'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED2 0x0000001F -#define EFUSE_RPT4_RESERVED2_M ((EFUSE_RPT4_RESERVED2_V)<<(EFUSE_RPT4_RESERVED2_S)) -#define EFUSE_RPT4_RESERVED2_V 0x1F -#define EFUSE_RPT4_RESERVED2_S 27 -/* EFUSE_SECURE_VERSION : RO ;bitpos:[26:11] ;default: 16'h0 ; */ -/*description: The value of SECURE_VERSION.*/ -#define EFUSE_SECURE_VERSION 0x0000FFFF -#define EFUSE_SECURE_VERSION_M ((EFUSE_SECURE_VERSION_V)<<(EFUSE_SECURE_VERSION_S)) -#define EFUSE_SECURE_VERSION_V 0xFFFF -#define EFUSE_SECURE_VERSION_S 11 -/* EFUSE_FORCE_SEND_RESUME : RO ;bitpos:[10] ;default: 1'h0 ; */ -/*description: The value of FORCE_SEND_RESUME.*/ -#define EFUSE_FORCE_SEND_RESUME (BIT(10)) -#define EFUSE_FORCE_SEND_RESUME_M (BIT(10)) -#define EFUSE_FORCE_SEND_RESUME_V 0x1 -#define EFUSE_FORCE_SEND_RESUME_S 10 -/* EFUSE_FLASH_TYPE : RO ;bitpos:[9] ;default: 1'h0 ; */ -/*description: The value of FLASH_TYPE.*/ -#define EFUSE_FLASH_TYPE (BIT(9)) -#define EFUSE_FLASH_TYPE_M (BIT(9)) -#define EFUSE_FLASH_TYPE_V 0x1 -#define EFUSE_FLASH_TYPE_S 9 -/* EFUSE_PIN_POWER_SELECTION : RO ;bitpos:[8] ;default: 1'h0 ; */ -/*description: The value of PIN_POWER_SELECTION.*/ -#define EFUSE_PIN_POWER_SELECTION (BIT(8)) -#define EFUSE_PIN_POWER_SELECTION_M (BIT(8)) -#define EFUSE_PIN_POWER_SELECTION_V 0x1 -#define EFUSE_PIN_POWER_SELECTION_S 8 -/* EFUSE_UART_PRINT_CONTROL : RO ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: The value of UART_PRINT_CONTROL.*/ -#define EFUSE_UART_PRINT_CONTROL 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_M ((EFUSE_UART_PRINT_CONTROL_V)<<(EFUSE_UART_PRINT_CONTROL_S)) -#define EFUSE_UART_PRINT_CONTROL_V 0x3 -#define EFUSE_UART_PRINT_CONTROL_S 6 -/* EFUSE_ENABLE_SECURITY_DOWNLOAD : RO ;bitpos:[5] ;default: 1'h0 ; */ -/*description: The value of ENABLE_SECURITY_DOWNLOAD.*/ -#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x1 -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 -/* EFUSE_DIS_USB_DOWNLOAD_MODE : RO ;bitpos:[4] ;default: 1'h0 ; */ -/*description: The value of DIS_USB_DOWNLOAD_MODE.*/ -#define EFUSE_DIS_USB_DOWNLOAD_MODE (BIT(4)) -#define EFUSE_DIS_USB_DOWNLOAD_MODE_M (BIT(4)) -#define EFUSE_DIS_USB_DOWNLOAD_MODE_V 0x1 -#define EFUSE_DIS_USB_DOWNLOAD_MODE_S 4 -/* EFUSE_RPT4_RESERVED3 : RO ;bitpos:[3] ;default: 1'h0 ; */ -/*description: The value of RPT4_RESERVED4.*/ -#define EFUSE_RPT4_RESERVED3 (BIT(3)) -#define EFUSE_RPT4_RESERVED3_M (BIT(3)) -#define EFUSE_RPT4_RESERVED3_V 0x1 -#define EFUSE_RPT4_RESERVED3_S 3 -/* EFUSE_UART_PRINT_CHANNEL : RO ;bitpos:[2] ;default: 1'h0 ; */ -/*description: The value of UART_PRINT_CHANNEL.*/ -#define EFUSE_UART_PRINT_CHANNEL (BIT(2)) -#define EFUSE_UART_PRINT_CHANNEL_M (BIT(2)) -#define EFUSE_UART_PRINT_CHANNEL_V 0x1 -#define EFUSE_UART_PRINT_CHANNEL_S 2 -/* EFUSE_DIS_LEGACY_SPI_BOOT : RO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: The value of DIS_LEGACY_SPI_BOOT.*/ -#define EFUSE_DIS_LEGACY_SPI_BOOT (BIT(1)) -#define EFUSE_DIS_LEGACY_SPI_BOOT_M (BIT(1)) -#define EFUSE_DIS_LEGACY_SPI_BOOT_V 0x1 -#define EFUSE_DIS_LEGACY_SPI_BOOT_S 1 -/* EFUSE_DIS_DOWNLOAD_MODE : RO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The value of DIS_DOWNLOAD_MODE.*/ -#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_M (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_V 0x1 +/** EFUSE_RD_REPEAT_DATA3_REG register + * Register 4 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) +/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; + * Set this bit to disable all download boot modes. + */ +#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) +#define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MODE_S 0 +/** EFUSE_DIS_LEGACY_SPI_BOOT : RO; bitpos: [1]; default: 0; + * Set this bit to disable Legacy SPI boot mode. + */ +#define EFUSE_DIS_LEGACY_SPI_BOOT (BIT(1)) +#define EFUSE_DIS_LEGACY_SPI_BOOT_M (EFUSE_DIS_LEGACY_SPI_BOOT_V << EFUSE_DIS_LEGACY_SPI_BOOT_S) +#define EFUSE_DIS_LEGACY_SPI_BOOT_V 0x00000001U +#define EFUSE_DIS_LEGACY_SPI_BOOT_S 1 +/** EFUSE_UART_PRINT_CHANNEL : RO; bitpos: [2]; default: 0; + * Selects the default UART for printing boot messages. 0: UART0. 1: UART1. + */ +#define EFUSE_UART_PRINT_CHANNEL (BIT(2)) +#define EFUSE_UART_PRINT_CHANNEL_M (EFUSE_UART_PRINT_CHANNEL_V << EFUSE_UART_PRINT_CHANNEL_S) +#define EFUSE_UART_PRINT_CHANNEL_V 0x00000001U +#define EFUSE_UART_PRINT_CHANNEL_S 2 +/** EFUSE_RPT4_RESERVED3 : RO; bitpos: [3]; default: 0; + * Reserved (used for four backups method). + */ +#define EFUSE_RPT4_RESERVED3 (BIT(3)) +#define EFUSE_RPT4_RESERVED3_M (EFUSE_RPT4_RESERVED3_V << EFUSE_RPT4_RESERVED3_S) +#define EFUSE_RPT4_RESERVED3_V 0x00000001U +#define EFUSE_RPT4_RESERVED3_S 3 +/** EFUSE_DIS_USB_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0; + * Set this bit to disable use of USB OTG in UART download boot mode. + */ +#define EFUSE_DIS_USB_DOWNLOAD_MODE (BIT(4)) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_M (EFUSE_DIS_USB_DOWNLOAD_MODE_V << EFUSE_DIS_USB_DOWNLOAD_MODE_S) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_V 0x00000001U +#define EFUSE_DIS_USB_DOWNLOAD_MODE_S 4 +/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0; + * Set this bit to enable secure UART download mode (read/write flash only). + */ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001U +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 +/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0; + * Set the default UART boot message output mode. 00: Enabled. 01: Enable when GPIO46 + * is low at reset. 10: Enable when GPIO46 is high at reset. 11: Disabled. + */ +#define EFUSE_UART_PRINT_CONTROL 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) +#define EFUSE_UART_PRINT_CONTROL_V 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_S 6 +/** EFUSE_PIN_POWER_SELECTION : RO; bitpos: [8]; default: 0; + * Set default power supply for GPIO33-GPIO37, set when SPI flash is initialized. 0: + * VDD3P3_CPU. 1: VDD_SPI. + */ +#define EFUSE_PIN_POWER_SELECTION (BIT(8)) +#define EFUSE_PIN_POWER_SELECTION_M (EFUSE_PIN_POWER_SELECTION_V << EFUSE_PIN_POWER_SELECTION_S) +#define EFUSE_PIN_POWER_SELECTION_V 0x00000001U +#define EFUSE_PIN_POWER_SELECTION_S 8 +/** EFUSE_FLASH_TYPE : RO; bitpos: [9]; default: 0; + * SPI flash type. 0: maximum four data lines, 1: eight data lines. + */ +#define EFUSE_FLASH_TYPE (BIT(9)) +#define EFUSE_FLASH_TYPE_M (EFUSE_FLASH_TYPE_V << EFUSE_FLASH_TYPE_S) +#define EFUSE_FLASH_TYPE_V 0x00000001U +#define EFUSE_FLASH_TYPE_S 9 +/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [10]; default: 0; + * If set, forces ROM code to send an SPI flash resume command during SPI boot. + */ +#define EFUSE_FORCE_SEND_RESUME (BIT(10)) +#define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) +#define EFUSE_FORCE_SEND_RESUME_V 0x00000001U +#define EFUSE_FORCE_SEND_RESUME_S 10 +/** EFUSE_SECURE_VERSION : RO; bitpos: [26:11]; default: 0; + * Secure version (used by ESP-IDF anti-rollback feature). + */ +#define EFUSE_SECURE_VERSION 0x0000FFFFU +#define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) +#define EFUSE_SECURE_VERSION_V 0x0000FFFFU +#define EFUSE_SECURE_VERSION_S 11 +/** EFUSE_RPT4_RESERVED2 : RO; bitpos: [31:27]; default: 0; + * Reserved (used for four backups method). + */ +#define EFUSE_RPT4_RESERVED2 0x0000001FU +#define EFUSE_RPT4_RESERVED2_M (EFUSE_RPT4_RESERVED2_V << EFUSE_RPT4_RESERVED2_S) +#define EFUSE_RPT4_RESERVED2_V 0x0000001FU +#define EFUSE_RPT4_RESERVED2_S 27 -#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x040) -/* EFUSE_RPT1_RESERVED0 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT1_RESERVED0 0x000000FF -#define EFUSE_RPT1_RESERVED0_M ((EFUSE_RPT1_RESERVED0_V)<<(EFUSE_RPT1_RESERVED0_S)) -#define EFUSE_RPT1_RESERVED0_V 0xFF -#define EFUSE_RPT1_RESERVED0_S 24 -/* EFUSE_RPT4_RESERVED4 : RO ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: Reserved ( four backup method ).*/ -#define EFUSE_RPT4_RESERVED4 0x00FFFFFF -#define EFUSE_RPT4_RESERVED4_M ((EFUSE_RPT4_RESERVED4_V)<<(EFUSE_RPT4_RESERVED4_S)) -#define EFUSE_RPT4_RESERVED4_V 0xFFFFFF -#define EFUSE_RPT4_RESERVED4_S 0 - -#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x044) -/* EFUSE_MAC_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the low 32 bits of MAC address.*/ -#define EFUSE_MAC_0 0xFFFFFFFF -#define EFUSE_MAC_0_M ((EFUSE_MAC_0_V)<<(EFUSE_MAC_0_S)) -#define EFUSE_MAC_0_V 0xFFFFFFFF +/** EFUSE_RD_REPEAT_DATA4_REG register + * Register 5 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) +/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [0]; default: 0; + * Disables check of wafer version major + */ +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR (BIT(0)) +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S) +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V 0x00000001U +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S 0 +/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [1]; default: 0; + * Disables check of blk version major + */ +#define EFUSE_DISABLE_BLK_VERSION_MAJOR (BIT(1)) +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S) +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V 0x00000001U +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S 1 +/** EFUSE_RESERVED_0_162 : R; bitpos: [23:2]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_0_162 0x003FFFFFU +#define EFUSE_RESERVED_0_162_M (EFUSE_RESERVED_0_162_V << EFUSE_RESERVED_0_162_S) +#define EFUSE_RESERVED_0_162_V 0x003FFFFFU +#define EFUSE_RESERVED_0_162_S 2 + +/** EFUSE_RD_MAC_SPI_SYS_0_REG register + * Register 0 of BLOCK1. + */ +#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44) +/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0; + * Stores the low 32 bits of MAC address. + */ +#define EFUSE_MAC_0 0xFFFFFFFFU +#define EFUSE_MAC_0_M (EFUSE_MAC_0_V << EFUSE_MAC_0_S) +#define EFUSE_MAC_0_V 0xFFFFFFFFU #define EFUSE_MAC_0_S 0 -#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x048) -/* EFUSE_SPI_PAD_CONF_0 : RO ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: Stores the zeroth part of SPI_PAD_CONF.*/ -#define EFUSE_SPI_PAD_CONF_0 0x0000FFFF -#define EFUSE_SPI_PAD_CONF_0_M ((EFUSE_SPI_PAD_CONF_0_V)<<(EFUSE_SPI_PAD_CONF_0_S)) -#define EFUSE_SPI_PAD_CONF_0_V 0xFFFF -#define EFUSE_SPI_PAD_CONF_0_S 16 -/* EFUSE_MAC_1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: Stores the high 16 bits of MAC address.*/ -#define EFUSE_MAC_1 0x0000FFFF -#define EFUSE_MAC_1_M ((EFUSE_MAC_1_V)<<(EFUSE_MAC_1_S)) -#define EFUSE_MAC_1_V 0xFFFF +/** EFUSE_RD_MAC_SPI_SYS_1_REG register + * Register 1 of BLOCK1. + */ +#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48) +/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0; + * Stores the high 16 bits of MAC address. + */ +#define EFUSE_MAC_1 0x0000FFFFU +#define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) +#define EFUSE_MAC_1_V 0x0000FFFFU #define EFUSE_MAC_1_S 0 +/** EFUSE_SPI_PAD_CONFIG_CLK : R; bitpos: [21:16]; default: 0; + * SPI_PAD_configure CLK + */ +#define EFUSE_SPI_PAD_CONFIG_CLK 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_CLK_M (EFUSE_SPI_PAD_CONFIG_CLK_V << EFUSE_SPI_PAD_CONFIG_CLK_S) +#define EFUSE_SPI_PAD_CONFIG_CLK_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_CLK_S 16 +/** EFUSE_SPI_PAD_CONFIG_Q : R; bitpos: [27:22]; default: 0; + * SPI_PAD_configure Q(D1) + */ +#define EFUSE_SPI_PAD_CONFIG_Q 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_Q_M (EFUSE_SPI_PAD_CONFIG_Q_V << EFUSE_SPI_PAD_CONFIG_Q_S) +#define EFUSE_SPI_PAD_CONFIG_Q_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_Q_S 22 +/** EFUSE_SPI_PAD_CONFIG_D : R; bitpos: [31:28]; default: 0; + * SPI_PAD_configure D(D0) + */ +#define EFUSE_SPI_PAD_CONFIG_D 0x0000000FU +#define EFUSE_SPI_PAD_CONFIG_D_M (EFUSE_SPI_PAD_CONFIG_D_V << EFUSE_SPI_PAD_CONFIG_D_S) +#define EFUSE_SPI_PAD_CONFIG_D_V 0x0000000FU +#define EFUSE_SPI_PAD_CONFIG_D_S 28 + +/** EFUSE_RD_MAC_SPI_SYS_2_REG register + * Register 2 of BLOCK1. + */ +#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c) +/** EFUSE_SPI_PAD_CONFIG_D_1 : R; bitpos: [1:0]; default: 0; + * SPI_PAD_configure D(D0) + */ +#define EFUSE_SPI_PAD_CONFIG_D_1 0x00000003U +#define EFUSE_SPI_PAD_CONFIG_D_1_M (EFUSE_SPI_PAD_CONFIG_D_1_V << EFUSE_SPI_PAD_CONFIG_D_1_S) +#define EFUSE_SPI_PAD_CONFIG_D_1_V 0x00000003U +#define EFUSE_SPI_PAD_CONFIG_D_1_S 0 +/** EFUSE_SPI_PAD_CONFIG_CS : R; bitpos: [7:2]; default: 0; + * SPI_PAD_configure CS + */ +#define EFUSE_SPI_PAD_CONFIG_CS 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_CS_M (EFUSE_SPI_PAD_CONFIG_CS_V << EFUSE_SPI_PAD_CONFIG_CS_S) +#define EFUSE_SPI_PAD_CONFIG_CS_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_CS_S 2 +/** EFUSE_SPI_PAD_CONFIG_HD : R; bitpos: [13:8]; default: 0; + * SPI_PAD_configure HD(D3) + */ +#define EFUSE_SPI_PAD_CONFIG_HD 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_HD_M (EFUSE_SPI_PAD_CONFIG_HD_V << EFUSE_SPI_PAD_CONFIG_HD_S) +#define EFUSE_SPI_PAD_CONFIG_HD_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_HD_S 8 +/** EFUSE_SPI_PAD_CONFIG_WP : R; bitpos: [19:14]; default: 0; + * SPI_PAD_configure WP(D2) + */ +#define EFUSE_SPI_PAD_CONFIG_WP 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_WP_M (EFUSE_SPI_PAD_CONFIG_WP_V << EFUSE_SPI_PAD_CONFIG_WP_S) +#define EFUSE_SPI_PAD_CONFIG_WP_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_WP_S 14 +/** EFUSE_SPI_PAD_CONFIG_DQS : R; bitpos: [25:20]; default: 0; + * SPI_PAD_configure DQS + */ +#define EFUSE_SPI_PAD_CONFIG_DQS 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_DQS_M (EFUSE_SPI_PAD_CONFIG_DQS_V << EFUSE_SPI_PAD_CONFIG_DQS_S) +#define EFUSE_SPI_PAD_CONFIG_DQS_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_DQS_S 20 +/** EFUSE_SPI_PAD_CONFIG_D4 : R; bitpos: [31:26]; default: 0; + * SPI_PAD_configure D4 + */ +#define EFUSE_SPI_PAD_CONFIG_D4 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D4_M (EFUSE_SPI_PAD_CONFIG_D4_V << EFUSE_SPI_PAD_CONFIG_D4_S) +#define EFUSE_SPI_PAD_CONFIG_D4_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D4_S 26 -#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x04c) -/* EFUSE_SPI_PAD_CONF_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first part of SPI_PAD_CONF.*/ -#define EFUSE_SPI_PAD_CONF_1 0xFFFFFFFF -#define EFUSE_SPI_PAD_CONF_1_M ((EFUSE_SPI_PAD_CONF_1_V)<<(EFUSE_SPI_PAD_CONF_1_S)) -#define EFUSE_SPI_PAD_CONF_1_V 0xFFFFFFFF -#define EFUSE_SPI_PAD_CONF_1_S 0 - -#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x050) -/* EFUSE_PSRAM_VERSION : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: PSRAM version */ -#define EFUSE_PSRAM_VERSION 0x0000000F -#define EFUSE_PSRAM_VERSION_M ((EFUSE_PSRAM_VERSION_V)<<(EFUSE_PSRAM_VERSION_S)) -#define EFUSE_PSRAM_VERSION_V 0xF -#define EFUSE_PSRAM_VERSION_S 28 -/* EFUSE_FLASH_VERSION : RO ;bitpos:[24:21] ;default: 4'h0 ; */ -/*description: Flash version */ -#define EFUSE_FLASH_VERSION 0x0000000F -#define EFUSE_FLASH_VERSION_M ((EFUSE_FLASH_VERSION_V)<<(EFUSE_FLASH_VERSION_S)) -#define EFUSE_FLASH_VERSION_V 0xF +/** EFUSE_RD_MAC_SPI_SYS_3_REG register + * Register 3 of BLOCK1. + */ +#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) +/** EFUSE_SPI_PAD_CONFIG_D5 : R; bitpos: [5:0]; default: 0; + * SPI_PAD_configure D5 + */ +#define EFUSE_SPI_PAD_CONFIG_D5 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D5_M (EFUSE_SPI_PAD_CONFIG_D5_V << EFUSE_SPI_PAD_CONFIG_D5_S) +#define EFUSE_SPI_PAD_CONFIG_D5_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D5_S 0 +/** EFUSE_SPI_PAD_CONFIG_D6 : R; bitpos: [11:6]; default: 0; + * SPI_PAD_configure D6 + */ +#define EFUSE_SPI_PAD_CONFIG_D6 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D6_M (EFUSE_SPI_PAD_CONFIG_D6_V << EFUSE_SPI_PAD_CONFIG_D6_S) +#define EFUSE_SPI_PAD_CONFIG_D6_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D6_S 6 +/** EFUSE_SPI_PAD_CONFIG_D7 : R; bitpos: [17:12]; default: 0; + * SPI_PAD_configure D7 + */ +#define EFUSE_SPI_PAD_CONFIG_D7 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D7_M (EFUSE_SPI_PAD_CONFIG_D7_V << EFUSE_SPI_PAD_CONFIG_D7_S) +#define EFUSE_SPI_PAD_CONFIG_D7_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D7_S 12 +/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [19:18]; default: 0; + * WAFER_VERSION_MAJOR + */ +#define EFUSE_WAFER_VERSION_MAJOR 0x00000003U +#define EFUSE_WAFER_VERSION_MAJOR_M (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S) +#define EFUSE_WAFER_VERSION_MAJOR_V 0x00000003U +#define EFUSE_WAFER_VERSION_MAJOR_S 18 +/** EFUSE_WAFER_VERSION_MINOR_HI : R; bitpos: [20]; default: 0; + * WAFER_VERSION_MINOR most significant bit + */ +#define EFUSE_WAFER_VERSION_MINOR_HI (BIT(20)) +#define EFUSE_WAFER_VERSION_MINOR_HI_M (EFUSE_WAFER_VERSION_MINOR_HI_V << EFUSE_WAFER_VERSION_MINOR_HI_S) +#define EFUSE_WAFER_VERSION_MINOR_HI_V 0x00000001U +#define EFUSE_WAFER_VERSION_MINOR_HI_S 20 +/** EFUSE_FLASH_VERSION : R; bitpos: [24:21]; default: 0; + * Flash version + */ +#define EFUSE_FLASH_VERSION 0x0000000FU +#define EFUSE_FLASH_VERSION_M (EFUSE_FLASH_VERSION_V << EFUSE_FLASH_VERSION_S) +#define EFUSE_FLASH_VERSION_V 0x0000000FU #define EFUSE_FLASH_VERSION_S 21 -/* EFUSE_WAFER_VERSION : RO ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: WAFER version 0:A */ -#define EFUSE_WAFER_VERSION 0x00000007 -#define EFUSE_WAFER_VERSION_M ((EFUSE_WAFER_VERSION_V)<<(EFUSE_WAFER_VERSION_S)) -#define EFUSE_WAFER_VERSION_V 0x7 -#define EFUSE_WAFER_VERSION_S 18 -/* EFUSE_SPI_PAD_CONF_2 : RO ;bitpos:[17:0] ;default: 18'h0 ; */ -/*description: Stores the second part of SPI_PAD_CONF.*/ -#define EFUSE_SPI_PAD_CONF_2 0x0003FFFF -#define EFUSE_SPI_PAD_CONF_2_M ((EFUSE_SPI_PAD_CONF_2_V)<<(EFUSE_SPI_PAD_CONF_2_S)) -#define EFUSE_SPI_PAD_CONF_2_V 0x3FFFF -#define EFUSE_SPI_PAD_CONF_2_S 0 - -#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x054) -/* EFUSE_SYS_DATA_PART0_1 : RO ;bitpos:[31:4] ;default: 28'h0 ; */ -/*description: Stores the fist 32 bits of the zeroth part of system data.*/ -#define EFUSE_SYS_DATA_PART0_1 0x0FFFFFFF -#define EFUSE_SYS_DATA_PART0_1_M ((EFUSE_SYS_DATA_PART0_1_V)<<(EFUSE_SYS_DATA_PART0_1_S)) -#define EFUSE_SYS_DATA_PART0_1_V 0x0FFFFFFF -#define EFUSE_SYS_DATA_PART0_1_S 4 -/* EFUSE_PKG_VERSION : RO ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: Package version */ -#define EFUSE_PKG_VERSION 0x0000000F -#define EFUSE_PKG_VERSION_M ((EFUSE_PKG_VERSION_V)<<(EFUSE_PKG_VERSION_S)) -#define EFUSE_PKG_VERSION_V 0xF +/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [26:25]; default: 0; + * BLK_VERSION_MAJOR + */ +#define EFUSE_BLK_VERSION_MAJOR 0x00000003U +#define EFUSE_BLK_VERSION_MAJOR_M (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S) +#define EFUSE_BLK_VERSION_MAJOR_V 0x00000003U +#define EFUSE_BLK_VERSION_MAJOR_S 25 +/** EFUSE_RESERVED_1_123 : R; bitpos: [27]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_1_123 (BIT(27)) +#define EFUSE_RESERVED_1_123_M (EFUSE_RESERVED_1_123_V << EFUSE_RESERVED_1_123_S) +#define EFUSE_RESERVED_1_123_V 0x00000001U +#define EFUSE_RESERVED_1_123_S 27 +/** EFUSE_PSRAM_VERSION : R; bitpos: [31:28]; default: 0; + * PSRAM version + */ +#define EFUSE_PSRAM_VERSION 0x0000000FU +#define EFUSE_PSRAM_VERSION_M (EFUSE_PSRAM_VERSION_V << EFUSE_PSRAM_VERSION_S) +#define EFUSE_PSRAM_VERSION_V 0x0000000FU +#define EFUSE_PSRAM_VERSION_S 28 + +/** EFUSE_RD_MAC_SPI_SYS_4_REG register + * Register 4 of BLOCK1. + */ +#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) +/** EFUSE_PKG_VERSION : R; bitpos: [3:0]; default: 0; + * Package version + */ +#define EFUSE_PKG_VERSION 0x0000000FU +#define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S) +#define EFUSE_PKG_VERSION_V 0x0000000FU #define EFUSE_PKG_VERSION_S 0 +/** EFUSE_WAFER_VERSION_MINOR_LO : R; bitpos: [6:4]; default: 0; + * WAFER_VERSION_MINOR least significant bits + */ +#define EFUSE_WAFER_VERSION_MINOR_LO 0x00000007U +#define EFUSE_WAFER_VERSION_MINOR_LO_M (EFUSE_WAFER_VERSION_MINOR_LO_V << EFUSE_WAFER_VERSION_MINOR_LO_S) +#define EFUSE_WAFER_VERSION_MINOR_LO_V 0x00000007U +#define EFUSE_WAFER_VERSION_MINOR_LO_S 4 +/** EFUSE_RESERVED_1_135 : R; bitpos: [31:7]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_1_135 0x01FFFFFFU +#define EFUSE_RESERVED_1_135_M (EFUSE_RESERVED_1_135_V << EFUSE_RESERVED_1_135_S) +#define EFUSE_RESERVED_1_135_V 0x01FFFFFFU +#define EFUSE_RESERVED_1_135_S 7 -#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x058) -/* EFUSE_SYS_DATA_PART0_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of the zeroth part of system data.*/ -#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_2_M ((EFUSE_SYS_DATA_PART0_2_V)<<(EFUSE_SYS_DATA_PART0_2_S)) -#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFF +/** EFUSE_RD_MAC_SPI_SYS_5_REG register + * Register 5 of BLOCK1. + */ +#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58) +/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0; + * Stores the second part of the zeroth part of system data. + */ +#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_2_M (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S) +#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART0_2_S 0 -#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x05c) -/* EFUSE_SYS_DATA_PART1_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_0_M ((EFUSE_SYS_DATA_PART1_0_V)<<(EFUSE_SYS_DATA_PART1_0_S)) -#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_0_S 0 - -#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x060) -/* EFUSE_SYS_DATA_PART1_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_1_M ((EFUSE_SYS_DATA_PART1_1_V)<<(EFUSE_SYS_DATA_PART1_1_S)) -#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_1_S 0 - -#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x064) -/* EFUSE_SYS_DATA_PART1_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_2_M ((EFUSE_SYS_DATA_PART1_2_V)<<(EFUSE_SYS_DATA_PART1_2_S)) -#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_2_S 0 - -#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x068) -/* EFUSE_SYS_DATA_PART1_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_3_M ((EFUSE_SYS_DATA_PART1_3_V)<<(EFUSE_SYS_DATA_PART1_3_S)) -#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_3_S 0 - -#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x06c) -/* EFUSE_SYS_DATA_PART1_4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_4_M ((EFUSE_SYS_DATA_PART1_4_V)<<(EFUSE_SYS_DATA_PART1_4_S)) -#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_4_S 0 - -#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x070) -/* EFUSE_SYS_DATA_PART1_5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_5_M ((EFUSE_SYS_DATA_PART1_5_V)<<(EFUSE_SYS_DATA_PART1_5_S)) -#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_5_S 0 - -#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x074) -/* EFUSE_SYS_DATA_PART1_6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_6_M ((EFUSE_SYS_DATA_PART1_6_V)<<(EFUSE_SYS_DATA_PART1_6_S)) -#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_6_S 0 - -#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x078) -/* EFUSE_SYS_DATA_PART1_7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_7_M ((EFUSE_SYS_DATA_PART1_7_V)<<(EFUSE_SYS_DATA_PART1_7_S)) -#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_7_S 0 - -#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x07c) -/* EFUSE_USR_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA0 0xFFFFFFFF -#define EFUSE_USR_DATA0_M ((EFUSE_USR_DATA0_V)<<(EFUSE_USR_DATA0_S)) -#define EFUSE_USR_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART1_DATA0_REG register + * Register 0 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c) +/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ +#define EFUSE_OPTIONAL_UNIQUE_ID 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_M (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_S 0 + +/** EFUSE_RD_SYS_PART1_DATA1_REG register + * Register 1 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60) +/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ +#define EFUSE_OPTIONAL_UNIQUE_ID_1 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_1_M (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_1_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_1_S 0 + +/** EFUSE_RD_SYS_PART1_DATA2_REG register + * Register 2 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64) +/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ +#define EFUSE_OPTIONAL_UNIQUE_ID_2 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_2_M (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_2_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_2_S 0 + +/** EFUSE_RD_SYS_PART1_DATA3_REG register + * Register 3 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68) +/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ +#define EFUSE_OPTIONAL_UNIQUE_ID_3 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_3_M (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_3_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_3_S 0 + +/** EFUSE_RD_SYS_PART1_DATA4_REG register + * Register 4 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c) +/** EFUSE_ADC_CALIB : R; bitpos: [3:0]; default: 0; + * 4 bit of ADC calibration + */ +#define EFUSE_ADC_CALIB 0x0000000FU +#define EFUSE_ADC_CALIB_M (EFUSE_ADC_CALIB_V << EFUSE_ADC_CALIB_S) +#define EFUSE_ADC_CALIB_V 0x0000000FU +#define EFUSE_ADC_CALIB_S 0 +/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [6:4]; default: 0; + * BLK_VERSION_MINOR of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2 + */ +#define EFUSE_BLK_VERSION_MINOR 0x00000007U +#define EFUSE_BLK_VERSION_MINOR_M (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S) +#define EFUSE_BLK_VERSION_MINOR_V 0x00000007U +#define EFUSE_BLK_VERSION_MINOR_S 4 +/** EFUSE_TEMP_CALIB : R; bitpos: [15:7]; default: 0; + * Temperature calibration data + */ +#define EFUSE_TEMP_CALIB 0x000001FFU +#define EFUSE_TEMP_CALIB_M (EFUSE_TEMP_CALIB_V << EFUSE_TEMP_CALIB_S) +#define EFUSE_TEMP_CALIB_V 0x000001FFU +#define EFUSE_TEMP_CALIB_S 7 +/** EFUSE_RTCCALIB_V1IDX_A10H : R; bitpos: [23:16]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A10H 0x000000FFU +#define EFUSE_RTCCALIB_V1IDX_A10H_M (EFUSE_RTCCALIB_V1IDX_A10H_V << EFUSE_RTCCALIB_V1IDX_A10H_S) +#define EFUSE_RTCCALIB_V1IDX_A10H_V 0x000000FFU +#define EFUSE_RTCCALIB_V1IDX_A10H_S 16 +/** EFUSE_RTCCALIB_V1IDX_A11H : R; bitpos: [31:24]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A11H 0x000000FFU +#define EFUSE_RTCCALIB_V1IDX_A11H_M (EFUSE_RTCCALIB_V1IDX_A11H_V << EFUSE_RTCCALIB_V1IDX_A11H_S) +#define EFUSE_RTCCALIB_V1IDX_A11H_V 0x000000FFU +#define EFUSE_RTCCALIB_V1IDX_A11H_S 24 + +/** EFUSE_RD_SYS_PART1_DATA5_REG register + * Register 5 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70) +/** EFUSE_RTCCALIB_V1IDX_A12H : R; bitpos: [7:0]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A12H 0x000000FFU +#define EFUSE_RTCCALIB_V1IDX_A12H_M (EFUSE_RTCCALIB_V1IDX_A12H_V << EFUSE_RTCCALIB_V1IDX_A12H_S) +#define EFUSE_RTCCALIB_V1IDX_A12H_V 0x000000FFU +#define EFUSE_RTCCALIB_V1IDX_A12H_S 0 +/** EFUSE_RTCCALIB_V1IDX_A13H : R; bitpos: [15:8]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A13H 0x000000FFU +#define EFUSE_RTCCALIB_V1IDX_A13H_M (EFUSE_RTCCALIB_V1IDX_A13H_V << EFUSE_RTCCALIB_V1IDX_A13H_S) +#define EFUSE_RTCCALIB_V1IDX_A13H_V 0x000000FFU +#define EFUSE_RTCCALIB_V1IDX_A13H_S 8 +/** EFUSE_RTCCALIB_V1IDX_A20H : R; bitpos: [23:16]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A20H 0x000000FFU +#define EFUSE_RTCCALIB_V1IDX_A20H_M (EFUSE_RTCCALIB_V1IDX_A20H_V << EFUSE_RTCCALIB_V1IDX_A20H_S) +#define EFUSE_RTCCALIB_V1IDX_A20H_V 0x000000FFU +#define EFUSE_RTCCALIB_V1IDX_A20H_S 16 +/** EFUSE_RTCCALIB_V1IDX_A21H : R; bitpos: [31:24]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A21H 0x000000FFU +#define EFUSE_RTCCALIB_V1IDX_A21H_M (EFUSE_RTCCALIB_V1IDX_A21H_V << EFUSE_RTCCALIB_V1IDX_A21H_S) +#define EFUSE_RTCCALIB_V1IDX_A21H_V 0x000000FFU +#define EFUSE_RTCCALIB_V1IDX_A21H_S 24 + +/** EFUSE_RD_SYS_PART1_DATA6_REG register + * Register 6 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74) +/** EFUSE_RTCCALIB_V1IDX_A22H : R; bitpos: [7:0]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A22H 0x000000FFU +#define EFUSE_RTCCALIB_V1IDX_A22H_M (EFUSE_RTCCALIB_V1IDX_A22H_V << EFUSE_RTCCALIB_V1IDX_A22H_S) +#define EFUSE_RTCCALIB_V1IDX_A22H_V 0x000000FFU +#define EFUSE_RTCCALIB_V1IDX_A22H_S 0 +/** EFUSE_RTCCALIB_V1IDX_A23H : R; bitpos: [15:8]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A23H 0x000000FFU +#define EFUSE_RTCCALIB_V1IDX_A23H_M (EFUSE_RTCCALIB_V1IDX_A23H_V << EFUSE_RTCCALIB_V1IDX_A23H_S) +#define EFUSE_RTCCALIB_V1IDX_A23H_V 0x000000FFU +#define EFUSE_RTCCALIB_V1IDX_A23H_S 8 +/** EFUSE_RTCCALIB_V1IDX_A10L : R; bitpos: [21:16]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A10L 0x0000003FU +#define EFUSE_RTCCALIB_V1IDX_A10L_M (EFUSE_RTCCALIB_V1IDX_A10L_V << EFUSE_RTCCALIB_V1IDX_A10L_S) +#define EFUSE_RTCCALIB_V1IDX_A10L_V 0x0000003FU +#define EFUSE_RTCCALIB_V1IDX_A10L_S 16 +/** EFUSE_RTCCALIB_V1IDX_A11L : R; bitpos: [27:22]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A11L 0x0000003FU +#define EFUSE_RTCCALIB_V1IDX_A11L_M (EFUSE_RTCCALIB_V1IDX_A11L_V << EFUSE_RTCCALIB_V1IDX_A11L_S) +#define EFUSE_RTCCALIB_V1IDX_A11L_V 0x0000003FU +#define EFUSE_RTCCALIB_V1IDX_A11L_S 22 +/** EFUSE_RTCCALIB_V1IDX_A12L : R; bitpos: [31:28]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A12L 0x0000000FU +#define EFUSE_RTCCALIB_V1IDX_A12L_M (EFUSE_RTCCALIB_V1IDX_A12L_V << EFUSE_RTCCALIB_V1IDX_A12L_S) +#define EFUSE_RTCCALIB_V1IDX_A12L_V 0x0000000FU +#define EFUSE_RTCCALIB_V1IDX_A12L_S 28 + +/** EFUSE_RD_SYS_PART1_DATA7_REG register + * Register 7 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78) +/** EFUSE_RTCCALIB_V1IDX_A12L_1 : R; bitpos: [1:0]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A12L_1 0x00000003U +#define EFUSE_RTCCALIB_V1IDX_A12L_1_M (EFUSE_RTCCALIB_V1IDX_A12L_1_V << EFUSE_RTCCALIB_V1IDX_A12L_1_S) +#define EFUSE_RTCCALIB_V1IDX_A12L_1_V 0x00000003U +#define EFUSE_RTCCALIB_V1IDX_A12L_1_S 0 +/** EFUSE_RTCCALIB_V1IDX_A13L : R; bitpos: [7:2]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A13L 0x0000003FU +#define EFUSE_RTCCALIB_V1IDX_A13L_M (EFUSE_RTCCALIB_V1IDX_A13L_V << EFUSE_RTCCALIB_V1IDX_A13L_S) +#define EFUSE_RTCCALIB_V1IDX_A13L_V 0x0000003FU +#define EFUSE_RTCCALIB_V1IDX_A13L_S 2 +/** EFUSE_RTCCALIB_V1IDX_A20L : R; bitpos: [13:8]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A20L 0x0000003FU +#define EFUSE_RTCCALIB_V1IDX_A20L_M (EFUSE_RTCCALIB_V1IDX_A20L_V << EFUSE_RTCCALIB_V1IDX_A20L_S) +#define EFUSE_RTCCALIB_V1IDX_A20L_V 0x0000003FU +#define EFUSE_RTCCALIB_V1IDX_A20L_S 8 +/** EFUSE_RTCCALIB_V1IDX_A21L : R; bitpos: [19:14]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A21L 0x0000003FU +#define EFUSE_RTCCALIB_V1IDX_A21L_M (EFUSE_RTCCALIB_V1IDX_A21L_V << EFUSE_RTCCALIB_V1IDX_A21L_S) +#define EFUSE_RTCCALIB_V1IDX_A21L_V 0x0000003FU +#define EFUSE_RTCCALIB_V1IDX_A21L_S 14 +/** EFUSE_RTCCALIB_V1IDX_A22L : R; bitpos: [25:20]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A22L 0x0000003FU +#define EFUSE_RTCCALIB_V1IDX_A22L_M (EFUSE_RTCCALIB_V1IDX_A22L_V << EFUSE_RTCCALIB_V1IDX_A22L_S) +#define EFUSE_RTCCALIB_V1IDX_A22L_V 0x0000003FU +#define EFUSE_RTCCALIB_V1IDX_A22L_S 20 +/** EFUSE_RTCCALIB_V1IDX_A23L : R; bitpos: [31:26]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A23L 0x0000003FU +#define EFUSE_RTCCALIB_V1IDX_A23L_M (EFUSE_RTCCALIB_V1IDX_A23L_V << EFUSE_RTCCALIB_V1IDX_A23L_S) +#define EFUSE_RTCCALIB_V1IDX_A23L_V 0x0000003FU +#define EFUSE_RTCCALIB_V1IDX_A23L_S 26 + +/** EFUSE_RD_USR_DATA0_REG register + * Register 0 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c) +/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA0 0xFFFFFFFFU +#define EFUSE_USR_DATA0_M (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S) +#define EFUSE_USR_DATA0_V 0xFFFFFFFFU #define EFUSE_USR_DATA0_S 0 -#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x080) -/* EFUSE_USR_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA1 0xFFFFFFFF -#define EFUSE_USR_DATA1_M ((EFUSE_USR_DATA1_V)<<(EFUSE_USR_DATA1_S)) -#define EFUSE_USR_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA1_REG register + * Register 1 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) +/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA1 0xFFFFFFFFU +#define EFUSE_USR_DATA1_M (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S) +#define EFUSE_USR_DATA1_V 0xFFFFFFFFU #define EFUSE_USR_DATA1_S 0 -#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x084) -/* EFUSE_USR_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA2 0xFFFFFFFF -#define EFUSE_USR_DATA2_M ((EFUSE_USR_DATA2_V)<<(EFUSE_USR_DATA2_S)) -#define EFUSE_USR_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA2_REG register + * Register 2 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) +/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA2 0xFFFFFFFFU +#define EFUSE_USR_DATA2_M (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S) +#define EFUSE_USR_DATA2_V 0xFFFFFFFFU #define EFUSE_USR_DATA2_S 0 -#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x088) -/* EFUSE_USR_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA3 0xFFFFFFFF -#define EFUSE_USR_DATA3_M ((EFUSE_USR_DATA3_V)<<(EFUSE_USR_DATA3_S)) -#define EFUSE_USR_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA3_REG register + * Register 3 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) +/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA3 0xFFFFFFFFU +#define EFUSE_USR_DATA3_M (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S) +#define EFUSE_USR_DATA3_V 0xFFFFFFFFU #define EFUSE_USR_DATA3_S 0 -#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x08c) -/* EFUSE_USR_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA4 0xFFFFFFFF -#define EFUSE_USR_DATA4_M ((EFUSE_USR_DATA4_V)<<(EFUSE_USR_DATA4_S)) -#define EFUSE_USR_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA4_REG register + * Register 4 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c) +/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA4 0xFFFFFFFFU +#define EFUSE_USR_DATA4_M (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S) +#define EFUSE_USR_DATA4_V 0xFFFFFFFFU #define EFUSE_USR_DATA4_S 0 -#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x090) -/* EFUSE_USR_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA5 0xFFFFFFFF -#define EFUSE_USR_DATA5_M ((EFUSE_USR_DATA5_V)<<(EFUSE_USR_DATA5_S)) -#define EFUSE_USR_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA5_REG register + * Register 5 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) +/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA5 0xFFFFFFFFU +#define EFUSE_USR_DATA5_M (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S) +#define EFUSE_USR_DATA5_V 0xFFFFFFFFU #define EFUSE_USR_DATA5_S 0 -#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x094) -/* EFUSE_USR_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA6 0xFFFFFFFF -#define EFUSE_USR_DATA6_M ((EFUSE_USR_DATA6_V)<<(EFUSE_USR_DATA6_S)) -#define EFUSE_USR_DATA6_V 0xFFFFFFFF -#define EFUSE_USR_DATA6_S 0 - -#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x098) -/* EFUSE_USR_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA7 0xFFFFFFFF -#define EFUSE_USR_DATA7_M ((EFUSE_USR_DATA7_V)<<(EFUSE_USR_DATA7_S)) -#define EFUSE_USR_DATA7_V 0xFFFFFFFF -#define EFUSE_USR_DATA7_S 0 - -#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x09c) -/* EFUSE_KEY0_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA0 0xFFFFFFFF -#define EFUSE_KEY0_DATA0_M ((EFUSE_KEY0_DATA0_V)<<(EFUSE_KEY0_DATA0_S)) -#define EFUSE_KEY0_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA6_REG register + * Register 6 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) +/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_3_192 0x000000FFU +#define EFUSE_RESERVED_3_192_M (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S) +#define EFUSE_RESERVED_3_192_V 0x000000FFU +#define EFUSE_RESERVED_3_192_S 0 +/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0; + * Custom MAC + */ +#define EFUSE_CUSTOM_MAC 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_M (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S) +#define EFUSE_CUSTOM_MAC_V 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_S 8 + +/** EFUSE_RD_USR_DATA7_REG register + * Register 7 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) +/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0; + * Custom MAC + */ +#define EFUSE_CUSTOM_MAC_1 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_1_M (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S) +#define EFUSE_CUSTOM_MAC_1_V 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_1_S 0 +/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_3_248 0x000000FFU +#define EFUSE_RESERVED_3_248_M (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S) +#define EFUSE_RESERVED_3_248_V 0x000000FFU +#define EFUSE_RESERVED_3_248_S 24 + +/** EFUSE_RD_KEY0_DATA0_REG register + * Register 0 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c) +/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA0 0xFFFFFFFFU +#define EFUSE_KEY0_DATA0_M (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S) +#define EFUSE_KEY0_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA0_S 0 -#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0x0a0) -/* EFUSE_KEY0_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA1 0xFFFFFFFF -#define EFUSE_KEY0_DATA1_M ((EFUSE_KEY0_DATA1_V)<<(EFUSE_KEY0_DATA1_S)) -#define EFUSE_KEY0_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA1_REG register + * Register 1 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0) +/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA1 0xFFFFFFFFU +#define EFUSE_KEY0_DATA1_M (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S) +#define EFUSE_KEY0_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA1_S 0 -#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0x0a4) -/* EFUSE_KEY0_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA2 0xFFFFFFFF -#define EFUSE_KEY0_DATA2_M ((EFUSE_KEY0_DATA2_V)<<(EFUSE_KEY0_DATA2_S)) -#define EFUSE_KEY0_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA2_REG register + * Register 2 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4) +/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA2 0xFFFFFFFFU +#define EFUSE_KEY0_DATA2_M (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S) +#define EFUSE_KEY0_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA2_S 0 -#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0x0a8) -/* EFUSE_KEY0_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA3 0xFFFFFFFF -#define EFUSE_KEY0_DATA3_M ((EFUSE_KEY0_DATA3_V)<<(EFUSE_KEY0_DATA3_S)) -#define EFUSE_KEY0_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA3_REG register + * Register 3 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8) +/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA3 0xFFFFFFFFU +#define EFUSE_KEY0_DATA3_M (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S) +#define EFUSE_KEY0_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA3_S 0 -#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0x0ac) -/* EFUSE_KEY0_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA4 0xFFFFFFFF -#define EFUSE_KEY0_DATA4_M ((EFUSE_KEY0_DATA4_V)<<(EFUSE_KEY0_DATA4_S)) -#define EFUSE_KEY0_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA4_REG register + * Register 4 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac) +/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA4 0xFFFFFFFFU +#define EFUSE_KEY0_DATA4_M (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S) +#define EFUSE_KEY0_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA4_S 0 -#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0x0b0) -/* EFUSE_KEY0_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA5 0xFFFFFFFF -#define EFUSE_KEY0_DATA5_M ((EFUSE_KEY0_DATA5_V)<<(EFUSE_KEY0_DATA5_S)) -#define EFUSE_KEY0_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA5_REG register + * Register 5 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0) +/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA5 0xFFFFFFFFU +#define EFUSE_KEY0_DATA5_M (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S) +#define EFUSE_KEY0_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA5_S 0 -#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0x0b4) -/* EFUSE_KEY0_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA6 0xFFFFFFFF -#define EFUSE_KEY0_DATA6_M ((EFUSE_KEY0_DATA6_V)<<(EFUSE_KEY0_DATA6_S)) -#define EFUSE_KEY0_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA6_REG register + * Register 6 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4) +/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA6 0xFFFFFFFFU +#define EFUSE_KEY0_DATA6_M (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S) +#define EFUSE_KEY0_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA6_S 0 -#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0x0b8) -/* EFUSE_KEY0_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA7 0xFFFFFFFF -#define EFUSE_KEY0_DATA7_M ((EFUSE_KEY0_DATA7_V)<<(EFUSE_KEY0_DATA7_S)) -#define EFUSE_KEY0_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA7_REG register + * Register 7 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8) +/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA7 0xFFFFFFFFU +#define EFUSE_KEY0_DATA7_M (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S) +#define EFUSE_KEY0_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA7_S 0 -#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0x0bc) -/* EFUSE_KEY1_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA0 0xFFFFFFFF -#define EFUSE_KEY1_DATA0_M ((EFUSE_KEY1_DATA0_V)<<(EFUSE_KEY1_DATA0_S)) -#define EFUSE_KEY1_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA0_REG register + * Register 0 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc) +/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA0 0xFFFFFFFFU +#define EFUSE_KEY1_DATA0_M (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S) +#define EFUSE_KEY1_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA0_S 0 -#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0x0c0) -/* EFUSE_KEY1_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA1 0xFFFFFFFF -#define EFUSE_KEY1_DATA1_M ((EFUSE_KEY1_DATA1_V)<<(EFUSE_KEY1_DATA1_S)) -#define EFUSE_KEY1_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA1_REG register + * Register 1 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0) +/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA1 0xFFFFFFFFU +#define EFUSE_KEY1_DATA1_M (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S) +#define EFUSE_KEY1_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA1_S 0 -#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0x0c4) -/* EFUSE_KEY1_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA2 0xFFFFFFFF -#define EFUSE_KEY1_DATA2_M ((EFUSE_KEY1_DATA2_V)<<(EFUSE_KEY1_DATA2_S)) -#define EFUSE_KEY1_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA2_REG register + * Register 2 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4) +/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA2 0xFFFFFFFFU +#define EFUSE_KEY1_DATA2_M (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S) +#define EFUSE_KEY1_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA2_S 0 -#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0x0c8) -/* EFUSE_KEY1_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA3 0xFFFFFFFF -#define EFUSE_KEY1_DATA3_M ((EFUSE_KEY1_DATA3_V)<<(EFUSE_KEY1_DATA3_S)) -#define EFUSE_KEY1_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA3_REG register + * Register 3 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8) +/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA3 0xFFFFFFFFU +#define EFUSE_KEY1_DATA3_M (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S) +#define EFUSE_KEY1_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA3_S 0 -#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0x0cc) -/* EFUSE_KEY1_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA4 0xFFFFFFFF -#define EFUSE_KEY1_DATA4_M ((EFUSE_KEY1_DATA4_V)<<(EFUSE_KEY1_DATA4_S)) -#define EFUSE_KEY1_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA4_REG register + * Register 4 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc) +/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA4 0xFFFFFFFFU +#define EFUSE_KEY1_DATA4_M (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S) +#define EFUSE_KEY1_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA4_S 0 -#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0x0d0) -/* EFUSE_KEY1_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA5 0xFFFFFFFF -#define EFUSE_KEY1_DATA5_M ((EFUSE_KEY1_DATA5_V)<<(EFUSE_KEY1_DATA5_S)) -#define EFUSE_KEY1_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA5_REG register + * Register 5 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0) +/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA5 0xFFFFFFFFU +#define EFUSE_KEY1_DATA5_M (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S) +#define EFUSE_KEY1_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA5_S 0 -#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0x0d4) -/* EFUSE_KEY1_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA6 0xFFFFFFFF -#define EFUSE_KEY1_DATA6_M ((EFUSE_KEY1_DATA6_V)<<(EFUSE_KEY1_DATA6_S)) -#define EFUSE_KEY1_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA6_REG register + * Register 6 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4) +/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA6 0xFFFFFFFFU +#define EFUSE_KEY1_DATA6_M (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S) +#define EFUSE_KEY1_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA6_S 0 -#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0x0d8) -/* EFUSE_KEY1_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA7 0xFFFFFFFF -#define EFUSE_KEY1_DATA7_M ((EFUSE_KEY1_DATA7_V)<<(EFUSE_KEY1_DATA7_S)) -#define EFUSE_KEY1_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA7_REG register + * Register 7 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8) +/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA7 0xFFFFFFFFU +#define EFUSE_KEY1_DATA7_M (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S) +#define EFUSE_KEY1_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA7_S 0 -#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0x0dc) -/* EFUSE_KEY2_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA0 0xFFFFFFFF -#define EFUSE_KEY2_DATA0_M ((EFUSE_KEY2_DATA0_V)<<(EFUSE_KEY2_DATA0_S)) -#define EFUSE_KEY2_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA0_REG register + * Register 0 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc) +/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA0 0xFFFFFFFFU +#define EFUSE_KEY2_DATA0_M (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S) +#define EFUSE_KEY2_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA0_S 0 -#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0x0e0) -/* EFUSE_KEY2_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA1 0xFFFFFFFF -#define EFUSE_KEY2_DATA1_M ((EFUSE_KEY2_DATA1_V)<<(EFUSE_KEY2_DATA1_S)) -#define EFUSE_KEY2_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA1_REG register + * Register 1 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0) +/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA1 0xFFFFFFFFU +#define EFUSE_KEY2_DATA1_M (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S) +#define EFUSE_KEY2_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA1_S 0 -#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0x0e4) -/* EFUSE_KEY2_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA2 0xFFFFFFFF -#define EFUSE_KEY2_DATA2_M ((EFUSE_KEY2_DATA2_V)<<(EFUSE_KEY2_DATA2_S)) -#define EFUSE_KEY2_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA2_REG register + * Register 2 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4) +/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA2 0xFFFFFFFFU +#define EFUSE_KEY2_DATA2_M (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S) +#define EFUSE_KEY2_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA2_S 0 -#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0x0e8) -/* EFUSE_KEY2_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA3 0xFFFFFFFF -#define EFUSE_KEY2_DATA3_M ((EFUSE_KEY2_DATA3_V)<<(EFUSE_KEY2_DATA3_S)) -#define EFUSE_KEY2_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA3_REG register + * Register 3 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8) +/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA3 0xFFFFFFFFU +#define EFUSE_KEY2_DATA3_M (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S) +#define EFUSE_KEY2_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA3_S 0 -#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0x0ec) -/* EFUSE_KEY2_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA4 0xFFFFFFFF -#define EFUSE_KEY2_DATA4_M ((EFUSE_KEY2_DATA4_V)<<(EFUSE_KEY2_DATA4_S)) -#define EFUSE_KEY2_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA4_REG register + * Register 4 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec) +/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA4 0xFFFFFFFFU +#define EFUSE_KEY2_DATA4_M (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S) +#define EFUSE_KEY2_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA4_S 0 -#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0x0f0) -/* EFUSE_KEY2_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA5 0xFFFFFFFF -#define EFUSE_KEY2_DATA5_M ((EFUSE_KEY2_DATA5_V)<<(EFUSE_KEY2_DATA5_S)) -#define EFUSE_KEY2_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA5_REG register + * Register 5 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0) +/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA5 0xFFFFFFFFU +#define EFUSE_KEY2_DATA5_M (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S) +#define EFUSE_KEY2_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA5_S 0 -#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0x0f4) -/* EFUSE_KEY2_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA6 0xFFFFFFFF -#define EFUSE_KEY2_DATA6_M ((EFUSE_KEY2_DATA6_V)<<(EFUSE_KEY2_DATA6_S)) -#define EFUSE_KEY2_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA6_REG register + * Register 6 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4) +/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA6 0xFFFFFFFFU +#define EFUSE_KEY2_DATA6_M (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S) +#define EFUSE_KEY2_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA6_S 0 -#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0x0f8) -/* EFUSE_KEY2_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA7 0xFFFFFFFF -#define EFUSE_KEY2_DATA7_M ((EFUSE_KEY2_DATA7_V)<<(EFUSE_KEY2_DATA7_S)) -#define EFUSE_KEY2_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA7_REG register + * Register 7 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8) +/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA7 0xFFFFFFFFU +#define EFUSE_KEY2_DATA7_M (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S) +#define EFUSE_KEY2_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA7_S 0 -#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0x0fc) -/* EFUSE_KEY3_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA0 0xFFFFFFFF -#define EFUSE_KEY3_DATA0_M ((EFUSE_KEY3_DATA0_V)<<(EFUSE_KEY3_DATA0_S)) -#define EFUSE_KEY3_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA0_REG register + * Register 0 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc) +/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA0 0xFFFFFFFFU +#define EFUSE_KEY3_DATA0_M (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S) +#define EFUSE_KEY3_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA0_S 0 -#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) -/* EFUSE_KEY3_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA1 0xFFFFFFFF -#define EFUSE_KEY3_DATA1_M ((EFUSE_KEY3_DATA1_V)<<(EFUSE_KEY3_DATA1_S)) -#define EFUSE_KEY3_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA1_REG register + * Register 1 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) +/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA1 0xFFFFFFFFU +#define EFUSE_KEY3_DATA1_M (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S) +#define EFUSE_KEY3_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA1_S 0 -#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) -/* EFUSE_KEY3_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA2 0xFFFFFFFF -#define EFUSE_KEY3_DATA2_M ((EFUSE_KEY3_DATA2_V)<<(EFUSE_KEY3_DATA2_S)) -#define EFUSE_KEY3_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA2_REG register + * Register 2 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) +/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA2 0xFFFFFFFFU +#define EFUSE_KEY3_DATA2_M (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S) +#define EFUSE_KEY3_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA2_S 0 -#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) -/* EFUSE_KEY3_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA3 0xFFFFFFFF -#define EFUSE_KEY3_DATA3_M ((EFUSE_KEY3_DATA3_V)<<(EFUSE_KEY3_DATA3_S)) -#define EFUSE_KEY3_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA3_REG register + * Register 3 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) +/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA3 0xFFFFFFFFU +#define EFUSE_KEY3_DATA3_M (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S) +#define EFUSE_KEY3_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA3_S 0 -#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c) -/* EFUSE_KEY3_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA4 0xFFFFFFFF -#define EFUSE_KEY3_DATA4_M ((EFUSE_KEY3_DATA4_V)<<(EFUSE_KEY3_DATA4_S)) -#define EFUSE_KEY3_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA4_REG register + * Register 4 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c) +/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA4 0xFFFFFFFFU +#define EFUSE_KEY3_DATA4_M (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S) +#define EFUSE_KEY3_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA4_S 0 -#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) -/* EFUSE_KEY3_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA5 0xFFFFFFFF -#define EFUSE_KEY3_DATA5_M ((EFUSE_KEY3_DATA5_V)<<(EFUSE_KEY3_DATA5_S)) -#define EFUSE_KEY3_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA5_REG register + * Register 5 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) +/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA5 0xFFFFFFFFU +#define EFUSE_KEY3_DATA5_M (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S) +#define EFUSE_KEY3_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA5_S 0 -#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) -/* EFUSE_KEY3_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA6 0xFFFFFFFF -#define EFUSE_KEY3_DATA6_M ((EFUSE_KEY3_DATA6_V)<<(EFUSE_KEY3_DATA6_S)) -#define EFUSE_KEY3_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA6_REG register + * Register 6 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) +/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA6 0xFFFFFFFFU +#define EFUSE_KEY3_DATA6_M (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S) +#define EFUSE_KEY3_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA6_S 0 -#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) -/* EFUSE_KEY3_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA7 0xFFFFFFFF -#define EFUSE_KEY3_DATA7_M ((EFUSE_KEY3_DATA7_V)<<(EFUSE_KEY3_DATA7_S)) -#define EFUSE_KEY3_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA7_REG register + * Register 7 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) +/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA7 0xFFFFFFFFU +#define EFUSE_KEY3_DATA7_M (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S) +#define EFUSE_KEY3_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA7_S 0 -#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c) -/* EFUSE_KEY4_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA0 0xFFFFFFFF -#define EFUSE_KEY4_DATA0_M ((EFUSE_KEY4_DATA0_V)<<(EFUSE_KEY4_DATA0_S)) -#define EFUSE_KEY4_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA0_REG register + * Register 0 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c) +/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA0 0xFFFFFFFFU +#define EFUSE_KEY4_DATA0_M (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S) +#define EFUSE_KEY4_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA0_S 0 -#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) -/* EFUSE_KEY4_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA1 0xFFFFFFFF -#define EFUSE_KEY4_DATA1_M ((EFUSE_KEY4_DATA1_V)<<(EFUSE_KEY4_DATA1_S)) -#define EFUSE_KEY4_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA1_REG register + * Register 1 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) +/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA1 0xFFFFFFFFU +#define EFUSE_KEY4_DATA1_M (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S) +#define EFUSE_KEY4_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA1_S 0 -#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) -/* EFUSE_KEY4_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA2 0xFFFFFFFF -#define EFUSE_KEY4_DATA2_M ((EFUSE_KEY4_DATA2_V)<<(EFUSE_KEY4_DATA2_S)) -#define EFUSE_KEY4_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA2_REG register + * Register 2 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) +/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA2 0xFFFFFFFFU +#define EFUSE_KEY4_DATA2_M (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S) +#define EFUSE_KEY4_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA2_S 0 -#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) -/* EFUSE_KEY4_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA3 0xFFFFFFFF -#define EFUSE_KEY4_DATA3_M ((EFUSE_KEY4_DATA3_V)<<(EFUSE_KEY4_DATA3_S)) -#define EFUSE_KEY4_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA3_REG register + * Register 3 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) +/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA3 0xFFFFFFFFU +#define EFUSE_KEY4_DATA3_M (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S) +#define EFUSE_KEY4_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA3_S 0 -#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c) -/* EFUSE_KEY4_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA4 0xFFFFFFFF -#define EFUSE_KEY4_DATA4_M ((EFUSE_KEY4_DATA4_V)<<(EFUSE_KEY4_DATA4_S)) -#define EFUSE_KEY4_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA4_REG register + * Register 4 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c) +/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA4 0xFFFFFFFFU +#define EFUSE_KEY4_DATA4_M (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S) +#define EFUSE_KEY4_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA4_S 0 -#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) -/* EFUSE_KEY4_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA5 0xFFFFFFFF -#define EFUSE_KEY4_DATA5_M ((EFUSE_KEY4_DATA5_V)<<(EFUSE_KEY4_DATA5_S)) -#define EFUSE_KEY4_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA5_REG register + * Register 5 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) +/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA5 0xFFFFFFFFU +#define EFUSE_KEY4_DATA5_M (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S) +#define EFUSE_KEY4_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA5_S 0 -#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) -/* EFUSE_KEY4_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA6 0xFFFFFFFF -#define EFUSE_KEY4_DATA6_M ((EFUSE_KEY4_DATA6_V)<<(EFUSE_KEY4_DATA6_S)) -#define EFUSE_KEY4_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA6_REG register + * Register 6 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) +/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA6 0xFFFFFFFFU +#define EFUSE_KEY4_DATA6_M (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S) +#define EFUSE_KEY4_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA6_S 0 -#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) -/* EFUSE_KEY4_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA7 0xFFFFFFFF -#define EFUSE_KEY4_DATA7_M ((EFUSE_KEY4_DATA7_V)<<(EFUSE_KEY4_DATA7_S)) -#define EFUSE_KEY4_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA7_REG register + * Register 7 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) +/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA7 0xFFFFFFFFU +#define EFUSE_KEY4_DATA7_M (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S) +#define EFUSE_KEY4_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA7_S 0 -#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c) -/* EFUSE_KEY5_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA0 0xFFFFFFFF -#define EFUSE_KEY5_DATA0_M ((EFUSE_KEY5_DATA0_V)<<(EFUSE_KEY5_DATA0_S)) -#define EFUSE_KEY5_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA0_REG register + * Register 0 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c) +/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA0 0xFFFFFFFFU +#define EFUSE_KEY5_DATA0_M (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S) +#define EFUSE_KEY5_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA0_S 0 -#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) -/* EFUSE_KEY5_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA1 0xFFFFFFFF -#define EFUSE_KEY5_DATA1_M ((EFUSE_KEY5_DATA1_V)<<(EFUSE_KEY5_DATA1_S)) -#define EFUSE_KEY5_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA1_REG register + * Register 1 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) +/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA1 0xFFFFFFFFU +#define EFUSE_KEY5_DATA1_M (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S) +#define EFUSE_KEY5_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA1_S 0 -#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) -/* EFUSE_KEY5_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA2 0xFFFFFFFF -#define EFUSE_KEY5_DATA2_M ((EFUSE_KEY5_DATA2_V)<<(EFUSE_KEY5_DATA2_S)) -#define EFUSE_KEY5_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA2_REG register + * Register 2 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) +/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA2 0xFFFFFFFFU +#define EFUSE_KEY5_DATA2_M (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S) +#define EFUSE_KEY5_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA2_S 0 -#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) -/* EFUSE_KEY5_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA3 0xFFFFFFFF -#define EFUSE_KEY5_DATA3_M ((EFUSE_KEY5_DATA3_V)<<(EFUSE_KEY5_DATA3_S)) -#define EFUSE_KEY5_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA3_REG register + * Register 3 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) +/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA3 0xFFFFFFFFU +#define EFUSE_KEY5_DATA3_M (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S) +#define EFUSE_KEY5_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA3_S 0 -#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c) -/* EFUSE_KEY5_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA4 0xFFFFFFFF -#define EFUSE_KEY5_DATA4_M ((EFUSE_KEY5_DATA4_V)<<(EFUSE_KEY5_DATA4_S)) -#define EFUSE_KEY5_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA4_REG register + * Register 4 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c) +/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA4 0xFFFFFFFFU +#define EFUSE_KEY5_DATA4_M (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S) +#define EFUSE_KEY5_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA4_S 0 -#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) -/* EFUSE_KEY5_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA5 0xFFFFFFFF -#define EFUSE_KEY5_DATA5_M ((EFUSE_KEY5_DATA5_V)<<(EFUSE_KEY5_DATA5_S)) -#define EFUSE_KEY5_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA5_REG register + * Register 5 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) +/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA5 0xFFFFFFFFU +#define EFUSE_KEY5_DATA5_M (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S) +#define EFUSE_KEY5_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA5_S 0 -#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) -/* EFUSE_KEY5_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA6 0xFFFFFFFF -#define EFUSE_KEY5_DATA6_M ((EFUSE_KEY5_DATA6_V)<<(EFUSE_KEY5_DATA6_S)) -#define EFUSE_KEY5_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA6_REG register + * Register 6 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) +/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA6 0xFFFFFFFFU +#define EFUSE_KEY5_DATA6_M (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S) +#define EFUSE_KEY5_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA6_S 0 -#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) -/* EFUSE_KEY5_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA7 0xFFFFFFFF -#define EFUSE_KEY5_DATA7_M ((EFUSE_KEY5_DATA7_V)<<(EFUSE_KEY5_DATA7_S)) -#define EFUSE_KEY5_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA7_REG register + * Register 7 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) +/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA7 0xFFFFFFFFU +#define EFUSE_KEY5_DATA7_M (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S) +#define EFUSE_KEY5_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA7_S 0 -#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c) -/* EFUSE_SYS_DATA_PART2_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_0_M ((EFUSE_SYS_DATA_PART2_0_V)<<(EFUSE_SYS_DATA_PART2_0_S)) -#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA0_REG register + * Register 0 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c) +/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S) +#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_0_S 0 -#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) -/* EFUSE_SYS_DATA_PART2_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_1_M ((EFUSE_SYS_DATA_PART2_1_V)<<(EFUSE_SYS_DATA_PART2_1_S)) -#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA1_REG register + * Register 1 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) +/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S) +#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_1_S 0 -#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) -/* EFUSE_SYS_DATA_PART2_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_2_M ((EFUSE_SYS_DATA_PART2_2_V)<<(EFUSE_SYS_DATA_PART2_2_S)) -#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA2_REG register + * Register 2 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) +/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S) +#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_2_S 0 -#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) -/* EFUSE_SYS_DATA_PART2_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_3_M ((EFUSE_SYS_DATA_PART2_3_V)<<(EFUSE_SYS_DATA_PART2_3_S)) -#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA3_REG register + * Register 3 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) +/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S) +#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_3_S 0 -#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c) -/* EFUSE_SYS_DATA_PART2_4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_4_M ((EFUSE_SYS_DATA_PART2_4_V)<<(EFUSE_SYS_DATA_PART2_4_S)) -#define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA4_REG register + * Register 4 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c) +/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_4_M (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S) +#define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_4_S 0 -#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) -/* EFUSE_SYS_DATA_PART2_5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_5_M ((EFUSE_SYS_DATA_PART2_5_V)<<(EFUSE_SYS_DATA_PART2_5_S)) -#define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA5_REG register + * Register 5 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) +/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_5_M (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S) +#define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_5_S 0 -#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) -/* EFUSE_SYS_DATA_PART2_6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_6_M ((EFUSE_SYS_DATA_PART2_6_V)<<(EFUSE_SYS_DATA_PART2_6_S)) -#define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA6_REG register + * Register 6 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) +/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_6_M (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S) +#define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_6_S 0 -#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) -/* EFUSE_SYS_DATA_PART2_7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_7_M ((EFUSE_SYS_DATA_PART2_7_V)<<(EFUSE_SYS_DATA_PART2_7_S)) -#define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA7_REG register + * Register 7 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) +/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_7_M (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S) +#define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_7_S 0 -#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) -/* EFUSE_VDD_SPI_DREFH_ERR : RO ;bitpos:[31:30] ;default: 2'h0 ; */ -/*description: If any bit in VDD_SPI_DREFH is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_DREFH_ERR 0x00000003 -#define EFUSE_VDD_SPI_DREFH_ERR_M ((EFUSE_VDD_SPI_DREFH_ERR_V)<<(EFUSE_VDD_SPI_DREFH_ERR_S)) -#define EFUSE_VDD_SPI_DREFH_ERR_V 0x3 -#define EFUSE_VDD_SPI_DREFH_ERR_S 30 -/* EFUSE_VDD_SPI_MODECURLIM_ERR : RO ;bitpos:[29] ;default: 1'h0 ; */ -/*description: If VDD_SPI_MODECURLIM is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_MODECURLIM_ERR (BIT(29)) -#define EFUSE_VDD_SPI_MODECURLIM_ERR_M (BIT(29)) -#define EFUSE_VDD_SPI_MODECURLIM_ERR_V 0x1 -#define EFUSE_VDD_SPI_MODECURLIM_ERR_S 29 -/* EFUSE_RPT4_RESERVED0_ERR : RO ;bitpos:[28:27] ;default: 2'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED0_ERR 0x00000003 -#define EFUSE_RPT4_RESERVED0_ERR_M ((EFUSE_RPT4_RESERVED0_ERR_V)<<(EFUSE_RPT4_RESERVED0_ERR_S)) -#define EFUSE_RPT4_RESERVED0_ERR_V 0x3 -#define EFUSE_RPT4_RESERVED0_ERR_S 27 -/* EFUSE_USB_FORCE_NOPERSIST_ERR : RO ;bitpos:[26] ;default: 1'h0 ; */ -/*description: Record error infomation of the burning result of usb_force_nopersist.*/ -#define EFUSE_USB_FORCE_NOPERSIST_ERR (BIT(26)) -#define EFUSE_USB_FORCE_NOPERSIST_ERR_M (BIT(26)) -#define EFUSE_USB_FORCE_NOPERSIST_ERR_V 0x1 -#define EFUSE_USB_FORCE_NOPERSIST_ERR_S 26 -/* EFUSE_EXT_PHY_ENABLE_ERR : RO ;bitpos:[25] ;default: 1'h0 ; */ -/*description: If EXT_PHY_ENABLE is 1 then it indicates a programming error.*/ -#define EFUSE_EXT_PHY_ENABLE_ERR (BIT(25)) -#define EFUSE_EXT_PHY_ENABLE_ERR_M (BIT(25)) -#define EFUSE_EXT_PHY_ENABLE_ERR_V 0x1 -#define EFUSE_EXT_PHY_ENABLE_ERR_S 25 -/* EFUSE_USB_EXCHG_PINS_ERR : RO ;bitpos:[24] ;default: 1'h0 ; */ -/*description: If USB_EXCHG_PINS is 1 then it indicates a programming error.*/ -#define EFUSE_USB_EXCHG_PINS_ERR (BIT(24)) -#define EFUSE_USB_EXCHG_PINS_ERR_M (BIT(24)) -#define EFUSE_USB_EXCHG_PINS_ERR_V 0x1 -#define EFUSE_USB_EXCHG_PINS_ERR_S 24 -/* EFUSE_USB_DREFL_ERR : RO ;bitpos:[23:22] ;default: 2'h0 ; */ -/*description: If any bit in USB_DREFL is 1 then it indicates a programming error.*/ -#define EFUSE_USB_DREFL_ERR 0x00000003 -#define EFUSE_USB_DREFL_ERR_M ((EFUSE_USB_DREFL_ERR_V)<<(EFUSE_USB_DREFL_ERR_S)) -#define EFUSE_USB_DREFL_ERR_V 0x3 -#define EFUSE_USB_DREFL_ERR_S 22 -/* EFUSE_USB_DREFH_ERR : RO ;bitpos:[21:20] ;default: 2'h0 ; */ -/*description: If any bit in USB_DREFH is 1 then it indicates a programming error.*/ -#define EFUSE_USB_DREFH_ERR 0x00000003 -#define EFUSE_USB_DREFH_ERR_M ((EFUSE_USB_DREFH_ERR_V)<<(EFUSE_USB_DREFH_ERR_S)) -#define EFUSE_USB_DREFH_ERR_V 0x3 -#define EFUSE_USB_DREFH_ERR_S 20 -/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO ;bitpos:[19] ;default: 1'h0 ; */ -/*description: If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(19)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (BIT(19)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 19 -/* EFUSE_HARD_DIS_JTAG_ERR : RO ;bitpos:[18] ;default: 1'h0 ; */ -/*description: If HARD_DIS_JTAG is 1 then it indicates a programming error.*/ -#define EFUSE_HARD_DIS_JTAG_ERR (BIT(18)) -#define EFUSE_HARD_DIS_JTAG_ERR_M (BIT(18)) -#define EFUSE_HARD_DIS_JTAG_ERR_V 0x1 -#define EFUSE_HARD_DIS_JTAG_ERR_S 18 -/* EFUSE_SOFT_DIS_JTAG_ERR : RO ;bitpos:[17] ;default: 1'h0 ; */ -/*description: If SOFT_DIS_JTAG is 1 then it indicates a programming error.*/ -#define EFUSE_SOFT_DIS_JTAG_ERR (BIT(17)) -#define EFUSE_SOFT_DIS_JTAG_ERR_M (BIT(17)) -#define EFUSE_SOFT_DIS_JTAG_ERR_V 0x1 -#define EFUSE_SOFT_DIS_JTAG_ERR_S 17 -/* EFUSE_DIS_EFUSE_ATE_WR_ERR : RO ;bitpos:[16] ;default: 1'h0 ; */ -/*description: If DIS_EFUSE_ATE_WR is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_EFUSE_ATE_WR_ERR (BIT(16)) -#define EFUSE_DIS_EFUSE_ATE_WR_ERR_M (BIT(16)) -#define EFUSE_DIS_EFUSE_ATE_WR_ERR_V 0x1 -#define EFUSE_DIS_EFUSE_ATE_WR_ERR_S 16 -/* EFUSE_DIS_BOOT_REMAP_ERR : RO ;bitpos:[15] ;default: 1'h0 ; */ -/*description: If DIS_BOOT_REMAP is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_BOOT_REMAP_ERR (BIT(15)) -#define EFUSE_DIS_BOOT_REMAP_ERR_M (BIT(15)) -#define EFUSE_DIS_BOOT_REMAP_ERR_V 0x1 -#define EFUSE_DIS_BOOT_REMAP_ERR_S 15 -/* EFUSE_DIS_CAN_ERR : RO ;bitpos:[14] ;default: 1'h0 ; */ -/*description: If DIS_CAN is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_CAN_ERR (BIT(14)) -#define EFUSE_DIS_CAN_ERR_M (BIT(14)) -#define EFUSE_DIS_CAN_ERR_V 0x1 -#define EFUSE_DIS_CAN_ERR_S 14 -/* EFUSE_DIS_USB_ERR : RO ;bitpos:[13] ;default: 1'h0 ; */ -/*description: If DIS_USB is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_USB_ERR (BIT(13)) -#define EFUSE_DIS_USB_ERR_M (BIT(13)) -#define EFUSE_DIS_USB_ERR_V 0x1 -#define EFUSE_DIS_USB_ERR_S 13 -/* EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO ;bitpos:[12] ;default: 1'h0 ; */ -/*description: If DIS_FORCE_DOWNLOAD is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x1 -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 -/* EFUSE_DIS_DOWNLOAD_DCACHE_ERR : RO ;bitpos:[11] ;default: 1'h0 ; */ -/*description: If DIS_DOWNLOAD_DCACHE is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR (BIT(11)) -#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_M (BIT(11)) -#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V 0x1 -#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S 11 -/* EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO ;bitpos:[10] ;default: 1'h0 ; */ -/*description: If DIS_DOWNLOAD_ICACHE is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V 0x1 -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S 10 -/* EFUSE_DIS_DCACHE_ERR : RO ;bitpos:[9] ;default: 1'h0 ; */ -/*description: If DIS_DCACHE is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_DCACHE_ERR (BIT(9)) -#define EFUSE_DIS_DCACHE_ERR_M (BIT(9)) -#define EFUSE_DIS_DCACHE_ERR_V 0x1 -#define EFUSE_DIS_DCACHE_ERR_S 9 -/* EFUSE_DIS_ICACHE_ERR : RO ;bitpos:[8] ;default: 1'h0 ; */ -/*description: If DIS_ICACHE is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_ICACHE_ERR (BIT(8)) -#define EFUSE_DIS_ICACHE_ERR_M (BIT(8)) -#define EFUSE_DIS_ICACHE_ERR_V 0x1 -#define EFUSE_DIS_ICACHE_ERR_S 8 -/* EFUSE_DIS_RTC_RAM_BOOT_ERR : RO ;bitpos:[7] ;default: 1'h0 ; */ -/*description: If DIS_RTC_RAM_BOOT is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_RTC_RAM_BOOT_ERR (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_ERR_M (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_ERR_V 0x1 -#define EFUSE_DIS_RTC_RAM_BOOT_ERR_S 7 -/* EFUSE_RD_DIS_ERR : RO ;bitpos:[6:0] ;default: 7'h0 ; */ -/*description: If any bit in RD_DIS is 1 then it indicates a programming error.*/ -#define EFUSE_RD_DIS_ERR 0x0000007F -#define EFUSE_RD_DIS_ERR_M ((EFUSE_RD_DIS_ERR_V)<<(EFUSE_RD_DIS_ERR_S)) -#define EFUSE_RD_DIS_ERR_V 0x7F +/** EFUSE_RD_REPEAT_ERR0_REG register + * Programming error record register 0 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) +/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_RD_DIS. + */ +#define EFUSE_RD_DIS_ERR 0x0000007FU +#define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S) +#define EFUSE_RD_DIS_ERR_V 0x0000007FU #define EFUSE_RD_DIS_ERR_S 0 +/** EFUSE_DIS_RTC_RAM_BOOT_ERR : RO; bitpos: [7]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_RTC_RAM_BOOT. + */ +#define EFUSE_DIS_RTC_RAM_BOOT_ERR (BIT(7)) +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_M (EFUSE_DIS_RTC_RAM_BOOT_ERR_V << EFUSE_DIS_RTC_RAM_BOOT_ERR_S) +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_V 0x00000001U +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_S 7 +/** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_ICACHE. + */ +#define EFUSE_DIS_ICACHE_ERR (BIT(8)) +#define EFUSE_DIS_ICACHE_ERR_M (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S) +#define EFUSE_DIS_ICACHE_ERR_V 0x00000001U +#define EFUSE_DIS_ICACHE_ERR_S 8 +/** EFUSE_DIS_DCACHE_ERR : RO; bitpos: [9]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_DCACHE. + */ +#define EFUSE_DIS_DCACHE_ERR (BIT(9)) +#define EFUSE_DIS_DCACHE_ERR_M (EFUSE_DIS_DCACHE_ERR_V << EFUSE_DIS_DCACHE_ERR_S) +#define EFUSE_DIS_DCACHE_ERR_V 0x00000001U +#define EFUSE_DIS_DCACHE_ERR_S 9 +/** EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO; bitpos: [10]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_ICACHE. + */ +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR (BIT(10)) +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M (EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V << EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S 10 +/** EFUSE_DIS_DOWNLOAD_DCACHE_ERR : RO; bitpos: [11]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_DCACHE. + */ +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR (BIT(11)) +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_M (EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V << EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S 11 +/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_FORCE_DOWNLOAD. + */ +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x00000001U +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 +/** EFUSE_DIS_USB_ERR : RO; bitpos: [13]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_USB. + */ +#define EFUSE_DIS_USB_ERR (BIT(13)) +#define EFUSE_DIS_USB_ERR_M (EFUSE_DIS_USB_ERR_V << EFUSE_DIS_USB_ERR_S) +#define EFUSE_DIS_USB_ERR_V 0x00000001U +#define EFUSE_DIS_USB_ERR_S 13 +/** EFUSE_DIS_CAN_ERR : RO; bitpos: [14]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_CAN. + */ +#define EFUSE_DIS_CAN_ERR (BIT(14)) +#define EFUSE_DIS_CAN_ERR_M (EFUSE_DIS_CAN_ERR_V << EFUSE_DIS_CAN_ERR_S) +#define EFUSE_DIS_CAN_ERR_V 0x00000001U +#define EFUSE_DIS_CAN_ERR_S 14 +/** EFUSE_DIS_BOOT_REMAP_ERR : RO; bitpos: [15]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_BOOT_REMAP. + */ +#define EFUSE_DIS_BOOT_REMAP_ERR (BIT(15)) +#define EFUSE_DIS_BOOT_REMAP_ERR_M (EFUSE_DIS_BOOT_REMAP_ERR_V << EFUSE_DIS_BOOT_REMAP_ERR_S) +#define EFUSE_DIS_BOOT_REMAP_ERR_V 0x00000001U +#define EFUSE_DIS_BOOT_REMAP_ERR_S 15 +/** EFUSE_RPT4_RESERVED5_ERR : RO; bitpos: [16]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED5. + */ +#define EFUSE_RPT4_RESERVED5_ERR (BIT(16)) +#define EFUSE_RPT4_RESERVED5_ERR_M (EFUSE_RPT4_RESERVED5_ERR_V << EFUSE_RPT4_RESERVED5_ERR_S) +#define EFUSE_RPT4_RESERVED5_ERR_V 0x00000001U +#define EFUSE_RPT4_RESERVED5_ERR_S 16 +/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [17]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_SOFT_DIS_JTAG. + */ +#define EFUSE_SOFT_DIS_JTAG_ERR (BIT(17)) +#define EFUSE_SOFT_DIS_JTAG_ERR_M (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S) +#define EFUSE_SOFT_DIS_JTAG_ERR_V 0x00000001U +#define EFUSE_SOFT_DIS_JTAG_ERR_S 17 +/** EFUSE_HARD_DIS_JTAG_ERR : RO; bitpos: [18]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_HARD_DIS_JTAG. + */ +#define EFUSE_HARD_DIS_JTAG_ERR (BIT(18)) +#define EFUSE_HARD_DIS_JTAG_ERR_M (EFUSE_HARD_DIS_JTAG_ERR_V << EFUSE_HARD_DIS_JTAG_ERR_S) +#define EFUSE_HARD_DIS_JTAG_ERR_V 0x00000001U +#define EFUSE_HARD_DIS_JTAG_ERR_S 18 +/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [19]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT. + */ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(19)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 19 +/** EFUSE_USB_DREFH_ERR : RO; bitpos: [21:20]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_USB_DREFH. + */ +#define EFUSE_USB_DREFH_ERR 0x00000003U +#define EFUSE_USB_DREFH_ERR_M (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S) +#define EFUSE_USB_DREFH_ERR_V 0x00000003U +#define EFUSE_USB_DREFH_ERR_S 20 +/** EFUSE_USB_DREFL_ERR : RO; bitpos: [23:22]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_USB_DREFL. + */ +#define EFUSE_USB_DREFL_ERR 0x00000003U +#define EFUSE_USB_DREFL_ERR_M (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S) +#define EFUSE_USB_DREFL_ERR_V 0x00000003U +#define EFUSE_USB_DREFL_ERR_S 22 +/** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [24]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_USB_EXCHG_PINS. + */ +#define EFUSE_USB_EXCHG_PINS_ERR (BIT(24)) +#define EFUSE_USB_EXCHG_PINS_ERR_M (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S) +#define EFUSE_USB_EXCHG_PINS_ERR_V 0x00000001U +#define EFUSE_USB_EXCHG_PINS_ERR_S 24 +/** EFUSE_EXT_PHY_ENABLE_ERR : RO; bitpos: [25]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_EXT_PHY_ENABLE. + */ +#define EFUSE_EXT_PHY_ENABLE_ERR (BIT(25)) +#define EFUSE_EXT_PHY_ENABLE_ERR_M (EFUSE_EXT_PHY_ENABLE_ERR_V << EFUSE_EXT_PHY_ENABLE_ERR_S) +#define EFUSE_EXT_PHY_ENABLE_ERR_V 0x00000001U +#define EFUSE_EXT_PHY_ENABLE_ERR_S 25 +/** EFUSE_USB_FORCE_NOPERSIST_ERR : RO; bitpos: [26]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_USB_FORCE_NOPERSIST. + */ +#define EFUSE_USB_FORCE_NOPERSIST_ERR (BIT(26)) +#define EFUSE_USB_FORCE_NOPERSIST_ERR_M (EFUSE_USB_FORCE_NOPERSIST_ERR_V << EFUSE_USB_FORCE_NOPERSIST_ERR_S) +#define EFUSE_USB_FORCE_NOPERSIST_ERR_V 0x00000001U +#define EFUSE_USB_FORCE_NOPERSIST_ERR_S 26 +/** EFUSE_RPT4_RESERVED0_ERR : RO; bitpos: [28:27]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED0. + */ +#define EFUSE_RPT4_RESERVED0_ERR 0x00000003U +#define EFUSE_RPT4_RESERVED0_ERR_M (EFUSE_RPT4_RESERVED0_ERR_V << EFUSE_RPT4_RESERVED0_ERR_S) +#define EFUSE_RPT4_RESERVED0_ERR_V 0x00000003U +#define EFUSE_RPT4_RESERVED0_ERR_S 27 +/** EFUSE_VDD_SPI_MODECURLIM_ERR : RO; bitpos: [29]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_MODECURLIM. + */ +#define EFUSE_VDD_SPI_MODECURLIM_ERR (BIT(29)) +#define EFUSE_VDD_SPI_MODECURLIM_ERR_M (EFUSE_VDD_SPI_MODECURLIM_ERR_V << EFUSE_VDD_SPI_MODECURLIM_ERR_S) +#define EFUSE_VDD_SPI_MODECURLIM_ERR_V 0x00000001U +#define EFUSE_VDD_SPI_MODECURLIM_ERR_S 29 +/** EFUSE_VDD_SPI_DREFH_ERR : RO; bitpos: [31:30]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DREFH. + */ +#define EFUSE_VDD_SPI_DREFH_ERR 0x00000003U +#define EFUSE_VDD_SPI_DREFH_ERR_M (EFUSE_VDD_SPI_DREFH_ERR_V << EFUSE_VDD_SPI_DREFH_ERR_S) +#define EFUSE_VDD_SPI_DREFH_ERR_V 0x00000003U +#define EFUSE_VDD_SPI_DREFH_ERR_S 30 -#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) -/* EFUSE_KEY_PURPOSE_1_ERR : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_1 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_1_ERR_M ((EFUSE_KEY_PURPOSE_1_ERR_V)<<(EFUSE_KEY_PURPOSE_1_ERR_S)) -#define EFUSE_KEY_PURPOSE_1_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_1_ERR_S 28 -/* EFUSE_KEY_PURPOSE_0_ERR : RO ;bitpos:[27:24] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_0 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_0_ERR_M ((EFUSE_KEY_PURPOSE_0_ERR_V)<<(EFUSE_KEY_PURPOSE_0_ERR_S)) -#define EFUSE_KEY_PURPOSE_0_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_0_ERR_S 24 -/* EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO ;bitpos:[23] ;default: 1'h0 ; */ -/*description: If SECURE_BOOT_KEY_REVOKE2 is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 -/* EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO ;bitpos:[22] ;default: 1'h0 ; */ -/*description: If SECURE_BOOT_KEY_REVOKE1 is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 -/* EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO ;bitpos:[21] ;default: 1'h0 ; */ -/*description: If SECURE_BOOT_KEY_REVOKE0 is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 -/* EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: If any bit in SPI_BOOT_CRYPT_CNT is 1 then it indicates a programming error.*/ -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M ((EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)) -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x7 -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 -/* EFUSE_WDT_DELAY_SEL_ERR : RO ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: If any bit in WDT_DELAY_SEL is 1 then it indicates a programming error.*/ -#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003 -#define EFUSE_WDT_DELAY_SEL_ERR_M ((EFUSE_WDT_DELAY_SEL_ERR_V)<<(EFUSE_WDT_DELAY_SEL_ERR_S)) -#define EFUSE_WDT_DELAY_SEL_ERR_V 0x3 -#define EFUSE_WDT_DELAY_SEL_ERR_S 16 -/* EFUSE_VDD_SPI_DCAP_ERR : RO ;bitpos:[15:14] ;default: 2'h0 ; */ -/*description: If any bit in VDD_SPI_DCAP is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_DCAP_ERR 0x00000003 -#define EFUSE_VDD_SPI_DCAP_ERR_M ((EFUSE_VDD_SPI_DCAP_ERR_V)<<(EFUSE_VDD_SPI_DCAP_ERR_S)) -#define EFUSE_VDD_SPI_DCAP_ERR_V 0x3 -#define EFUSE_VDD_SPI_DCAP_ERR_S 14 -/* EFUSE_VDD_SPI_INIT_ERR : RO ;bitpos:[13:12] ;default: 2'h0 ; */ -/*description: If any bit in VDD_SPI_INIT is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_INIT_ERR 0x00000003 -#define EFUSE_VDD_SPI_INIT_ERR_M ((EFUSE_VDD_SPI_INIT_ERR_V)<<(EFUSE_VDD_SPI_INIT_ERR_S)) -#define EFUSE_VDD_SPI_INIT_ERR_V 0x3 -#define EFUSE_VDD_SPI_INIT_ERR_S 12 -/* EFUSE_VDD_SPI_DCURLIM_ERR : RO ;bitpos:[11:9] ;default: 3'h0 ; */ -/*description: If any bit in VDD_SPI_DCURLIM is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_DCURLIM_ERR 0x00000007 -#define EFUSE_VDD_SPI_DCURLIM_ERR_M ((EFUSE_VDD_SPI_DCURLIM_ERR_V)<<(EFUSE_VDD_SPI_DCURLIM_ERR_S)) -#define EFUSE_VDD_SPI_DCURLIM_ERR_V 0x7 -#define EFUSE_VDD_SPI_DCURLIM_ERR_S 9 -/* EFUSE_VDD_SPI_ENCURLIM_ERR : RO ;bitpos:[8] ;default: 1'h0 ; */ -/*description: If VDD_SPI_ENCURLIM is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_ENCURLIM_ERR (BIT(8)) -#define EFUSE_VDD_SPI_ENCURLIM_ERR_M (BIT(8)) -#define EFUSE_VDD_SPI_ENCURLIM_ERR_V 0x1 -#define EFUSE_VDD_SPI_ENCURLIM_ERR_S 8 -/* EFUSE_VDD_SPI_EN_INIT_ERR : RO ;bitpos:[7] ;default: 1'h0 ; */ -/*description: If VDD_SPI_EN_INIT is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_EN_INIT_ERR (BIT(7)) -#define EFUSE_VDD_SPI_EN_INIT_ERR_M (BIT(7)) -#define EFUSE_VDD_SPI_EN_INIT_ERR_V 0x1 -#define EFUSE_VDD_SPI_EN_INIT_ERR_S 7 -/* EFUSE_VDD_SPI_FORCE_ERR : RO ;bitpos:[6] ;default: 1'h0 ; */ -/*description: If VDD_SPI_FORCE is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_FORCE_ERR (BIT(6)) -#define EFUSE_VDD_SPI_FORCE_ERR_M (BIT(6)) -#define EFUSE_VDD_SPI_FORCE_ERR_V 0x1 -#define EFUSE_VDD_SPI_FORCE_ERR_S 6 -/* EFUSE_VDD_SPI_TIEH_ERR : RO ;bitpos:[5] ;default: 1'h0 ; */ -/*description: If VDD_SPI_TIEH is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_TIEH_ERR (BIT(5)) -#define EFUSE_VDD_SPI_TIEH_ERR_M (BIT(5)) -#define EFUSE_VDD_SPI_TIEH_ERR_V 0x1 -#define EFUSE_VDD_SPI_TIEH_ERR_S 5 -/* EFUSE_VDD_SPI_XPD_ERR : RO ;bitpos:[4] ;default: 1'h0 ; */ -/*description: If VDD_SPI_XPD is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_XPD_ERR (BIT(4)) -#define EFUSE_VDD_SPI_XPD_ERR_M (BIT(4)) -#define EFUSE_VDD_SPI_XPD_ERR_V 0x1 -#define EFUSE_VDD_SPI_XPD_ERR_S 4 -/* EFUSE_VDD_SPI_DREFL_ERR : RO ;bitpos:[3:2] ;default: 2'h0 ; */ -/*description: If any bit in VDD_SPI_DREFL is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_DREFL_ERR 0x00000003 -#define EFUSE_VDD_SPI_DREFL_ERR_M ((EFUSE_VDD_SPI_DREFL_ERR_V)<<(EFUSE_VDD_SPI_DREFL_ERR_S)) -#define EFUSE_VDD_SPI_DREFL_ERR_V 0x3 -#define EFUSE_VDD_SPI_DREFL_ERR_S 2 -/* EFUSE_VDD_SPI_DREFM_ERR : RO ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: If any bit in VDD_SPI_DREFM is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_DREFM_ERR 0x00000003 -#define EFUSE_VDD_SPI_DREFM_ERR_M ((EFUSE_VDD_SPI_DREFM_ERR_V)<<(EFUSE_VDD_SPI_DREFM_ERR_S)) -#define EFUSE_VDD_SPI_DREFM_ERR_V 0x3 +/** EFUSE_RD_REPEAT_ERR1_REG register + * Programming error record register 1 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) +/** EFUSE_VDD_SPI_DREFM_ERR : RO; bitpos: [1:0]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DREFM. + */ +#define EFUSE_VDD_SPI_DREFM_ERR 0x00000003U +#define EFUSE_VDD_SPI_DREFM_ERR_M (EFUSE_VDD_SPI_DREFM_ERR_V << EFUSE_VDD_SPI_DREFM_ERR_S) +#define EFUSE_VDD_SPI_DREFM_ERR_V 0x00000003U #define EFUSE_VDD_SPI_DREFM_ERR_S 0 +/** EFUSE_VDD_SPI_DREFL_ERR : RO; bitpos: [3:2]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DREFL. + */ +#define EFUSE_VDD_SPI_DREFL_ERR 0x00000003U +#define EFUSE_VDD_SPI_DREFL_ERR_M (EFUSE_VDD_SPI_DREFL_ERR_V << EFUSE_VDD_SPI_DREFL_ERR_S) +#define EFUSE_VDD_SPI_DREFL_ERR_V 0x00000003U +#define EFUSE_VDD_SPI_DREFL_ERR_S 2 +/** EFUSE_VDD_SPI_XPD_ERR : RO; bitpos: [4]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_XPD. + */ +#define EFUSE_VDD_SPI_XPD_ERR (BIT(4)) +#define EFUSE_VDD_SPI_XPD_ERR_M (EFUSE_VDD_SPI_XPD_ERR_V << EFUSE_VDD_SPI_XPD_ERR_S) +#define EFUSE_VDD_SPI_XPD_ERR_V 0x00000001U +#define EFUSE_VDD_SPI_XPD_ERR_S 4 +/** EFUSE_VDD_SPI_TIEH_ERR : RO; bitpos: [5]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_TIEH. + */ +#define EFUSE_VDD_SPI_TIEH_ERR (BIT(5)) +#define EFUSE_VDD_SPI_TIEH_ERR_M (EFUSE_VDD_SPI_TIEH_ERR_V << EFUSE_VDD_SPI_TIEH_ERR_S) +#define EFUSE_VDD_SPI_TIEH_ERR_V 0x00000001U +#define EFUSE_VDD_SPI_TIEH_ERR_S 5 +/** EFUSE_VDD_SPI_FORCE_ERR : RO; bitpos: [6]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_FORCE. + */ +#define EFUSE_VDD_SPI_FORCE_ERR (BIT(6)) +#define EFUSE_VDD_SPI_FORCE_ERR_M (EFUSE_VDD_SPI_FORCE_ERR_V << EFUSE_VDD_SPI_FORCE_ERR_S) +#define EFUSE_VDD_SPI_FORCE_ERR_V 0x00000001U +#define EFUSE_VDD_SPI_FORCE_ERR_S 6 +/** EFUSE_VDD_SPI_EN_INIT_ERR : RO; bitpos: [7]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_EN_INIT. + */ +#define EFUSE_VDD_SPI_EN_INIT_ERR (BIT(7)) +#define EFUSE_VDD_SPI_EN_INIT_ERR_M (EFUSE_VDD_SPI_EN_INIT_ERR_V << EFUSE_VDD_SPI_EN_INIT_ERR_S) +#define EFUSE_VDD_SPI_EN_INIT_ERR_V 0x00000001U +#define EFUSE_VDD_SPI_EN_INIT_ERR_S 7 +/** EFUSE_VDD_SPI_ENCURLIM_ERR : RO; bitpos: [8]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_ENCURLIM. + */ +#define EFUSE_VDD_SPI_ENCURLIM_ERR (BIT(8)) +#define EFUSE_VDD_SPI_ENCURLIM_ERR_M (EFUSE_VDD_SPI_ENCURLIM_ERR_V << EFUSE_VDD_SPI_ENCURLIM_ERR_S) +#define EFUSE_VDD_SPI_ENCURLIM_ERR_V 0x00000001U +#define EFUSE_VDD_SPI_ENCURLIM_ERR_S 8 +/** EFUSE_VDD_SPI_DCURLIM_ERR : RO; bitpos: [11:9]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DCURLIM. + */ +#define EFUSE_VDD_SPI_DCURLIM_ERR 0x00000007U +#define EFUSE_VDD_SPI_DCURLIM_ERR_M (EFUSE_VDD_SPI_DCURLIM_ERR_V << EFUSE_VDD_SPI_DCURLIM_ERR_S) +#define EFUSE_VDD_SPI_DCURLIM_ERR_V 0x00000007U +#define EFUSE_VDD_SPI_DCURLIM_ERR_S 9 +/** EFUSE_VDD_SPI_INIT_ERR : RO; bitpos: [13:12]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_INIT. + */ +#define EFUSE_VDD_SPI_INIT_ERR 0x00000003U +#define EFUSE_VDD_SPI_INIT_ERR_M (EFUSE_VDD_SPI_INIT_ERR_V << EFUSE_VDD_SPI_INIT_ERR_S) +#define EFUSE_VDD_SPI_INIT_ERR_V 0x00000003U +#define EFUSE_VDD_SPI_INIT_ERR_S 12 +/** EFUSE_VDD_SPI_DCAP_ERR : RO; bitpos: [15:14]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DCAP. + */ +#define EFUSE_VDD_SPI_DCAP_ERR 0x00000003U +#define EFUSE_VDD_SPI_DCAP_ERR_M (EFUSE_VDD_SPI_DCAP_ERR_V << EFUSE_VDD_SPI_DCAP_ERR_S) +#define EFUSE_VDD_SPI_DCAP_ERR_V 0x00000003U +#define EFUSE_VDD_SPI_DCAP_ERR_S 14 +/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_WDT_DELAY_SEL. + */ +#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003U +#define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) +#define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003U +#define EFUSE_WDT_DELAY_SEL_ERR_S 16 +/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_SPI_BOOT_CRYPT_CNT. + */ +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 +/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_KEY_REVOKE0. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 +/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_KEY_REVOKE1. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 +/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_KEY_REVOKE2. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 +/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_0. + */ +#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_ERR_M (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S) +#define EFUSE_KEY_PURPOSE_0_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_ERR_S 24 +/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_1. + */ +#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_ERR_M (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S) +#define EFUSE_KEY_PURPOSE_1_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_ERR_S 28 -#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) -/* EFUSE_FLASH_TPUW_ERR : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: If any bit in FLASH_TPUM is 1 then it indicates a programming error.*/ -#define EFUSE_FLASH_TPUW_ERR 0x0000000F -#define EFUSE_FLASH_TPUW_ERR_M ((EFUSE_FLASH_TPUW_ERR_V)<<(EFUSE_FLASH_TPUW_ERR_S)) -#define EFUSE_FLASH_TPUW_ERR_V 0xF -#define EFUSE_FLASH_TPUW_ERR_S 28 -/* EFUSE_RPT4_RESERVED1_ERR : RO ;bitpos:[27:22] ;default: 6'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED1_ERR 0x0000003F -#define EFUSE_RPT4_RESERVED1_ERR_M ((EFUSE_RPT4_RESERVED1_ERR_V)<<(EFUSE_RPT4_RESERVED1_ERR_S)) -#define EFUSE_RPT4_RESERVED1_ERR_V 0x3F -#define EFUSE_RPT4_RESERVED1_ERR_S 22 -/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO ;bitpos:[21] ;default: 1'h0 ; */ -/*description: If SECURE_BOOT_AGGRESSIVE_REVOKE is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 -/* EFUSE_SECURE_BOOT_EN_ERR : RO ;bitpos:[20] ;default: 1'h0 ; */ -/*description: If SECURE_BOOT_EN is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_ERR_M (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_EN_ERR_S 20 -/* EFUSE_KEY_PURPOSE_6_ERR : RO ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_6 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_6_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_6_ERR_M ((EFUSE_KEY_PURPOSE_6_ERR_V)<<(EFUSE_KEY_PURPOSE_6_ERR_S)) -#define EFUSE_KEY_PURPOSE_6_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_6_ERR_S 16 -/* EFUSE_KEY_PURPOSE_5_ERR : RO ;bitpos:[15:12] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_5 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_5_ERR_M ((EFUSE_KEY_PURPOSE_5_ERR_V)<<(EFUSE_KEY_PURPOSE_5_ERR_S)) -#define EFUSE_KEY_PURPOSE_5_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_5_ERR_S 12 -/* EFUSE_KEY_PURPOSE_4_ERR : RO ;bitpos:[11:8] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_4 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_4_ERR_M ((EFUSE_KEY_PURPOSE_4_ERR_V)<<(EFUSE_KEY_PURPOSE_4_ERR_S)) -#define EFUSE_KEY_PURPOSE_4_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_4_ERR_S 8 -/* EFUSE_KEY_PURPOSE_3_ERR : RO ;bitpos:[7:4] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_3 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_3_ERR_M ((EFUSE_KEY_PURPOSE_3_ERR_V)<<(EFUSE_KEY_PURPOSE_3_ERR_S)) -#define EFUSE_KEY_PURPOSE_3_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_3_ERR_S 4 -/* EFUSE_KEY_PURPOSE_2_ERR : RO ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_2 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_2_ERR_M ((EFUSE_KEY_PURPOSE_2_ERR_V)<<(EFUSE_KEY_PURPOSE_2_ERR_S)) -#define EFUSE_KEY_PURPOSE_2_ERR_V 0xF +/** EFUSE_RD_REPEAT_ERR2_REG register + * Programming error record register 2 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) +/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_2. + */ +#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_ERR_M (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S) +#define EFUSE_KEY_PURPOSE_2_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_2_ERR_S 0 +/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_3. + */ +#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_ERR_M (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S) +#define EFUSE_KEY_PURPOSE_3_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_ERR_S 4 +/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_4. + */ +#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_ERR_M (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S) +#define EFUSE_KEY_PURPOSE_4_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_ERR_S 8 +/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_5. + */ +#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_ERR_M (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S) +#define EFUSE_KEY_PURPOSE_5_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_ERR_S 12 +/** EFUSE_KEY_PURPOSE_6_ERR : RO; bitpos: [19:16]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_6. + */ +#define EFUSE_KEY_PURPOSE_6_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_6_ERR_M (EFUSE_KEY_PURPOSE_6_ERR_V << EFUSE_KEY_PURPOSE_6_ERR_S) +#define EFUSE_KEY_PURPOSE_6_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_6_ERR_S 16 +/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_EN. + */ +#define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S) +#define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_EN_ERR_S 20 +/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0; + * Any bit equal to 1 denotes a programming error in + * EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE. + */ +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 +/** EFUSE_RPT4_RESERVED1_ERR : RO; bitpos: [27:22]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED1. + */ +#define EFUSE_RPT4_RESERVED1_ERR 0x0000003FU +#define EFUSE_RPT4_RESERVED1_ERR_M (EFUSE_RPT4_RESERVED1_ERR_V << EFUSE_RPT4_RESERVED1_ERR_S) +#define EFUSE_RPT4_RESERVED1_ERR_V 0x0000003FU +#define EFUSE_RPT4_RESERVED1_ERR_S 22 +/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_FLASH_TPUW. + */ +#define EFUSE_FLASH_TPUW_ERR 0x0000000FU +#define EFUSE_FLASH_TPUW_ERR_M (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S) +#define EFUSE_FLASH_TPUW_ERR_V 0x0000000FU +#define EFUSE_FLASH_TPUW_ERR_S 28 -#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) -/* EFUSE_RPT4_RESERVED2_ERR : RO ;bitpos:[31:27] ;default: 5'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED2_ERR 0x0000001F -#define EFUSE_RPT4_RESERVED2_ERR_M ((EFUSE_RPT4_RESERVED2_ERR_V)<<(EFUSE_RPT4_RESERVED2_ERR_S)) -#define EFUSE_RPT4_RESERVED2_ERR_V 0x1F -#define EFUSE_RPT4_RESERVED2_ERR_S 27 -/* EFUSE_SECURE_VERSION_ERR : RO ;bitpos:[26:11] ;default: 16'h0 ; */ -/*description: If any bit in SECURE_VERSION is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_VERSION_ERR 0x0000FFFF -#define EFUSE_SECURE_VERSION_ERR_M ((EFUSE_SECURE_VERSION_ERR_V)<<(EFUSE_SECURE_VERSION_ERR_S)) -#define EFUSE_SECURE_VERSION_ERR_V 0xFFFF -#define EFUSE_SECURE_VERSION_ERR_S 11 -/* EFUSE_FORCE_SEND_RESUME_ERR : RO ;bitpos:[10] ;default: 1'h0 ; */ -/*description: If FORCE_SEND_RESUME is 1 then it indicates a programming error.*/ -#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(10)) -#define EFUSE_FORCE_SEND_RESUME_ERR_M (BIT(10)) -#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x1 -#define EFUSE_FORCE_SEND_RESUME_ERR_S 10 -/* EFUSE_FLASH_TYPE_ERR : RO ;bitpos:[9] ;default: 1'h0 ; */ -/*description: If FLASH_TYPE is 1 then it indicates a programming error.*/ -#define EFUSE_FLASH_TYPE_ERR (BIT(9)) -#define EFUSE_FLASH_TYPE_ERR_M (BIT(9)) -#define EFUSE_FLASH_TYPE_ERR_V 0x1 -#define EFUSE_FLASH_TYPE_ERR_S 9 -/* EFUSE_PIN_POWER_SELECTION_ERR : RO ;bitpos:[8] ;default: 1'h0 ; */ -/*description: If PIN_POWER_SELECTION is 1 then it indicates a programming error.*/ -#define EFUSE_PIN_POWER_SELECTION_ERR (BIT(8)) -#define EFUSE_PIN_POWER_SELECTION_ERR_M (BIT(8)) -#define EFUSE_PIN_POWER_SELECTION_ERR_V 0x1 -#define EFUSE_PIN_POWER_SELECTION_ERR_S 8 -/* EFUSE_UART_PRINT_CONTROL_ERR : RO ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: If any bit in UART_PRINT_CONTROL is 1 then it indicates a programming error.*/ -#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_ERR_M ((EFUSE_UART_PRINT_CONTROL_ERR_V)<<(EFUSE_UART_PRINT_CONTROL_ERR_S)) -#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x3 -#define EFUSE_UART_PRINT_CONTROL_ERR_S 6 -/* EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO ;bitpos:[5] ;default: 1'h0 ; */ -/*description: If ENABLE_SECURITY_DOWNLOAD is 1 then it indicates a programming error.*/ -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x1 -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 -/* EFUSE_DIS_USB_DOWNLOAD_MODE_ERR : RO ;bitpos:[4] ;default: 1'h0 ; */ -/*description: If DIS_USB_DOWNLOAD_MODE is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR (BIT(4)) -#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_M (BIT(4)) -#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V 0x1 -#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S 4 -/* EFUSE_RPT4_RESERVED3_ERR : RO ;bitpos:[3] ;default: 1'h0 ; */ -/*description: If RPT4_RESERVED3 is 1 then it indicates a programming error.*/ -#define EFUSE_RPT4_RESERVED3_ERR (BIT(3)) -#define EFUSE_RPT4_RESERVED3_ERR_M (BIT(3)) -#define EFUSE_RPT4_RESERVED3_ERR_V 0x1 -#define EFUSE_RPT4_RESERVED3_ERR_S 3 -/* EFUSE_UART_PRINT_CHANNEL_ERR : RO ;bitpos:[2] ;default: 1'h0 ; */ -/*description: If UART_PRINT_CHANNEL is 1 then it indicates a programming error.*/ -#define EFUSE_UART_PRINT_CHANNEL_ERR (BIT(2)) -#define EFUSE_UART_PRINT_CHANNEL_ERR_M (BIT(2)) -#define EFUSE_UART_PRINT_CHANNEL_ERR_V 0x1 -#define EFUSE_UART_PRINT_CHANNEL_ERR_S 2 -/* EFUSE_DIS_LEGACY_SPI_BOOT_ERR : RO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: If DIS_LEGACY_SPI_BOOT is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR (BIT(1)) -#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_M (BIT(1)) -#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V 0x1 -#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S 1 -/* EFUSE_DIS_DOWNLOAD_MODE_ERR : RO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: If DIS_DOWNLOAD_MODE is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x1 +/** EFUSE_RD_REPEAT_ERR3_REG register + * Programming error record register 3 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) +/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_MODE. + */ +#define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 +/** EFUSE_DIS_LEGACY_SPI_BOOT_ERR : RO; bitpos: [1]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_LEGACY_SPI_BOOT. + */ +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR (BIT(1)) +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_M (EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V << EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S) +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V 0x00000001U +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S 1 +/** EFUSE_UART_PRINT_CHANNEL_ERR : RO; bitpos: [2]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_UART_PRINT_CHANNEL. + */ +#define EFUSE_UART_PRINT_CHANNEL_ERR (BIT(2)) +#define EFUSE_UART_PRINT_CHANNEL_ERR_M (EFUSE_UART_PRINT_CHANNEL_ERR_V << EFUSE_UART_PRINT_CHANNEL_ERR_S) +#define EFUSE_UART_PRINT_CHANNEL_ERR_V 0x00000001U +#define EFUSE_UART_PRINT_CHANNEL_ERR_S 2 +/** EFUSE_RPT4_RESERVED3_ERR : RO; bitpos: [3]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED3. + */ +#define EFUSE_RPT4_RESERVED3_ERR (BIT(3)) +#define EFUSE_RPT4_RESERVED3_ERR_M (EFUSE_RPT4_RESERVED3_ERR_V << EFUSE_RPT4_RESERVED3_ERR_S) +#define EFUSE_RPT4_RESERVED3_ERR_V 0x00000001U +#define EFUSE_RPT4_RESERVED3_ERR_S 3 +/** EFUSE_DIS_USB_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_USB_DOWNLOAD_MODE. + */ +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR (BIT(4)) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V 0x00000001U +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S 4 +/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_ENABLE_SECURITY_DOWNLOAD. + */ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x00000001U +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 +/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_UART_PRINT_CONTROL. + */ +#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_ERR_M (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S) +#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_ERR_S 6 +/** EFUSE_PIN_POWER_SELECTION_ERR : RO; bitpos: [8]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_PIN_POWER_SELECTION. + */ +#define EFUSE_PIN_POWER_SELECTION_ERR (BIT(8)) +#define EFUSE_PIN_POWER_SELECTION_ERR_M (EFUSE_PIN_POWER_SELECTION_ERR_V << EFUSE_PIN_POWER_SELECTION_ERR_S) +#define EFUSE_PIN_POWER_SELECTION_ERR_V 0x00000001U +#define EFUSE_PIN_POWER_SELECTION_ERR_S 8 +/** EFUSE_FLASH_TYPE_ERR : RO; bitpos: [9]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_FLASH_TYPE. + */ +#define EFUSE_FLASH_TYPE_ERR (BIT(9)) +#define EFUSE_FLASH_TYPE_ERR_M (EFUSE_FLASH_TYPE_ERR_V << EFUSE_FLASH_TYPE_ERR_S) +#define EFUSE_FLASH_TYPE_ERR_V 0x00000001U +#define EFUSE_FLASH_TYPE_ERR_S 9 +/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [10]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_FORCE_SEND_RESUME. + */ +#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(10)) +#define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S) +#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001U +#define EFUSE_FORCE_SEND_RESUME_ERR_S 10 +/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [26:11]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_SECURE_VERSION. + */ +#define EFUSE_SECURE_VERSION_ERR 0x0000FFFFU +#define EFUSE_SECURE_VERSION_ERR_M (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S) +#define EFUSE_SECURE_VERSION_ERR_V 0x0000FFFFU +#define EFUSE_SECURE_VERSION_ERR_S 11 +/** EFUSE_RPT4_RESERVED2_ERR : RO; bitpos: [31:27]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED2. + */ +#define EFUSE_RPT4_RESERVED2_ERR 0x0000001FU +#define EFUSE_RPT4_RESERVED2_ERR_M (EFUSE_RPT4_RESERVED2_ERR_V << EFUSE_RPT4_RESERVED2_ERR_S) +#define EFUSE_RPT4_RESERVED2_ERR_V 0x0000001FU +#define EFUSE_RPT4_RESERVED2_ERR_S 27 -#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x18C) -/* EFUSE_RPT1_RESERVED0_ERR : RO ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT1_RESERVED0_ERR 0x000000FF -#define EFUSE_RPT1_RESERVED0_ERR_M ((EFUSE_RPT1_RESERVED0_ERR_V)<<(EFUSE_RPT1_RESERVED0_ERR_S)) -#define EFUSE_RPT1_RESERVED0_ERR_V 0xFF -#define EFUSE_RPT1_RESERVED0_ERR_S 24 -/* EFUSE_RPT4_RESERVED4_ERR : RO ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: Reserved ( four backup method ).*/ -#define EFUSE_RPT4_RESERVED4_ERR 0x00FFFFFF -#define EFUSE_RPT4_RESERVED4_ERR_M ((EFUSE_RPT4_RESERVED4_ERR_V)<<(EFUSE_RPT4_RESERVED4_ERR_S)) -#define EFUSE_RPT4_RESERVED4_ERR_V 0xFFFFFF +/** EFUSE_RD_REPEAT_ERR4_REG register + * Programming error record register 4 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x190) +/** EFUSE_RPT4_RESERVED4_ERR : RO; bitpos: [23:0]; default: 0; + * If any bit in RPT4_RESERVED4 is 1, there is a programming error in + * EFUSE_RPT4_RESERVED4. + */ +#define EFUSE_RPT4_RESERVED4_ERR 0x00FFFFFFU +#define EFUSE_RPT4_RESERVED4_ERR_M (EFUSE_RPT4_RESERVED4_ERR_V << EFUSE_RPT4_RESERVED4_ERR_S) +#define EFUSE_RPT4_RESERVED4_ERR_V 0x00FFFFFFU #define EFUSE_RPT4_RESERVED4_ERR_S 0 -#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0) -/* EFUSE_KEY4_FAIL : RO ;bitpos:[31] ;default: 1'h0 ; */ -/*description: 0: Means no failure and that the data of key$n is reliable*/ -#define EFUSE_KEY4_FAIL (BIT(31)) -#define EFUSE_KEY4_FAIL_M (BIT(31)) -#define EFUSE_KEY4_FAIL_V 0x1 -#define EFUSE_KEY4_FAIL_S 31 -/* EFUSE_KEY4_ERR_NUM : RO ;bitpos:[30:28] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY4_ERR_NUM 0x00000007 -#define EFUSE_KEY4_ERR_NUM_M ((EFUSE_KEY4_ERR_NUM_V)<<(EFUSE_KEY4_ERR_NUM_S)) -#define EFUSE_KEY4_ERR_NUM_V 0x7 -#define EFUSE_KEY4_ERR_NUM_S 28 -/* EFUSE_KEY3_FAIL : RO ;bitpos:[27] ;default: 1'h0 ; */ -/*description: 0: Means no failure and that the data of key$n is reliable*/ -#define EFUSE_KEY3_FAIL (BIT(27)) -#define EFUSE_KEY3_FAIL_M (BIT(27)) -#define EFUSE_KEY3_FAIL_V 0x1 -#define EFUSE_KEY3_FAIL_S 27 -/* EFUSE_KEY3_ERR_NUM : RO ;bitpos:[26:24] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY3_ERR_NUM 0x00000007 -#define EFUSE_KEY3_ERR_NUM_M ((EFUSE_KEY3_ERR_NUM_V)<<(EFUSE_KEY3_ERR_NUM_S)) -#define EFUSE_KEY3_ERR_NUM_V 0x7 -#define EFUSE_KEY3_ERR_NUM_S 24 -/* EFUSE_KEY2_FAIL : RO ;bitpos:[23] ;default: 1'h0 ; */ -/*description: 0: Means no failure and that the data of key$n is reliable*/ -#define EFUSE_KEY2_FAIL (BIT(23)) -#define EFUSE_KEY2_FAIL_M (BIT(23)) -#define EFUSE_KEY2_FAIL_V 0x1 -#define EFUSE_KEY2_FAIL_S 23 -/* EFUSE_KEY2_ERR_NUM : RO ;bitpos:[22:20] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY2_ERR_NUM 0x00000007 -#define EFUSE_KEY2_ERR_NUM_M ((EFUSE_KEY2_ERR_NUM_V)<<(EFUSE_KEY2_ERR_NUM_S)) -#define EFUSE_KEY2_ERR_NUM_V 0x7 -#define EFUSE_KEY2_ERR_NUM_S 20 -/* EFUSE_KEY1_FAIL : RO ;bitpos:[19] ;default: 1'h0 ; */ -/*description: 0: Means no failure and that the data of key$n is reliable*/ -#define EFUSE_KEY1_FAIL (BIT(19)) -#define EFUSE_KEY1_FAIL_M (BIT(19)) -#define EFUSE_KEY1_FAIL_V 0x1 -#define EFUSE_KEY1_FAIL_S 19 -/* EFUSE_KEY1_ERR_NUM : RO ;bitpos:[18:16] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY1_ERR_NUM 0x00000007 -#define EFUSE_KEY1_ERR_NUM_M ((EFUSE_KEY1_ERR_NUM_V)<<(EFUSE_KEY1_ERR_NUM_S)) -#define EFUSE_KEY1_ERR_NUM_V 0x7 -#define EFUSE_KEY1_ERR_NUM_S 16 -/* EFUSE_KEY0_FAIL : RO ;bitpos:[15] ;default: 1'h0 ; */ -/*description: 0: Means no failure and that the data of key$n is reliable*/ -#define EFUSE_KEY0_FAIL (BIT(15)) -#define EFUSE_KEY0_FAIL_M (BIT(15)) -#define EFUSE_KEY0_FAIL_V 0x1 -#define EFUSE_KEY0_FAIL_S 15 -/* EFUSE_KEY0_ERR_NUM : RO ;bitpos:[14:12] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY0_ERR_NUM 0x00000007 -#define EFUSE_KEY0_ERR_NUM_M ((EFUSE_KEY0_ERR_NUM_V)<<(EFUSE_KEY0_ERR_NUM_S)) -#define EFUSE_KEY0_ERR_NUM_V 0x7 -#define EFUSE_KEY0_ERR_NUM_S 12 -/* EFUSE_USR_DATA_FAIL : RO ;bitpos:[11] ;default: 1'h0 ; */ -/*description: 0: Means no failure and that the user data is reliable*/ -#define EFUSE_USR_DATA_FAIL (BIT(11)) -#define EFUSE_USR_DATA_FAIL_M (BIT(11)) -#define EFUSE_USR_DATA_FAIL_V 0x1 -#define EFUSE_USR_DATA_FAIL_S 11 -/* EFUSE_USR_DATA_ERR_NUM : RO ;bitpos:[10:8] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_USR_DATA_ERR_NUM 0x00000007 -#define EFUSE_USR_DATA_ERR_NUM_M ((EFUSE_USR_DATA_ERR_NUM_V)<<(EFUSE_USR_DATA_ERR_NUM_S)) -#define EFUSE_USR_DATA_ERR_NUM_V 0x7 -#define EFUSE_USR_DATA_ERR_NUM_S 8 -/* EFUSE_SYS_PART1_FAIL : RO ;bitpos:[7] ;default: 1'h0 ; */ -/*description: 0: Means no failure and that the data of system part1 is reliable*/ -#define EFUSE_SYS_PART1_FAIL (BIT(7)) -#define EFUSE_SYS_PART1_FAIL_M (BIT(7)) -#define EFUSE_SYS_PART1_FAIL_V 0x1 -#define EFUSE_SYS_PART1_FAIL_S 7 -/* EFUSE_SYS_PART1_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_SYS_PART1_NUM 0x00000007 -#define EFUSE_SYS_PART1_NUM_M ((EFUSE_SYS_PART1_NUM_V)<<(EFUSE_SYS_PART1_NUM_S)) -#define EFUSE_SYS_PART1_NUM_V 0x7 -#define EFUSE_SYS_PART1_NUM_S 4 -/* EFUSE_MAC_SPI_8M_FAIL : RO ;bitpos:[3] ;default: 1'h0 ; */ -/*description: 0: Means no failure and that the data of MAC_SPI_8M is reliable*/ -#define EFUSE_MAC_SPI_8M_FAIL (BIT(3)) -#define EFUSE_MAC_SPI_8M_FAIL_M (BIT(3)) -#define EFUSE_MAC_SPI_8M_FAIL_V 0x1 -#define EFUSE_MAC_SPI_8M_FAIL_S 3 -/* EFUSE_MAC_SPI_8M_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_MAC_SPI_8M_ERR_NUM 0x00000007 -#define EFUSE_MAC_SPI_8M_ERR_NUM_M ((EFUSE_MAC_SPI_8M_ERR_NUM_V)<<(EFUSE_MAC_SPI_8M_ERR_NUM_S)) -#define EFUSE_MAC_SPI_8M_ERR_NUM_V 0x7 +/** EFUSE_RD_RS_ERR0_REG register + * Programming error record register 0 of BLOCK1-10. + */ +#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0) +/** EFUSE_MAC_SPI_8M_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes in BLOCK1. + */ +#define EFUSE_MAC_SPI_8M_ERR_NUM 0x00000007U +#define EFUSE_MAC_SPI_8M_ERR_NUM_M (EFUSE_MAC_SPI_8M_ERR_NUM_V << EFUSE_MAC_SPI_8M_ERR_NUM_S) +#define EFUSE_MAC_SPI_8M_ERR_NUM_V 0x00000007U #define EFUSE_MAC_SPI_8M_ERR_NUM_S 0 +/** EFUSE_MAC_SPI_8M_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of BLOCK1 is reliable. 1: Means that + * programming BLOCK1 data failed and the number of error bytes is over 5. + */ +#define EFUSE_MAC_SPI_8M_FAIL (BIT(3)) +#define EFUSE_MAC_SPI_8M_FAIL_M (EFUSE_MAC_SPI_8M_FAIL_V << EFUSE_MAC_SPI_8M_FAIL_S) +#define EFUSE_MAC_SPI_8M_FAIL_V 0x00000001U +#define EFUSE_MAC_SPI_8M_FAIL_S 3 +/** EFUSE_SYS_PART1_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes in BLOCK2. + */ +#define EFUSE_SYS_PART1_NUM 0x00000007U +#define EFUSE_SYS_PART1_NUM_M (EFUSE_SYS_PART1_NUM_V << EFUSE_SYS_PART1_NUM_S) +#define EFUSE_SYS_PART1_NUM_V 0x00000007U +#define EFUSE_SYS_PART1_NUM_S 4 +/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of BLOCK2 is reliable. 1: Means that + * programming BLOCK2 data failed and the number of error bytes is over 5. + */ +#define EFUSE_SYS_PART1_FAIL (BIT(7)) +#define EFUSE_SYS_PART1_FAIL_M (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S) +#define EFUSE_SYS_PART1_FAIL_V 0x00000001U +#define EFUSE_SYS_PART1_FAIL_S 7 +/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; + * The value of this signal means the number of error bytes in BLOCK3. + */ +#define EFUSE_USR_DATA_ERR_NUM 0x00000007U +#define EFUSE_USR_DATA_ERR_NUM_M (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S) +#define EFUSE_USR_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_USR_DATA_ERR_NUM_S 8 +/** EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; + * 0: Means no failure and that the data of BLOCK3 is reliable. 1: Means that + * programming BLOCK3 data failed and the number of error bytes is over 5. + */ +#define EFUSE_USR_DATA_FAIL (BIT(11)) +#define EFUSE_USR_DATA_FAIL_M (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S) +#define EFUSE_USR_DATA_FAIL_V 0x00000001U +#define EFUSE_USR_DATA_FAIL_S 11 +/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0; + * The value of this signal means the number of error bytes in KEY0. + */ +#define EFUSE_KEY0_ERR_NUM 0x00000007U +#define EFUSE_KEY0_ERR_NUM_M (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S) +#define EFUSE_KEY0_ERR_NUM_V 0x00000007U +#define EFUSE_KEY0_ERR_NUM_S 12 +/** EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0; + * 0: Means no failure and that the data of KEY0 is reliable. 1: Means that + * programming KEY0 failed and the number of error bytes is over 5. + */ +#define EFUSE_KEY0_FAIL (BIT(15)) +#define EFUSE_KEY0_FAIL_M (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S) +#define EFUSE_KEY0_FAIL_V 0x00000001U +#define EFUSE_KEY0_FAIL_S 15 +/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0; + * The value of this signal means the number of error bytes in KEY1. + */ +#define EFUSE_KEY1_ERR_NUM 0x00000007U +#define EFUSE_KEY1_ERR_NUM_M (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S) +#define EFUSE_KEY1_ERR_NUM_V 0x00000007U +#define EFUSE_KEY1_ERR_NUM_S 16 +/** EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0; + * 0: Means no failure and that the data of KEY1 is reliable. 1: Means that + * programming KEY1 failed and the number of error bytes is over 5. + */ +#define EFUSE_KEY1_FAIL (BIT(19)) +#define EFUSE_KEY1_FAIL_M (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S) +#define EFUSE_KEY1_FAIL_V 0x00000001U +#define EFUSE_KEY1_FAIL_S 19 +/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0; + * The value of this signal means the number of error bytes in KEY2. + */ +#define EFUSE_KEY2_ERR_NUM 0x00000007U +#define EFUSE_KEY2_ERR_NUM_M (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S) +#define EFUSE_KEY2_ERR_NUM_V 0x00000007U +#define EFUSE_KEY2_ERR_NUM_S 20 +/** EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0; + * 0: Means no failure and that the data of KEY2 is reliable. 1: Means that + * programming KEY2 failed and the number of error bytes is over 5. + */ +#define EFUSE_KEY2_FAIL (BIT(23)) +#define EFUSE_KEY2_FAIL_M (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S) +#define EFUSE_KEY2_FAIL_V 0x00000001U +#define EFUSE_KEY2_FAIL_S 23 +/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0; + * The value of this signal means the number of error bytes in KEY3. + */ +#define EFUSE_KEY3_ERR_NUM 0x00000007U +#define EFUSE_KEY3_ERR_NUM_M (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S) +#define EFUSE_KEY3_ERR_NUM_V 0x00000007U +#define EFUSE_KEY3_ERR_NUM_S 24 +/** EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0; + * 0: Means no failure and that the data of KEY3 is reliable. 1: Means that + * programming KEY3 failed and the number of error bytes is over 5. + */ +#define EFUSE_KEY3_FAIL (BIT(27)) +#define EFUSE_KEY3_FAIL_M (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S) +#define EFUSE_KEY3_FAIL_V 0x00000001U +#define EFUSE_KEY3_FAIL_S 27 +/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0; + * The value of this signal means the number of error bytes in KEY4. + */ +#define EFUSE_KEY4_ERR_NUM 0x00000007U +#define EFUSE_KEY4_ERR_NUM_M (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S) +#define EFUSE_KEY4_ERR_NUM_V 0x00000007U +#define EFUSE_KEY4_ERR_NUM_S 28 +/** EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0; + * 0: Means no failure and that the data of KEY4 is reliable. 1: Means that + * programming KEY4 failed and the number of error bytes is over 5. + */ +#define EFUSE_KEY4_FAIL (BIT(31)) +#define EFUSE_KEY4_FAIL_M (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S) +#define EFUSE_KEY4_FAIL_V 0x00000001U +#define EFUSE_KEY4_FAIL_S 31 -#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4) -/* EFUSE_SYS_PART2_FAIL : RO ;bitpos:[7] ;default: 1'h0 ; */ -/*description: 0: Means no failure and that the data of system part2 is reliable*/ -#define EFUSE_SYS_PART2_FAIL (BIT(7)) -#define EFUSE_SYS_PART2_FAIL_M (BIT(7)) -#define EFUSE_SYS_PART2_FAIL_V 0x1 -#define EFUSE_SYS_PART2_FAIL_S 7 -/* EFUSE_SYS_PART2_ERR_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_SYS_PART2_ERR_NUM 0x00000007 -#define EFUSE_SYS_PART2_ERR_NUM_M ((EFUSE_SYS_PART2_ERR_NUM_V)<<(EFUSE_SYS_PART2_ERR_NUM_S)) -#define EFUSE_SYS_PART2_ERR_NUM_V 0x7 -#define EFUSE_SYS_PART2_ERR_NUM_S 4 -/* EFUSE_KEY5_FAIL : RO ;bitpos:[3] ;default: 1'h0 ; */ -/*description: 0: Means no failure and that the data of KEY5 is reliable*/ -#define EFUSE_KEY5_FAIL (BIT(3)) -#define EFUSE_KEY5_FAIL_M (BIT(3)) -#define EFUSE_KEY5_FAIL_V 0x1 -#define EFUSE_KEY5_FAIL_S 3 -/* EFUSE_KEY5_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY5_ERR_NUM 0x00000007 -#define EFUSE_KEY5_ERR_NUM_M ((EFUSE_KEY5_ERR_NUM_V)<<(EFUSE_KEY5_ERR_NUM_S)) -#define EFUSE_KEY5_ERR_NUM_V 0x7 +/** EFUSE_RD_RS_ERR1_REG register + * Programming error record register 1 of BLOCK1-10. + */ +#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4) +/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes in KEY5. + */ +#define EFUSE_KEY5_ERR_NUM 0x00000007U +#define EFUSE_KEY5_ERR_NUM_M (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S) +#define EFUSE_KEY5_ERR_NUM_V 0x00000007U #define EFUSE_KEY5_ERR_NUM_S 0 +/** EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of KEY5 is reliable. 1: Means that + * programming user data failed and the number of error bytes is over 5. + */ +#define EFUSE_KEY5_FAIL (BIT(3)) +#define EFUSE_KEY5_FAIL_M (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S) +#define EFUSE_KEY5_FAIL_V 0x00000001U +#define EFUSE_KEY5_FAIL_S 3 +/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes in BLOCK10. + */ +#define EFUSE_SYS_PART2_ERR_NUM 0x00000007U +#define EFUSE_SYS_PART2_ERR_NUM_M (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S) +#define EFUSE_SYS_PART2_ERR_NUM_V 0x00000007U +#define EFUSE_SYS_PART2_ERR_NUM_S 4 +/** EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of BLOCK10 is reliable. 1: Means that + * programming BLOCK10 data failed and the number of error bytes is over 5. + */ +#define EFUSE_SYS_PART2_FAIL (BIT(7)) +#define EFUSE_SYS_PART2_FAIL_M (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S) +#define EFUSE_SYS_PART2_FAIL_V 0x00000001U +#define EFUSE_SYS_PART2_FAIL_S 7 -#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) -/* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ -/*description: Set this bit and force to enable clock signal of eFuse memory.*/ -#define EFUSE_CLK_EN (BIT(16)) -#define EFUSE_CLK_EN_M (BIT(16)) -#define EFUSE_CLK_EN_V 0x1 -#define EFUSE_CLK_EN_S 16 -/* EFUSE_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: Set this bit to force eFuse SRAM into working mode.*/ -#define EFUSE_MEM_FORCE_PU (BIT(2)) -#define EFUSE_MEM_FORCE_PU_M (BIT(2)) -#define EFUSE_MEM_FORCE_PU_V 0x1 -#define EFUSE_MEM_FORCE_PU_S 2 -/* EFUSE_MEM_CLK_FORCE_ON : R/W ;bitpos:[1] ;default: 1'h1 ; */ -/*description: Set this bit and force to activate clock signal of eFuse SRAM.*/ -#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) -#define EFUSE_MEM_CLK_FORCE_ON_M (BIT(1)) -#define EFUSE_MEM_CLK_FORCE_ON_V 0x1 +/** EFUSE_CLK_REG register + * eFuse clock configuration register. + */ +#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) +/** EFUSE_EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; + * If set, forces eFuse SRAM into power-saving mode. + */ +#define EFUSE_EFUSE_MEM_FORCE_PD (BIT(0)) +#define EFUSE_EFUSE_MEM_FORCE_PD_M (EFUSE_EFUSE_MEM_FORCE_PD_V << EFUSE_EFUSE_MEM_FORCE_PD_S) +#define EFUSE_EFUSE_MEM_FORCE_PD_V 0x00000001U +#define EFUSE_EFUSE_MEM_FORCE_PD_S 0 +/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1; + * If set, forces to activate clock signal of eFuse SRAM. + */ +#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) +#define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) +#define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001U #define EFUSE_MEM_CLK_FORCE_ON_S 1 -/* EFUSE_MEM_FORCE_PD : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to force eFuse SRAM into power-saving mode.*/ -#define EFUSE_MEM_FORCE_PD (BIT(0)) -#define EFUSE_MEM_FORCE_PD_M (BIT(0)) -#define EFUSE_MEM_FORCE_PD_V 0x1 -#define EFUSE_MEM_FORCE_PD_S 0 - -#define EFUSE_WRITE_OP_CODE 0x5a5a -#define EFUSE_READ_OP_CODE 0x5aa5 - -#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) -/* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: 0x5A5A: Operate programming command*/ -#define EFUSE_OP_CODE 0x0000FFFF -#define EFUSE_OP_CODE_M ((EFUSE_OP_CODE_V)<<(EFUSE_OP_CODE_S)) -#define EFUSE_OP_CODE_V 0xFFFF +/** EFUSE_EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; + * If set, forces eFuse SRAM into working mode. + */ +#define EFUSE_EFUSE_MEM_FORCE_PU (BIT(2)) +#define EFUSE_EFUSE_MEM_FORCE_PU_M (EFUSE_EFUSE_MEM_FORCE_PU_V << EFUSE_EFUSE_MEM_FORCE_PU_S) +#define EFUSE_EFUSE_MEM_FORCE_PU_V 0x00000001U +#define EFUSE_EFUSE_MEM_FORCE_PU_S 2 +/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; + * If set, forces to enable clock signal of eFuse memory. + */ +#define EFUSE_CLK_EN (BIT(16)) +#define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) +#define EFUSE_CLK_EN_V 0x00000001U +#define EFUSE_CLK_EN_S 16 + +/** EFUSE_CONF_REG register + * eFuse operation mode configuration register. + */ +#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) +/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; + * 0x5A5A: Operate programming command. 0x5AA5: Operate read command. + */ +#define EFUSE_OP_CODE 0x0000FFFFU +#define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) +#define EFUSE_OP_CODE_V 0x0000FFFFU #define EFUSE_OP_CODE_S 0 -#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0) -/* EFUSE_REPEAT_ERR_CNT : RO ;bitpos:[17:10] ;default: 8'h0 ; */ -/*description: Indicates the number of error bits during programming BLOCK0.*/ -#define EFUSE_REPEAT_ERR_CNT 0x000000FF -#define EFUSE_REPEAT_ERR_CNT_M ((EFUSE_REPEAT_ERR_CNT_V)<<(EFUSE_REPEAT_ERR_CNT_S)) -#define EFUSE_REPEAT_ERR_CNT_V 0xFF -#define EFUSE_REPEAT_ERR_CNT_S 10 -/* EFUSE_OTP_VDDQ_IS_SW : RO ;bitpos:[9] ;default: 1'h0 ; */ -/*description: The value of OTP_VDDQ_IS_SW.*/ -#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) -#define EFUSE_OTP_VDDQ_IS_SW_M (BIT(9)) -#define EFUSE_OTP_VDDQ_IS_SW_V 0x1 -#define EFUSE_OTP_VDDQ_IS_SW_S 9 -/* EFUSE_OTP_PGENB_SW : RO ;bitpos:[8] ;default: 1'h0 ; */ -/*description: The value of OTP_PGENB_SW.*/ -#define EFUSE_OTP_PGENB_SW (BIT(8)) -#define EFUSE_OTP_PGENB_SW_M (BIT(8)) -#define EFUSE_OTP_PGENB_SW_V 0x1 -#define EFUSE_OTP_PGENB_SW_S 8 -/* EFUSE_OTP_CSB_SW : RO ;bitpos:[7] ;default: 1'h0 ; */ -/*description: The value of OTP_CSB_SW.*/ -#define EFUSE_OTP_CSB_SW (BIT(7)) -#define EFUSE_OTP_CSB_SW_M (BIT(7)) -#define EFUSE_OTP_CSB_SW_V 0x1 -#define EFUSE_OTP_CSB_SW_S 7 -/* EFUSE_OTP_STROBE_SW : RO ;bitpos:[6] ;default: 1'h0 ; */ -/*description: The value of OTP_STROBE_SW.*/ -#define EFUSE_OTP_STROBE_SW (BIT(6)) -#define EFUSE_OTP_STROBE_SW_M (BIT(6)) -#define EFUSE_OTP_STROBE_SW_V 0x1 -#define EFUSE_OTP_STROBE_SW_S 6 -/* EFUSE_OTP_VDDQ_C_SYNC2 : RO ;bitpos:[5] ;default: 1'h0 ; */ -/*description: The value of OTP_VDDQ_C_SYNC2.*/ -#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) -#define EFUSE_OTP_VDDQ_C_SYNC2_M (BIT(5)) -#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x1 -#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 -/* EFUSE_OTP_LOAD_SW : RO ;bitpos:[4] ;default: 1'h0 ; */ -/*description: The value of OTP_LOAD_SW.*/ -#define EFUSE_OTP_LOAD_SW (BIT(4)) -#define EFUSE_OTP_LOAD_SW_M (BIT(4)) -#define EFUSE_OTP_LOAD_SW_V 0x1 -#define EFUSE_OTP_LOAD_SW_S 4 -/* EFUSE_STATE : RO ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: Indicates the state of the eFuse state machine.*/ -#define EFUSE_STATE 0x0000000F -#define EFUSE_STATE_M ((EFUSE_STATE_V)<<(EFUSE_STATE_S)) -#define EFUSE_STATE_V 0xF +/** EFUSE_STATUS_REG register + * eFuse status register. + */ +#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0) +/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0; + * Indicates the state of the eFuse state machine. + */ +#define EFUSE_STATE 0x0000000FU +#define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) +#define EFUSE_STATE_V 0x0000000FU #define EFUSE_STATE_S 0 +/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0; + * The value of OTP_LOAD_SW. + */ +#define EFUSE_OTP_LOAD_SW (BIT(4)) +#define EFUSE_OTP_LOAD_SW_M (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S) +#define EFUSE_OTP_LOAD_SW_V 0x00000001U +#define EFUSE_OTP_LOAD_SW_S 4 +/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0; + * The value of OTP_VDDQ_C_SYNC2. + */ +#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) +#define EFUSE_OTP_VDDQ_C_SYNC2_M (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S) +#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x00000001U +#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 +/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0; + * The value of OTP_STROBE_SW. + */ +#define EFUSE_OTP_STROBE_SW (BIT(6)) +#define EFUSE_OTP_STROBE_SW_M (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S) +#define EFUSE_OTP_STROBE_SW_V 0x00000001U +#define EFUSE_OTP_STROBE_SW_S 6 +/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0; + * The value of OTP_CSB_SW. + */ +#define EFUSE_OTP_CSB_SW (BIT(7)) +#define EFUSE_OTP_CSB_SW_M (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S) +#define EFUSE_OTP_CSB_SW_V 0x00000001U +#define EFUSE_OTP_CSB_SW_S 7 +/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0; + * The value of OTP_PGENB_SW. + */ +#define EFUSE_OTP_PGENB_SW (BIT(8)) +#define EFUSE_OTP_PGENB_SW_M (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S) +#define EFUSE_OTP_PGENB_SW_V 0x00000001U +#define EFUSE_OTP_PGENB_SW_S 8 +/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0; + * The value of OTP_VDDQ_IS_SW. + */ +#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) +#define EFUSE_OTP_VDDQ_IS_SW_M (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S) +#define EFUSE_OTP_VDDQ_IS_SW_V 0x00000001U +#define EFUSE_OTP_VDDQ_IS_SW_S 9 +/** EFUSE_REPEAT_ERR_CNT : RO; bitpos: [17:10]; default: 0; + * Indicates the number of error bits during programming BLOCK0. + */ +#define EFUSE_REPEAT_ERR_CNT 0x000000FFU +#define EFUSE_REPEAT_ERR_CNT_M (EFUSE_REPEAT_ERR_CNT_V << EFUSE_REPEAT_ERR_CNT_S) +#define EFUSE_REPEAT_ERR_CNT_V 0x000000FFU +#define EFUSE_REPEAT_ERR_CNT_S 10 -#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4) -/* EFUSE_BLK_NUM : R/W ;bitpos:[5:2] ;default: 4'h0 ; */ -/*description: The serial number of the block to be programmed. Value 0-10 corresponds - to block number 0-10 respectively.*/ -#define EFUSE_BLK_NUM 0x0000000F -#define EFUSE_BLK_NUM_M ((EFUSE_BLK_NUM_V)<<(EFUSE_BLK_NUM_S)) -#define EFUSE_BLK_NUM_V 0xF -#define EFUSE_BLK_NUM_S 2 -/* EFUSE_PGM_CMD : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: Set this bit to send programming command.*/ -#define EFUSE_PGM_CMD (BIT(1)) -#define EFUSE_PGM_CMD_M (BIT(1)) -#define EFUSE_PGM_CMD_V 0x1 -#define EFUSE_PGM_CMD_S 1 -/* EFUSE_READ_CMD : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to send read command.*/ -#define EFUSE_READ_CMD (BIT(0)) -#define EFUSE_READ_CMD_M (BIT(0)) -#define EFUSE_READ_CMD_V 0x1 +/** EFUSE_CMD_REG register + * eFuse command register. + */ +#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4) +/** EFUSE_READ_CMD : R/W; bitpos: [0]; default: 0; + * Set this bit to send read command. + */ +#define EFUSE_READ_CMD (BIT(0)) +#define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) +#define EFUSE_READ_CMD_V 0x00000001U #define EFUSE_READ_CMD_S 0 +/** EFUSE_PGM_CMD : R/W; bitpos: [1]; default: 0; + * Set this bit to send programming command. + */ +#define EFUSE_PGM_CMD (BIT(1)) +#define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) +#define EFUSE_PGM_CMD_V 0x00000001U +#define EFUSE_PGM_CMD_S 1 +/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0; + * The serial number of the block to be programmed. Value 0-10 corresponds to block + * number 0-10, respectively. + */ +#define EFUSE_BLK_NUM 0x0000000FU +#define EFUSE_BLK_NUM_M (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S) +#define EFUSE_BLK_NUM_V 0x0000000FU +#define EFUSE_BLK_NUM_S 2 -#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8) -/* EFUSE_PGM_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: The raw bit signal for pgm_done interrupt.*/ -#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) -#define EFUSE_PGM_DONE_INT_RAW_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_RAW_V 0x1 -#define EFUSE_PGM_DONE_INT_RAW_S 1 -/* EFUSE_READ_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The raw bit signal for read_done interrupt.*/ -#define EFUSE_READ_DONE_INT_RAW (BIT(0)) -#define EFUSE_READ_DONE_INT_RAW_M (BIT(0)) -#define EFUSE_READ_DONE_INT_RAW_V 0x1 +/** EFUSE_INT_RAW_REG register + * eFuse raw interrupt register. + */ +#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8) +/** EFUSE_READ_DONE_INT_RAW : RO; bitpos: [0]; default: 0; + * The raw bit signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_RAW (BIT(0)) +#define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) +#define EFUSE_READ_DONE_INT_RAW_V 0x00000001U #define EFUSE_READ_DONE_INT_RAW_S 0 +/** EFUSE_PGM_DONE_INT_RAW : RO; bitpos: [1]; default: 0; + * The raw bit signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) +#define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) +#define EFUSE_PGM_DONE_INT_RAW_V 0x00000001U +#define EFUSE_PGM_DONE_INT_RAW_S 1 -#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc) -/* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: The status signal for pgm_done interrupt.*/ -#define EFUSE_PGM_DONE_INT_ST (BIT(1)) -#define EFUSE_PGM_DONE_INT_ST_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_ST_V 0x1 -#define EFUSE_PGM_DONE_INT_ST_S 1 -/* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The status signal for read_done interrupt.*/ -#define EFUSE_READ_DONE_INT_ST (BIT(0)) -#define EFUSE_READ_DONE_INT_ST_M (BIT(0)) -#define EFUSE_READ_DONE_INT_ST_V 0x1 +/** EFUSE_INT_ST_REG register + * eFuse interrupt status register. + */ +#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc) +/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The status signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_ST (BIT(0)) +#define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) +#define EFUSE_READ_DONE_INT_ST_V 0x00000001U #define EFUSE_READ_DONE_INT_ST_S 0 +/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The status signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_ST (BIT(1)) +#define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) +#define EFUSE_PGM_DONE_INT_ST_V 0x00000001U +#define EFUSE_PGM_DONE_INT_ST_S 1 -#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0) -/* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: The enable signal for pgm_done interrupt.*/ -#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) -#define EFUSE_PGM_DONE_INT_ENA_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_ENA_V 0x1 -#define EFUSE_PGM_DONE_INT_ENA_S 1 -/* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The enable signal for read_done interrupt.*/ -#define EFUSE_READ_DONE_INT_ENA (BIT(0)) -#define EFUSE_READ_DONE_INT_ENA_M (BIT(0)) -#define EFUSE_READ_DONE_INT_ENA_V 0x1 +/** EFUSE_INT_ENA_REG register + * eFuse interrupt enable register. + */ +#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0) +/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_ENA (BIT(0)) +#define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) +#define EFUSE_READ_DONE_INT_ENA_V 0x00000001U #define EFUSE_READ_DONE_INT_ENA_S 0 +/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) +#define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) +#define EFUSE_PGM_DONE_INT_ENA_V 0x00000001U +#define EFUSE_PGM_DONE_INT_ENA_S 1 -#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4) -/* EFUSE_PGM_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: The clear signal for pgm_done interrupt.*/ -#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) -#define EFUSE_PGM_DONE_INT_CLR_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_CLR_V 0x1 -#define EFUSE_PGM_DONE_INT_CLR_S 1 -/* EFUSE_READ_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The clear signal for read_done interrupt.*/ -#define EFUSE_READ_DONE_INT_CLR (BIT(0)) -#define EFUSE_READ_DONE_INT_CLR_M (BIT(0)) -#define EFUSE_READ_DONE_INT_CLR_V 0x1 +/** EFUSE_INT_CLR_REG register + * eFuse interrupt clear register. + */ +#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4) +/** EFUSE_READ_DONE_INT_CLR : WO; bitpos: [0]; default: 0; + * The clear signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_CLR (BIT(0)) +#define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) +#define EFUSE_READ_DONE_INT_CLR_V 0x00000001U #define EFUSE_READ_DONE_INT_CLR_S 0 +/** EFUSE_PGM_DONE_INT_CLR : WO; bitpos: [1]; default: 0; + * The clear signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) +#define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) +#define EFUSE_PGM_DONE_INT_CLR_V 0x00000001U +#define EFUSE_PGM_DONE_INT_CLR_S 1 -#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8) -/* EFUSE_OE_CLR : R/W ;bitpos:[17] ;default: 1'h0 ; */ -/*description: Reduces the power supply of the programming voltage.*/ -#define EFUSE_OE_CLR (BIT(17)) -#define EFUSE_OE_CLR_M (BIT(17)) -#define EFUSE_OE_CLR_V 0x1 -#define EFUSE_OE_CLR_S 17 -/* EFUSE_DAC_NUM : R/W ;bitpos:[16:9] ;default: 8'd255 ; */ -/*description: Controls the rising period of the programming voltage.*/ -#define EFUSE_DAC_NUM 0x000000FF -#define EFUSE_DAC_NUM_M ((EFUSE_DAC_NUM_V)<<(EFUSE_DAC_NUM_S)) -#define EFUSE_DAC_NUM_V 0xFF -#define EFUSE_DAC_NUM_S 9 -/* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: Don't care.*/ -#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) -#define EFUSE_DAC_CLK_PAD_SEL_M (BIT(8)) -#define EFUSE_DAC_CLK_PAD_SEL_V 0x1 -#define EFUSE_DAC_CLK_PAD_SEL_S 8 -/* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd28 ; */ -/*description: Controls the division factor of the rising clock of the programming voltage.*/ -#define EFUSE_DAC_CLK_DIV 0x000000FF -#define EFUSE_DAC_CLK_DIV_M ((EFUSE_DAC_CLK_DIV_V)<<(EFUSE_DAC_CLK_DIV_S)) -#define EFUSE_DAC_CLK_DIV_V 0xFF +/** EFUSE_DAC_CONF_REG register + * Controls the eFuse programming voltage. + */ +#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8) +/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 28; + * Controls the division factor of the rising clock of the programming voltage. + */ +#define EFUSE_DAC_CLK_DIV 0x000000FFU +#define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) +#define EFUSE_DAC_CLK_DIV_V 0x000000FFU #define EFUSE_DAC_CLK_DIV_S 0 +/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0; + * Don't care. + */ +#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) +#define EFUSE_DAC_CLK_PAD_SEL_M (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S) +#define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001U +#define EFUSE_DAC_CLK_PAD_SEL_S 8 +/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ +#define EFUSE_DAC_NUM 0x000000FFU +#define EFUSE_DAC_NUM_M (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S) +#define EFUSE_DAC_NUM_V 0x000000FFU +#define EFUSE_DAC_NUM_S 9 +/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ +#define EFUSE_OE_CLR (BIT(17)) +#define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) +#define EFUSE_OE_CLR_V 0x00000001U +#define EFUSE_OE_CLR_S 17 -#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) -/* EFUSE_READ_INIT_NUM : R/W ;bitpos:[31:24] ;default: 8'h12 ; */ -/*description: Configures the initial read time of eFuse.*/ -#define EFUSE_READ_INIT_NUM 0x000000FF -#define EFUSE_READ_INIT_NUM_M ((EFUSE_READ_INIT_NUM_V)<<(EFUSE_READ_INIT_NUM_S)) -#define EFUSE_READ_INIT_NUM_V 0xFF -#define EFUSE_READ_INIT_NUM_S 24 -/* EFUSE_TSUR_A : R/W ;bitpos:[23:16] ;default: 8'h1 ; */ -/*description: Configures the setup time of read operation.*/ -#define EFUSE_TSUR_A 0x000000FF -#define EFUSE_TSUR_A_M ((EFUSE_TSUR_A_V)<<(EFUSE_TSUR_A_S)) -#define EFUSE_TSUR_A_V 0xFF -#define EFUSE_TSUR_A_S 16 -/* EFUSE_TRD : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ -/*description: Configures the length of pulse of read operation.*/ -#define EFUSE_TRD 0x000000FF -#define EFUSE_TRD_M ((EFUSE_TRD_V)<<(EFUSE_TRD_S)) -#define EFUSE_TRD_V 0xFF -#define EFUSE_TRD_S 8 -/* EFUSE_THR_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */ -/*description: Configures the hold time of read operation.*/ -#define EFUSE_THR_A 0x000000FF -#define EFUSE_THR_A_M ((EFUSE_THR_A_V)<<(EFUSE_THR_A_S)) -#define EFUSE_THR_A_V 0xFF +/** EFUSE_RD_TIM_CONF_REG register + * Configures read timing parameters. + */ +#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) +/** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1; + * Configures the hold time of read operation. + */ +#define EFUSE_THR_A 0x000000FFU +#define EFUSE_THR_A_M (EFUSE_THR_A_V << EFUSE_THR_A_S) +#define EFUSE_THR_A_V 0x000000FFU #define EFUSE_THR_A_S 0 +/** EFUSE_TRD : R/W; bitpos: [15:8]; default: 1; + * Configures the length of pulse of read operation. + */ +#define EFUSE_TRD 0x000000FFU +#define EFUSE_TRD_M (EFUSE_TRD_V << EFUSE_TRD_S) +#define EFUSE_TRD_V 0x000000FFU +#define EFUSE_TRD_S 8 +/** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1; + * Configures the setup time of read operation. + */ +#define EFUSE_TSUR_A 0x000000FFU +#define EFUSE_TSUR_A_M (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S) +#define EFUSE_TSUR_A_V 0x000000FFU +#define EFUSE_TSUR_A_S 16 +/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18; + * Configures the initial read time of eFuse. + */ +#define EFUSE_READ_INIT_NUM 0x000000FFU +#define EFUSE_READ_INIT_NUM_M (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S) +#define EFUSE_READ_INIT_NUM_V 0x000000FFU +#define EFUSE_READ_INIT_NUM_S 24 -#define EFUSE_WR_TIM_CONF0_REG (DR_REG_EFUSE_BASE + 0x1F0) -/* EFUSE_TPGM : R/W ;bitpos:[31:16] ;default: 16'hc8 ; */ -/*description: Configures the length of pulse during programming 1 to eFuse.*/ -#define EFUSE_TPGM 0x0000FFFF -#define EFUSE_TPGM_M ((EFUSE_TPGM_V)<<(EFUSE_TPGM_S)) -#define EFUSE_TPGM_V 0xFFFF -#define EFUSE_TPGM_S 16 -/* EFUSE_TPGM_INACTIVE : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ -/*description: Configures the length of pulse during programming 0 to eFuse.*/ -#define EFUSE_TPGM_INACTIVE 0x000000FF -#define EFUSE_TPGM_INACTIVE_M ((EFUSE_TPGM_INACTIVE_V)<<(EFUSE_TPGM_INACTIVE_S)) -#define EFUSE_TPGM_INACTIVE_V 0xFF -#define EFUSE_TPGM_INACTIVE_S 8 -/* EFUSE_THP_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */ -/*description: Configures the hold time of programming operation.*/ -#define EFUSE_THP_A 0x000000FF -#define EFUSE_THP_A_M ((EFUSE_THP_A_V)<<(EFUSE_THP_A_S)) -#define EFUSE_THP_A_V 0xFF +/** EFUSE_WR_TIM_CONF0_REG register + * Configuration register 0 of eFuse programming timing parameters. + */ +#define EFUSE_WR_TIM_CONF0_REG (DR_REG_EFUSE_BASE + 0x1f0) +/** EFUSE_THP_A : R/W; bitpos: [7:0]; default: 1; + * Configures the hold time of programming operation. + */ +#define EFUSE_THP_A 0x000000FFU +#define EFUSE_THP_A_M (EFUSE_THP_A_V << EFUSE_THP_A_S) +#define EFUSE_THP_A_V 0x000000FFU #define EFUSE_THP_A_S 0 +/** EFUSE_TPGM_INACTIVE : R/W; bitpos: [15:8]; default: 1; + * Configures the length of pulse during programming 0 to eFuse. + */ +#define EFUSE_TPGM_INACTIVE 0x000000FFU +#define EFUSE_TPGM_INACTIVE_M (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S) +#define EFUSE_TPGM_INACTIVE_V 0x000000FFU +#define EFUSE_TPGM_INACTIVE_S 8 +/** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 200; + * Configures the length of pulse during programming 1 to eFuse. + */ +#define EFUSE_TPGM 0x0000FFFFU +#define EFUSE_TPGM_M (EFUSE_TPGM_V << EFUSE_TPGM_S) +#define EFUSE_TPGM_V 0x0000FFFFU +#define EFUSE_TPGM_S 16 -#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1F4) -/* EFUSE_PWR_ON_NUM : R/W ;bitpos:[23:8] ;default: 16'h2880 ; */ -/*description: Configures the power up time for VDDQ.*/ -#define EFUSE_PWR_ON_NUM 0x0000FFFF -#define EFUSE_PWR_ON_NUM_M ((EFUSE_PWR_ON_NUM_V)<<(EFUSE_PWR_ON_NUM_S)) -#define EFUSE_PWR_ON_NUM_V 0xFFFF -#define EFUSE_PWR_ON_NUM_S 8 -/* EFUSE_TSUP_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */ -/*description: Configures the setup time of programming operation.*/ -#define EFUSE_TSUP_A 0x000000FF -#define EFUSE_TSUP_A_M ((EFUSE_TSUP_A_V)<<(EFUSE_TSUP_A_S)) -#define EFUSE_TSUP_A_V 0xFF +/** EFUSE_WR_TIM_CONF1_REG register + * Configuration register 1 of eFuse programming timing parameters. + */ +#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f4) +/** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1; + * Configures the setup time of programming operation. + */ +#define EFUSE_TSUP_A 0x000000FFU +#define EFUSE_TSUP_A_M (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S) +#define EFUSE_TSUP_A_V 0x000000FFU #define EFUSE_TSUP_A_S 0 +/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 10368; + * Configures the power up time for VDDQ. + */ +#define EFUSE_PWR_ON_NUM 0x0000FFFFU +#define EFUSE_PWR_ON_NUM_M (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S) +#define EFUSE_PWR_ON_NUM_V 0x0000FFFFU +#define EFUSE_PWR_ON_NUM_S 8 -#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1F8) -/* EFUSE_PWR_OFF_NUM : R/W ;bitpos:[15:0] ;default: 16'h190 ; */ -/*description: Configures the power outage time for VDDQ.*/ -#define EFUSE_PWR_OFF_NUM 0x0000FFFF -#define EFUSE_PWR_OFF_NUM_M ((EFUSE_PWR_OFF_NUM_V)<<(EFUSE_PWR_OFF_NUM_S)) -#define EFUSE_PWR_OFF_NUM_V 0xFFFF +/** EFUSE_WR_TIM_CONF2_REG register + * Configuration register 2 of eFuse programming timing parameters. + */ +#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f8) +/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400; + * Configures the power outage time for VDDQ. + */ +#define EFUSE_PWR_OFF_NUM 0x0000FFFFU +#define EFUSE_PWR_OFF_NUM_M (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S) +#define EFUSE_PWR_OFF_NUM_V 0x0000FFFFU #define EFUSE_PWR_OFF_NUM_S 0 -#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1FC) -/* EFUSE_DATE : R/W ;bitpos:[31:0] ;default: 32'h19081100 ; */ -/*description: Stores eFuse version.*/ -#define EFUSE_DATE 0xFFFFFFFF -#define EFUSE_DATE_M ((EFUSE_DATE_V)<<(EFUSE_DATE_S)) -#define EFUSE_DATE_V 0xFFFFFFFF +/** EFUSE_DATE_REG register + * Version control register. + */ +#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) +/** EFUSE_DATE : R/W; bitpos: [31:0]; default: 419959040; + * Version control register. + */ +#define EFUSE_DATE 0xFFFFFFFFU +#define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S) +#define EFUSE_DATE_V 0xFFFFFFFFU #define EFUSE_DATE_S 0 #ifdef __cplusplus } #endif - - - -#endif /*_SOC_EFUSE_REG_H_ */ diff --git a/tools/sdk/esp32s2/include/soc/esp32s2/include/soc/efuse_struct.h b/tools/sdk/esp32s2/include/soc/esp32s2/include/soc/efuse_struct.h index 705c47a4124..88f99599f55 100644 --- a/tools/sdk/esp32s2/include/soc/esp32s2/include/soc/efuse_struct.h +++ b/tools/sdk/esp32s2/include/soc/esp32s2/include/soc/efuse_struct.h @@ -1,542 +1,2440 @@ -/* - * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once #include - #ifdef __cplusplus extern "C" { #endif -typedef volatile struct efuse_dev_s { - uint32_t pgm_data0; /**/ - union { - struct { - uint32_t rd_dis: 7; - uint32_t dis_rtc_ram_boot: 1; - uint32_t dis_icache: 1; - uint32_t dis_dcache: 1; - uint32_t dis_download_icache: 1; - uint32_t dis_download_dcache: 1; - uint32_t dis_force_download: 1; - uint32_t dis_usb: 1; - uint32_t dis_can: 1; - uint32_t dis_sdio_access: 1; - uint32_t dis_efuse_ate_wr: 1; - uint32_t soft_dis_jtag: 1; - uint32_t hard_dis_jtag: 1; - uint32_t dis_download_manual_encrypt: 1; - uint32_t usb_drefh: 2; - uint32_t usb_drefl: 2; - uint32_t usb_exchg_pins: 1; - uint32_t ext_phy_enable: 1; - uint32_t usb_force_b: 1; - uint32_t usb_dres: 2; - uint32_t sdio_modecurlim: 1; - uint32_t sdio_drefh: 2; - }; - uint32_t val; - } pgm_data1; - union { - struct { - uint32_t sdio_drefm: 2; - uint32_t sdio_drefl: 2; - uint32_t sdio_xpd: 1; - uint32_t sdio_tieh: 1; - uint32_t sdio_force: 1; - uint32_t sdio_en_init: 1; - uint32_t sdio_encurlim: 1; - uint32_t sdio_dcurlim: 3; - uint32_t sdio_init: 2; - uint32_t sdio_dcap: 2; - uint32_t wdt_delay_sel: 2; - uint32_t spi_boot_crypt_cnt: 3; - uint32_t secure_boot_key_revoke0: 1; - uint32_t secure_boot_key_revoke1: 1; - uint32_t secure_boot_key_revoke2: 1; - uint32_t key_purpose_0: 4; - uint32_t key_purpose_1: 4; - }; - uint32_t val; - } pgm_data2; - union { - struct { - uint32_t key_purpose_2: 4; - uint32_t key_purpose_3: 4; - uint32_t key_purpose_4: 4; - uint32_t key_purpose_5: 4; - uint32_t key_purpose_6: 4; - uint32_t secure_boot_en: 1; - uint32_t secure_boot_aggressive_revoke: 1; - uint32_t xtal_freq: 6; - uint32_t flash_tpuw: 4; - }; - uint32_t val; - } pgm_data3; - union { - struct { - uint32_t dis_download_mode: 1; - uint32_t dis_legacy_spi_boot: 1; - uint32_t uart_print_channel: 1; - uint32_t dis_tiny_basic: 1; - uint32_t dis_usb_download_mode: 1; - uint32_t enable_security_download: 1; - uint32_t uart_print_control: 2; - uint32_t reserve: 24; - }; - uint32_t val; - } pgm_data4; - union { - struct { - uint32_t chip_version:24; - uint32_t rs_data_23: 8; - }; - uint32_t val; - } pgm_data5; - uint32_t pgm_data6; /**/ - uint32_t pgm_data7; /**/ - uint32_t pgm_check_value0; /**/ - uint32_t pgm_check_value1; /**/ - uint32_t pgm_check_value2; /**/ - uint32_t rd_wr_dis; /**/ - union { - struct { - uint32_t rd_dis: 7; - uint32_t dis_rtc_ram_boot: 1; - uint32_t dis_icache: 1; - uint32_t dis_dcache: 1; - uint32_t dis_download_icache: 1; - uint32_t dis_download_dcache: 1; - uint32_t dis_force_download: 1; - uint32_t dis_usb: 1; - uint32_t dis_can: 1; - uint32_t dis_sdio_access: 1; - uint32_t dis_ate_wr: 1; - uint32_t soft_dis_jtag: 1; - uint32_t hard_dis_jtag: 1; - uint32_t dis_download_manual_encrypt: 1; - uint32_t usb_drefh: 2; - uint32_t usb_drefl: 2; - uint32_t usb_exchg_pins: 1; - uint32_t ext_phy_enable: 1; - uint32_t usb_force_b: 1; - uint32_t usb_dres: 2; - uint32_t sdio_modecurlim: 1; - uint32_t sdio_drefh: 2; - }; - uint32_t val; - } rd_repeat_data0; - union { - struct { - uint32_t sdio_drefm: 2; - uint32_t sdio_drefl: 2; - uint32_t sdio_xpd: 1; - uint32_t sdio_tieh: 1; - uint32_t sdio_force: 1; - uint32_t sdio_en_init: 1; - uint32_t sdio_encurlim: 1; - uint32_t sdio_dcurlim: 3; - uint32_t sdio_init: 2; - uint32_t eufse_sdio_dcap: 2; - uint32_t wdt_delay_sel: 2; - uint32_t spi_boot_crypt_cnt: 3; - uint32_t secure_boot_key_revoke0: 1; - uint32_t secure_boot_key_revoke1: 1; - uint32_t secure_boot_key_revoke2: 1; - uint32_t key_purpose_0: 4; - uint32_t key_purpose_1: 4; - }; - uint32_t val; - } rd_repeat_data1; - union { - struct { - uint32_t key_purpose_2: 4; - uint32_t key_purpose_3: 4; - uint32_t key_purpose_4: 4; - uint32_t key_purpose_5: 4; - uint32_t key_purpose_6: 4; - uint32_t secure_boot_en: 1; - uint32_t secure_boot_aggressive_revoke: 1; - uint32_t xtal_freq: 6; - uint32_t flash_tpuw: 4; - }; - uint32_t val; - } rd_repeat_data2; - union { - struct { - uint32_t dis_download_mode: 1; - uint32_t dis_legacy_spi_boot: 1; - uint32_t uart_print_channel: 1; - uint32_t dis_tiny_basic: 1; - uint32_t dis_usb_download_mode: 1; - uint32_t enable_security_download: 1; - uint32_t uart_print_control: 2; - uint32_t reserve: 24; - }; - uint32_t val; - } rd_repeat_data3; - union { - struct { - uint32_t disable_wafer_version_major: 1; - uint32_t disable_blk_version_major: 1; - uint32_t rpt4_reserved4:22; - uint32_t reserved24: 8; - }; - uint32_t val; - } rd_repeat_data4; - uint32_t rd_mac_spi_8m_0; /**/ - union { - struct { - uint32_t mac_1: 16; - uint32_t spi_pad_conf_0:16; - }; - uint32_t val; - } rd_mac_spi_8m_1; - union { - struct { - uint32_t spi_pad_conf_1:20; - uint32_t clk8m_freq: 12; - }; - uint32_t val; - } rd_mac_spi_8m_2; - union { - struct { - uint32_t spi_pad_conf_2: 18; - uint32_t wafer_version_major: 2; - uint32_t wafer_version_minor_high: 1; // most significant bit - uint32_t reserve1: 4; - uint32_t blk_version_major: 2; - uint32_t reserve2: 5; - }; - uint32_t val; - } rd_mac_spi_8m_3; - union { - struct { - uint32_t pkg_version: 4; - uint32_t wafer_version_minor_low: 3; // least significant bits - uint32_t reserve: 25; - }; - uint32_t val; - } rd_mac_spi_8m_4; - uint32_t rd_mac_spi_8m_5; /**/ - uint32_t rd_sys_data0; /**/ - uint32_t rd_sys_data1; /**/ - uint32_t rd_sys_data2; /**/ - uint32_t rd_sys_data3; /**/ - union { - struct { - uint32_t ocode_low: 4; - uint32_t blk_version_minor : 3; - uint32_t reserved1: 9; - uint32_t ocode_hi: 3; - uint32_t reserved2: 13; - }; - uint32_t val; - } rd_sys_data4; /**/ - uint32_t rd_sys_data5; /**/ - uint32_t rd_sys_data6; /**/ - uint32_t rd_sys_data7; /**/ - uint32_t rd_usr_data0; /**/ - uint32_t rd_usr_data1; /**/ - uint32_t rd_usr_data2; /**/ - uint32_t rd_usr_data3; /**/ - uint32_t rd_usr_data4; /**/ - uint32_t rd_usr_data5; /**/ - uint32_t rd_usr_data6; /**/ - uint32_t rd_usr_data7; /**/ - uint32_t rd_key0_data0; /**/ - uint32_t rd_key0_data1; /**/ - uint32_t rd_key0_data2; /**/ - uint32_t rd_key0_data3; /**/ - uint32_t rd_key0_data4; /**/ - uint32_t rd_key0_data5; /**/ - uint32_t rd_key0_data6; /**/ - uint32_t rd_key0_data7; /**/ - uint32_t rd_key1_data0; /**/ - uint32_t rd_key1_data1; /**/ - uint32_t rd_key1_data2; /**/ - uint32_t rd_key1_data3; /**/ - uint32_t rd_key1_data4; /**/ - uint32_t rd_key1_data5; /**/ - uint32_t rd_key1_data6; /**/ - uint32_t rd_key1_data7; /**/ - uint32_t rd_key2_data0; /**/ - uint32_t rd_key2_data1; /**/ - uint32_t rd_key2_data2; /**/ - uint32_t rd_key2_data3; /**/ - uint32_t rd_key2_data4; /**/ - uint32_t rd_key2_data5; /**/ - uint32_t rd_key2_data6; /**/ - uint32_t rd_key2_data7; /**/ - uint32_t rd_key3_data0; /**/ - uint32_t rd_key3_data1; /**/ - uint32_t rd_key3_data2; /**/ - uint32_t rd_key3_data3; /**/ - uint32_t rd_key3_data4; /**/ - uint32_t rd_key3_data5; /**/ - uint32_t rd_key3_data6; /**/ - uint32_t rd_key3_data7; /**/ - uint32_t rd_key4_data0; /**/ - uint32_t rd_key4_data1; /**/ - uint32_t rd_key4_data2; /**/ - uint32_t rd_key4_data3; /**/ - uint32_t rd_key4_data4; /**/ - uint32_t rd_key4_data5; /**/ - uint32_t rd_key4_data6; /**/ - uint32_t rd_key4_data7; /**/ - uint32_t rd_key5_data0; /**/ - uint32_t rd_key5_data1; /**/ - uint32_t rd_key5_data2; /**/ - uint32_t rd_key5_data3; /**/ - uint32_t rd_key5_data4; /**/ - uint32_t rd_key5_data5; /**/ - uint32_t rd_key5_data6; /**/ - uint32_t rd_key5_data7; /**/ - uint32_t rd_key6_data0; /**/ - uint32_t rd_key6_data1; /**/ - uint32_t rd_key6_data2; /**/ - uint32_t rd_key6_data3; /**/ - uint32_t rd_key6_data4; /**/ - uint32_t rd_key6_data5; /**/ - uint32_t rd_key6_data6; /**/ - uint32_t rd_key6_data7; /**/ - union { - struct { - uint32_t rd_rd_dis_err: 7; - uint32_t rd_dis_rtc_ram_boot_err: 1; - uint32_t rd_dis_icache_err: 1; - uint32_t rd_dis_dcache_err: 1; - uint32_t rd_dis_download_icache_err: 1; - uint32_t rd_dis_download_dcache_err: 1; - uint32_t rd_dis_force_download: 1; - uint32_t rd_dis_usb_err: 1; - uint32_t rd_dis_can_err: 1; - uint32_t rd_dis_sdio_access_err: 1; - uint32_t rd_dis_efuse_ate_wr_err: 1; - uint32_t rd_soft_dis_jtag_err: 1; - uint32_t rd_hard_dis_jtag_err: 1; - uint32_t rd_dis_download_manual_encrypt_err: 1; - uint32_t rd_usb_drefh_err: 2; - uint32_t rd_usb_drefl_err: 2; - uint32_t rd_usb_exchg_pins_err: 1; - uint32_t rd_ext_phy_enable: 1; - uint32_t rd_usb_force: 1; - uint32_t rd_usb_dres_err: 2; - uint32_t rd_sdio_modecurlim_err: 1; - uint32_t rd_sdio_drefh_err: 2; - }; - uint32_t val; - } rd_repeat_err0; - union { - struct { - uint32_t rd_sdio_drefm_err: 2; - uint32_t rd_sdio_drefl_err: 2; - uint32_t rd_sdio_xpd_err: 1; - uint32_t rd_sdio_tieh_err: 1; - uint32_t rd_sdio_force_err: 1; - uint32_t rd_sdio_en_init_err: 1; - uint32_t rd_sdio_encurlim_err: 1; - uint32_t rd_sdio_dcurlim_err: 3; - uint32_t rd_sdio_init_err: 2; - uint32_t rd_sdio_dcap_err: 2; - uint32_t rd_wdt_delay_sel_err: 2; - uint32_t rd_spi_boot_crypt_cnt_err: 3; - uint32_t rd_secure_boot_key_revoke0_err: 1; - uint32_t rd_secure_boot_key_revoke1_err: 1; - uint32_t rd_secure_boot_key_revoke2_err: 1; - uint32_t rd_key_purpose_0_err: 4; - uint32_t rd_key_purpose_1_err: 4; - }; - uint32_t val; - } rd_repeat_err1; - union { - struct { - uint32_t rd_key_purpose_2_err: 4; - uint32_t rd_key_purpose_3_err: 4; - uint32_t rd_key_purpose_4_err: 4; - uint32_t rd_key_purpose_5_err: 4; - uint32_t rd_key_purpose_6_err: 4; - uint32_t rd_secure_boot_en_err: 1; - uint32_t rd_secure_boot_aggressive_revoke_err: 1; - uint32_t rd_xtal_freq_err: 6; - uint32_t rd_flash_tpuw_err: 4; - }; - uint32_t val; - } rd_repeat_err2; - union { - struct { - uint32_t rd_dis_download_mode_err: 1; - uint32_t rd_dis_legacy_spi_boot_err: 1; - uint32_t rd_uart_print_channel: 1; - uint32_t rd_dis_tiny_basic: 1; - uint32_t rd_dis_usb_download_mode: 1; - uint32_t rd_enable_security_download: 1; - uint32_t rd_uart_print_control: 2; - uint32_t rd_reserve_err: 24; - }; - uint32_t val; - } rd_repeat_err3; - union { - struct { - uint32_t rd_chip_version_err:24; - uint32_t reserved24: 8; - }; - uint32_t val; - } rd_repeat_err4; - uint32_t reserved_190; - uint32_t reserved_194; - uint32_t reserved_198; - uint32_t reserved_19c; - uint32_t reserved_1a0; - uint32_t reserved_1a4; - uint32_t reserved_1a8; - uint32_t reserved_1ac; - uint32_t reserved_1b0; - uint32_t reserved_1b4; - uint32_t reserved_1b8; - uint32_t reserved_1bc; - union { - struct { - uint32_t rd_mac_spi_8m_err_num: 3; - uint32_t rd_mac_spi_8m_fail: 1; - uint32_t rd_sys_err_num: 3; - uint32_t rd_sys_err_fail: 1; - uint32_t rd_usr_data_err_num: 3; - uint32_t rd_usr_data_fail: 1; - uint32_t rd_key0_err_num: 3; - uint32_t rd_key0_fail: 1; - uint32_t rd_key1_err_num: 3; - uint32_t rd_key1_fail: 1; - uint32_t rd_key2_err_num: 3; - uint32_t rd_key2_fail: 1; - uint32_t rd_key3_err_num: 3; - uint32_t rd_key3_fail: 1; - uint32_t rd_key4_err_num: 3; - uint32_t rd_key4_fail: 1; - }; - uint32_t val; - } rd_rs_err0; - union { - struct { - uint32_t rd_key5_err_num: 3; - uint32_t rd_key5_fail: 1; - uint32_t rd_key6_err_num: 3; - uint32_t rd_key6_fail: 1; - uint32_t reserved8: 24; - }; - uint32_t val; - } rd_rs_err1; - union { - struct { - uint32_t mem_pd: 1; - uint32_t reserved1: 15; - uint32_t clk_en: 1; - uint32_t reserved17:15; - }; - uint32_t val; - } clk; - union { - struct { - uint32_t op_code: 16; - uint32_t reserved16:16; - }; - uint32_t val; - } conf; - union { - struct { - uint32_t state: 3; - uint32_t otp_load_sw: 1; - uint32_t otp_vddq_c_sync2: 1; - uint32_t otp_strobe_sw: 1; - uint32_t otp_csb_sw: 1; - uint32_t otp_pgenb_sw: 1; - uint32_t otp_vddq_is_sw: 1; - uint32_t repeat_err_cnt: 8; - uint32_t reserved17: 15; - }; - uint32_t val; - } status; - union { - struct { - uint32_t read_cmd: 1; - uint32_t pgm_cmd: 1; - uint32_t blk_num: 4; - uint32_t reserved6: 26; - }; - uint32_t val; - } cmd; - union { - struct { - uint32_t read_done: 1; - uint32_t pgm_done: 1; - uint32_t reserved2: 30; - }; - uint32_t val; - } int_raw; - union { - struct { - uint32_t read_done: 1; - uint32_t pgm_done: 1; - uint32_t reserved2: 30; - }; - uint32_t val; - } int_st; - union { - struct { - uint32_t read_done: 1; - uint32_t pgm_done: 1; - uint32_t reserved2: 30; - }; - uint32_t val; - } int_ena; - union { - struct { - uint32_t read_done: 1; - uint32_t pgm_done: 1; - uint32_t reserved2: 30; - }; - uint32_t val; - } int_clr; - union { - struct { - uint32_t dac_clk_div: 8; - uint32_t dac_clk_pad_sel: 1; - uint32_t reserved9: 23; - }; - uint32_t val; - } dac_conf; - union { - struct { - uint32_t thr_a: 8; - uint32_t trd: 8; - uint32_t tsur_a: 8; - uint32_t read_init_num: 8; - }; - uint32_t val; - } rd_tim_conf; - union { - struct { - uint32_t thp_a: 8; - uint32_t tpgm_inactive: 8; - uint32_t tpgm: 16; - }; - uint32_t val; - } wr_tim_conf0; - union { - struct { - uint32_t tsup_a: 8; - uint32_t pwr_on_num:16; - uint32_t reserved24: 8; - }; - uint32_t val; - } wr_tim_conf1; - uint32_t reserved_1f8; - uint32_t date; /**/ +/** Group: PGM Data Registers */ +/** Type of pgm_data0 register + * Register 0 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit data to be programmed. + */ + uint32_t pgm_data_0:32; + }; + uint32_t val; +} efuse_pgm_data0_reg_t; + +/** Type of pgm_data1 register + * Register 1 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1th 32-bit data to be programmed. + */ + uint32_t pgm_data_0:32; + }; + uint32_t val; +} efuse_pgm_data1_reg_t; + +/** Type of pgm_data2 register + * Register 2 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2th 32-bit data to be programmed. + */ + uint32_t pgm_data_0:32; + }; + uint32_t val; +} efuse_pgm_data2_reg_t; + +/** Type of pgm_data3 register + * Register 3 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 3th 32-bit data to be programmed. + */ + uint32_t pgm_data_0:32; + }; + uint32_t val; +} efuse_pgm_data3_reg_t; + +/** Type of pgm_data4 register + * Register 4 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 4th 32-bit data to be programmed. + */ + uint32_t pgm_data_0:32; + }; + uint32_t val; +} efuse_pgm_data4_reg_t; + +/** Type of pgm_data5 register + * Register 5 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 5th 32-bit data to be programmed. + */ + uint32_t pgm_data_0:32; + }; + uint32_t val; +} efuse_pgm_data5_reg_t; + +/** Type of pgm_data6 register + * Register 6 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 6th 32-bit data to be programmed. + */ + uint32_t pgm_data_0:32; + }; + uint32_t val; +} efuse_pgm_data6_reg_t; + +/** Type of pgm_data7 register + * Register 7 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 7th 32-bit data to be programmed. + */ + uint32_t pgm_data_0:32; + }; + uint32_t val; +} efuse_pgm_data7_reg_t; + +/** Type of pgm_check_value0 register + * Register 0 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_0:32; + }; + uint32_t val; +} efuse_pgm_check_value0_reg_t; + +/** Type of pgm_check_value1 register + * Register 1 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1th 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_0:32; + }; + uint32_t val; +} efuse_pgm_check_value1_reg_t; + +/** Type of pgm_check_value2 register + * Register 2 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2th 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_0:32; + }; + uint32_t val; +} efuse_pgm_check_value2_reg_t; + + +/** Group: Read Data Registers */ +/** Type of rd_wr_dis register + * Register 0 of BLOCK0. + */ +typedef union { + struct { + /** wr_dis : RO; bitpos: [31:0]; default: 0; + * Disables programming of individual eFuses. + */ + uint32_t wr_dis:32; + }; + uint32_t val; +} efuse_rd_wr_dis_reg_t; + +/** Type of rd_repeat_data0 register + * Register 1 of BLOCK0. + */ +typedef union { + struct { + /** rd_dis : RO; bitpos: [6:0]; default: 0; + * Disables software reading from individual eFuse blocks (BLOCK4-10). + */ + uint32_t rd_dis:7; + /** dis_rtc_ram_boot : RO; bitpos: [7]; default: 0; + * Reserved. + */ + uint32_t dis_rtc_ram_boot:1; + /** dis_icache : RO; bitpos: [8]; default: 0; + * Set this bit to disable Icache. + */ + uint32_t dis_icache:1; + /** dis_dcache : RO; bitpos: [9]; default: 0; + * Set this bit to disable Dcache. + */ + uint32_t dis_dcache:1; + /** dis_download_icache : RO; bitpos: [10]; default: 0; + * Disables Icache when SoC is in Download mode. + */ + uint32_t dis_download_icache:1; + /** dis_download_dcache : RO; bitpos: [11]; default: 0; + * Disables Dcache when SoC is in Download mode. + */ + uint32_t dis_download_dcache:1; + /** dis_force_download : RO; bitpos: [12]; default: 0; + * Set this bit to disable the function that forces chip into download mode. + */ + uint32_t dis_force_download:1; + /** dis_usb : RO; bitpos: [13]; default: 0; + * Set this bit to disable USB OTG function. + */ + uint32_t dis_usb:1; + /** dis_twai : RO; bitpos: [14]; default: 0; + * Set this bit to disable the TWAI Controller function. + */ + uint32_t dis_twai:1; + /** dis_boot_remap : RO; bitpos: [15]; default: 0; + * Disables capability to Remap RAM to ROM address space. + */ + uint32_t dis_boot_remap:1; + /** rpt4_reserved5 : RO; bitpos: [16]; default: 0; + * Reserved (used for four backups method). + */ + uint32_t rpt4_reserved5:1; + /** soft_dis_jtag : RO; bitpos: [17]; default: 0; + * Software disables JTAG. When software disabled, JTAG can be activated temporarily + * by HMAC peripheral. + */ + uint32_t soft_dis_jtag:1; + /** hard_dis_jtag : RO; bitpos: [18]; default: 0; + * Hardware disables JTAG permanently. + */ + uint32_t hard_dis_jtag:1; + /** dis_download_manual_encrypt : RO; bitpos: [19]; default: 0; + * Disables flash encryption when in download boot modes. + */ + uint32_t dis_download_manual_encrypt:1; + /** usb_drefh : RO; bitpos: [21:20]; default: 0; + * Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored + * in eFuse. + */ + uint32_t usb_drefh:2; + /** usb_drefl : RO; bitpos: [23:22]; default: 0; + * Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, + * stored in eFuse. + */ + uint32_t usb_drefl:2; + /** usb_exchg_pins : RO; bitpos: [24]; default: 0; + * Set this bit to exchange USB D+ and D- pins. + */ + uint32_t usb_exchg_pins:1; + /** usb_ext_phy_enable : RO; bitpos: [25]; default: 0; + * Set this bit to enable external USB PHY. + */ + uint32_t usb_ext_phy_enable:1; + /** usb_force_nopersist : RO; bitpos: [26]; default: 0; + * If set, forces USB BVALID to 1. + */ + uint32_t usb_force_nopersist:1; + /** block0_version : R; bitpos: [28:27]; default: 0; + * BLOCK0 efuse version + */ + uint32_t block0_version:2; + /** vdd_spi_modecurlim : RO; bitpos: [29]; default: 0; + * SPI regulator switches current limit mode. + */ + uint32_t vdd_spi_modecurlim:1; + /** vdd_spi_drefh : RO; bitpos: [31:30]; default: 0; + * SPI regulator high voltage reference. + */ + uint32_t vdd_spi_drefh:2; + }; + uint32_t val; +} efuse_rd_repeat_data0_reg_t; + +/** Type of rd_repeat_data1 register + * Register 2 of BLOCK0. + */ +typedef union { + struct { + /** vdd_spi_drefm : RO; bitpos: [1:0]; default: 0; + * SPI regulator medium voltage reference. + */ + uint32_t vdd_spi_drefm:2; + /** vdd_spi_drefl : RO; bitpos: [3:2]; default: 0; + * SPI regulator low voltage reference. + */ + uint32_t vdd_spi_drefl:2; + /** vdd_spi_xpd : RO; bitpos: [4]; default: 0; + * If VDD_SPI_FORCE is 1, this value determines if the VDD_SPI regulator is powered on. + */ + uint32_t vdd_spi_xpd:1; + /** vdd_spi_tieh : RO; bitpos: [5]; default: 0; + * If VDD_SPI_FORCE is 1, determines VDD_SPI voltage. 0: VDD_SPI connects to 1.8 V + * LDO. 1: VDD_SPI connects to VDD_RTC_IO. + */ + uint32_t vdd_spi_tieh:1; + /** vdd_spi_force : RO; bitpos: [6]; default: 0; + * Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TIEH to configure VDD_SPI LDO. + */ + uint32_t vdd_spi_force:1; + /** vdd_spi_en_init : RO; bitpos: [7]; default: 0; + * Set SPI regulator to 0 to configure init[1:0]=0. + */ + uint32_t vdd_spi_en_init:1; + /** vdd_spi_encurlim : RO; bitpos: [8]; default: 0; + * Set SPI regulator to 1 to enable output current limit. + */ + uint32_t vdd_spi_encurlim:1; + /** vdd_spi_dcurlim : RO; bitpos: [11:9]; default: 0; + * Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d). + */ + uint32_t vdd_spi_dcurlim:3; + /** vdd_spi_init : RO; bitpos: [13:12]; default: 0; + * Adds resistor from LDO output to ground. 0: no resistance. 1: 6 K. 2: 4 K. 3: 2 K. + */ + uint32_t vdd_spi_init:2; + /** vdd_spi_dcap : RO; bitpos: [15:14]; default: 0; + * Prevents SPI regulator from overshoot. + */ + uint32_t vdd_spi_dcap:2; + /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0; + * Selects RTC watchdog timeout threshold at startup. 0: 40,000 slow clock cycles. 1: + * 80,000 slow clock cycles. 2: 160,000 slow clock cycles. 3: 320,000 slow clock + * cycles. + */ + uint32_t wdt_delay_sel:2; + /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0; + * Enables encryption and decryption, when an SPI boot mode is set. Feature is enabled + * 1 or 3 bits are set in the eFuse, disabled otherwise. + */ + uint32_t spi_boot_crypt_cnt:3; + /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0; + * If set, revokes use of secure boot key digest 0. + */ + uint32_t secure_boot_key_revoke0:1; + /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0; + * If set, revokes use of secure boot key digest 1. + */ + uint32_t secure_boot_key_revoke1:1; + /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0; + * If set, revokes use of secure boot key digest 2. + */ + uint32_t secure_boot_key_revoke2:1; + /** key_purpose_0 : RO; bitpos: [27:24]; default: 0; + * Purpose of KEY0. Refer to Table Key Purpose Values. + */ + uint32_t key_purpose_0:4; + /** key_purpose_1 : RO; bitpos: [31:28]; default: 0; + * Purpose of KEY1. Refer to Table Key Purpose Values. + */ + uint32_t key_purpose_1:4; + }; + uint32_t val; +} efuse_rd_repeat_data1_reg_t; + +/** Type of rd_repeat_data2 register + * Register 3 of BLOCK0. + */ +typedef union { + struct { + /** key_purpose_2 : RO; bitpos: [3:0]; default: 0; + * Purpose of KEY2. Refer to Table Key Purpose Values. + */ + uint32_t key_purpose_2:4; + /** key_purpose_3 : RO; bitpos: [7:4]; default: 0; + * Purpose of KEY3. Refer to Table Key Purpose Values. + */ + uint32_t key_purpose_3:4; + /** key_purpose_4 : RO; bitpos: [11:8]; default: 0; + * Purpose of KEY4. Refer to Table Key Purpose Values. + */ + uint32_t key_purpose_4:4; + /** key_purpose_5 : RO; bitpos: [15:12]; default: 0; + * Purpose of KEY5. Refer to Table Key Purpose Values. + */ + uint32_t key_purpose_5:4; + /** key_purpose_6 : RO; bitpos: [19:16]; default: 0; + * Purpose of KEY6. Refer to Table Key Purpose Values. + */ + uint32_t key_purpose_6:4; + /** secure_boot_en : RO; bitpos: [20]; default: 0; + * Set this bit to enable secure boot. + */ + uint32_t secure_boot_en:1; + /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0; + * Set this bit to enable aggressive secure boot key revocation mode. + */ + uint32_t secure_boot_aggressive_revoke:1; + /** rpt4_reserved1 : RO; bitpos: [27:22]; default: 0; + * Reserved (used for four backups method). + */ + uint32_t rpt4_reserved1:6; + /** flash_tpuw : RO; bitpos: [31:28]; default: 0; + * Configures flash startup delay after SoC power-up, in unit of (ms/2). When the + * value is 15, delay is 7.5 ms. + */ + uint32_t flash_tpuw:4; + }; + uint32_t val; +} efuse_rd_repeat_data2_reg_t; + +/** Type of rd_repeat_data3 register + * Register 4 of BLOCK0. + */ +typedef union { + struct { + /** dis_download_mode : RO; bitpos: [0]; default: 0; + * Set this bit to disable all download boot modes. + */ + uint32_t dis_download_mode:1; + /** dis_legacy_spi_boot : RO; bitpos: [1]; default: 0; + * Set this bit to disable Legacy SPI boot mode. + */ + uint32_t dis_legacy_spi_boot:1; + /** uart_print_channel : RO; bitpos: [2]; default: 0; + * Selects the default UART for printing boot messages. 0: UART0. 1: UART1. + */ + uint32_t uart_print_channel:1; + /** rpt4_reserved3 : RO; bitpos: [3]; default: 0; + * Reserved (used for four backups method). + */ + uint32_t rpt4_reserved3:1; + /** dis_usb_download_mode : RO; bitpos: [4]; default: 0; + * Set this bit to disable use of USB OTG in UART download boot mode. + */ + uint32_t dis_usb_download_mode:1; + /** enable_security_download : RO; bitpos: [5]; default: 0; + * Set this bit to enable secure UART download mode (read/write flash only). + */ + uint32_t enable_security_download:1; + /** uart_print_control : RO; bitpos: [7:6]; default: 0; + * Set the default UART boot message output mode. 00: Enabled. 01: Enable when GPIO46 + * is low at reset. 10: Enable when GPIO46 is high at reset. 11: Disabled. + */ + uint32_t uart_print_control:2; + /** pin_power_selection : RO; bitpos: [8]; default: 0; + * Set default power supply for GPIO33-GPIO37, set when SPI flash is initialized. 0: + * VDD3P3_CPU. 1: VDD_SPI. + */ + uint32_t pin_power_selection:1; + /** flash_type : RO; bitpos: [9]; default: 0; + * SPI flash type. 0: maximum four data lines, 1: eight data lines. + */ + uint32_t flash_type:1; + /** force_send_resume : RO; bitpos: [10]; default: 0; + * If set, forces ROM code to send an SPI flash resume command during SPI boot. + */ + uint32_t force_send_resume:1; + /** secure_version : RO; bitpos: [26:11]; default: 0; + * Secure version (used by ESP-IDF anti-rollback feature). + */ + uint32_t secure_version:16; + /** rpt4_reserved2 : RO; bitpos: [31:27]; default: 0; + * Reserved (used for four backups method). + */ + uint32_t rpt4_reserved2:5; + }; + uint32_t val; +} efuse_rd_repeat_data3_reg_t; + +/** Type of rd_repeat_data4 register + * Register 5 of BLOCK0. + */ +typedef union { + struct { + /** disable_wafer_version_major : R; bitpos: [0]; default: 0; + * Disables check of wafer version major + */ + uint32_t disable_wafer_version_major:1; + /** disable_blk_version_major : R; bitpos: [1]; default: 0; + * Disables check of blk version major + */ + uint32_t disable_blk_version_major:1; + /** reserved_0_162 : R; bitpos: [23:2]; default: 0; + * reserved + */ + uint32_t reserved_0_162:22; + uint32_t reserved_24:8; + }; + uint32_t val; +} efuse_rd_repeat_data4_reg_t; + +/** Type of rd_mac_spi_sys_0 register + * Register 0 of BLOCK1. + */ +typedef union { + struct { + /** mac_0 : RO; bitpos: [31:0]; default: 0; + * Stores the low 32 bits of MAC address. + */ + uint32_t mac_0:32; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_0_reg_t; + +/** Type of rd_mac_spi_sys_1 register + * Register 1 of BLOCK1. + */ +typedef union { + struct { + /** mac_1 : RO; bitpos: [15:0]; default: 0; + * Stores the high 16 bits of MAC address. + */ + uint32_t mac_1:16; + /** spi_pad_config_clk : R; bitpos: [21:16]; default: 0; + * SPI_PAD_configure CLK + */ + uint32_t spi_pad_config_clk:6; + /** spi_pad_config_q : R; bitpos: [27:22]; default: 0; + * SPI_PAD_configure Q(D1) + */ + uint32_t spi_pad_config_q:6; + /** spi_pad_config_d : R; bitpos: [31:28]; default: 0; + * SPI_PAD_configure D(D0) + */ + uint32_t spi_pad_config_d:4; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_1_reg_t; + +/** Type of rd_mac_spi_sys_2 register + * Register 2 of BLOCK1. + */ +typedef union { + struct { + /** spi_pad_config_d_1 : R; bitpos: [1:0]; default: 0; + * SPI_PAD_configure D(D0) + */ + uint32_t spi_pad_config_d_1:2; + /** spi_pad_config_cs : R; bitpos: [7:2]; default: 0; + * SPI_PAD_configure CS + */ + uint32_t spi_pad_config_cs:6; + /** spi_pad_config_hd : R; bitpos: [13:8]; default: 0; + * SPI_PAD_configure HD(D3) + */ + uint32_t spi_pad_config_hd:6; + /** spi_pad_config_wp : R; bitpos: [19:14]; default: 0; + * SPI_PAD_configure WP(D2) + */ + uint32_t spi_pad_config_wp:6; + /** spi_pad_config_dqs : R; bitpos: [25:20]; default: 0; + * SPI_PAD_configure DQS + */ + uint32_t spi_pad_config_dqs:6; + /** spi_pad_config_d4 : R; bitpos: [31:26]; default: 0; + * SPI_PAD_configure D4 + */ + uint32_t spi_pad_config_d4:6; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_2_reg_t; + +/** Type of rd_mac_spi_sys_3 register + * Register 3 of BLOCK1. + */ +typedef union { + struct { + /** spi_pad_config_d5 : R; bitpos: [5:0]; default: 0; + * SPI_PAD_configure D5 + */ + uint32_t spi_pad_config_d5:6; + /** spi_pad_config_d6 : R; bitpos: [11:6]; default: 0; + * SPI_PAD_configure D6 + */ + uint32_t spi_pad_config_d6:6; + /** spi_pad_config_d7 : R; bitpos: [17:12]; default: 0; + * SPI_PAD_configure D7 + */ + uint32_t spi_pad_config_d7:6; + /** wafer_version_major : R; bitpos: [19:18]; default: 0; + * WAFER_VERSION_MAJOR + */ + uint32_t wafer_version_major:2; + /** wafer_version_minor_hi : R; bitpos: [20]; default: 0; + * WAFER_VERSION_MINOR most significant bit + */ + uint32_t wafer_version_minor_hi:1; + /** flash_version : R; bitpos: [24:21]; default: 0; + * Flash version + */ + uint32_t flash_version:4; + /** blk_version_major : R; bitpos: [26:25]; default: 0; + * BLK_VERSION_MAJOR + */ + uint32_t blk_version_major:2; + /** reserved_1_123 : R; bitpos: [27]; default: 0; + * reserved + */ + uint32_t reserved_1_123:1; + /** psram_version : R; bitpos: [31:28]; default: 0; + * PSRAM version + */ + uint32_t psram_version:4; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_3_reg_t; + +/** Type of rd_mac_spi_sys_4 register + * Register 4 of BLOCK1. + */ +typedef union { + struct { + /** pkg_version : R; bitpos: [3:0]; default: 0; + * Package version + */ + uint32_t pkg_version:4; + /** wafer_version_minor_lo : R; bitpos: [6:4]; default: 0; + * WAFER_VERSION_MINOR least significant bits + */ + uint32_t wafer_version_minor_lo:3; + /** reserved_1_135 : R; bitpos: [31:7]; default: 0; + * reserved + */ + uint32_t reserved_1_135:25; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_4_reg_t; + +/** Type of rd_mac_spi_sys_5 register + * Register 5 of BLOCK1. + */ +typedef union { + struct { + /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0; + * Stores the second part of the zeroth part of system data. + */ + uint32_t sys_data_part0_2:32; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_5_reg_t; + +/** Type of rd_sys_part1_data0 register + * Register 0 of BLOCK2 (system). + */ +typedef union { + struct { + /** optional_unique_id : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data0_reg_t; + +/** Type of rd_sys_part1_data1 register + * Register 1 of BLOCK2 (system). + */ +typedef union { + struct { + /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id_1:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data1_reg_t; + +/** Type of rd_sys_part1_data2 register + * Register 2 of BLOCK2 (system). + */ +typedef union { + struct { + /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id_2:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data2_reg_t; + +/** Type of rd_sys_part1_data3 register + * Register 3 of BLOCK2 (system). + */ +typedef union { + struct { + /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id_3:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data3_reg_t; + +/** Type of rd_sys_part1_data4 register + * Register 4 of BLOCK2 (system). + */ +typedef union { + struct { + /** adc_calib : R; bitpos: [3:0]; default: 0; + * 4 bit of ADC calibration + */ + uint32_t adc_calib:4; + /** blk_version_minor : R; bitpos: [6:4]; default: 0; + * BLK_VERSION_MINOR of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2 + */ + uint32_t blk_version_minor:3; + /** temp_calib : R; bitpos: [15:7]; default: 0; + * Temperature calibration data + */ + uint32_t temp_calib:9; + /** rtccalib_v1idx_a10h : R; bitpos: [23:16]; default: 0; */ + uint32_t rtccalib_v1idx_a10h:8; + /** rtccalib_v1idx_a11h : R; bitpos: [31:24]; default: 0; */ + uint32_t rtccalib_v1idx_a11h:8; + }; + uint32_t val; +} efuse_rd_sys_part1_data4_reg_t; + +/** Type of rd_sys_part1_data5 register + * Register 5 of BLOCK2 (system). + */ +typedef union { + struct { + /** rtccalib_v1idx_a12h : R; bitpos: [7:0]; default: 0; */ + uint32_t rtccalib_v1idx_a12h:8; + /** rtccalib_v1idx_a13h : R; bitpos: [15:8]; default: 0; */ + uint32_t rtccalib_v1idx_a13h:8; + /** rtccalib_v1idx_a20h : R; bitpos: [23:16]; default: 0; */ + uint32_t rtccalib_v1idx_a20h:8; + /** rtccalib_v1idx_a21h : R; bitpos: [31:24]; default: 0; */ + uint32_t rtccalib_v1idx_a21h:8; + }; + uint32_t val; +} efuse_rd_sys_part1_data5_reg_t; + +/** Type of rd_sys_part1_data6 register + * Register 6 of BLOCK2 (system). + */ +typedef union { + struct { + /** rtccalib_v1idx_a22h : R; bitpos: [7:0]; default: 0; */ + uint32_t rtccalib_v1idx_a22h:8; + /** rtccalib_v1idx_a23h : R; bitpos: [15:8]; default: 0; */ + uint32_t rtccalib_v1idx_a23h:8; + /** rtccalib_v1idx_a10l : R; bitpos: [21:16]; default: 0; */ + uint32_t rtccalib_v1idx_a10l:6; + /** rtccalib_v1idx_a11l : R; bitpos: [27:22]; default: 0; */ + uint32_t rtccalib_v1idx_a11l:6; + /** rtccalib_v1idx_a12l : R; bitpos: [31:28]; default: 0; */ + uint32_t rtccalib_v1idx_a12l:4; + }; + uint32_t val; +} efuse_rd_sys_part1_data6_reg_t; + +/** Type of rd_sys_part1_data7 register + * Register 7 of BLOCK2 (system). + */ +typedef union { + struct { + /** rtccalib_v1idx_a12l_1 : R; bitpos: [1:0]; default: 0; */ + uint32_t rtccalib_v1idx_a12l_1:2; + /** rtccalib_v1idx_a13l : R; bitpos: [7:2]; default: 0; */ + uint32_t rtccalib_v1idx_a13l:6; + /** rtccalib_v1idx_a20l : R; bitpos: [13:8]; default: 0; */ + uint32_t rtccalib_v1idx_a20l:6; + /** rtccalib_v1idx_a21l : R; bitpos: [19:14]; default: 0; */ + uint32_t rtccalib_v1idx_a21l:6; + /** rtccalib_v1idx_a22l : R; bitpos: [25:20]; default: 0; */ + uint32_t rtccalib_v1idx_a22l:6; + /** rtccalib_v1idx_a23l : R; bitpos: [31:26]; default: 0; */ + uint32_t rtccalib_v1idx_a23l:6; + }; + uint32_t val; +} efuse_rd_sys_part1_data7_reg_t; + +/** Type of rd_usr_data0 register + * Register 0 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of BLOCK3 (user). + */ + uint32_t usr_data0:32; + }; + uint32_t val; +} efuse_rd_usr_data0_reg_t; + +/** Type of rd_usr_data1 register + * Register 1 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of BLOCK3 (user). + */ + uint32_t usr_data1:32; + }; + uint32_t val; +} efuse_rd_usr_data1_reg_t; + +/** Type of rd_usr_data2 register + * Register 2 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of BLOCK3 (user). + */ + uint32_t usr_data2:32; + }; + uint32_t val; +} efuse_rd_usr_data2_reg_t; + +/** Type of rd_usr_data3 register + * Register 3 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of BLOCK3 (user). + */ + uint32_t usr_data3:32; + }; + uint32_t val; +} efuse_rd_usr_data3_reg_t; + +/** Type of rd_usr_data4 register + * Register 4 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of BLOCK3 (user). + */ + uint32_t usr_data4:32; + }; + uint32_t val; +} efuse_rd_usr_data4_reg_t; + +/** Type of rd_usr_data5 register + * Register 5 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of BLOCK3 (user). + */ + uint32_t usr_data5:32; + }; + uint32_t val; +} efuse_rd_usr_data5_reg_t; + +/** Type of rd_usr_data6 register + * Register 6 of BLOCK3 (user). + */ +typedef union { + struct { + /** reserved_3_192 : R; bitpos: [7:0]; default: 0; + * reserved + */ + uint32_t reserved_3_192:8; + /** custom_mac : R; bitpos: [31:8]; default: 0; + * Custom MAC + */ + uint32_t custom_mac:24; + }; + uint32_t val; +} efuse_rd_usr_data6_reg_t; + +/** Type of rd_usr_data7 register + * Register 7 of BLOCK3 (user). + */ +typedef union { + struct { + /** custom_mac_1 : R; bitpos: [23:0]; default: 0; + * Custom MAC + */ + uint32_t custom_mac_1:24; + /** reserved_3_248 : R; bitpos: [31:24]; default: 0; + * reserved + */ + uint32_t reserved_3_248:8; + }; + uint32_t val; +} efuse_rd_usr_data7_reg_t; + +/** Type of rd_key0_data0 register + * Register 0 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY0. + */ + uint32_t key0_data0:32; + }; + uint32_t val; +} efuse_rd_key0_data0_reg_t; + +/** Type of rd_key0_data1 register + * Register 1 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY0. + */ + uint32_t key0_data1:32; + }; + uint32_t val; +} efuse_rd_key0_data1_reg_t; + +/** Type of rd_key0_data2 register + * Register 2 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY0. + */ + uint32_t key0_data2:32; + }; + uint32_t val; +} efuse_rd_key0_data2_reg_t; + +/** Type of rd_key0_data3 register + * Register 3 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY0. + */ + uint32_t key0_data3:32; + }; + uint32_t val; +} efuse_rd_key0_data3_reg_t; + +/** Type of rd_key0_data4 register + * Register 4 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY0. + */ + uint32_t key0_data4:32; + }; + uint32_t val; +} efuse_rd_key0_data4_reg_t; + +/** Type of rd_key0_data5 register + * Register 5 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY0. + */ + uint32_t key0_data5:32; + }; + uint32_t val; +} efuse_rd_key0_data5_reg_t; + +/** Type of rd_key0_data6 register + * Register 6 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY0. + */ + uint32_t key0_data6:32; + }; + uint32_t val; +} efuse_rd_key0_data6_reg_t; + +/** Type of rd_key0_data7 register + * Register 7 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY0. + */ + uint32_t key0_data7:32; + }; + uint32_t val; +} efuse_rd_key0_data7_reg_t; + +/** Type of rd_key1_data0 register + * Register 0 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY1. + */ + uint32_t key1_data0:32; + }; + uint32_t val; +} efuse_rd_key1_data0_reg_t; + +/** Type of rd_key1_data1 register + * Register 1 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY1. + */ + uint32_t key1_data1:32; + }; + uint32_t val; +} efuse_rd_key1_data1_reg_t; + +/** Type of rd_key1_data2 register + * Register 2 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY1. + */ + uint32_t key1_data2:32; + }; + uint32_t val; +} efuse_rd_key1_data2_reg_t; + +/** Type of rd_key1_data3 register + * Register 3 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY1. + */ + uint32_t key1_data3:32; + }; + uint32_t val; +} efuse_rd_key1_data3_reg_t; + +/** Type of rd_key1_data4 register + * Register 4 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY1. + */ + uint32_t key1_data4:32; + }; + uint32_t val; +} efuse_rd_key1_data4_reg_t; + +/** Type of rd_key1_data5 register + * Register 5 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY1. + */ + uint32_t key1_data5:32; + }; + uint32_t val; +} efuse_rd_key1_data5_reg_t; + +/** Type of rd_key1_data6 register + * Register 6 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY1. + */ + uint32_t key1_data6:32; + }; + uint32_t val; +} efuse_rd_key1_data6_reg_t; + +/** Type of rd_key1_data7 register + * Register 7 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY1. + */ + uint32_t key1_data7:32; + }; + uint32_t val; +} efuse_rd_key1_data7_reg_t; + +/** Type of rd_key2_data0 register + * Register 0 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY2. + */ + uint32_t key2_data0:32; + }; + uint32_t val; +} efuse_rd_key2_data0_reg_t; + +/** Type of rd_key2_data1 register + * Register 1 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY2. + */ + uint32_t key2_data1:32; + }; + uint32_t val; +} efuse_rd_key2_data1_reg_t; + +/** Type of rd_key2_data2 register + * Register 2 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY2. + */ + uint32_t key2_data2:32; + }; + uint32_t val; +} efuse_rd_key2_data2_reg_t; + +/** Type of rd_key2_data3 register + * Register 3 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY2. + */ + uint32_t key2_data3:32; + }; + uint32_t val; +} efuse_rd_key2_data3_reg_t; + +/** Type of rd_key2_data4 register + * Register 4 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY2. + */ + uint32_t key2_data4:32; + }; + uint32_t val; +} efuse_rd_key2_data4_reg_t; + +/** Type of rd_key2_data5 register + * Register 5 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY2. + */ + uint32_t key2_data5:32; + }; + uint32_t val; +} efuse_rd_key2_data5_reg_t; + +/** Type of rd_key2_data6 register + * Register 6 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY2. + */ + uint32_t key2_data6:32; + }; + uint32_t val; +} efuse_rd_key2_data6_reg_t; + +/** Type of rd_key2_data7 register + * Register 7 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY2. + */ + uint32_t key2_data7:32; + }; + uint32_t val; +} efuse_rd_key2_data7_reg_t; + +/** Type of rd_key3_data0 register + * Register 0 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY3. + */ + uint32_t key3_data0:32; + }; + uint32_t val; +} efuse_rd_key3_data0_reg_t; + +/** Type of rd_key3_data1 register + * Register 1 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY3. + */ + uint32_t key3_data1:32; + }; + uint32_t val; +} efuse_rd_key3_data1_reg_t; + +/** Type of rd_key3_data2 register + * Register 2 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY3. + */ + uint32_t key3_data2:32; + }; + uint32_t val; +} efuse_rd_key3_data2_reg_t; + +/** Type of rd_key3_data3 register + * Register 3 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY3. + */ + uint32_t key3_data3:32; + }; + uint32_t val; +} efuse_rd_key3_data3_reg_t; + +/** Type of rd_key3_data4 register + * Register 4 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY3. + */ + uint32_t key3_data4:32; + }; + uint32_t val; +} efuse_rd_key3_data4_reg_t; + +/** Type of rd_key3_data5 register + * Register 5 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY3. + */ + uint32_t key3_data5:32; + }; + uint32_t val; +} efuse_rd_key3_data5_reg_t; + +/** Type of rd_key3_data6 register + * Register 6 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY3. + */ + uint32_t key3_data6:32; + }; + uint32_t val; +} efuse_rd_key3_data6_reg_t; + +/** Type of rd_key3_data7 register + * Register 7 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY3. + */ + uint32_t key3_data7:32; + }; + uint32_t val; +} efuse_rd_key3_data7_reg_t; + +/** Type of rd_key4_data0 register + * Register 0 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY4. + */ + uint32_t key4_data0:32; + }; + uint32_t val; +} efuse_rd_key4_data0_reg_t; + +/** Type of rd_key4_data1 register + * Register 1 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY4. + */ + uint32_t key4_data1:32; + }; + uint32_t val; +} efuse_rd_key4_data1_reg_t; + +/** Type of rd_key4_data2 register + * Register 2 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY4. + */ + uint32_t key4_data2:32; + }; + uint32_t val; +} efuse_rd_key4_data2_reg_t; + +/** Type of rd_key4_data3 register + * Register 3 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY4. + */ + uint32_t key4_data3:32; + }; + uint32_t val; +} efuse_rd_key4_data3_reg_t; + +/** Type of rd_key4_data4 register + * Register 4 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY4. + */ + uint32_t key4_data4:32; + }; + uint32_t val; +} efuse_rd_key4_data4_reg_t; + +/** Type of rd_key4_data5 register + * Register 5 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY4. + */ + uint32_t key4_data5:32; + }; + uint32_t val; +} efuse_rd_key4_data5_reg_t; + +/** Type of rd_key4_data6 register + * Register 6 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY4. + */ + uint32_t key4_data6:32; + }; + uint32_t val; +} efuse_rd_key4_data6_reg_t; + +/** Type of rd_key4_data7 register + * Register 7 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY4. + */ + uint32_t key4_data7:32; + }; + uint32_t val; +} efuse_rd_key4_data7_reg_t; + +/** Type of rd_key5_data0 register + * Register 0 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY5. + */ + uint32_t key5_data0:32; + }; + uint32_t val; +} efuse_rd_key5_data0_reg_t; + +/** Type of rd_key5_data1 register + * Register 1 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY5. + */ + uint32_t key5_data1:32; + }; + uint32_t val; +} efuse_rd_key5_data1_reg_t; + +/** Type of rd_key5_data2 register + * Register 2 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY5. + */ + uint32_t key5_data2:32; + }; + uint32_t val; +} efuse_rd_key5_data2_reg_t; + +/** Type of rd_key5_data3 register + * Register 3 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY5. + */ + uint32_t key5_data3:32; + }; + uint32_t val; +} efuse_rd_key5_data3_reg_t; + +/** Type of rd_key5_data4 register + * Register 4 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY5. + */ + uint32_t key5_data4:32; + }; + uint32_t val; +} efuse_rd_key5_data4_reg_t; + +/** Type of rd_key5_data5 register + * Register 5 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY5. + */ + uint32_t key5_data5:32; + }; + uint32_t val; +} efuse_rd_key5_data5_reg_t; + +/** Type of rd_key5_data6 register + * Register 6 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY5. + */ + uint32_t key5_data6:32; + }; + uint32_t val; +} efuse_rd_key5_data6_reg_t; + +/** Type of rd_key5_data7 register + * Register 7 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY5. + */ + uint32_t key5_data7:32; + }; + uint32_t val; +} efuse_rd_key5_data7_reg_t; + +/** Type of rd_sys_part2_data0 register + * Register 0 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_0:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data0_reg_t; + +/** Type of rd_sys_part2_data1 register + * Register 1 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_1:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data1_reg_t; + +/** Type of rd_sys_part2_data2 register + * Register 2 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_2:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data2_reg_t; + +/** Type of rd_sys_part2_data3 register + * Register 3 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_3:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data3_reg_t; + +/** Type of rd_sys_part2_data4 register + * Register 4 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_4:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data4_reg_t; + +/** Type of rd_sys_part2_data5 register + * Register 5 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_5:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data5_reg_t; + +/** Type of rd_sys_part2_data6 register + * Register 6 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_6:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data6_reg_t; + +/** Type of rd_sys_part2_data7 register + * Register 7 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_7:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data7_reg_t; + + +/** Group: Error Status Registers */ +/** Type of rd_repeat_err0 register + * Programming error record register 0 of BLOCK0. + */ +typedef union { + struct { + /** rd_dis_err : RO; bitpos: [6:0]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_RD_DIS. + */ + uint32_t rd_dis_err:7; + /** dis_rtc_ram_boot_err : RO; bitpos: [7]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_RTC_RAM_BOOT. + */ + uint32_t dis_rtc_ram_boot_err:1; + /** dis_icache_err : RO; bitpos: [8]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_ICACHE. + */ + uint32_t dis_icache_err:1; + /** dis_dcache_err : RO; bitpos: [9]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_DCACHE. + */ + uint32_t dis_dcache_err:1; + /** dis_download_icache_err : RO; bitpos: [10]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_ICACHE. + */ + uint32_t dis_download_icache_err:1; + /** dis_download_dcache_err : RO; bitpos: [11]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_DCACHE. + */ + uint32_t dis_download_dcache_err:1; + /** dis_force_download_err : RO; bitpos: [12]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_FORCE_DOWNLOAD. + */ + uint32_t dis_force_download_err:1; + /** dis_usb_err : RO; bitpos: [13]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_USB. + */ + uint32_t dis_usb_err:1; + /** dis_can_err : RO; bitpos: [14]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_CAN. + */ + uint32_t dis_can_err:1; + /** dis_boot_remap_err : RO; bitpos: [15]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_BOOT_REMAP. + */ + uint32_t dis_boot_remap_err:1; + /** rpt4_reserved5_err : RO; bitpos: [16]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED5. + */ + uint32_t rpt4_reserved5_err:1; + /** soft_dis_jtag_err : RO; bitpos: [17]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_SOFT_DIS_JTAG. + */ + uint32_t soft_dis_jtag_err:1; + /** hard_dis_jtag_err : RO; bitpos: [18]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_HARD_DIS_JTAG. + */ + uint32_t hard_dis_jtag_err:1; + /** dis_download_manual_encrypt_err : RO; bitpos: [19]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT. + */ + uint32_t dis_download_manual_encrypt_err:1; + /** usb_drefh_err : RO; bitpos: [21:20]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_USB_DREFH. + */ + uint32_t usb_drefh_err:2; + /** usb_drefl_err : RO; bitpos: [23:22]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_USB_DREFL. + */ + uint32_t usb_drefl_err:2; + /** usb_exchg_pins_err : RO; bitpos: [24]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_USB_EXCHG_PINS. + */ + uint32_t usb_exchg_pins_err:1; + /** ext_phy_enable_err : RO; bitpos: [25]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_EXT_PHY_ENABLE. + */ + uint32_t ext_phy_enable_err:1; + /** usb_force_nopersist_err : RO; bitpos: [26]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_USB_FORCE_NOPERSIST. + */ + uint32_t usb_force_nopersist_err:1; + /** rpt4_reserved0_err : RO; bitpos: [28:27]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED0. + */ + uint32_t rpt4_reserved0_err:2; + /** vdd_spi_modecurlim_err : RO; bitpos: [29]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_MODECURLIM. + */ + uint32_t vdd_spi_modecurlim_err:1; + /** vdd_spi_drefh_err : RO; bitpos: [31:30]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DREFH. + */ + uint32_t vdd_spi_drefh_err:2; + }; + uint32_t val; +} efuse_rd_repeat_err0_reg_t; + +/** Type of rd_repeat_err1 register + * Programming error record register 1 of BLOCK0. + */ +typedef union { + struct { + /** vdd_spi_drefm_err : RO; bitpos: [1:0]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DREFM. + */ + uint32_t vdd_spi_drefm_err:2; + /** vdd_spi_drefl_err : RO; bitpos: [3:2]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DREFL. + */ + uint32_t vdd_spi_drefl_err:2; + /** vdd_spi_xpd_err : RO; bitpos: [4]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_XPD. + */ + uint32_t vdd_spi_xpd_err:1; + /** vdd_spi_tieh_err : RO; bitpos: [5]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_TIEH. + */ + uint32_t vdd_spi_tieh_err:1; + /** vdd_spi_force_err : RO; bitpos: [6]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_FORCE. + */ + uint32_t vdd_spi_force_err:1; + /** vdd_spi_en_init_err : RO; bitpos: [7]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_EN_INIT. + */ + uint32_t vdd_spi_en_init_err:1; + /** vdd_spi_encurlim_err : RO; bitpos: [8]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_ENCURLIM. + */ + uint32_t vdd_spi_encurlim_err:1; + /** vdd_spi_dcurlim_err : RO; bitpos: [11:9]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DCURLIM. + */ + uint32_t vdd_spi_dcurlim_err:3; + /** vdd_spi_init_err : RO; bitpos: [13:12]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_INIT. + */ + uint32_t vdd_spi_init_err:2; + /** vdd_spi_dcap_err : RO; bitpos: [15:14]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DCAP. + */ + uint32_t vdd_spi_dcap_err:2; + /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_WDT_DELAY_SEL. + */ + uint32_t wdt_delay_sel_err:2; + /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_SPI_BOOT_CRYPT_CNT. + */ + uint32_t spi_boot_crypt_cnt_err:3; + /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_KEY_REVOKE0. + */ + uint32_t secure_boot_key_revoke0_err:1; + /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_KEY_REVOKE1. + */ + uint32_t secure_boot_key_revoke1_err:1; + /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_KEY_REVOKE2. + */ + uint32_t secure_boot_key_revoke2_err:1; + /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_0. + */ + uint32_t key_purpose_0_err:4; + /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_1. + */ + uint32_t key_purpose_1_err:4; + }; + uint32_t val; +} efuse_rd_repeat_err1_reg_t; + +/** Type of rd_repeat_err2 register + * Programming error record register 2 of BLOCK0. + */ +typedef union { + struct { + /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_2. + */ + uint32_t key_purpose_2_err:4; + /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_3. + */ + uint32_t key_purpose_3_err:4; + /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_4. + */ + uint32_t key_purpose_4_err:4; + /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_5. + */ + uint32_t key_purpose_5_err:4; + /** key_purpose_6_err : RO; bitpos: [19:16]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_6. + */ + uint32_t key_purpose_6_err:4; + /** secure_boot_en_err : RO; bitpos: [20]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_EN. + */ + uint32_t secure_boot_en_err:1; + /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0; + * Any bit equal to 1 denotes a programming error in + * EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE. + */ + uint32_t secure_boot_aggressive_revoke_err:1; + /** rpt4_reserved1_err : RO; bitpos: [27:22]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED1. + */ + uint32_t rpt4_reserved1_err:6; + /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_FLASH_TPUW. + */ + uint32_t flash_tpuw_err:4; + }; + uint32_t val; +} efuse_rd_repeat_err2_reg_t; + +/** Type of rd_repeat_err3 register + * Programming error record register 3 of BLOCK0. + */ +typedef union { + struct { + /** dis_download_mode_err : RO; bitpos: [0]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_MODE. + */ + uint32_t dis_download_mode_err:1; + /** dis_legacy_spi_boot_err : RO; bitpos: [1]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_LEGACY_SPI_BOOT. + */ + uint32_t dis_legacy_spi_boot_err:1; + /** uart_print_channel_err : RO; bitpos: [2]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_UART_PRINT_CHANNEL. + */ + uint32_t uart_print_channel_err:1; + /** rpt4_reserved3_err : RO; bitpos: [3]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED3. + */ + uint32_t rpt4_reserved3_err:1; + /** dis_usb_download_mode_err : RO; bitpos: [4]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_USB_DOWNLOAD_MODE. + */ + uint32_t dis_usb_download_mode_err:1; + /** enable_security_download_err : RO; bitpos: [5]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_ENABLE_SECURITY_DOWNLOAD. + */ + uint32_t enable_security_download_err:1; + /** uart_print_control_err : RO; bitpos: [7:6]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_UART_PRINT_CONTROL. + */ + uint32_t uart_print_control_err:2; + /** pin_power_selection_err : RO; bitpos: [8]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_PIN_POWER_SELECTION. + */ + uint32_t pin_power_selection_err:1; + /** flash_type_err : RO; bitpos: [9]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_FLASH_TYPE. + */ + uint32_t flash_type_err:1; + /** force_send_resume_err : RO; bitpos: [10]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_FORCE_SEND_RESUME. + */ + uint32_t force_send_resume_err:1; + /** secure_version_err : RO; bitpos: [26:11]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_SECURE_VERSION. + */ + uint32_t secure_version_err:16; + /** rpt4_reserved2_err : RO; bitpos: [31:27]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED2. + */ + uint32_t rpt4_reserved2_err:5; + }; + uint32_t val; +} efuse_rd_repeat_err3_reg_t; + +/** Type of rd_repeat_err4 register + * Programming error record register 4 of BLOCK0. + */ +typedef union { + struct { + /** rpt4_reserved4_err : RO; bitpos: [23:0]; default: 0; + * If any bit in RPT4_RESERVED4 is 1, there is a programming error in + * EFUSE_RPT4_RESERVED4. + */ + uint32_t rpt4_reserved4_err:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} efuse_rd_repeat_err4_reg_t; + +/** Type of rd_rs_err0 register + * Programming error record register 0 of BLOCK1-10. + */ +typedef union { + struct { + /** mac_spi_8m_err_num : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes in BLOCK1. + */ + uint32_t mac_spi_8m_err_num:3; + /** mac_spi_8m_fail : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of BLOCK1 is reliable. 1: Means that + * programming BLOCK1 data failed and the number of error bytes is over 5. + */ + uint32_t mac_spi_8m_fail:1; + /** sys_part1_num : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes in BLOCK2. + */ + uint32_t sys_part1_num:3; + /** sys_part1_fail : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of BLOCK2 is reliable. 1: Means that + * programming BLOCK2 data failed and the number of error bytes is over 5. + */ + uint32_t sys_part1_fail:1; + /** usr_data_err_num : RO; bitpos: [10:8]; default: 0; + * The value of this signal means the number of error bytes in BLOCK3. + */ + uint32_t usr_data_err_num:3; + /** usr_data_fail : RO; bitpos: [11]; default: 0; + * 0: Means no failure and that the data of BLOCK3 is reliable. 1: Means that + * programming BLOCK3 data failed and the number of error bytes is over 5. + */ + uint32_t usr_data_fail:1; + /** key0_err_num : RO; bitpos: [14:12]; default: 0; + * The value of this signal means the number of error bytes in KEY0. + */ + uint32_t key0_err_num:3; + /** key0_fail : RO; bitpos: [15]; default: 0; + * 0: Means no failure and that the data of KEY0 is reliable. 1: Means that + * programming KEY0 failed and the number of error bytes is over 5. + */ + uint32_t key0_fail:1; + /** key1_err_num : RO; bitpos: [18:16]; default: 0; + * The value of this signal means the number of error bytes in KEY1. + */ + uint32_t key1_err_num:3; + /** key1_fail : RO; bitpos: [19]; default: 0; + * 0: Means no failure and that the data of KEY1 is reliable. 1: Means that + * programming KEY1 failed and the number of error bytes is over 5. + */ + uint32_t key1_fail:1; + /** key2_err_num : RO; bitpos: [22:20]; default: 0; + * The value of this signal means the number of error bytes in KEY2. + */ + uint32_t key2_err_num:3; + /** key2_fail : RO; bitpos: [23]; default: 0; + * 0: Means no failure and that the data of KEY2 is reliable. 1: Means that + * programming KEY2 failed and the number of error bytes is over 5. + */ + uint32_t key2_fail:1; + /** key3_err_num : RO; bitpos: [26:24]; default: 0; + * The value of this signal means the number of error bytes in KEY3. + */ + uint32_t key3_err_num:3; + /** key3_fail : RO; bitpos: [27]; default: 0; + * 0: Means no failure and that the data of KEY3 is reliable. 1: Means that + * programming KEY3 failed and the number of error bytes is over 5. + */ + uint32_t key3_fail:1; + /** key4_err_num : RO; bitpos: [30:28]; default: 0; + * The value of this signal means the number of error bytes in KEY4. + */ + uint32_t key4_err_num:3; + /** key4_fail : RO; bitpos: [31]; default: 0; + * 0: Means no failure and that the data of KEY4 is reliable. 1: Means that + * programming KEY4 failed and the number of error bytes is over 5. + */ + uint32_t key4_fail:1; + }; + uint32_t val; +} efuse_rd_rs_err0_reg_t; + +/** Type of rd_rs_err1 register + * Programming error record register 1 of BLOCK1-10. + */ +typedef union { + struct { + /** key5_err_num : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes in KEY5. + */ + uint32_t key5_err_num:3; + /** key5_fail : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of KEY5 is reliable. 1: Means that + * programming user data failed and the number of error bytes is over 5. + */ + uint32_t key5_fail:1; + /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes in BLOCK10. + */ + uint32_t sys_part2_err_num:3; + /** sys_part2_fail : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of BLOCK10 is reliable. 1: Means that + * programming BLOCK10 data failed and the number of error bytes is over 5. + */ + uint32_t sys_part2_fail:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} efuse_rd_rs_err1_reg_t; + + +/** Group: Control/Status Registers */ +/** Type of clk register + * eFuse clock configuration register. + */ +typedef union { + struct { + /** efuse_mem_force_pd : R/W; bitpos: [0]; default: 0; + * If set, forces eFuse SRAM into power-saving mode. + */ + uint32_t efuse_mem_force_pd:1; + /** mem_clk_force_on : R/W; bitpos: [1]; default: 1; + * If set, forces to activate clock signal of eFuse SRAM. + */ + uint32_t mem_clk_force_on:1; + /** efuse_mem_force_pu : R/W; bitpos: [2]; default: 0; + * If set, forces eFuse SRAM into working mode. + */ + uint32_t efuse_mem_force_pu:1; + uint32_t reserved_3:13; + /** clk_en : R/W; bitpos: [16]; default: 0; + * If set, forces to enable clock signal of eFuse memory. + */ + uint32_t clk_en:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} efuse_clk_reg_t; + +/** Type of conf register + * eFuse operation mode configuration register. + */ +typedef union { + struct { + /** op_code : R/W; bitpos: [15:0]; default: 0; + * 0x5A5A: Operate programming command. 0x5AA5: Operate read command. + */ + uint32_t op_code:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} efuse_conf_reg_t; + +/** Type of status register + * eFuse status register. + */ +typedef union { + struct { + /** state : RO; bitpos: [3:0]; default: 0; + * Indicates the state of the eFuse state machine. + */ + uint32_t state:4; + /** otp_load_sw : RO; bitpos: [4]; default: 0; + * The value of OTP_LOAD_SW. + */ + uint32_t otp_load_sw:1; + /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0; + * The value of OTP_VDDQ_C_SYNC2. + */ + uint32_t otp_vddq_c_sync2:1; + /** otp_strobe_sw : RO; bitpos: [6]; default: 0; + * The value of OTP_STROBE_SW. + */ + uint32_t otp_strobe_sw:1; + /** otp_csb_sw : RO; bitpos: [7]; default: 0; + * The value of OTP_CSB_SW. + */ + uint32_t otp_csb_sw:1; + /** otp_pgenb_sw : RO; bitpos: [8]; default: 0; + * The value of OTP_PGENB_SW. + */ + uint32_t otp_pgenb_sw:1; + /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0; + * The value of OTP_VDDQ_IS_SW. + */ + uint32_t otp_vddq_is_sw:1; + /** repeat_err_cnt : RO; bitpos: [17:10]; default: 0; + * Indicates the number of error bits during programming BLOCK0. + */ + uint32_t repeat_err_cnt:8; + uint32_t reserved_18:14; + }; + uint32_t val; +} efuse_status_reg_t; + +/** Type of cmd register + * eFuse command register. + */ +typedef union { + struct { + /** read_cmd : R/W; bitpos: [0]; default: 0; + * Set this bit to send read command. + */ + uint32_t read_cmd:1; + /** pgm_cmd : R/W; bitpos: [1]; default: 0; + * Set this bit to send programming command. + */ + uint32_t pgm_cmd:1; + /** blk_num : R/W; bitpos: [5:2]; default: 0; + * The serial number of the block to be programmed. Value 0-10 corresponds to block + * number 0-10, respectively. + */ + uint32_t blk_num:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} efuse_cmd_reg_t; + +/** Type of dac_conf register + * Controls the eFuse programming voltage. + */ +typedef union { + struct { + /** dac_clk_div : R/W; bitpos: [7:0]; default: 28; + * Controls the division factor of the rising clock of the programming voltage. + */ + uint32_t dac_clk_div:8; + /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; + * Don't care. + */ + uint32_t dac_clk_pad_sel:1; + /** dac_num : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ + uint32_t dac_num:8; + /** oe_clr : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ + uint32_t oe_clr:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} efuse_dac_conf_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of int_raw register + * eFuse raw interrupt register. + */ +typedef union { + struct { + /** read_done_int_raw : RO; bitpos: [0]; default: 0; + * The raw bit signal for read_done interrupt. + */ + uint32_t read_done_int_raw:1; + /** pgm_done_int_raw : RO; bitpos: [1]; default: 0; + * The raw bit signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_raw_reg_t; + +/** Type of int_st register + * eFuse interrupt status register. + */ +typedef union { + struct { + /** read_done_int_st : RO; bitpos: [0]; default: 0; + * The status signal for read_done interrupt. + */ + uint32_t read_done_int_st:1; + /** pgm_done_int_st : RO; bitpos: [1]; default: 0; + * The status signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_st:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_st_reg_t; + +/** Type of int_ena register + * eFuse interrupt enable register. + */ +typedef union { + struct { + /** read_done_int_ena : R/W; bitpos: [0]; default: 0; + * The enable signal for read_done interrupt. + */ + uint32_t read_done_int_ena:1; + /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0; + * The enable signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_ena_reg_t; + +/** Type of int_clr register + * eFuse interrupt clear register. + */ +typedef union { + struct { + /** read_done_int_clr : WO; bitpos: [0]; default: 0; + * The clear signal for read_done interrupt. + */ + uint32_t read_done_int_clr:1; + /** pgm_done_int_clr : WO; bitpos: [1]; default: 0; + * The clear signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_clr_reg_t; + + +/** Group: Configuration Registers */ +/** Type of rd_tim_conf register + * Configures read timing parameters. + */ +typedef union { + struct { + /** thr_a : R/W; bitpos: [7:0]; default: 1; + * Configures the hold time of read operation. + */ + uint32_t thr_a:8; + /** trd : R/W; bitpos: [15:8]; default: 1; + * Configures the length of pulse of read operation. + */ + uint32_t trd:8; + /** tsur_a : R/W; bitpos: [23:16]; default: 1; + * Configures the setup time of read operation. + */ + uint32_t tsur_a:8; + /** read_init_num : R/W; bitpos: [31:24]; default: 18; + * Configures the initial read time of eFuse. + */ + uint32_t read_init_num:8; + }; + uint32_t val; +} efuse_rd_tim_conf_reg_t; + +/** Type of wr_tim_conf0 register + * Configuration register 0 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** thp_a : R/W; bitpos: [7:0]; default: 1; + * Configures the hold time of programming operation. + */ + uint32_t thp_a:8; + /** tpgm_inactive : R/W; bitpos: [15:8]; default: 1; + * Configures the length of pulse during programming 0 to eFuse. + */ + uint32_t tpgm_inactive:8; + /** tpgm : R/W; bitpos: [31:16]; default: 200; + * Configures the length of pulse during programming 1 to eFuse. + */ + uint32_t tpgm:16; + }; + uint32_t val; +} efuse_wr_tim_conf0_reg_t; + +/** Type of wr_tim_conf1 register + * Configuration register 1 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** tsup_a : R/W; bitpos: [7:0]; default: 1; + * Configures the setup time of programming operation. + */ + uint32_t tsup_a:8; + /** pwr_on_num : R/W; bitpos: [23:8]; default: 10368; + * Configures the power up time for VDDQ. + */ + uint32_t pwr_on_num:16; + uint32_t reserved_24:8; + }; + uint32_t val; +} efuse_wr_tim_conf1_reg_t; + +/** Type of wr_tim_conf2 register + * Configuration register 2 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** pwr_off_num : R/W; bitpos: [15:0]; default: 400; + * Configures the power outage time for VDDQ. + */ + uint32_t pwr_off_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} efuse_wr_tim_conf2_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Version control register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 419959040; + * Version control register. + */ + uint32_t date:32; + }; + uint32_t val; +} efuse_date_reg_t; + + +typedef struct { + volatile efuse_pgm_data0_reg_t pgm_data0; + volatile efuse_pgm_data1_reg_t pgm_data1; + volatile efuse_pgm_data2_reg_t pgm_data2; + volatile efuse_pgm_data3_reg_t pgm_data3; + volatile efuse_pgm_data4_reg_t pgm_data4; + volatile efuse_pgm_data5_reg_t pgm_data5; + volatile efuse_pgm_data6_reg_t pgm_data6; + volatile efuse_pgm_data7_reg_t pgm_data7; + volatile efuse_pgm_check_value0_reg_t pgm_check_value0; + volatile efuse_pgm_check_value1_reg_t pgm_check_value1; + volatile efuse_pgm_check_value2_reg_t pgm_check_value2; + volatile efuse_rd_wr_dis_reg_t rd_wr_dis; + volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; + volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1; + volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2; + volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3; + volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4; + volatile efuse_rd_mac_spi_sys_0_reg_t rd_mac_spi_sys_0; + volatile efuse_rd_mac_spi_sys_1_reg_t rd_mac_spi_sys_1; + volatile efuse_rd_mac_spi_sys_2_reg_t rd_mac_spi_sys_2; + volatile efuse_rd_mac_spi_sys_3_reg_t rd_mac_spi_sys_3; + volatile efuse_rd_mac_spi_sys_4_reg_t rd_mac_spi_sys_4; + volatile efuse_rd_mac_spi_sys_5_reg_t rd_mac_spi_sys_5; + volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0; + volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1; + volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2; + volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3; + volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4; + volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5; + volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6; + volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7; + volatile efuse_rd_usr_data0_reg_t rd_usr_data0; + volatile efuse_rd_usr_data1_reg_t rd_usr_data1; + volatile efuse_rd_usr_data2_reg_t rd_usr_data2; + volatile efuse_rd_usr_data3_reg_t rd_usr_data3; + volatile efuse_rd_usr_data4_reg_t rd_usr_data4; + volatile efuse_rd_usr_data5_reg_t rd_usr_data5; + volatile efuse_rd_usr_data6_reg_t rd_usr_data6; + volatile efuse_rd_usr_data7_reg_t rd_usr_data7; + volatile efuse_rd_key0_data0_reg_t rd_key0_data0; + volatile efuse_rd_key0_data1_reg_t rd_key0_data1; + volatile efuse_rd_key0_data2_reg_t rd_key0_data2; + volatile efuse_rd_key0_data3_reg_t rd_key0_data3; + volatile efuse_rd_key0_data4_reg_t rd_key0_data4; + volatile efuse_rd_key0_data5_reg_t rd_key0_data5; + volatile efuse_rd_key0_data6_reg_t rd_key0_data6; + volatile efuse_rd_key0_data7_reg_t rd_key0_data7; + volatile efuse_rd_key1_data0_reg_t rd_key1_data0; + volatile efuse_rd_key1_data1_reg_t rd_key1_data1; + volatile efuse_rd_key1_data2_reg_t rd_key1_data2; + volatile efuse_rd_key1_data3_reg_t rd_key1_data3; + volatile efuse_rd_key1_data4_reg_t rd_key1_data4; + volatile efuse_rd_key1_data5_reg_t rd_key1_data5; + volatile efuse_rd_key1_data6_reg_t rd_key1_data6; + volatile efuse_rd_key1_data7_reg_t rd_key1_data7; + volatile efuse_rd_key2_data0_reg_t rd_key2_data0; + volatile efuse_rd_key2_data1_reg_t rd_key2_data1; + volatile efuse_rd_key2_data2_reg_t rd_key2_data2; + volatile efuse_rd_key2_data3_reg_t rd_key2_data3; + volatile efuse_rd_key2_data4_reg_t rd_key2_data4; + volatile efuse_rd_key2_data5_reg_t rd_key2_data5; + volatile efuse_rd_key2_data6_reg_t rd_key2_data6; + volatile efuse_rd_key2_data7_reg_t rd_key2_data7; + volatile efuse_rd_key3_data0_reg_t rd_key3_data0; + volatile efuse_rd_key3_data1_reg_t rd_key3_data1; + volatile efuse_rd_key3_data2_reg_t rd_key3_data2; + volatile efuse_rd_key3_data3_reg_t rd_key3_data3; + volatile efuse_rd_key3_data4_reg_t rd_key3_data4; + volatile efuse_rd_key3_data5_reg_t rd_key3_data5; + volatile efuse_rd_key3_data6_reg_t rd_key3_data6; + volatile efuse_rd_key3_data7_reg_t rd_key3_data7; + volatile efuse_rd_key4_data0_reg_t rd_key4_data0; + volatile efuse_rd_key4_data1_reg_t rd_key4_data1; + volatile efuse_rd_key4_data2_reg_t rd_key4_data2; + volatile efuse_rd_key4_data3_reg_t rd_key4_data3; + volatile efuse_rd_key4_data4_reg_t rd_key4_data4; + volatile efuse_rd_key4_data5_reg_t rd_key4_data5; + volatile efuse_rd_key4_data6_reg_t rd_key4_data6; + volatile efuse_rd_key4_data7_reg_t rd_key4_data7; + volatile efuse_rd_key5_data0_reg_t rd_key5_data0; + volatile efuse_rd_key5_data1_reg_t rd_key5_data1; + volatile efuse_rd_key5_data2_reg_t rd_key5_data2; + volatile efuse_rd_key5_data3_reg_t rd_key5_data3; + volatile efuse_rd_key5_data4_reg_t rd_key5_data4; + volatile efuse_rd_key5_data5_reg_t rd_key5_data5; + volatile efuse_rd_key5_data6_reg_t rd_key5_data6; + volatile efuse_rd_key5_data7_reg_t rd_key5_data7; + volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0; + volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1; + volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2; + volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3; + volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4; + volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5; + volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6; + volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7; + volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0; + volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1; + volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2; + volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3; + uint32_t reserved_18c; + volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4; + uint32_t reserved_194[11]; + volatile efuse_rd_rs_err0_reg_t rd_rs_err0; + volatile efuse_rd_rs_err1_reg_t rd_rs_err1; + volatile efuse_clk_reg_t clk; + volatile efuse_conf_reg_t conf; + volatile efuse_status_reg_t status; + volatile efuse_cmd_reg_t cmd; + volatile efuse_int_raw_reg_t int_raw; + volatile efuse_int_st_reg_t int_st; + volatile efuse_int_ena_reg_t int_ena; + volatile efuse_int_clr_reg_t int_clr; + volatile efuse_dac_conf_reg_t dac_conf; + volatile efuse_rd_tim_conf_reg_t rd_tim_conf; + volatile efuse_wr_tim_conf0_reg_t wr_tim_conf0; + volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1; + volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2; + volatile efuse_date_reg_t date; } efuse_dev_t; + extern efuse_dev_t EFUSE; + +#ifndef __cplusplus +_Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure"); +#endif + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32s2/include/soc/esp32s2/include/soc/soc_caps.h b/tools/sdk/esp32s2/include/soc/esp32s2/include/soc/soc_caps.h index 2a74a93803d..94e210a282e 100644 --- a/tools/sdk/esp32s2/include/soc/esp32s2/include/soc/soc_caps.h +++ b/tools/sdk/esp32s2/include/soc/esp32s2/include/soc/soc_caps.h @@ -375,6 +375,7 @@ #define SOC_EFUSE_SOFT_DIS_JTAG 1 #define SOC_EFUSE_DIS_BOOT_REMAP 1 #define SOC_EFUSE_DIS_LEGACY_SPI_BOOT 1 +#define SOC_EFUSE_DIS_ICACHE 1 /*-------------------------- Secure Boot CAPS----------------------------*/ #define SOC_SECURE_BOOT_V2_RSA 1 diff --git a/tools/sdk/esp32s2/include/soc/esp32s2/include/soc/usb_reg.h b/tools/sdk/esp32s2/include/soc/esp32s2/include/soc/usb_reg.h index 361144e0c1c..8a965288a70 100644 --- a/tools/sdk/esp32s2/include/soc/esp32s2/include/soc/usb_reg.h +++ b/tools/sdk/esp32s2/include/soc/esp32s2/include/soc/usb_reg.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -1491,6 +1483,17 @@ extern "C" { #define USB_NZSTSOUTHSHK_M (USB_NZSTSOUTHSHK_V << USB_NZSTSOUTHSHK_S) #define USB_NZSTSOUTHSHK_V 0x00000001 #define USB_NZSTSOUTHSHK_S 2 +/** USB_ENA32KHZSUSP : R/W; bitpos: [3]; default: 0; + * This bit can be set only if FS PHY interface is selected. + * Otherwise, this bit needs to be set to zero. + * 1'b0: USB 1.1 Full-Speed Serial transiver not selected + * 1'b1: If FS PHY interface is choosen and this bit is set, the PHY clock during Suspend + * must be switched from 48 MHz to 32 KHz + */ +#define USB_ENA32KHZSUSP (BIT(3)) +#define USB_ENA32KHZSUSP_M (USB_ENA32KHZSUSP_V << USB_ENA32KHZSUSP_S) +#define USB_ENA32KHZSUSP_V 0x00000001 +#define USB_ENA32KHZSUSP_S 3 /** USB_DEVADDR : R/W; bitpos: [11:4]; default: 0; * Device Address. */ diff --git a/tools/sdk/esp32s2/include/spi_flash/include/esp_spi_flash_counters.h b/tools/sdk/esp32s2/include/spi_flash/include/esp_spi_flash_counters.h index ab8157c256d..3355ee16bc2 100644 --- a/tools/sdk/esp32s2/include/spi_flash/include/esp_spi_flash_counters.h +++ b/tools/sdk/esp32s2/include/spi_flash/include/esp_spi_flash_counters.h @@ -1,16 +1,8 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -32,31 +24,38 @@ typedef struct { uint32_t count; // number of times operation was executed uint32_t time; // total time taken, in microseconds uint32_t bytes; // total number of bytes -} spi_flash_counter_t; +} esp_flash_counter_t; typedef struct { - spi_flash_counter_t read; - spi_flash_counter_t write; - spi_flash_counter_t erase; -} spi_flash_counters_t; + esp_flash_counter_t read; + esp_flash_counter_t write; + esp_flash_counter_t erase; +} esp_flash_counters_t; + +// for deprecate old api +typedef esp_flash_counter_t spi_flash_counter_t; +typedef esp_flash_counters_t spi_flash_counters_t; /** * @brief Reset SPI flash operation counters */ -void spi_flash_reset_counters(void); +void esp_flash_reset_counters(void); +void spi_flash_reset_counters(void) __attribute__((deprecated("Please use 'esp_flash_reset_counters' instead"))); /** * @brief Print SPI flash operation counters */ -void spi_flash_dump_counters(void); +void esp_flash_dump_counters(FILE* stream); +void spi_flash_dump_counters(void) __attribute__((deprecated("Please use 'esp_flash_dump_counters' instead"))); /** * @brief Return current SPI flash operation counters * - * @return pointer to the spi_flash_counters_t structure holding values + * @return pointer to the esp_flash_counters_t structure holding values * of the operation counters */ -const spi_flash_counters_t* spi_flash_get_counters(void); +const esp_flash_counters_t* esp_flash_get_counters(void); +const spi_flash_counters_t* spi_flash_get_counters(void) __attribute__((deprecated("Please use 'esp_flash_get_counters' instead"))); #ifdef __cplusplus } diff --git a/tools/sdk/esp32s2/include/tcp_transport/include/esp_transport_socks_proxy.h b/tools/sdk/esp32s2/include/tcp_transport/include/esp_transport_socks_proxy.h new file mode 100644 index 00000000000..566ed9a6de6 --- /dev/null +++ b/tools/sdk/esp32s2/include/tcp_transport/include/esp_transport_socks_proxy.h @@ -0,0 +1,61 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "esp_transport.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum socks_version_t {SOCKS4 = 4} socks_version_t; + +typedef enum socks_transport_response_t { + // The following values correspond to transport operation + SOCKS_RESPONSE_TARGET_NOT_FOUND = 0xF0, + SOCKS_RESPONSE_PROXY_UNREACHABLE = 0xF1, + SOCKS_TIMEOUT = 0xF2, + // The following values are defined by the SOCKS4 protocol + SOCKS_RESPONSE_SUCCESS = 0x5a, + SOCKS_RESPONSE_REQUEST_REJECTED = 0x5B, + SOCKS_RESPONSE_NOT_RUNNING_IDENTD = 0x5c, + SOCKS_RESPONSE_COULD_NOT_CONFIRM_ID = 0x5d, +} socks_transport_error_t; + +/* + * Socks configuration structure + */ +typedef struct esp_transport_socks_proxy_config_t { + const socks_version_t version; /*!< Socks protocol version.*/ + const char *address;/*!< Proxy address*/ + const int port; /*< Proxy port*/ +} esp_transport_socks_proxy_config_t; + +/** +* @brief Create a proxy transport +* @param parent_handle Handle for the parent transport +* @param config Pointer to the configuration structure to use +* +* @return +* - transport Handler for the created transport. +* - NULL in case of failure +*/ +esp_transport_handle_t esp_transport_socks_proxy_init(esp_transport_handle_t parent_handle, const esp_transport_socks_proxy_config_t *config); + +/** +* @brief Changes the configuration of the proxy +* @param socks_transport Handle for the transport +* @param config Pointer to the configuration structure to use +* +* @return +* - ESP_OK on success +*/ +esp_err_t esp_transport_socks_proxy_set_config(esp_transport_handle_t socks_transport, const esp_transport_socks_proxy_config_t *config); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/ld/sections.ld b/tools/sdk/esp32s2/ld/sections.ld index 7febdb9fd22..de4fdf74bbd 100644 --- a/tools/sdk/esp32s2/ld/sections.ld +++ b/tools/sdk/esp32s2/ld/sections.ld @@ -1,6 +1,6 @@ /* Automatically generated file; DO NOT EDIT */ /* Espressif IoT Development Framework Linker Script */ -/* Generated from: /Users/ficeto/Desktop/ESP32/ESP-IDF-5/esp32-arduino-lib-builder/esp-idf/components/esp_system/ld/esp32s2/sections.ld.in */ +/* Generated from: /home/runner/work/esp32-arduino-lib-builder/esp32-arduino-lib-builder/esp-idf/components/esp_system/ld/esp32s2/sections.ld.in */ /* * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD @@ -602,7 +602,7 @@ SECTIONS *libesp_system.a:esp_system_chip.*(.literal.esp_get_free_heap_size .literal.esp_get_free_internal_heap_size .literal.esp_get_idf_version .literal.esp_get_minimum_free_heap_size .text .text.esp_get_free_heap_size .text.esp_get_free_internal_heap_size .text.esp_get_idf_version .text.esp_get_minimum_free_heap_size) *libfreertos.a:app_startup.*(.literal .literal.* .text .text.*) *libheap.a:multi_heap.*(.literal.multi_heap_check .literal.multi_heap_dump .literal.multi_heap_dump_tlsf .literal.multi_heap_get_info_impl .literal.multi_heap_register_impl .literal.tlsf_check_hook .text .text.multi_heap_check .text.multi_heap_dump .text.multi_heap_dump_tlsf .text.multi_heap_free_size_impl .text.multi_heap_get_info_impl .text.multi_heap_get_info_tlsf .text.multi_heap_minimum_free_size_impl .text.multi_heap_register_impl .text.tlsf_check_hook) - *libheap.a:multi_heap_poisoning.*(.literal.multi_heap_free_size .literal.multi_heap_get_info .literal.multi_heap_minimum_free_size .literal.multi_heap_register .text .text.multi_heap_free_size .text.multi_heap_get_info .text.multi_heap_minimum_free_size .text.multi_heap_register .text.subtract_poison_overhead) + *libheap.a:multi_heap_poisoning.*(.literal.multi_heap_free_size .literal.multi_heap_get_info .literal.multi_heap_minimum_free_size .literal.multi_heap_register .text .text.multi_heap_free_size .text.multi_heap_get_info .text.multi_heap_minimum_free_size .text.multi_heap_register) *libheap.a:tlsf.*(.literal.default_walker .literal.tlsf_add_pool .literal.tlsf_check .literal.tlsf_check_pool .literal.tlsf_create .literal.tlsf_create_with_pool .literal.tlsf_remove_pool .literal.tlsf_walk_pool .text .text.default_walker .text.integrity_walker .text.tlsf_add_pool .text.tlsf_check .text.tlsf_check_pool .text.tlsf_create .text.tlsf_create_with_pool .text.tlsf_destroy .text.tlsf_fit_size .text.tlsf_pool_overhead .text.tlsf_remove_pool .text.tlsf_walk_pool) *liblog.a:log.*(.literal.esp_log_level_get .literal.esp_log_level_set .literal.esp_log_set_vprintf .literal.esp_log_writev .literal.heap_bubble_down .literal.s_log_level_get_and_unlock .text .text.esp_log_level_get .text.esp_log_level_set .text.esp_log_set_vprintf .text.esp_log_writev .text.heap_bubble_down .text.s_log_level_get_and_unlock) *liblog.a:log_freertos.*(.literal.esp_log_system_timestamp .text .text.esp_log_system_timestamp) diff --git a/tools/sdk/esp32s2/lib/libapp_trace.a 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542eca02852..16ce797b49c 100644 --- a/tools/sdk/esp32s2/platformio-build.py +++ b/tools/sdk/esp32s2/platformio-build.py @@ -106,6 +106,7 @@ "-u", "pthread_include_pthread_cond_impl", "-u", "pthread_include_pthread_local_storage_impl", "-u", "pthread_include_pthread_rwlock_impl", + "-u", "pthread_include_pthread_semaphore_impl", "-u", "ld_include_highint_hdl", "-u", "start_app", "-u", "__ubsan_include", @@ -127,6 +128,7 @@ join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "freertos", "FreeRTOS-Kernel", "portable", "xtensa", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "freertos", "esp_additions", "include", "freertos"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "freertos", "esp_additions", "include"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "freertos", "esp_additions", "arch", "xtensa", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "esp_hw_support", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "esp_hw_support", "include", "soc"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "esp_hw_support", "include", "soc", "esp32s2"), @@ -231,6 +233,7 @@ join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "esp_http_server", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "esp_https_ota", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "esp_https_server", "include"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "esp_psram", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "esp_lcd", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "esp_lcd", "interface"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "protobuf-c", "protobuf-c"), @@ -238,7 +241,6 @@ join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "protocomm", "include", "security"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "protocomm", "include", "transports"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "esp_local_ctrl", "include"), - join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "esp_psram", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "espcoredump", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "espcoredump", "include", "port", "xtensa"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "wear_levelling", "include"), @@ -285,9 +287,6 @@ join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "esp-dl", "include", "layer"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "esp-dl", "include", "detect"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "esp-dl", "include", "model_zoo"), - join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "esp-sr", "esp-tts", "esp_tts_chinese", "include"), - join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "esp32-camera", "driver", "include"), - join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "esp32-camera", "conversions", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "espressif__esp-dsp", "modules", "dotprod", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "espressif__esp-dsp", "modules", "support", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "espressif__esp-dsp", "modules", "windows", "include"), @@ -313,6 +312,9 @@ join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "espressif__esp-dsp", "modules", "common", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "espressif__esp-dsp", "modules", "kalman", "ekf", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "espressif__esp-dsp", "modules", "kalman", "ekf_imu13states", "include"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "esp-sr", "esp-tts", "esp_tts_chinese", "include"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "esp32-camera", "driver", "include"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "esp32-camera", "conversions", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "fb_gfx", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", env.BoardConfig().get("build.arduino.memory_type", (env.BoardConfig().get("build.flash_mode", "dio") + "_qspi")), "include"), join(FRAMEWORK_DIR, "cores", env.BoardConfig().get("build.core")) @@ -325,12 +327,12 @@ ], LIBS=[ - "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lapp_trace", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lunity", "-lcmock", "-lconsole", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-lesp_hid", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_https_server", "-lesp_lcd", "-lprotobuf-c", "-lprotocomm", "-lesp_local_ctrl", "-lesp_psram", "-lespcoredump", "-lwear_levelling", "-lsdmmc", "-lfatfs", "-ljson", "-lmqtt", "-lperfmon", "-lspiffs", "-ltouch_element", "-lulp", "-lusb", "-lwifi_provisioning", "-lespressif__mdns", "-lcbor", "-lrmaker_common", "-lesp_diagnostics", "-lrtc_store", "-lesp_insights", "-ljson_parser", "-ljson_generator", "-lesp_schedule", "-lespressif__esp_secure_cert_mgr", "-lesp_rainmaker", "-lgpio_button", "-lqrcode", "-lws2812_led", "-larduino_tinyusb", "-lesp32-camera", "-lesp_littlefs", "-lespressif__esp-dsp", "-lfb_gfx", "-lapp_trace", "-lapp_trace", "-lcmock", "-lunity", "-lesp_lcd", "-lperfmon", "-ltouch_element", "-lusb", "-lesp_hid", "-lfatfs", "-lwear_levelling", "-lsdmmc", "-lesp_insights", "-lcbor", "-lesp_diagnostics", "-lrtc_store", "-lesp_rainmaker", "-lesp_local_ctrl", "-lesp_https_server", "-lwifi_provisioning", "-lprotocomm", "-lprotobuf-c", "-ljson", "-lespressif__mdns", "-ljson_parser", "-ljson_generator", "-lesp_schedule", "-lespressif__esp_secure_cert_mgr", "-lqrcode", "-lrmaker_common", "-lconsole", "-lmqtt", "-lcat_face_detect", "-lhuman_face_detect", "-lcolor_detect", "-lmfn", "-ldl", "-lspiffs", "-lesp_tts_chinese", "-lvoice_set_xiaole", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxt_hal", "-lc", "-lm", "-lnewlib", "-lstdc++", "-lpthread", "-lgcc", "-lcxx", "-lphy", "-lesp_phy", "-lphy", "-lesp_phy", "-lphy" + "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lapp_trace", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lunity", "-lcmock", "-lconsole", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-lesp_hid", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_https_server", "-lesp_psram", "-lesp_lcd", "-lprotobuf-c", "-lprotocomm", "-lesp_local_ctrl", "-lespcoredump", "-lwear_levelling", "-lsdmmc", "-lfatfs", "-ljson", "-lmqtt", "-lperfmon", "-lspiffs", "-ltouch_element", "-lulp", "-lusb", "-lwifi_provisioning", "-lespressif__mdns", "-lcbor", "-lrmaker_common", "-lesp_diagnostics", "-lrtc_store", "-lesp_insights", "-ljson_parser", "-ljson_generator", "-lesp_schedule", "-lespressif__esp_secure_cert_mgr", "-lesp_rainmaker", "-lgpio_button", "-lqrcode", "-lws2812_led", "-larduino_tinyusb", "-lespressif__esp-dsp", "-lesp32-camera", "-lesp_littlefs", "-lfb_gfx", "-lapp_trace", "-lapp_trace", "-lcmock", "-lunity", "-lesp_lcd", "-lperfmon", "-ltouch_element", "-lusb", "-lesp_hid", "-lfatfs", "-lwear_levelling", "-lsdmmc", "-lesp_insights", "-lcbor", "-lesp_diagnostics", "-lrtc_store", "-lesp_rainmaker", "-lesp_local_ctrl", "-lesp_https_server", "-lwifi_provisioning", "-lprotocomm", "-lprotobuf-c", "-ljson", "-lespressif__mdns", "-ljson_parser", "-ljson_generator", "-lesp_schedule", "-lespressif__esp_secure_cert_mgr", "-lqrcode", "-lrmaker_common", "-lconsole", "-lmqtt", "-lcat_face_detect", "-lhuman_face_detect", "-lcolor_detect", "-lmfn", "-ldl", "-lspiffs", "-lespressif__esp-dsp", "-lesp_tts_chinese", "-lvoice_set_xiaole", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxt_hal", "-lc", "-lm", "-lnewlib", "-lstdc++", "-lpthread", "-lgcc", "-lcxx", "-lphy", "-lesp_phy", "-lphy", "-lesp_phy", "-lphy" ], CPPDEFINES=[ "ESP_PLATFORM", - ("IDF_VER", '\\"v5.1-dev-4124-gbb9200acec\\"'), + ("IDF_VER", '\\"v5.1-dev-4528-g420ebd208a\\"'), ("MBEDTLS_CONFIG_FILE", '\\"mbedtls/esp_config.h\\"'), ("SOC_MMU_PAGE_SIZE", 'CONFIG_MMU_PAGE_SIZE'), "UNITY_INCLUDE_CONFIG_H", diff --git a/tools/sdk/esp32s2/qio_qspi/include/sdkconfig.h b/tools/sdk/esp32s2/qio_qspi/include/sdkconfig.h index 745c2ccfdb6..7f2fa4208c9 100644 --- a/tools/sdk/esp32s2/qio_qspi/include/sdkconfig.h +++ b/tools/sdk/esp32s2/qio_qspi/include/sdkconfig.h @@ -214,6 +214,7 @@ #define CONFIG_SOC_EFUSE_SOFT_DIS_JTAG 1 #define CONFIG_SOC_EFUSE_DIS_BOOT_REMAP 1 #define CONFIG_SOC_EFUSE_DIS_LEGACY_SPI_BOOT 1 +#define CONFIG_SOC_EFUSE_DIS_ICACHE 1 #define CONFIG_SOC_SECURE_BOOT_V2_RSA 1 #define CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 #define CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 @@ -287,6 +288,7 @@ #define CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE 1 #define CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP 1 #define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x10 +#define CONFIG_BOOTLOADER_RESERVE_RTC_MEM 1 #define CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT 1 #define CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED 1 #define CONFIG_SECURE_BOOT_V2_PREFERRED 1 @@ -992,5 +994,5 @@ #define CONFIG_WARN_WRITE_STRINGS CONFIG_COMPILER_WARN_WRITE_STRINGS #define CONFIG_WPA_MBEDTLS_CRYPTO CONFIG_ESP_WIFI_MBEDTLS_CRYPTO #define CONFIG_WPA_MBEDTLS_TLS_CLIENT CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT -#define CONFIG_ARDUINO_IDF_COMMIT "" +#define CONFIG_ARDUINO_IDF_COMMIT "420ebd208a" #define CONFIG_ARDUINO_IDF_BRANCH "release/v5.1" diff --git a/tools/sdk/esp32s2/qio_qspi/libspi_flash.a b/tools/sdk/esp32s2/qio_qspi/libspi_flash.a index bbef97da31a..92b31444620 100644 Binary files a/tools/sdk/esp32s2/qio_qspi/libspi_flash.a and b/tools/sdk/esp32s2/qio_qspi/libspi_flash.a differ diff --git a/tools/sdk/esp32s2/qout_qspi/include/sdkconfig.h b/tools/sdk/esp32s2/qout_qspi/include/sdkconfig.h index 8570010fc7c..ed9ade02e34 100644 --- a/tools/sdk/esp32s2/qout_qspi/include/sdkconfig.h +++ b/tools/sdk/esp32s2/qout_qspi/include/sdkconfig.h @@ -214,6 +214,7 @@ #define CONFIG_SOC_EFUSE_SOFT_DIS_JTAG 1 #define CONFIG_SOC_EFUSE_DIS_BOOT_REMAP 1 #define CONFIG_SOC_EFUSE_DIS_LEGACY_SPI_BOOT 1 +#define CONFIG_SOC_EFUSE_DIS_ICACHE 1 #define CONFIG_SOC_SECURE_BOOT_V2_RSA 1 #define CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 #define CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 @@ -287,6 +288,7 @@ #define CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE 1 #define CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP 1 #define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x10 +#define CONFIG_BOOTLOADER_RESERVE_RTC_MEM 1 #define CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT 1 #define CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED 1 #define CONFIG_SECURE_BOOT_V2_PREFERRED 1 @@ -992,5 +994,5 @@ #define CONFIG_WARN_WRITE_STRINGS CONFIG_COMPILER_WARN_WRITE_STRINGS #define CONFIG_WPA_MBEDTLS_CRYPTO CONFIG_ESP_WIFI_MBEDTLS_CRYPTO #define CONFIG_WPA_MBEDTLS_TLS_CLIENT CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT -#define CONFIG_ARDUINO_IDF_COMMIT "" +#define CONFIG_ARDUINO_IDF_COMMIT "420ebd208a" #define CONFIG_ARDUINO_IDF_BRANCH "release/v5.1" diff --git a/tools/sdk/esp32s2/qout_qspi/libspi_flash.a b/tools/sdk/esp32s2/qout_qspi/libspi_flash.a index ac2f2fec9b0..64436a1c04b 100644 Binary files a/tools/sdk/esp32s2/qout_qspi/libspi_flash.a and b/tools/sdk/esp32s2/qout_qspi/libspi_flash.a differ diff --git a/tools/sdk/esp32s2/sdkconfig b/tools/sdk/esp32s2/sdkconfig index b700c8929b8..092975cc7e0 100644 --- a/tools/sdk/esp32s2/sdkconfig +++ b/tools/sdk/esp32s2/sdkconfig @@ -213,6 +213,7 @@ CONFIG_SOC_EFUSE_HARD_DIS_JTAG=y CONFIG_SOC_EFUSE_SOFT_DIS_JTAG=y CONFIG_SOC_EFUSE_DIS_BOOT_REMAP=y CONFIG_SOC_EFUSE_DIS_LEGACY_SPI_BOOT=y +CONFIG_SOC_EFUSE_DIS_ICACHE=y CONFIG_SOC_SECURE_BOOT_V2_RSA=y CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS=3 CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS=y @@ -313,6 +314,7 @@ CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP=y # CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS is not set CONFIG_BOOTLOADER_RESERVE_RTC_SIZE=0x10 # CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC is not set +CONFIG_BOOTLOADER_RESERVE_RTC_MEM=y CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT=y # end of Bootloader config @@ -997,7 +999,6 @@ CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL=0 # ESP Ringbuf # # CONFIG_RINGBUF_PLACE_FUNCTIONS_INTO_FLASH is not set -# CONFIG_RINGBUF_PLACE_ISR_FUNCTIONS_INTO_FLASH is not set # end of ESP Ringbuf # @@ -1161,12 +1162,19 @@ CONFIG_ESP_WIFI_MBEDTLS_CRYPTO=y CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT=y # CONFIG_ESP_WIFI_WAPI_PSK is not set # CONFIG_ESP_WIFI_SUITE_B_192 is not set -# CONFIG_ESP_WIFI_WPS_STRICT is not set # CONFIG_ESP_WIFI_11KV_SUPPORT is not set # CONFIG_ESP_WIFI_MBO_SUPPORT is not set # CONFIG_ESP_WIFI_DPP_SUPPORT is not set # CONFIG_ESP_WIFI_11R_SUPPORT is not set # CONFIG_ESP_WIFI_WPS_SOFTAP_REGISTRAR is not set + +# +# WPS Configuration Options +# +# CONFIG_ESP_WIFI_WPS_STRICT is not set +# CONFIG_ESP_WIFI_WPS_PASSPHRASE is not set +# end of WPS Configuration Options + # CONFIG_ESP_WIFI_DEBUG_PRINT is not set # CONFIG_ESP_WIFI_TESTING_OPTIONS is not set # end of Wi-Fi @@ -1303,6 +1311,7 @@ CONFIG_HEAP_POISONING_LIGHT=y CONFIG_HEAP_TRACING_OFF=y # CONFIG_HEAP_TRACING_STANDALONE is not set # CONFIG_HEAP_TRACING_TOHOST is not set +# CONFIG_HEAP_USE_HOOKS is not set # CONFIG_HEAP_TASK_TRACKING is not set # CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS is not set # end of Heap memory debugging @@ -2030,6 +2039,8 @@ CONFIG_MDNS_PREDEF_NETIF_ETH=y # end of mDNS # end of Component config +# CONFIG_IDF_EXPERIMENTAL_FEATURES is not set + # Deprecated options for backward compatibility # CONFIG_APP_BUILD_TYPE_ELF_RAM is not set # CONFIG_NO_BLOBS is not set @@ -2166,12 +2177,12 @@ CONFIG_WPA_MBEDTLS_CRYPTO=y CONFIG_WPA_MBEDTLS_TLS_CLIENT=y # CONFIG_WPA_WAPI_PSK is not set # CONFIG_WPA_SUITE_B_192 is not set -# CONFIG_WPA_WPS_STRICT is not set # CONFIG_WPA_11KV_SUPPORT is not set # CONFIG_WPA_MBO_SUPPORT is not set # CONFIG_WPA_DPP_SUPPORT is not set # CONFIG_WPA_11R_SUPPORT is not set # CONFIG_WPA_WPS_SOFTAP_REGISTRAR is not set +# CONFIG_WPA_WPS_STRICT is not set # CONFIG_WPA_DEBUG_PRINT is not set # CONFIG_WPA_TESTING_OPTIONS is not set CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH=y diff --git a/tools/sdk/esp32s3/bin/bootloader_dio_80m.elf b/tools/sdk/esp32s3/bin/bootloader_dio_80m.elf index 18115baac72..5a0534e9881 100755 Binary files a/tools/sdk/esp32s3/bin/bootloader_dio_80m.elf and b/tools/sdk/esp32s3/bin/bootloader_dio_80m.elf differ diff --git a/tools/sdk/esp32s3/bin/bootloader_opi_80m.elf b/tools/sdk/esp32s3/bin/bootloader_opi_80m.elf index 18115baac72..5a0534e9881 100755 Binary files a/tools/sdk/esp32s3/bin/bootloader_opi_80m.elf and b/tools/sdk/esp32s3/bin/bootloader_opi_80m.elf differ diff --git a/tools/sdk/esp32s3/bin/bootloader_qio_120m.elf b/tools/sdk/esp32s3/bin/bootloader_qio_120m.elf index 1946247ab2b..66d49e29c26 100755 Binary files a/tools/sdk/esp32s3/bin/bootloader_qio_120m.elf and b/tools/sdk/esp32s3/bin/bootloader_qio_120m.elf differ diff --git a/tools/sdk/esp32s3/bin/bootloader_qio_80m.elf b/tools/sdk/esp32s3/bin/bootloader_qio_80m.elf index 18619b830c1..a7cb84b68d4 100755 Binary files a/tools/sdk/esp32s3/bin/bootloader_qio_80m.elf and b/tools/sdk/esp32s3/bin/bootloader_qio_80m.elf differ diff --git a/tools/sdk/esp32s3/dio_opi/include/sdkconfig.h b/tools/sdk/esp32s3/dio_opi/include/sdkconfig.h index 4990719440d..2dbdd8d85ad 100644 --- a/tools/sdk/esp32s3/dio_opi/include/sdkconfig.h +++ b/tools/sdk/esp32s3/dio_opi/include/sdkconfig.h @@ -272,6 +272,8 @@ #define CONFIG_SOC_EFUSE_DIS_USB_JTAG 1 #define CONFIG_SOC_EFUSE_SOFT_DIS_JTAG 1 #define CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT 1 +#define CONFIG_SOC_EFUSE_DIS_ICACHE 1 +#define CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 #define CONFIG_SOC_SECURE_BOOT_V2_RSA 1 #define CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 #define CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 @@ -309,6 +311,7 @@ #define CONFIG_SOC_BLE_SUPPORTED 1 #define CONFIG_SOC_BLE_MESH_SUPPORTED 1 #define CONFIG_SOC_BLE_50_SUPPORTED 1 +#define CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED 1 #define CONFIG_IDF_CMAKE 1 #define CONFIG_IDF_TARGET_ARCH_XTENSA 1 #define CONFIG_IDF_TARGET_ARCH "xtensa" @@ -330,6 +333,7 @@ #define CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE 1 #define CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP 1 #define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x10 +#define CONFIG_BOOTLOADER_RESERVE_RTC_MEM 1 #define CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT 1 #define CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED 1 #define CONFIG_SECURE_BOOT_V2_PREFERRED 1 @@ -733,13 +737,12 @@ #define CONFIG_BT_SMP_ENABLE 1 #define CONFIG_BT_BLE_ESTAB_LINK_CONN_TOUT 30 #define CONFIG_BT_MAX_DEVICE_NAME_LEN 32 -#define CONFIG_BT_BLE_RPA_SUPPORTED 1 #define CONFIG_BT_BLE_RPA_TIMEOUT 900 #define CONFIG_BT_BLE_50_FEATURES_SUPPORTED 1 #define CONFIG_BT_BLE_42_FEATURES_SUPPORTED 1 #define CONFIG_BT_CTRL_MODE_EFF 1 -#define CONFIG_BT_CTRL_BLE_MAX_ACT 10 -#define CONFIG_BT_CTRL_BLE_MAX_ACT_EFF 10 +#define CONFIG_BT_CTRL_BLE_MAX_ACT 6 +#define CONFIG_BT_CTRL_BLE_MAX_ACT_EFF 6 #define CONFIG_BT_CTRL_BLE_STATIC_ACL_TX_BUF_NB 0 #define CONFIG_BT_CTRL_PINNED_TO_CORE_0 1 #define CONFIG_BT_CTRL_PINNED_TO_CORE 0 @@ -1462,5 +1465,5 @@ #define CONFIG_WARN_WRITE_STRINGS CONFIG_COMPILER_WARN_WRITE_STRINGS #define CONFIG_WPA_MBEDTLS_CRYPTO CONFIG_ESP_WIFI_MBEDTLS_CRYPTO #define CONFIG_WPA_MBEDTLS_TLS_CLIENT CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT -#define CONFIG_ARDUINO_IDF_COMMIT "" +#define CONFIG_ARDUINO_IDF_COMMIT "420ebd208a" #define CONFIG_ARDUINO_IDF_BRANCH "release/v5.1" diff --git a/tools/sdk/esp32s3/dio_opi/libbootloader_support.a b/tools/sdk/esp32s3/dio_opi/libbootloader_support.a index 4ef2c2f9ab0..02f7340d42a 100644 Binary files a/tools/sdk/esp32s3/dio_opi/libbootloader_support.a and b/tools/sdk/esp32s3/dio_opi/libbootloader_support.a differ diff --git a/tools/sdk/esp32s3/dio_opi/libesp_hw_support.a b/tools/sdk/esp32s3/dio_opi/libesp_hw_support.a index 43e2bd42f02..45caf3ad046 100644 Binary files a/tools/sdk/esp32s3/dio_opi/libesp_hw_support.a and b/tools/sdk/esp32s3/dio_opi/libesp_hw_support.a differ diff --git a/tools/sdk/esp32s3/dio_opi/libesp_psram.a b/tools/sdk/esp32s3/dio_opi/libesp_psram.a index 73fe240d808..df8f936f060 100644 Binary files a/tools/sdk/esp32s3/dio_opi/libesp_psram.a and b/tools/sdk/esp32s3/dio_opi/libesp_psram.a differ diff --git a/tools/sdk/esp32s3/dio_opi/libesp_system.a b/tools/sdk/esp32s3/dio_opi/libesp_system.a index ae68e467a34..bea899d256e 100644 Binary files a/tools/sdk/esp32s3/dio_opi/libesp_system.a and b/tools/sdk/esp32s3/dio_opi/libesp_system.a differ diff --git a/tools/sdk/esp32s3/dio_opi/libfreertos.a b/tools/sdk/esp32s3/dio_opi/libfreertos.a index cea0d5580d5..3ee1893d659 100644 Binary files a/tools/sdk/esp32s3/dio_opi/libfreertos.a and b/tools/sdk/esp32s3/dio_opi/libfreertos.a differ diff --git a/tools/sdk/esp32s3/dio_opi/libspi_flash.a b/tools/sdk/esp32s3/dio_opi/libspi_flash.a index 0ee000f50f8..8ade2f38ac8 100644 Binary files a/tools/sdk/esp32s3/dio_opi/libspi_flash.a and b/tools/sdk/esp32s3/dio_opi/libspi_flash.a differ diff --git a/tools/sdk/esp32s3/dio_opi/sections.ld b/tools/sdk/esp32s3/dio_opi/sections.ld index 715a6161a7f..c55ecc8bf85 100644 --- a/tools/sdk/esp32s3/dio_opi/sections.ld +++ b/tools/sdk/esp32s3/dio_opi/sections.ld @@ -1,6 +1,6 @@ /* Automatically generated file; DO NOT EDIT */ /* Espressif IoT Development Framework Linker Script */ -/* Generated from: /Users/ficeto/Desktop/ESP32/ESP-IDF-5/esp32-arduino-lib-builder/esp-idf/components/esp_system/ld/esp32s3/sections.ld.in */ +/* Generated from: /home/runner/work/esp32-arduino-lib-builder/esp32-arduino-lib-builder/esp-idf/components/esp_system/ld/esp32s3/sections.ld.in */ /* * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD @@ -496,7 +496,7 @@ SECTIONS *libesp_system.a:esp_system_chip.*(.literal.esp_get_free_heap_size .literal.esp_get_free_internal_heap_size .literal.esp_get_idf_version .literal.esp_get_minimum_free_heap_size .text .text.esp_get_free_heap_size .text.esp_get_free_internal_heap_size .text.esp_get_idf_version .text.esp_get_minimum_free_heap_size) *libfreertos.a:app_startup.*(.literal .literal.* .text .text.*) *libheap.a:multi_heap.*(.literal.multi_heap_check .literal.multi_heap_dump .literal.multi_heap_dump_tlsf .literal.multi_heap_get_info_impl .literal.multi_heap_register_impl .literal.tlsf_check_hook .text .text.multi_heap_check .text.multi_heap_dump .text.multi_heap_dump_tlsf .text.multi_heap_free_size_impl .text.multi_heap_get_info_impl .text.multi_heap_get_info_tlsf .text.multi_heap_minimum_free_size_impl .text.multi_heap_register_impl .text.tlsf_check_hook) - *libheap.a:multi_heap_poisoning.*(.literal.multi_heap_free_size .literal.multi_heap_get_info .literal.multi_heap_minimum_free_size .literal.multi_heap_register .text .text.multi_heap_free_size .text.multi_heap_get_info .text.multi_heap_minimum_free_size .text.multi_heap_register .text.subtract_poison_overhead) + *libheap.a:multi_heap_poisoning.*(.literal.multi_heap_free_size .literal.multi_heap_get_info .literal.multi_heap_minimum_free_size .literal.multi_heap_register .text .text.multi_heap_free_size .text.multi_heap_get_info .text.multi_heap_minimum_free_size .text.multi_heap_register) *libheap.a:tlsf.*(.literal.default_walker .literal.tlsf_add_pool .literal.tlsf_check .literal.tlsf_check_pool .literal.tlsf_create .literal.tlsf_create_with_pool .literal.tlsf_remove_pool .literal.tlsf_walk_pool .text .text.default_walker .text.integrity_walker .text.tlsf_add_pool .text.tlsf_check .text.tlsf_check_pool .text.tlsf_create .text.tlsf_create_with_pool .text.tlsf_destroy .text.tlsf_fit_size .text.tlsf_pool_overhead .text.tlsf_remove_pool .text.tlsf_walk_pool) *liblog.a:log.*(.literal.esp_log_level_get .literal.esp_log_level_set .literal.esp_log_set_vprintf .literal.esp_log_writev .literal.heap_bubble_down .literal.s_log_level_get_and_unlock .text .text.esp_log_level_get .text.esp_log_level_set .text.esp_log_set_vprintf .text.esp_log_writev .text.heap_bubble_down .text.s_log_level_get_and_unlock) *liblog.a:log_freertos.*(.literal.esp_log_system_timestamp .text .text.esp_log_system_timestamp) diff --git a/tools/sdk/esp32s3/dio_qspi/include/sdkconfig.h b/tools/sdk/esp32s3/dio_qspi/include/sdkconfig.h index 593747cd5b0..e16f7ecd892 100644 --- a/tools/sdk/esp32s3/dio_qspi/include/sdkconfig.h +++ b/tools/sdk/esp32s3/dio_qspi/include/sdkconfig.h @@ -272,6 +272,8 @@ #define CONFIG_SOC_EFUSE_DIS_USB_JTAG 1 #define CONFIG_SOC_EFUSE_SOFT_DIS_JTAG 1 #define CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT 1 +#define CONFIG_SOC_EFUSE_DIS_ICACHE 1 +#define CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 #define CONFIG_SOC_SECURE_BOOT_V2_RSA 1 #define CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 #define CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 @@ -309,6 +311,7 @@ #define CONFIG_SOC_BLE_SUPPORTED 1 #define CONFIG_SOC_BLE_MESH_SUPPORTED 1 #define CONFIG_SOC_BLE_50_SUPPORTED 1 +#define CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED 1 #define CONFIG_IDF_CMAKE 1 #define CONFIG_IDF_TARGET_ARCH_XTENSA 1 #define CONFIG_IDF_TARGET_ARCH "xtensa" @@ -330,6 +333,7 @@ #define CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE 1 #define CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP 1 #define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x10 +#define CONFIG_BOOTLOADER_RESERVE_RTC_MEM 1 #define CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT 1 #define CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED 1 #define CONFIG_SECURE_BOOT_V2_PREFERRED 1 @@ -733,13 +737,12 @@ #define CONFIG_BT_SMP_ENABLE 1 #define CONFIG_BT_BLE_ESTAB_LINK_CONN_TOUT 30 #define CONFIG_BT_MAX_DEVICE_NAME_LEN 32 -#define CONFIG_BT_BLE_RPA_SUPPORTED 1 #define CONFIG_BT_BLE_RPA_TIMEOUT 900 #define CONFIG_BT_BLE_50_FEATURES_SUPPORTED 1 #define CONFIG_BT_BLE_42_FEATURES_SUPPORTED 1 #define CONFIG_BT_CTRL_MODE_EFF 1 -#define CONFIG_BT_CTRL_BLE_MAX_ACT 10 -#define CONFIG_BT_CTRL_BLE_MAX_ACT_EFF 10 +#define CONFIG_BT_CTRL_BLE_MAX_ACT 6 +#define CONFIG_BT_CTRL_BLE_MAX_ACT_EFF 6 #define CONFIG_BT_CTRL_BLE_STATIC_ACL_TX_BUF_NB 0 #define CONFIG_BT_CTRL_PINNED_TO_CORE_0 1 #define CONFIG_BT_CTRL_PINNED_TO_CORE 0 @@ -859,11 +862,9 @@ #define CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY 1 #define CONFIG_SPIRAM_CLK_IO 30 #define CONFIG_SPIRAM_CS_IO 26 -#define CONFIG_SPIRAM_SPEED_40M 1 -#define CONFIG_SPIRAM_SPEED 40 -#define CONFIG_SPIRAM_BOOT_INIT 1 +#define CONFIG_SPIRAM_SPEED_80M 1 +#define CONFIG_SPIRAM_SPEED 80 #define CONFIG_SPIRAM_USE_MALLOC 1 -#define CONFIG_SPIRAM_MEMTEST 1 #define CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL 4096 #define CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP 1 #define CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL 0 @@ -1462,5 +1463,5 @@ #define CONFIG_WARN_WRITE_STRINGS CONFIG_COMPILER_WARN_WRITE_STRINGS #define CONFIG_WPA_MBEDTLS_CRYPTO CONFIG_ESP_WIFI_MBEDTLS_CRYPTO #define CONFIG_WPA_MBEDTLS_TLS_CLIENT CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT -#define CONFIG_ARDUINO_IDF_COMMIT "" +#define CONFIG_ARDUINO_IDF_COMMIT "420ebd208a" #define CONFIG_ARDUINO_IDF_BRANCH "release/v5.1" diff --git a/tools/sdk/esp32s3/dio_qspi/libbootloader_support.a b/tools/sdk/esp32s3/dio_qspi/libbootloader_support.a index 4ef2c2f9ab0..02f7340d42a 100644 Binary files a/tools/sdk/esp32s3/dio_qspi/libbootloader_support.a and b/tools/sdk/esp32s3/dio_qspi/libbootloader_support.a differ diff --git a/tools/sdk/esp32s3/dio_qspi/libesp_hw_support.a b/tools/sdk/esp32s3/dio_qspi/libesp_hw_support.a index ab0bff1efbc..ae06a8d8da3 100644 Binary files a/tools/sdk/esp32s3/dio_qspi/libesp_hw_support.a and b/tools/sdk/esp32s3/dio_qspi/libesp_hw_support.a differ diff --git a/tools/sdk/esp32s3/dio_qspi/libesp_psram.a b/tools/sdk/esp32s3/dio_qspi/libesp_psram.a index b2a666db3b1..2bb493b5051 100644 Binary files a/tools/sdk/esp32s3/dio_qspi/libesp_psram.a and b/tools/sdk/esp32s3/dio_qspi/libesp_psram.a differ diff --git a/tools/sdk/esp32s3/dio_qspi/libesp_system.a b/tools/sdk/esp32s3/dio_qspi/libesp_system.a index 67936f4e521..1e70838e0e0 100644 Binary files a/tools/sdk/esp32s3/dio_qspi/libesp_system.a and b/tools/sdk/esp32s3/dio_qspi/libesp_system.a differ diff --git a/tools/sdk/esp32s3/dio_qspi/libfreertos.a b/tools/sdk/esp32s3/dio_qspi/libfreertos.a index cea0d5580d5..3ee1893d659 100644 Binary files a/tools/sdk/esp32s3/dio_qspi/libfreertos.a and b/tools/sdk/esp32s3/dio_qspi/libfreertos.a differ diff --git a/tools/sdk/esp32s3/dio_qspi/libspi_flash.a b/tools/sdk/esp32s3/dio_qspi/libspi_flash.a index 0d4772d1058..a39765e7540 100644 Binary files a/tools/sdk/esp32s3/dio_qspi/libspi_flash.a and b/tools/sdk/esp32s3/dio_qspi/libspi_flash.a differ diff --git a/tools/sdk/esp32s3/dio_qspi/sections.ld b/tools/sdk/esp32s3/dio_qspi/sections.ld index 04b403f89cb..bad0471018f 100644 --- a/tools/sdk/esp32s3/dio_qspi/sections.ld +++ b/tools/sdk/esp32s3/dio_qspi/sections.ld @@ -1,6 +1,6 @@ /* Automatically generated file; DO NOT EDIT */ /* Espressif IoT Development Framework Linker Script */ -/* Generated from: /Users/ficeto/Desktop/ESP32/ESP-IDF-5/esp32-arduino-lib-builder/esp-idf/components/esp_system/ld/esp32s3/sections.ld.in */ +/* Generated from: /home/runner/work/esp32-arduino-lib-builder/esp32-arduino-lib-builder/esp-idf/components/esp_system/ld/esp32s3/sections.ld.in */ /* * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD @@ -496,7 +496,7 @@ SECTIONS *libesp_system.a:esp_system_chip.*(.literal.esp_get_free_heap_size .literal.esp_get_free_internal_heap_size .literal.esp_get_idf_version .literal.esp_get_minimum_free_heap_size .text .text.esp_get_free_heap_size .text.esp_get_free_internal_heap_size .text.esp_get_idf_version .text.esp_get_minimum_free_heap_size) *libfreertos.a:app_startup.*(.literal .literal.* .text .text.*) *libheap.a:multi_heap.*(.literal.multi_heap_check .literal.multi_heap_dump .literal.multi_heap_dump_tlsf .literal.multi_heap_get_info_impl .literal.multi_heap_register_impl .literal.tlsf_check_hook .text .text.multi_heap_check .text.multi_heap_dump .text.multi_heap_dump_tlsf .text.multi_heap_free_size_impl .text.multi_heap_get_info_impl .text.multi_heap_get_info_tlsf .text.multi_heap_minimum_free_size_impl .text.multi_heap_register_impl .text.tlsf_check_hook) - *libheap.a:multi_heap_poisoning.*(.literal.multi_heap_free_size .literal.multi_heap_get_info .literal.multi_heap_minimum_free_size .literal.multi_heap_register .text .text.multi_heap_free_size .text.multi_heap_get_info .text.multi_heap_minimum_free_size .text.multi_heap_register .text.subtract_poison_overhead) + *libheap.a:multi_heap_poisoning.*(.literal.multi_heap_free_size .literal.multi_heap_get_info .literal.multi_heap_minimum_free_size .literal.multi_heap_register .text .text.multi_heap_free_size .text.multi_heap_get_info .text.multi_heap_minimum_free_size .text.multi_heap_register) *libheap.a:tlsf.*(.literal.default_walker .literal.tlsf_add_pool .literal.tlsf_check .literal.tlsf_check_pool .literal.tlsf_create .literal.tlsf_create_with_pool .literal.tlsf_remove_pool .literal.tlsf_walk_pool .text .text.default_walker .text.integrity_walker .text.tlsf_add_pool .text.tlsf_check .text.tlsf_check_pool .text.tlsf_create .text.tlsf_create_with_pool .text.tlsf_destroy .text.tlsf_fit_size .text.tlsf_pool_overhead .text.tlsf_remove_pool .text.tlsf_walk_pool) *liblog.a:log.*(.literal.esp_log_level_get .literal.esp_log_level_set .literal.esp_log_set_vprintf .literal.esp_log_writev .literal.heap_bubble_down .literal.s_log_level_get_and_unlock .text .text.esp_log_level_get .text.esp_log_level_set .text.esp_log_set_vprintf .text.esp_log_writev .text.heap_bubble_down .text.s_log_level_get_and_unlock) *liblog.a:log_freertos.*(.literal.esp_log_system_timestamp .text .text.esp_log_system_timestamp) diff --git a/tools/sdk/esp32s3/esp_sr/srmodels.bin b/tools/sdk/esp32s3/esp_sr/srmodels.bin index 429e3079aae..3be4bce8f3c 100644 Binary files a/tools/sdk/esp32s3/esp_sr/srmodels.bin and b/tools/sdk/esp32s3/esp_sr/srmodels.bin differ diff --git a/tools/sdk/esp32s3/flags/defines b/tools/sdk/esp32s3/flags/defines index 5847d2162fb..2c8b36ae704 100644 --- a/tools/sdk/esp32s3/flags/defines +++ b/tools/sdk/esp32s3/flags/defines @@ -1 +1 @@ --DESP_PLATFORM -DIDF_VER=\"v5.1-dev-4124-gbb9200acec\" -DMBEDTLS_CONFIG_FILE=\"mbedtls/esp_config.h\" -DSOC_MMU_PAGE_SIZE=CONFIG_MMU_PAGE_SIZE -DUNITY_INCLUDE_CONFIG_H -D_GNU_SOURCE -D_POSIX_READER_WRITER_LOCKS -DconfigENABLE_FREERTOS_DEBUG_OCDAWARE=1 \ No newline at end of file +-DESP_PLATFORM -DIDF_VER=\"v5.1-dev-4528-g420ebd208a\" -DMBEDTLS_CONFIG_FILE=\"mbedtls/esp_config.h\" -DSOC_MMU_PAGE_SIZE=CONFIG_MMU_PAGE_SIZE -DUNITY_INCLUDE_CONFIG_H -D_GNU_SOURCE -D_POSIX_READER_WRITER_LOCKS -DconfigENABLE_FREERTOS_DEBUG_OCDAWARE=1 \ No newline at end of file diff --git a/tools/sdk/esp32s3/flags/includes b/tools/sdk/esp32s3/flags/includes index de54ed95967..e85a741d096 100644 --- a/tools/sdk/esp32s3/flags/includes +++ b/tools/sdk/esp32s3/flags/includes @@ -1 +1 @@ --iwithprefixbefore newlib/platform_include -iwithprefixbefore freertos/FreeRTOS-Kernel/include -iwithprefixbefore freertos/FreeRTOS-Kernel/portable/xtensa/include -iwithprefixbefore freertos/esp_additions/include/freertos -iwithprefixbefore freertos/esp_additions/include -iwithprefixbefore esp_hw_support/include -iwithprefixbefore esp_hw_support/include/soc -iwithprefixbefore esp_hw_support/include/soc/esp32s3 -iwithprefixbefore esp_hw_support/port/esp32s3 -iwithprefixbefore heap/include -iwithprefixbefore log/include -iwithprefixbefore soc/include -iwithprefixbefore soc/esp32s3 -iwithprefixbefore soc/esp32s3/include -iwithprefixbefore hal/esp32s3/include -iwithprefixbefore hal/include -iwithprefixbefore hal/platform_port/include -iwithprefixbefore esp_rom/include -iwithprefixbefore esp_rom/include/esp32s3 -iwithprefixbefore esp_rom/esp32s3 -iwithprefixbefore esp_common/include -iwithprefixbefore esp_system/include -iwithprefixbefore esp_system/port/soc -iwithprefixbefore esp_system/port/include/private -iwithprefixbefore xtensa/include -iwithprefixbefore xtensa/esp32s3/include -iwithprefixbefore lwip/include -iwithprefixbefore lwip/include/apps -iwithprefixbefore lwip/include/apps/sntp -iwithprefixbefore lwip/lwip/src/include -iwithprefixbefore lwip/port/include -iwithprefixbefore lwip/port/freertos/include -iwithprefixbefore lwip/port/esp32xx/include -iwithprefixbefore lwip/port/esp32xx/include/arch -iwithprefixbefore espressif__mdns/include -iwithprefixbefore console -iwithprefixbefore vfs/include -iwithprefixbefore esp_netif/include -iwithprefixbefore esp_event/include -iwithprefixbefore esp_ringbuf/include -iwithprefixbefore efuse/include -iwithprefixbefore efuse/esp32s3/include -iwithprefixbefore driver/include -iwithprefixbefore driver/deprecated -iwithprefixbefore driver/analog_comparator/include -iwithprefixbefore driver/dac/include -iwithprefixbefore driver/gpio/include -iwithprefixbefore driver/gptimer/include -iwithprefixbefore driver/i2c/include -iwithprefixbefore driver/i2s/include -iwithprefixbefore driver/ledc/include -iwithprefixbefore driver/mcpwm/include -iwithprefixbefore driver/parlio/include -iwithprefixbefore driver/pcnt/include -iwithprefixbefore driver/rmt/include -iwithprefixbefore driver/sdio_slave/include -iwithprefixbefore driver/sdmmc/include -iwithprefixbefore driver/sigma_delta/include -iwithprefixbefore driver/spi/include -iwithprefixbefore driver/temperature_sensor/include -iwithprefixbefore driver/touch_sensor/include -iwithprefixbefore driver/twai/include -iwithprefixbefore driver/uart/include -iwithprefixbefore driver/usb_serial_jtag/include -iwithprefixbefore driver/touch_sensor/esp32s3/include -iwithprefixbefore esp_pm/include -iwithprefixbefore mbedtls/port/include -iwithprefixbefore mbedtls/mbedtls/include -iwithprefixbefore mbedtls/mbedtls/library -iwithprefixbefore mbedtls/esp_crt_bundle/include -iwithprefixbefore esp_app_format/include -iwithprefixbefore bootloader_support/include -iwithprefixbefore bootloader_support/bootloader_flash/include -iwithprefixbefore esp_partition/include -iwithprefixbefore app_update/include -iwithprefixbefore esp_mm/include -iwithprefixbefore spi_flash/include -iwithprefixbefore pthread/include -iwithprefixbefore esp_timer/include -iwithprefixbefore app_trace/include -iwithprefixbefore nvs_flash/include -iwithprefixbefore esp_phy/include -iwithprefixbefore esp_phy/esp32s3/include -iwithprefixbefore wpa_supplicant/include -iwithprefixbefore wpa_supplicant/port/include -iwithprefixbefore wpa_supplicant/esp_supplicant/include -iwithprefixbefore esp_coex/include -iwithprefixbefore esp_wifi/include -iwithprefixbefore esp_wifi/wifi_apps/include -iwithprefixbefore bt/include/esp32c3/include -iwithprefixbefore bt/common/osi/include -iwithprefixbefore bt/common/api/include/api -iwithprefixbefore bt/common/btc/profile/esp/blufi/include -iwithprefixbefore bt/common/btc/profile/esp/include -iwithprefixbefore bt/host/bluedroid/api/include/api -iwithprefixbefore bt/esp_ble_mesh/mesh_common/include -iwithprefixbefore bt/esp_ble_mesh/mesh_common/tinycrypt/include -iwithprefixbefore bt/esp_ble_mesh/mesh_core -iwithprefixbefore bt/esp_ble_mesh/mesh_core/include -iwithprefixbefore bt/esp_ble_mesh/mesh_core/storage -iwithprefixbefore bt/esp_ble_mesh/btc/include -iwithprefixbefore bt/esp_ble_mesh/mesh_models/common/include -iwithprefixbefore bt/esp_ble_mesh/mesh_models/client/include -iwithprefixbefore bt/esp_ble_mesh/mesh_models/server/include -iwithprefixbefore bt/esp_ble_mesh/api/core/include -iwithprefixbefore bt/esp_ble_mesh/api/models/include -iwithprefixbefore bt/esp_ble_mesh/api -iwithprefixbefore bt/porting/ext/tinycrypt/include -iwithprefixbefore unity/include -iwithprefixbefore unity/unity/src -iwithprefixbefore cmock/CMock/src -iwithprefixbefore http_parser -iwithprefixbefore esp-tls -iwithprefixbefore esp-tls/esp-tls-crypto -iwithprefixbefore esp_adc/include -iwithprefixbefore esp_adc/interface -iwithprefixbefore esp_adc/esp32s3/include -iwithprefixbefore esp_adc/deprecated/include -iwithprefixbefore esp_eth/include -iwithprefixbefore esp_gdbstub/include -iwithprefixbefore esp_gdbstub/xtensa -iwithprefixbefore esp_gdbstub/esp32s3 -iwithprefixbefore esp_hid/include -iwithprefixbefore tcp_transport/include -iwithprefixbefore esp_http_client/include -iwithprefixbefore esp_http_server/include -iwithprefixbefore esp_https_ota/include -iwithprefixbefore esp_https_server/include -iwithprefixbefore esp_lcd/include -iwithprefixbefore esp_lcd/interface -iwithprefixbefore protobuf-c/protobuf-c -iwithprefixbefore protocomm/include/common -iwithprefixbefore protocomm/include/security -iwithprefixbefore protocomm/include/transports -iwithprefixbefore esp_local_ctrl/include -iwithprefixbefore esp_psram/include -iwithprefixbefore espcoredump/include -iwithprefixbefore espcoredump/include/port/xtensa -iwithprefixbefore wear_levelling/include -iwithprefixbefore sdmmc/include -iwithprefixbefore fatfs/diskio -iwithprefixbefore fatfs/vfs -iwithprefixbefore fatfs/src -iwithprefixbefore idf_test/include -iwithprefixbefore idf_test/include/esp32s3 -iwithprefixbefore ieee802154/include -iwithprefixbefore json/cJSON -iwithprefixbefore mqtt/esp-mqtt/include -iwithprefixbefore perfmon/include -iwithprefixbefore spiffs/include -iwithprefixbefore touch_element/include -iwithprefixbefore ulp/ulp_common/include -iwithprefixbefore ulp/ulp_common/include/esp32s3 -iwithprefixbefore usb/include -iwithprefixbefore wifi_provisioning/include -iwithprefixbefore cbor/port/include -iwithprefixbefore rmaker_common/include -iwithprefixbefore esp_diagnostics/include -iwithprefixbefore rtc_store/include -iwithprefixbefore esp_insights/include -iwithprefixbefore json_parser/upstream/include -iwithprefixbefore json_parser/upstream -iwithprefixbefore json_generator/upstream -iwithprefixbefore esp_schedule/include -iwithprefixbefore espressif__esp_secure_cert_mgr/include -iwithprefixbefore esp_rainmaker/include -iwithprefixbefore gpio_button/button/include -iwithprefixbefore qrcode/include -iwithprefixbefore ws2812_led -iwithprefixbefore freertos/FreeRTOS-Kernel/include/freertos -iwithprefixbefore arduino_tinyusb/tinyusb/src -iwithprefixbefore arduino_tinyusb/include -iwithprefixbefore esp_littlefs/include -iwithprefixbefore esp-dl/include -iwithprefixbefore esp-dl/include/tool -iwithprefixbefore esp-dl/include/typedef -iwithprefixbefore esp-dl/include/image -iwithprefixbefore esp-dl/include/math -iwithprefixbefore esp-dl/include/nn -iwithprefixbefore esp-dl/include/layer -iwithprefixbefore esp-dl/include/detect -iwithprefixbefore esp-dl/include/model_zoo -iwithprefixbefore esp-sr/src/include -iwithprefixbefore esp-sr/esp-tts/esp_tts_chinese/include -iwithprefixbefore esp-sr/include/esp32s3 -iwithprefixbefore esp32-camera/driver/include -iwithprefixbefore esp32-camera/conversions/include -iwithprefixbefore espressif__esp-dsp/modules/dotprod/include -iwithprefixbefore espressif__esp-dsp/modules/support/include -iwithprefixbefore espressif__esp-dsp/modules/windows/include -iwithprefixbefore espressif__esp-dsp/modules/windows/hann/include -iwithprefixbefore espressif__esp-dsp/modules/windows/blackman/include -iwithprefixbefore espressif__esp-dsp/modules/windows/blackman_harris/include -iwithprefixbefore espressif__esp-dsp/modules/windows/blackman_nuttall/include -iwithprefixbefore espressif__esp-dsp/modules/windows/nuttall/include -iwithprefixbefore espressif__esp-dsp/modules/windows/flat_top/include -iwithprefixbefore espressif__esp-dsp/modules/iir/include -iwithprefixbefore espressif__esp-dsp/modules/fir/include -iwithprefixbefore espressif__esp-dsp/modules/math/include -iwithprefixbefore espressif__esp-dsp/modules/math/add/include -iwithprefixbefore espressif__esp-dsp/modules/math/sub/include -iwithprefixbefore espressif__esp-dsp/modules/math/mul/include -iwithprefixbefore espressif__esp-dsp/modules/math/addc/include -iwithprefixbefore espressif__esp-dsp/modules/math/mulc/include -iwithprefixbefore espressif__esp-dsp/modules/math/sqrt/include -iwithprefixbefore espressif__esp-dsp/modules/matrix/include -iwithprefixbefore espressif__esp-dsp/modules/fft/include -iwithprefixbefore espressif__esp-dsp/modules/dct/include -iwithprefixbefore espressif__esp-dsp/modules/conv/include -iwithprefixbefore espressif__esp-dsp/modules/common/include -iwithprefixbefore espressif__esp-dsp/modules/kalman/ekf/include -iwithprefixbefore espressif__esp-dsp/modules/kalman/ekf_imu13states/include -iwithprefixbefore fb_gfx/include \ No newline at end of file +-iwithprefixbefore newlib/platform_include -iwithprefixbefore freertos/FreeRTOS-Kernel/include -iwithprefixbefore freertos/FreeRTOS-Kernel/portable/xtensa/include -iwithprefixbefore freertos/esp_additions/include/freertos -iwithprefixbefore freertos/esp_additions/include -iwithprefixbefore freertos/esp_additions/arch/xtensa/include -iwithprefixbefore esp_hw_support/include -iwithprefixbefore esp_hw_support/include/soc -iwithprefixbefore esp_hw_support/include/soc/esp32s3 -iwithprefixbefore esp_hw_support/port/esp32s3 -iwithprefixbefore heap/include -iwithprefixbefore log/include -iwithprefixbefore soc/include -iwithprefixbefore soc/esp32s3 -iwithprefixbefore soc/esp32s3/include -iwithprefixbefore hal/esp32s3/include -iwithprefixbefore hal/include -iwithprefixbefore hal/platform_port/include -iwithprefixbefore esp_rom/include -iwithprefixbefore esp_rom/include/esp32s3 -iwithprefixbefore esp_rom/esp32s3 -iwithprefixbefore esp_common/include -iwithprefixbefore esp_system/include -iwithprefixbefore esp_system/port/soc -iwithprefixbefore esp_system/port/include/private -iwithprefixbefore xtensa/include -iwithprefixbefore xtensa/esp32s3/include -iwithprefixbefore lwip/include -iwithprefixbefore lwip/include/apps -iwithprefixbefore lwip/include/apps/sntp -iwithprefixbefore lwip/lwip/src/include -iwithprefixbefore lwip/port/include -iwithprefixbefore lwip/port/freertos/include -iwithprefixbefore lwip/port/esp32xx/include -iwithprefixbefore lwip/port/esp32xx/include/arch -iwithprefixbefore espressif__mdns/include -iwithprefixbefore console -iwithprefixbefore vfs/include -iwithprefixbefore esp_netif/include -iwithprefixbefore esp_event/include -iwithprefixbefore esp_ringbuf/include -iwithprefixbefore efuse/include -iwithprefixbefore efuse/esp32s3/include -iwithprefixbefore driver/include -iwithprefixbefore driver/deprecated -iwithprefixbefore driver/analog_comparator/include -iwithprefixbefore driver/dac/include -iwithprefixbefore driver/gpio/include -iwithprefixbefore driver/gptimer/include -iwithprefixbefore driver/i2c/include -iwithprefixbefore driver/i2s/include -iwithprefixbefore driver/ledc/include -iwithprefixbefore driver/mcpwm/include -iwithprefixbefore driver/parlio/include -iwithprefixbefore driver/pcnt/include -iwithprefixbefore driver/rmt/include -iwithprefixbefore driver/sdio_slave/include -iwithprefixbefore driver/sdmmc/include -iwithprefixbefore driver/sigma_delta/include -iwithprefixbefore driver/spi/include -iwithprefixbefore driver/temperature_sensor/include -iwithprefixbefore driver/touch_sensor/include -iwithprefixbefore driver/twai/include -iwithprefixbefore driver/uart/include -iwithprefixbefore driver/usb_serial_jtag/include -iwithprefixbefore driver/touch_sensor/esp32s3/include -iwithprefixbefore esp_pm/include -iwithprefixbefore mbedtls/port/include -iwithprefixbefore mbedtls/mbedtls/include -iwithprefixbefore mbedtls/mbedtls/library -iwithprefixbefore mbedtls/esp_crt_bundle/include -iwithprefixbefore esp_app_format/include -iwithprefixbefore bootloader_support/include -iwithprefixbefore bootloader_support/bootloader_flash/include -iwithprefixbefore esp_partition/include -iwithprefixbefore app_update/include -iwithprefixbefore esp_mm/include -iwithprefixbefore spi_flash/include -iwithprefixbefore pthread/include -iwithprefixbefore esp_timer/include -iwithprefixbefore app_trace/include -iwithprefixbefore nvs_flash/include -iwithprefixbefore esp_phy/include -iwithprefixbefore esp_phy/esp32s3/include -iwithprefixbefore wpa_supplicant/include -iwithprefixbefore wpa_supplicant/port/include -iwithprefixbefore wpa_supplicant/esp_supplicant/include -iwithprefixbefore esp_coex/include -iwithprefixbefore esp_wifi/include -iwithprefixbefore esp_wifi/wifi_apps/include -iwithprefixbefore bt/include/esp32c3/include -iwithprefixbefore bt/common/osi/include -iwithprefixbefore bt/common/api/include/api -iwithprefixbefore bt/common/btc/profile/esp/blufi/include -iwithprefixbefore bt/common/btc/profile/esp/include -iwithprefixbefore bt/host/bluedroid/api/include/api -iwithprefixbefore bt/esp_ble_mesh/mesh_common/include -iwithprefixbefore bt/esp_ble_mesh/mesh_common/tinycrypt/include -iwithprefixbefore bt/esp_ble_mesh/mesh_core -iwithprefixbefore bt/esp_ble_mesh/mesh_core/include -iwithprefixbefore bt/esp_ble_mesh/mesh_core/storage -iwithprefixbefore bt/esp_ble_mesh/btc/include -iwithprefixbefore bt/esp_ble_mesh/mesh_models/common/include -iwithprefixbefore bt/esp_ble_mesh/mesh_models/client/include -iwithprefixbefore bt/esp_ble_mesh/mesh_models/server/include -iwithprefixbefore bt/esp_ble_mesh/api/core/include -iwithprefixbefore bt/esp_ble_mesh/api/models/include -iwithprefixbefore bt/esp_ble_mesh/api -iwithprefixbefore bt/porting/ext/tinycrypt/include -iwithprefixbefore unity/include -iwithprefixbefore unity/unity/src -iwithprefixbefore cmock/CMock/src -iwithprefixbefore http_parser -iwithprefixbefore esp-tls -iwithprefixbefore esp-tls/esp-tls-crypto -iwithprefixbefore esp_adc/include -iwithprefixbefore esp_adc/interface -iwithprefixbefore esp_adc/esp32s3/include -iwithprefixbefore esp_adc/deprecated/include -iwithprefixbefore esp_eth/include -iwithprefixbefore esp_gdbstub/include -iwithprefixbefore esp_gdbstub/xtensa -iwithprefixbefore esp_gdbstub/esp32s3 -iwithprefixbefore esp_hid/include -iwithprefixbefore tcp_transport/include -iwithprefixbefore esp_http_client/include -iwithprefixbefore esp_http_server/include -iwithprefixbefore esp_https_ota/include -iwithprefixbefore esp_https_server/include -iwithprefixbefore esp_psram/include -iwithprefixbefore esp_lcd/include -iwithprefixbefore esp_lcd/interface -iwithprefixbefore protobuf-c/protobuf-c -iwithprefixbefore protocomm/include/common -iwithprefixbefore protocomm/include/security -iwithprefixbefore protocomm/include/transports -iwithprefixbefore esp_local_ctrl/include -iwithprefixbefore espcoredump/include -iwithprefixbefore espcoredump/include/port/xtensa -iwithprefixbefore wear_levelling/include -iwithprefixbefore sdmmc/include -iwithprefixbefore fatfs/diskio -iwithprefixbefore fatfs/vfs -iwithprefixbefore fatfs/src -iwithprefixbefore idf_test/include -iwithprefixbefore idf_test/include/esp32s3 -iwithprefixbefore ieee802154/include -iwithprefixbefore json/cJSON -iwithprefixbefore mqtt/esp-mqtt/include -iwithprefixbefore perfmon/include -iwithprefixbefore spiffs/include -iwithprefixbefore touch_element/include -iwithprefixbefore ulp/ulp_common/include -iwithprefixbefore ulp/ulp_common/include/esp32s3 -iwithprefixbefore usb/include -iwithprefixbefore wifi_provisioning/include -iwithprefixbefore cbor/port/include -iwithprefixbefore rmaker_common/include -iwithprefixbefore esp_diagnostics/include -iwithprefixbefore rtc_store/include -iwithprefixbefore esp_insights/include -iwithprefixbefore json_parser/upstream/include -iwithprefixbefore json_parser/upstream -iwithprefixbefore json_generator/upstream -iwithprefixbefore esp_schedule/include -iwithprefixbefore espressif__esp_secure_cert_mgr/include -iwithprefixbefore esp_rainmaker/include -iwithprefixbefore gpio_button/button/include -iwithprefixbefore qrcode/include -iwithprefixbefore ws2812_led -iwithprefixbefore freertos/FreeRTOS-Kernel/include/freertos -iwithprefixbefore arduino_tinyusb/tinyusb/src -iwithprefixbefore arduino_tinyusb/include -iwithprefixbefore esp_littlefs/include -iwithprefixbefore esp-dl/include -iwithprefixbefore esp-dl/include/tool -iwithprefixbefore esp-dl/include/typedef -iwithprefixbefore esp-dl/include/image -iwithprefixbefore esp-dl/include/math -iwithprefixbefore esp-dl/include/nn -iwithprefixbefore esp-dl/include/layer -iwithprefixbefore esp-dl/include/detect -iwithprefixbefore esp-dl/include/model_zoo -iwithprefixbefore espressif__esp-dsp/modules/dotprod/include -iwithprefixbefore espressif__esp-dsp/modules/support/include -iwithprefixbefore espressif__esp-dsp/modules/windows/include -iwithprefixbefore espressif__esp-dsp/modules/windows/hann/include -iwithprefixbefore espressif__esp-dsp/modules/windows/blackman/include -iwithprefixbefore espressif__esp-dsp/modules/windows/blackman_harris/include -iwithprefixbefore espressif__esp-dsp/modules/windows/blackman_nuttall/include -iwithprefixbefore espressif__esp-dsp/modules/windows/nuttall/include -iwithprefixbefore espressif__esp-dsp/modules/windows/flat_top/include -iwithprefixbefore espressif__esp-dsp/modules/iir/include -iwithprefixbefore espressif__esp-dsp/modules/fir/include -iwithprefixbefore espressif__esp-dsp/modules/math/include -iwithprefixbefore espressif__esp-dsp/modules/math/add/include -iwithprefixbefore espressif__esp-dsp/modules/math/sub/include -iwithprefixbefore espressif__esp-dsp/modules/math/mul/include -iwithprefixbefore espressif__esp-dsp/modules/math/addc/include -iwithprefixbefore espressif__esp-dsp/modules/math/mulc/include -iwithprefixbefore espressif__esp-dsp/modules/math/sqrt/include -iwithprefixbefore espressif__esp-dsp/modules/matrix/include -iwithprefixbefore espressif__esp-dsp/modules/fft/include -iwithprefixbefore espressif__esp-dsp/modules/dct/include -iwithprefixbefore espressif__esp-dsp/modules/conv/include -iwithprefixbefore espressif__esp-dsp/modules/common/include -iwithprefixbefore espressif__esp-dsp/modules/kalman/ekf/include -iwithprefixbefore espressif__esp-dsp/modules/kalman/ekf_imu13states/include -iwithprefixbefore esp-sr/src/include -iwithprefixbefore esp-sr/esp-tts/esp_tts_chinese/include -iwithprefixbefore esp-sr/include/esp32s3 -iwithprefixbefore esp32-camera/driver/include -iwithprefixbefore esp32-camera/conversions/include -iwithprefixbefore fb_gfx/include \ No newline at end of file diff --git a/tools/sdk/esp32s3/flags/ld_flags b/tools/sdk/esp32s3/flags/ld_flags index 0511080bbe8..9ccfa2b52ef 100644 --- a/tools/sdk/esp32s3/flags/ld_flags +++ b/tools/sdk/esp32s3/flags/ld_flags @@ -1 +1 @@ --mlongcalls -Wl,--cref -Wl,--defsym=IDF_TARGET_ESP32S3=0 -Wl,--no-warn-rwx-segments -fno-rtti -fno-lto -Wl,--gc-sections -Wl,--warn-common -Wl,--wrap=esp_log_write -Wl,--wrap=esp_log_writev -Wl,--wrap=log_printf -u _Z5setupv -u _Z4loopv -u esp_app_desc -u pthread_include_pthread_impl -u pthread_include_pthread_cond_impl -u pthread_include_pthread_local_storage_impl -u pthread_include_pthread_rwlock_impl -u ld_include_highint_hdl -u start_app -u start_app_other_cores -u __ubsan_include -Wl,--wrap=longjmp -u __assert_func -Wl,--undefined=uxTopUsedPriority -Wl,--undefined=FreeRTOS_openocd_params -u app_main -u newlib_include_heap_impl -u newlib_include_syscalls_impl -u newlib_include_pthread_impl -u newlib_include_assert_impl -u __cxa_guard_dummy -u include_esp_phy_override -u vfs_include_syscalls_impl \ No newline at end of file +-mlongcalls -Wl,--cref -Wl,--defsym=IDF_TARGET_ESP32S3=0 -Wl,--no-warn-rwx-segments -fno-rtti -fno-lto -Wl,--gc-sections -Wl,--warn-common -Wl,--wrap=esp_log_write -Wl,--wrap=esp_log_writev -Wl,--wrap=log_printf -u _Z5setupv -u _Z4loopv -u esp_app_desc -u pthread_include_pthread_impl -u pthread_include_pthread_cond_impl -u pthread_include_pthread_local_storage_impl -u pthread_include_pthread_rwlock_impl -u pthread_include_pthread_semaphore_impl -u ld_include_highint_hdl -u start_app -u start_app_other_cores -u __ubsan_include -Wl,--wrap=longjmp -u __assert_func -Wl,--undefined=uxTopUsedPriority -Wl,--undefined=FreeRTOS_openocd_params -u app_main -u newlib_include_heap_impl -u newlib_include_syscalls_impl -u newlib_include_pthread_impl -u newlib_include_assert_impl -u __cxa_guard_dummy -u include_esp_phy_override -u vfs_include_syscalls_impl \ No newline at end of file diff --git a/tools/sdk/esp32s3/flags/ld_libs b/tools/sdk/esp32s3/flags/ld_libs index 1c14654f8d8..58329f37520 100644 --- a/tools/sdk/esp32s3/flags/ld_libs +++ b/tools/sdk/esp32s3/flags/ld_libs @@ -1 +1 @@ --lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lapp_trace -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lbt -lunity -lcmock -lconsole -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -lesp_hid -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_https_server -lesp_lcd -lprotobuf-c -lprotocomm -lesp_local_ctrl -lesp_psram -lespcoredump -lwear_levelling -lsdmmc -lfatfs -ljson -lmqtt -lperfmon -lspiffs -ltouch_element -lulp -lusb -lwifi_provisioning -lespressif__mdns -lcbor -lrmaker_common -lesp_diagnostics -lrtc_store -lesp_insights -ljson_parser -ljson_generator -lesp_schedule -lespressif__esp_secure_cert_mgr -lesp_rainmaker -lgpio_button -lqrcode -lws2812_led -larduino_tinyusb -lesp-sr -lesp32-camera -lesp_littlefs -lespressif__esp-dsp -lfb_gfx -lapp_trace -lapp_trace -lcmock -lunity -lesp_lcd -lperfmon -ltouch_element -lusb -lesp_hid -lfatfs -lwear_levelling -lsdmmc -lesp_insights -lcbor -lesp_diagnostics -lrtc_store -lesp_rainmaker -lesp_local_ctrl -lesp_https_server -lwifi_provisioning -lprotocomm -lbt -lbtdm_app -lprotobuf-c -lespressif__mdns -ljson_parser -ljson_generator -lesp_schedule -lespressif__esp_secure_cert_mgr -lqrcode -lrmaker_common -lconsole -lmqtt -lcat_face_detect -lhuman_face_detect -lcolor_detect -lmfn -ldl -lhufzip -lesp_audio_front_end -lesp_audio_processor -lmultinet -lwakenet -lesp-sr -lhufzip -lesp_audio_front_end -lesp_audio_processor -lmultinet -lwakenet -ljson -lspiffs -ldl_lib -lfst -lc_speech_features -lespressif__esp-dsp -lesp_tts_chinese -lvoice_set_xiaole -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxt_hal -lc -lm -lnewlib -lstdc++ -lpthread -lgcc -lcxx -lphy -lbtbb -lesp_phy -lphy -lbtbb -lesp_phy -lphy -lbtbb \ No newline at end of file +-lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lapp_trace -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lbt -lunity -lcmock -lconsole -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -lesp_hid -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_https_server -lesp_psram -lesp_lcd -lprotobuf-c -lprotocomm -lesp_local_ctrl -lespcoredump -lwear_levelling -lsdmmc -lfatfs -ljson -lmqtt -lperfmon -lspiffs -ltouch_element -lulp -lusb -lwifi_provisioning -lespressif__mdns -lcbor -lrmaker_common -lesp_diagnostics -lrtc_store -lesp_insights -ljson_parser -ljson_generator -lesp_schedule -lespressif__esp_secure_cert_mgr -lesp_rainmaker -lgpio_button -lqrcode -lws2812_led -larduino_tinyusb -lespressif__esp-dsp -lesp-sr -lesp32-camera -lesp_littlefs -lfb_gfx -lapp_trace -lapp_trace -lcmock -lunity -lesp_lcd -lperfmon -ltouch_element -lusb -lesp_hid -lfatfs -lwear_levelling -lsdmmc -lesp_insights -lcbor -lesp_diagnostics -lrtc_store -lesp_rainmaker -lesp_local_ctrl -lesp_https_server -lwifi_provisioning -lprotocomm -lbt -lbtdm_app -lprotobuf-c -lespressif__mdns -ljson_parser -ljson_generator -lesp_schedule -lespressif__esp_secure_cert_mgr -lqrcode -lrmaker_common -lconsole -lmqtt -lcat_face_detect -lhuman_face_detect -lcolor_detect -lmfn -ldl -lhufzip -lesp_audio_front_end -lesp_audio_processor -lmultinet -lwakenet -lesp-sr -lhufzip -lesp_audio_front_end -lesp_audio_processor -lmultinet -lwakenet -ljson -lspiffs -lespressif__esp-dsp -ldl_lib -lfst -lc_speech_features -lespressif__esp-dsp -lesp_tts_chinese -lvoice_set_xiaole -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxtensa -lesp_ringbuf -lefuse -ldriver -lesp_pm -lmbedtls -lesp_app_format -lbootloader_support -lesp_partition -lapp_update -lesp_mm -lspi_flash -lpthread -lesp_system -lesp_rom -lhal -llog -lheap -lsoc -lesp_hw_support -lfreertos -lnewlib -lcxx -lesp_common -lesp_timer -lesp_event -lnvs_flash -lesp_phy -lvfs -llwip -lesp_netif -lwpa_supplicant -lesp_coex -lesp_wifi -lhttp_parser -lesp-tls -lesp_adc -lesp_eth -lesp_gdbstub -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_psram -lespcoredump -lulp -lmbedtls_2 -lmbedcrypto -lmbedx509 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lsmartconfig -lwapi -lxt_hal -lc -lm -lnewlib -lstdc++ -lpthread -lgcc -lcxx -lphy -lbtbb -lesp_phy -lphy -lbtbb -lesp_phy -lphy -lbtbb \ No newline at end of file diff --git a/tools/sdk/esp32s3/include/bootloader_support/include/bootloader_common.h b/tools/sdk/esp32s3/include/bootloader_support/include/bootloader_common.h index 6145a72ef8e..b74acf560c7 100644 --- a/tools/sdk/esp32s3/include/bootloader_support/include/bootloader_common.h +++ b/tools/sdk/esp32s3/include/bootloader_support/include/bootloader_common.h @@ -173,7 +173,7 @@ esp_err_t bootloader_common_check_chip_validity(const esp_image_header_t* img_hd */ void bootloader_common_vddsdio_configure(void); -#if defined( CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP ) || defined( CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC ) +#if CONFIG_BOOTLOADER_RESERVE_RTC_MEM /** * @brief Returns partition from rtc_retain_mem * @@ -223,6 +223,21 @@ void bootloader_common_reset_rtc_retain_mem(void); */ uint16_t bootloader_common_get_rtc_retain_mem_reboot_counter(void); +/** + * @brief Returns True if Factory reset has happened + * + * Reset the status after reading it. + * + * @return True: Factory reset has happened + * False: No Factory reset + */ +bool bootloader_common_get_rtc_retain_mem_factory_reset_state(void); + +/** + * @brief Sets Factory reset status + */ +void bootloader_common_set_rtc_retain_mem_factory_reset_state(void); + /** * @brief Returns rtc_retain_mem * @@ -233,7 +248,7 @@ uint16_t bootloader_common_get_rtc_retain_mem_reboot_counter(void); */ rtc_retain_mem_t* bootloader_common_get_rtc_retain_mem(void); -#endif +#endif // CONFIG_BOOTLOADER_RESERVE_RTC_MEM #ifdef __cplusplus } diff --git a/tools/sdk/esp32s3/include/bootloader_support/include/esp_image_format.h b/tools/sdk/esp32s3/include/bootloader_support/include/esp_image_format.h index 20545f5d7f6..5ec2ff0282f 100644 --- a/tools/sdk/esp32s3/include/bootloader_support/include/esp_image_format.h +++ b/tools/sdk/esp32s3/include/bootloader_support/include/esp_image_format.h @@ -47,7 +47,14 @@ typedef enum { typedef struct { esp_partition_pos_t partition; /*!< Partition of application which worked before goes to the deep sleep. */ uint16_t reboot_counter; /*!< Reboot counter. Reset only when power is off. */ - uint16_t reserve; /*!< Reserve */ + union { + struct { + uint8_t factory_reset_state : 1; /* True when Factory reset has occurred */ + uint8_t reserve : 7; /* Reserve */ + }; + uint8_t val; + } flags; + uint8_t reserve; /*!< Reserve */ #ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC uint8_t custom[CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE]; /*!< Reserve for custom propose */ #endif @@ -57,6 +64,8 @@ typedef struct { ESP_STATIC_ASSERT(offsetof(rtc_retain_mem_t, crc) == sizeof(rtc_retain_mem_t) - sizeof(uint32_t), "CRC field must be the last field of rtc_retain_mem_t structure"); +#ifdef CONFIG_BOOTLOADER_RESERVE_RTC_MEM + #ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC ESP_STATIC_ASSERT(CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE % 4 == 0, "CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE must be a multiple of 4 bytes"); /* The custom field must be the penultimate field */ @@ -64,19 +73,16 @@ ESP_STATIC_ASSERT(offsetof(rtc_retain_mem_t, custom) == sizeof(rtc_retain_mem_t) "custom field in rtc_retain_mem_t structure must be the field before the CRC one"); #endif -#if defined(CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP) || defined(CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC) ESP_STATIC_ASSERT(CONFIG_BOOTLOADER_RESERVE_RTC_SIZE % 4 == 0, "CONFIG_BOOTLOADER_RESERVE_RTC_SIZE must be a multiple of 4 bytes"); -#endif #ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC #define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE + CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE) -#elif defined(CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP) +#else #define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE) #endif -#if defined(CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP) || defined(CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC) ESP_STATIC_ASSERT(sizeof(rtc_retain_mem_t) <= ESP_BOOTLOADER_RESERVE_RTC, "Reserved RTC area must exceed size of rtc_retain_mem_t"); -#endif +#endif // CONFIG_BOOTLOADER_RESERVE_RTC_MEM /** * @brief Verify an app image. diff --git a/tools/sdk/esp32s3/include/bt/host/bluedroid/api/include/api/esp_gap_bt_api.h b/tools/sdk/esp32s3/include/bt/host/bluedroid/api/include/api/esp_gap_bt_api.h index 76197f81a3e..78d31125ce8 100644 --- a/tools/sdk/esp32s3/include/bt/host/bluedroid/api/include/api/esp_gap_bt_api.h +++ b/tools/sdk/esp32s3/include/bt/host/bluedroid/api/include/api/esp_gap_bt_api.h @@ -576,7 +576,9 @@ esp_err_t esp_bt_gap_config_eir_data(esp_bt_eir_data_t *eir_data); /** * @brief This function is called to set class of device. * The structure esp_bt_gap_cb_t will be called with ESP_BT_GAP_SET_COD_EVT after set COD ends. - * Some profile have special restrictions on class of device, changes may cause these profile do not work. + * This function should be called after Bluetooth profiles are initialized, otherwise the user configured + * class of device can be overwritten. + * Some profiles have special restrictions on class of device, and changes may make these profiles unable to work. * * @param[in] cod - class of device * @param[in] mode - setting mode diff --git a/tools/sdk/esp32s3/include/driver/include/esp_private/spi_common_internal.h b/tools/sdk/esp32s3/include/driver/include/esp_private/spi_common_internal.h index 83b9c1ad6b3..6cc711b5224 100644 --- a/tools/sdk/esp32s3/include/driver/include/esp_private/spi_common_internal.h +++ b/tools/sdk/esp32s3/include/driver/include/esp_private/spi_common_internal.h @@ -13,6 +13,10 @@ #include "freertos/FreeRTOS.h" #include "hal/spi_types.h" #include "esp_pm.h" +#if SOC_GDMA_SUPPORTED +#include "esp_private/gdma.h" +#endif + #ifdef __cplusplus extern "C" @@ -130,6 +134,22 @@ esp_err_t spicommon_dma_chan_alloc(spi_host_device_t host_id, spi_dma_chan_t dma */ esp_err_t spicommon_dma_chan_free(spi_host_device_t host_id); +#if SOC_GDMA_SUPPORTED +/** + * @brief Get SPI GDMA Handle for GMDA Supported Chip + * + * @param host_id SPI host ID + * @param gdma_handle GDMA Handle to Return + * @param gdma_direction GDMA Channel Direction in Enum + * - GDMA_CHANNEL_DIRECTION_TX + * - GDMA_CHANNEL_DIRECTION_RX + * + * @return + * - ESP_OK: On success + */ +esp_err_t spicommon_gdma_get_handle(spi_host_device_t host_id, gdma_channel_handle_t *gdma_handle, gdma_channel_direction_t gdma_direction); +#endif + /** * @brief Connect a SPI peripheral to GPIO pins * diff --git a/tools/sdk/esp32s3/include/driver/ledc/include/driver/ledc.h b/tools/sdk/esp32s3/include/driver/ledc/include/driver/ledc.h index 509b81634d3..c0e2f14530f 100644 --- a/tools/sdk/esp32s3/include/driver/ledc/include/driver/ledc.h +++ b/tools/sdk/esp32s3/include/driver/ledc/include/driver/ledc.h @@ -450,10 +450,10 @@ esp_err_t ledc_fade_start(ledc_mode_t speed_mode, ledc_channel_t channel, ledc_f #if SOC_LEDC_SUPPORT_FADE_STOP /** - * @brief Stop LEDC fading. Duty of the channel will stay at its present vlaue. + * @brief Stop LEDC fading. The duty of the channel is garanteed to be fixed at most one PWM cycle after the function returns. * @note This API can be called if a new fixed duty or a new fade want to be set while the last fade operation is still running in progress. * @note Call this API will abort the fading operation only if it was started by calling ledc_fade_start with LEDC_FADE_NO_WAIT mode. - * @note If a fade was started with LEDC_FADE_WAIT_DONE mode, calling this API afterwards is no use in stopping the fade. Fade will continue until it reachs the target duty. + * @note If a fade was started with LEDC_FADE_WAIT_DONE mode, calling this API afterwards HAS no use in stopping the fade. Fade will continue until it reachs the target duty. * @param speed_mode Select the LEDC channel group with specified speed mode. Note that not all targets support high speed mode. * @param channel LEDC channel number * diff --git a/tools/sdk/esp32s3/include/driver/rmt/include/driver/rmt_rx.h b/tools/sdk/esp32s3/include/driver/rmt/include/driver/rmt_rx.h index c750a59a734..ddb409d94a7 100644 --- a/tools/sdk/esp32s3/include/driver/rmt/include/driver/rmt_rx.h +++ b/tools/sdk/esp32s3/include/driver/rmt/include/driver/rmt_rx.h @@ -29,10 +29,12 @@ typedef struct { * @brief RMT RX channel specific configuration */ typedef struct { - int gpio_num; /*!< GPIO number used by RMT RX channel. Set to -1 if unused */ + gpio_num_t gpio_num; /*!< GPIO number used by RMT RX channel. Set to -1 if unused */ rmt_clock_source_t clk_src; /*!< Clock source of RMT RX channel, channels in the same group must use the same clock source */ uint32_t resolution_hz; /*!< Channel clock resolution, in Hz */ - size_t mem_block_symbols; /*!< Size of memory block, in number of `rmt_symbol_word_t`, must be an even */ + size_t mem_block_symbols; /*!< Size of memory block, in number of `rmt_symbol_word_t`, must be an even. + In the DMA mode, this field controls the DMA buffer size, it can be set to a large value (e.g. 1024); + In the normal mode, this field controls the number of RMT memory block that will be used by the channel. */ struct { uint32_t invert_in: 1; /*!< Whether to invert the incoming RMT channel signal */ uint32_t with_dma: 1; /*!< If set, the driver will allocate an RMT channel with DMA capability */ diff --git a/tools/sdk/esp32s3/include/driver/rmt/include/driver/rmt_tx.h b/tools/sdk/esp32s3/include/driver/rmt/include/driver/rmt_tx.h index 83b1cef392e..9444ae3aabc 100644 --- a/tools/sdk/esp32s3/include/driver/rmt/include/driver/rmt_tx.h +++ b/tools/sdk/esp32s3/include/driver/rmt/include/driver/rmt_tx.h @@ -30,10 +30,12 @@ typedef struct { * @brief RMT TX channel specific configuration */ typedef struct { - int gpio_num; /*!< GPIO number used by RMT TX channel. Set to -1 if unused */ + gpio_num_t gpio_num; /*!< GPIO number used by RMT TX channel. Set to -1 if unused */ rmt_clock_source_t clk_src; /*!< Clock source of RMT TX channel, channels in the same group must use the same clock source */ uint32_t resolution_hz; /*!< Channel clock resolution, in Hz */ - size_t mem_block_symbols; /*!< Size of memory block, in number of `rmt_symbol_word_t`, must be an even */ + size_t mem_block_symbols; /*!< Size of memory block, in number of `rmt_symbol_word_t`, must be an even. + In the DMA mode, this field controls the DMA buffer size, it can be set to a large value; + In the normal mode, this field controls the number of RMT memory block that will be used by the channel. */ size_t trans_queue_depth; /*!< Depth of internal transfer queue, increase this value can support more transfers pending in the background */ struct { uint32_t invert_out: 1; /*!< Whether to invert the RMT channel signal before output to GPIO pad */ diff --git a/tools/sdk/esp32s3/include/driver/rmt/include/driver/rmt_types.h b/tools/sdk/esp32s3/include/driver/rmt/include/driver/rmt_types.h index 2dea896ea67..63032d4d994 100644 --- a/tools/sdk/esp32s3/include/driver/rmt/include/driver/rmt_types.h +++ b/tools/sdk/esp32s3/include/driver/rmt/include/driver/rmt_types.h @@ -10,6 +10,7 @@ #include #include #include "hal/rmt_types.h" +#include "hal/gpio_types.h" // for gpio_num_t #ifdef __cplusplus extern "C" { diff --git a/tools/sdk/esp32s3/include/driver/sdmmc/include/driver/sdmmc_host.h b/tools/sdk/esp32s3/include/driver/sdmmc/include/driver/sdmmc_host.h index 1a4beb892a4..46b6f6af366 100644 --- a/tools/sdk/esp32s3/include/driver/sdmmc/include/driver/sdmmc_host.h +++ b/tools/sdk/esp32s3/include/driver/sdmmc/include/driver/sdmmc_host.h @@ -40,6 +40,7 @@ extern "C" { .get_bus_width = &sdmmc_host_get_slot_width, \ .set_bus_ddr_mode = &sdmmc_host_set_bus_ddr_mode, \ .set_card_clk = &sdmmc_host_set_card_clk, \ + .set_cclk_always_on = &sdmmc_host_set_cclk_always_on, \ .do_transaction = &sdmmc_host_do_transaction, \ .deinit = &sdmmc_host_deinit, \ .io_int_enable = sdmmc_host_io_int_enable, \ @@ -204,6 +205,19 @@ esp_err_t sdmmc_host_set_card_clk(int slot, uint32_t freq_khz); */ esp_err_t sdmmc_host_set_bus_ddr_mode(int slot, bool ddr_enabled); +/** + * @brief Enable or disable always-on card clock + * When cclk_always_on is false, the host controller is allowed to shut down + * the card clock between the commands. When cclk_always_on is true, the clock + * is generated even if no command is in progress. + * @param slot slot number + * @param cclk_always_on enable or disable always-on clock + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_ARG if the slot number is invalid + */ +esp_err_t sdmmc_host_set_cclk_always_on(int slot, bool cclk_always_on); + /** * @brief Send command to the card and get response * diff --git a/tools/sdk/esp32s3/include/driver/sdmmc/include/driver/sdmmc_types.h b/tools/sdk/esp32s3/include/driver/sdmmc/include/driver/sdmmc_types.h index 8a38d792e3a..bc74a38c1d5 100644 --- a/tools/sdk/esp32s3/include/driver/sdmmc/include/driver/sdmmc_types.h +++ b/tools/sdk/esp32s3/include/driver/sdmmc/include/driver/sdmmc_types.h @@ -175,6 +175,7 @@ typedef struct { size_t (*get_bus_width)(int slot); /*!< host function to get bus width */ esp_err_t (*set_bus_ddr_mode)(int slot, bool ddr_enable); /*!< host function to set DDR mode */ esp_err_t (*set_card_clk)(int slot, uint32_t freq_khz); /*!< host function to set card clock frequency */ + esp_err_t (*set_cclk_always_on)(int slot, bool cclk_always_on); /*!< host function to set whether the clock is always enabled */ esp_err_t (*do_transaction)(int slot, sdmmc_command_t* cmdinfo); /*!< host function to do a transaction */ union { esp_err_t (*deinit)(void); /*!< host function to deinitialize the driver */ diff --git a/tools/sdk/esp32s3/include/driver/spi/include/driver/sdspi_host.h b/tools/sdk/esp32s3/include/driver/spi/include/driver/sdspi_host.h index 3b127fbfefb..146cff69cd3 100644 --- a/tools/sdk/esp32s3/include/driver/spi/include/driver/sdspi_host.h +++ b/tools/sdk/esp32s3/include/driver/spi/include/driver/sdspi_host.h @@ -45,6 +45,7 @@ typedef int sdspi_dev_handle_t; .get_bus_width = NULL, \ .set_bus_ddr_mode = NULL, \ .set_card_clk = &sdspi_host_set_card_clk, \ + .set_cclk_always_on = NULL, \ .do_transaction = &sdspi_host_do_transaction, \ .deinit_p = &sdspi_host_remove_device, \ .io_int_enable = &sdspi_host_io_int_enable, \ diff --git a/tools/sdk/esp32s3/include/driver/uart/include/driver/uart.h b/tools/sdk/esp32s3/include/driver/uart/include/driver/uart.h index ba5f49306ea..314adf172dd 100644 --- a/tools/sdk/esp32s3/include/driver/uart/include/driver/uart.h +++ b/tools/sdk/esp32s3/include/driver/uart/include/driver/uart.h @@ -766,8 +766,10 @@ esp_err_t uart_get_collision_flag(uart_port_t uart_num, bool* collision_flag); * The character that triggers wakeup is not received by UART (i.e. it can not * be obtained from UART FIFO). Depending on the baud rate, a few characters * after that will also not be received. Note that when the chip enters and exits - * light sleep mode, APB frequency will be changing. To make sure that UART has - * correct baud rate all the time, select UART_SCLK_REF_TICK or UART_SCLK_XTAL as UART clock source in uart_config_t::source_clk. + * light sleep mode, APB frequency will be changing. To ensure that UART has + * correct Baud rate all the time, it is necessary to select a source clock which has + * a fixed frequency and remains active during sleep. For the supported clock sources + * of the chips, please refer to `uart_sclk_t` or `soc_periph_uart_clk_src_legacy_t` * * @note in ESP32, the wakeup signal can only be input via IO_MUX (i.e. * GPIO3 should be configured as function_1 to wake up UART0, diff --git a/tools/sdk/esp32s3/include/efuse/esp32s3/include/esp_efuse_table.h b/tools/sdk/esp32s3/include/efuse/esp32s3/include/esp_efuse_table.h index 93be6aae498..f34fce781a9 100644 --- a/tools/sdk/esp32s3/include/efuse/esp32s3/include/esp_efuse_table.h +++ b/tools/sdk/esp32s3/include/efuse/esp32s3/include/esp_efuse_table.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,7 +10,7 @@ extern "C" { #include "esp_efuse.h" -// md5_digest_table 87c5ae68b74dbafb114e14f6febff9e2 +// md5_digest_table 7f80667718451ae522bb4d60ced03d49 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -19,54 +19,166 @@ extern "C" { extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DCACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_ICACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_DCACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG[]; +#define ESP_EFUSE_WR_DIS_DIS_USB ESP_EFUSE_WR_DIS_DIS_USB_OTG +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[]; +#define ESP_EFUSE_WR_DIS_DIS_CAN ESP_EFUSE_WR_DIS_DIS_TWAI +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_APP_CPU[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[]; +#define ESP_EFUSE_WR_DIS_HARD_DIS_JTAG ESP_EFUSE_WR_DIS_DIS_PAD_JTAG +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG[]; +#define ESP_EFUSE_WR_DIS_DIS_USB_DEVICE ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_STRAP_JTAG_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_PHY_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_XPD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_TIEH[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_FORCE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[]; +#define ESP_EFUSE_WR_DIS_KEY0_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_0 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[]; +#define ESP_EFUSE_WR_DIS_KEY1_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_1 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[]; +#define ESP_EFUSE_WR_DIS_KEY2_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_2 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[]; +#define ESP_EFUSE_WR_DIS_KEY3_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_3 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[]; +#define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[]; +#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[]; +#define ESP_EFUSE_WR_DIS_DIS_LEGACY_SPI_BOOT ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[]; +#define ESP_EFUSE_WR_DIS_UART_PRINT_CHANNEL ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[]; +#define ESP_EFUSE_WR_DIS_DIS_USB_DOWNLOAD_MODE ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PIN_POWER_SELECTION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TYPE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_PAGE_SIZE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[]; +#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CLK[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_Q[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_HD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_WP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_DQS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D4[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D5[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D6[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D7[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_LO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_K_RTC_LDO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_K_DIG_LDO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_V_RTC_DBIAS20[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_V_DIG_DBIAS20[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIG_DBIAS_HVT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_HI[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CAL_VOL_ATTEN3[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_INIT_CODE_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_INIT_CODE_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_INIT_CODE_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_INIT_CODE_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CAL_VOL_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CAL_VOL_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CAL_VOL_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[]; +#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[]; +#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC +#define ESP_EFUSE_WR_DIS_USER_DATA_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[]; +#define ESP_EFUSE_WR_DIS_KEY0 ESP_EFUSE_WR_DIS_BLOCK_KEY0 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[]; +#define ESP_EFUSE_WR_DIS_KEY1 ESP_EFUSE_WR_DIS_BLOCK_KEY1 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[]; +#define ESP_EFUSE_WR_DIS_KEY2 ESP_EFUSE_WR_DIS_BLOCK_KEY2 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[]; +#define ESP_EFUSE_WR_DIS_KEY3 ESP_EFUSE_WR_DIS_BLOCK_KEY3 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[]; +#define ESP_EFUSE_WR_DIS_KEY4 ESP_EFUSE_WR_DIS_BLOCK_KEY4 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[]; +#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[]; +#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXT_PHY_ENABLE[]; +#define ESP_EFUSE_WR_DIS_EXT_PHY_ENABLE ESP_EFUSE_WR_DIS_USB_EXT_PHY_ENABLE +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[]; +#define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[]; +#define ESP_EFUSE_RD_DIS_KEY1 ESP_EFUSE_RD_DIS_BLOCK_KEY1 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[]; +#define ESP_EFUSE_RD_DIS_KEY2 ESP_EFUSE_RD_DIS_BLOCK_KEY2 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[]; +#define ESP_EFUSE_RD_DIS_KEY3 ESP_EFUSE_RD_DIS_BLOCK_KEY3 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[]; +#define ESP_EFUSE_RD_DIS_KEY4 ESP_EFUSE_RD_DIS_BLOCK_KEY4 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[]; +#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[]; +#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DCACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_DCACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG[]; +#define ESP_EFUSE_DIS_USB ESP_EFUSE_DIS_USB_OTG +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[]; +#define ESP_EFUSE_DIS_CAN ESP_EFUSE_DIS_TWAI extern const esp_efuse_desc_t* ESP_EFUSE_DIS_APP_CPU[]; extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_HARD_DIS_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[]; +#define ESP_EFUSE_HARD_DIS_JTAG ESP_EFUSE_DIS_PAD_JTAG extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[]; extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXT_PHY_ENABLE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_BTLC_GPIO_ENABLE[]; +#define ESP_EFUSE_EXT_PHY_ENABLE ESP_EFUSE_USB_EXT_PHY_ENABLE extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_XPD[]; extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_TIEH[]; extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_FORCE[]; @@ -76,23 +188,33 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[]; extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[]; +#define ESP_EFUSE_KEY0_PURPOSE ESP_EFUSE_KEY_PURPOSE_0 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[]; +#define ESP_EFUSE_KEY1_PURPOSE ESP_EFUSE_KEY_PURPOSE_1 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[]; +#define ESP_EFUSE_KEY2_PURPOSE ESP_EFUSE_KEY_PURPOSE_2 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[]; +#define ESP_EFUSE_KEY3_PURPOSE ESP_EFUSE_KEY_PURPOSE_3 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[]; +#define ESP_EFUSE_KEY4_PURPOSE ESP_EFUSE_KEY_PURPOSE_4 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[]; +#define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5 extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[]; +#define ESP_EFUSE_DIS_USB_DEVICE ESP_EFUSE_DIS_USB_SERIAL_JTAG extern const esp_efuse_desc_t* ESP_EFUSE_STRAP_JTAG_SEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_USB_PHY_SEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[]; +#define ESP_EFUSE_DIS_LEGACY_SPI_BOOT ESP_EFUSE_DIS_DIRECT_BOOT extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[]; +#define ESP_EFUSE_UART_PRINT_CHANNEL ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[]; +#define ESP_EFUSE_DIS_USB_DOWNLOAD_MODE ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[]; extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[]; extern const esp_efuse_desc_t* ESP_EFUSE_PIN_POWER_SELECTION[]; @@ -104,21 +226,28 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG_DOWNLOAD_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[]; +extern const esp_efuse_desc_t* ESP_EFUSE_MAC[]; +#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_LO[]; extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[]; +extern const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_HI[]; extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN3[]; extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; @@ -141,19 +270,24 @@ extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN0[]; extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN1[]; extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN2[]; extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[]; +#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[]; +#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_USER_DATA_MAC_CUSTOM +#define ESP_EFUSE_CUSTOM_MAC ESP_EFUSE_USER_DATA_MAC_CUSTOM extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[]; +#define ESP_EFUSE_BLOCK_KEY0 ESP_EFUSE_KEY0 extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[]; +#define ESP_EFUSE_BLOCK_KEY1 ESP_EFUSE_KEY1 extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[]; +#define ESP_EFUSE_BLOCK_KEY2 ESP_EFUSE_KEY2 extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[]; +#define ESP_EFUSE_BLOCK_KEY3 ESP_EFUSE_KEY3 extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[]; +#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4 extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[]; +#define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5 extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[]; -extern const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[]; -extern const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[]; -extern const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[]; +#define ESP_EFUSE_BLOCK_SYS_DATA2 ESP_EFUSE_SYS_DATA_PART2 #ifdef __cplusplus } diff --git a/tools/sdk/esp32s3/include/esp-tls/esp_tls.h b/tools/sdk/esp32s3/include/esp-tls/esp_tls.h index 3ada350379e..0efe587b53b 100644 --- a/tools/sdk/esp32s3/include/esp-tls/esp_tls.h +++ b/tools/sdk/esp32s3/include/esp-tls/esp_tls.h @@ -71,6 +71,15 @@ typedef struct tls_keep_alive_cfg { int keep_alive_count; /*!< Keep-alive packet retry send count */ } tls_keep_alive_cfg_t; +/* +* @brief ESP-TLS Address families +*/ +typedef enum esp_tls_addr_family { + ESP_TLS_AF_UNSPEC = 0, /**< Unspecified address family. */ + ESP_TLS_AF_INET, /**< IPv4 address family. */ + ESP_TLS_AF_INET6, /**< IPv6 address family. */ +} esp_tls_addr_family_t; + /** * @brief ESP-TLS configuration parameters * @@ -182,6 +191,8 @@ typedef struct esp_tls_cfg { #ifdef CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS esp_tls_client_session_t *client_session; /*! Pointer for the client session ticket context. */ #endif /* CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS */ + + esp_tls_addr_family_t addr_family; /*!< The address family to use when connecting to a host. */ } esp_tls_cfg_t; #ifdef CONFIG_ESP_TLS_SERVER diff --git a/tools/sdk/esp32s3/include/esp_coex/include/esp_coexist.h b/tools/sdk/esp32s3/include/esp_coex/include/esp_coexist.h index e3fb019d420..9ed897c28a7 100644 --- a/tools/sdk/esp32s3/include/esp_coex/include/esp_coexist.h +++ b/tools/sdk/esp32s3/include/esp_coex/include/esp_coexist.h @@ -201,6 +201,14 @@ esp_err_t esp_external_coex_set_validate_high(bool is_high_valid); #endif #endif +#if CONFIG_ESP_COEX_SW_COEXIST_ENABLE && CONFIG_SOC_IEEE802154_SUPPORTED +/** + * @brief Enable Wi-Fi and 802.15.4 coexistence. + * @return : ESP_OK - success, other - failed + */ +esp_err_t esp_coex_wifi_i154_enable(void); +#endif + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32s3/include/esp_coex/include/esp_coexist_adapter.h b/tools/sdk/esp32s3/include/esp_coex/include/esp_coexist_adapter.h index 11bf54d9b5e..fde83d1111d 100644 --- a/tools/sdk/esp32s3/include/esp_coex/include/esp_coexist_adapter.h +++ b/tools/sdk/esp32s3/include/esp_coex/include/esp_coexist_adapter.h @@ -38,7 +38,10 @@ typedef struct { void (* _free)(void *p); int64_t (* _esp_timer_get_time)(void); bool (* _env_is_chip)(void); +#if CONFIG_IDF_TARGET_ESP32C2 + // this function is only used on esp32c2 uint32_t (* _slowclk_cal_get)(void); +#endif void (* _timer_disarm)(void *timer); void (* _timer_done)(void *ptimer); void (* _timer_setfn)(void *ptimer, void *pfunction, void *parg); diff --git a/tools/sdk/esp32s3/include/esp_http_client/include/esp_http_client.h b/tools/sdk/esp32s3/include/esp_http_client/include/esp_http_client.h index 5638b7c6817..e1dbd5c8f1c 100644 --- a/tools/sdk/esp32s3/include/esp_http_client/include/esp_http_client.h +++ b/tools/sdk/esp32s3/include/esp_http_client/include/esp_http_client.h @@ -382,6 +382,34 @@ esp_err_t esp_http_client_set_password(esp_http_client_handle_t client, const ch */ esp_err_t esp_http_client_set_authtype(esp_http_client_handle_t client, esp_http_client_auth_type_t auth_type); +/** + * @brief Get http request user_data. + * The value stored from the esp_http_client_config_t will be written + * to the address passed into data. + * + * @param[in] client The esp_http_client handle + * @param[out] data A pointer to the pointer that will be set to user_data. + * + * @return + * - ESP_OK + * - ESP_ERR_INVALID_ARG + */ +esp_err_t esp_http_client_get_user_data(esp_http_client_handle_t client, void **data); + +/** + * @brief Set http request user_data. + * The value passed in +data+ will be available during event callbacks. + * No memory management will be performed on the user's behalf. + * + * @param[in] client The esp_http_client handle + * @param[in] data The pointer to the user data + * + * @return + * - ESP_OK + * - ESP_ERR_INVALID_ARG + */ +esp_err_t esp_http_client_set_user_data(esp_http_client_handle_t client, void *data); + /** * @brief Get HTTP client session errno * diff --git a/tools/sdk/esp32s3/include/esp_http_server/include/esp_http_server.h b/tools/sdk/esp32s3/include/esp_http_server/include/esp_http_server.h index 3826a40c9a3..39c2a82a31f 100644 --- a/tools/sdk/esp32s3/include/esp_http_server/include/esp_http_server.h +++ b/tools/sdk/esp32s3/include/esp_http_server/include/esp_http_server.h @@ -15,6 +15,7 @@ #include #include #include +#include #ifdef __cplusplus extern "C" { diff --git a/tools/sdk/esp32s3/include/esp_hw_support/include/esp_private/esp_modem_clock.h b/tools/sdk/esp32s3/include/esp_hw_support/include/esp_private/esp_modem_clock.h index 8b406550c66..bc678e039c3 100644 --- a/tools/sdk/esp32s3/include/esp_hw_support/include/esp_private/esp_modem_clock.h +++ b/tools/sdk/esp32s3/include/esp_hw_support/include/esp_private/esp_modem_clock.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,6 +10,7 @@ #include #include +#include "soc/soc_caps.h" #include "soc/periph_defs.h" #include "hal/modem_clock_types.h" diff --git a/tools/sdk/esp32s3/include/esp_hw_support/include/esp_private/gdma.h b/tools/sdk/esp32s3/include/esp_hw_support/include/esp_private/gdma.h index d71f3c6fc8a..bf5d97dd324 100644 --- a/tools/sdk/esp32s3/include/esp_hw_support/include/esp_private/gdma.h +++ b/tools/sdk/esp32s3/include/esp_hw_support/include/esp_private/gdma.h @@ -177,14 +177,28 @@ esp_err_t gdma_set_transfer_ability(gdma_channel_handle_t dma_chan, const gdma_t /** * @brief Apply channel strategy for GDMA channel * - * @param dma_chan GDMA channel handle, allocated by `gdma_new_channel` - * @param config Configuration of GDMA channel strategy + * @param[in] dma_chan GDMA channel handle, allocated by `gdma_new_channel` + * @param[in] config Configuration of GDMA channel strategy * - ESP_OK: Apply channel strategy successfully * - ESP_ERR_INVALID_ARG: Apply channel strategy failed because of invalid argument * - ESP_FAIL: Apply channel strategy failed because of other error */ esp_err_t gdma_apply_strategy(gdma_channel_handle_t dma_chan, const gdma_strategy_config_t *config); +/** + * @brief Set GDMA channel priority + * + * @note By default, all GDMA channels are with the same priority: 0. Channels with the same priority are served in round-robin manner. + * + * @param[in] dma_chan GDMA channel handle, allocated by `gdma_new_channel` + * @param[in] priority Priority of GDMA channel, higher value means higher priority + * @return + * - ESP_OK: Set GDMA channel priority successfully + * - ESP_ERR_INVALID_ARG: Set GDMA channel priority failed because of invalid argument, e.g. priority out of range [0,GDMA_LL_CHANNEL_MAX_PRIORITY] + * - ESP_FAIL: Set GDMA channel priority failed because of other error + */ +esp_err_t gdma_set_priority(gdma_channel_handle_t dma_chan, uint32_t priority); + /** * @brief Delete GDMA channel * @note If you call `gdma_new_channel` several times for a same peripheral, make sure you call this API the same times. @@ -251,6 +265,7 @@ esp_err_t gdma_register_rx_event_callbacks(gdma_channel_handle_t dma_chan, gdma_ * @return * - ESP_OK: Start DMA engine successfully * - ESP_ERR_INVALID_ARG: Start DMA engine failed because of invalid argument + * - ESP_ERR_INVALID_STATE: Start DMA engine failed because of invalid state, e.g. the channel is controlled by ETM, so can't start it manually * - ESP_FAIL: Start DMA engine failed because of other error */ esp_err_t gdma_start(gdma_channel_handle_t dma_chan, intptr_t desc_base_addr); @@ -265,6 +280,7 @@ esp_err_t gdma_start(gdma_channel_handle_t dma_chan, intptr_t desc_base_addr); * @return * - ESP_OK: Stop DMA engine successfully * - ESP_ERR_INVALID_ARG: Stop DMA engine failed because of invalid argument + * - ESP_ERR_INVALID_STATE: Stop DMA engine failed because of invalid state, e.g. the channel is controlled by ETM, so can't stop it manually * - ESP_FAIL: Stop DMA engine failed because of other error */ esp_err_t gdma_stop(gdma_channel_handle_t dma_chan); @@ -333,6 +349,7 @@ typedef struct { * @brief Get the ETM task for GDMA channel * * @note The created ETM task object can be deleted later by calling `esp_etm_del_task` + * @note If the GDMA task (e.g. start/stop) is controlled by ETM, then you can't use `gdma_start`/`gdma_stop` to control it. * * @param[in] dma_chan GDMA channel handle, allocated by `gdma_new_channel` * @param[in] config GDMA ETM task configuration diff --git a/tools/sdk/esp32s3/include/esp_hw_support/include/esp_private/sleep_modem.h b/tools/sdk/esp32s3/include/esp_hw_support/include/esp_private/sleep_modem.h index 7e11d88a9e6..7601aeebd82 100644 --- a/tools/sdk/esp32s3/include/esp_hw_support/include/esp_private/sleep_modem.h +++ b/tools/sdk/esp32s3/include/esp_hw_support/include/esp_private/sleep_modem.h @@ -42,6 +42,13 @@ void mac_bb_power_up_cb_execute(void); #if SOC_PM_SUPPORT_PMU_MODEM_STATE +/** + * @brief The retention action in the modem state of WiFi PHY module + * + * @param restore true for restore the PHY context, false for backup the PHY context + */ +void sleep_modem_wifi_do_phy_retention(bool restore); + /** * @brief Get WiFi modem state * diff --git a/tools/sdk/esp32s3/include/esp_hw_support/include/soc/esp32c2/memprot.h b/tools/sdk/esp32s3/include/esp_hw_support/include/soc/esp32c2/memprot.h deleted file mode 100644 index c7b1ad461e8..00000000000 --- a/tools/sdk/esp32s3/include/esp_hw_support/include/soc/esp32c2/memprot.h +++ /dev/null @@ -1,440 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - - -/* INTERNAL API - * generic interface to PMS memory protection features - */ - -#pragma once - -#include -#include -#include "esp_attr.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef IRAM_SRAM_START -#define IRAM_SRAM_START 0x4037C000 -#endif - -#ifndef DRAM_SRAM_START -#define DRAM_SRAM_START 0x3FC7C000 -#endif - -typedef enum { - MEMPROT_NONE = 0x00000000, - MEMPROT_IRAM0_SRAM = 0x00000001, - MEMPROT_DRAM0_SRAM = 0x00000002, - MEMPROT_ALL = 0xFFFFFFFF -} mem_type_prot_t; - -typedef enum { - MEMPROT_SPLITLINE_NONE = 0, - MEMPROT_IRAM0_DRAM0_SPLITLINE, - MEMPROT_IRAM0_LINE_0_SPLITLINE, - MEMPROT_IRAM0_LINE_1_SPLITLINE, - MEMPROT_DRAM0_DMA_LINE_0_SPLITLINE, - MEMPROT_DRAM0_DMA_LINE_1_SPLITLINE -} split_line_t; - -typedef enum { - MEMPROT_PMS_AREA_NONE = 0, - MEMPROT_IRAM0_PMS_AREA_0, - MEMPROT_IRAM0_PMS_AREA_1, - MEMPROT_IRAM0_PMS_AREA_2, - MEMPROT_IRAM0_PMS_AREA_3, - MEMPROT_DRAM0_PMS_AREA_0, - MEMPROT_DRAM0_PMS_AREA_1, - MEMPROT_DRAM0_PMS_AREA_2, - MEMPROT_DRAM0_PMS_AREA_3 -} pms_area_t; - -typedef enum -{ - MEMPROT_PMS_WORLD_0 = 0, - MEMPROT_PMS_WORLD_1, - MEMPROT_PMS_WORLD_2, - MEMPROT_PMS_WORLD_INVALID = 0xFFFFFFFF -} pms_world_t; - -typedef enum -{ - MEMPROT_PMS_OP_READ = 0, - MEMPROT_PMS_OP_WRITE, - MEMPROT_PMS_OP_FETCH, - MEMPROT_PMS_OP_INVALID = 0xFFFFFFFF -} pms_operation_type_t; - -/** - * @brief Converts Memory protection type to string - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - */ -const char *esp_memprot_mem_type_to_str(mem_type_prot_t mem_type); - -/** - * @brief Converts Split line type to string - * - * @param line_type Split line type (see split_line_t enum) - */ -const char *esp_memprot_split_line_to_str(split_line_t line_type); - -/** - * @brief Converts PMS Area type to string - * - * @param area_type PMS Area type (see pms_area_t enum) - */ -const char *esp_memprot_pms_to_str(pms_area_t area_type); - -/** - * @brief Returns PMS splitting address for given Split line type - * - * The value is taken from PMS configuration registers (IRam0 range) - * For details on split lines see 'esp_memprot_set_prot_int' function description - * - * @param line_type Split line type (see split_line_t enum) - * - * @return appropriate split line address - */ -uint32_t *esp_memprot_get_split_addr(split_line_t line_type); - -/** - * @brief Returns default main IRAM/DRAM splitting address - * - * The address value is given by _iram_text_end global (IRam0 range) - - * @return Main I/D split line (IRam0_DRam0_Split_Addr) - */ -void *esp_memprot_get_default_main_split_addr(void); - -/** - * @brief Sets a lock for the main IRAM/DRAM splitting address - * - * Locks can be unlocked only by digital system reset - */ -void esp_memprot_set_split_line_lock(void); - -/** - * @brief Gets a lock status for the main IRAM/DRAM splitting address - * - * @return true/false (locked/unlocked) - */ -bool esp_memprot_get_split_line_lock(void); - -/** - * @brief Sets required split line address - * - * @param line_type Split line type (see split_line_t enum) - * @param line_addr target address from a memory range relevant to given line_type (IRAM/DRAM) - */ -void esp_memprot_set_split_line(split_line_t line_type, const void *line_addr); - -/** - * @brief Sets a lock for PMS Area settings of required Memory type - * - * Locks can be unlocked only by digital system reset - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - */ -void esp_memprot_set_pms_lock(mem_type_prot_t mem_type); - -/** - * @brief Gets a lock status for PMS Area settings of required Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return true/false (locked/unlocked) - */ -bool esp_memprot_get_pms_lock(mem_type_prot_t mem_type); - -/** - * @brief Sets permissions for given PMS Area in IRam0 memory range (MEMPROT_IRAM0_SRAM) - * - * @param area_type IRam0 PMS Area type (see pms_area_t enum) - * @param r Read permission flag - * @param w Write permission flag - * @param x Execute permission flag - */ -void esp_memprot_iram_set_pms_area(pms_area_t area_type, bool r, bool w, bool x); - -/** - * @brief Gets current permissions for given PMS Area in IRam0 memory range (MEMPROT_IRAM0_SRAM) - * - * @param area_type IRam0 PMS Area type (see pms_area_t enum) - * @param r Read permission flag holder - * @param w Write permission flag holder - * @param x Execute permission flag holder - */ -void esp_memprot_iram_get_pms_area(pms_area_t area_type, bool *r, bool *w, bool *x); - -/** - * @brief Sets permissions for given PMS Area in DRam0 memory range (MEMPROT_DRAM0_SRAM) - * - * @param area_type DRam0 PMS Area type (see pms_area_t enum) - * @param r Read permission flag - * @param w Write permission flag - */ -void esp_memprot_dram_set_pms_area(pms_area_t area_type, bool r, bool w); - -/** - * @brief Gets current permissions for given PMS Area in DRam0 memory range (MEMPROT_DRAM0_SRAM) - * - * @param area_type DRam0 PMS Area type (see pms_area_t enum) - * @param r Read permission flag holder - * @param w Write permission flag holder - */ -void esp_memprot_dram_get_pms_area(pms_area_t area_type, bool *r, bool *w); - -/** - * @brief Sets a lock for PMS interrupt monitor settings of required Memory type - * - * Locks can be unlocked only by digital system reset - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - */ -void esp_memprot_set_monitor_lock(mem_type_prot_t mem_type); - -/** - * @brief Gets a lock status for PMS interrupt monitor settings of required Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return true/false (locked/unlocked) - */ -bool esp_memprot_get_monitor_lock(mem_type_prot_t mem_type); - -/** - * @brief Enable PMS violation interrupt monitoring of required Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * @param enable/disable - */ -void esp_memprot_set_monitor_en(mem_type_prot_t mem_type, bool enable); - -/** - * @brief Gets enable/disable status for PMS interrupt monitor settings of required Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return true/false (enabled/disabled) - */ -bool esp_memprot_get_monitor_en(mem_type_prot_t mem_type); - -/** - * @brief Gets CPU ID for currently active PMS violation interrupt - * - * @return CPU ID (CPU_PRO for ESP32-C2) - */ -int IRAM_ATTR esp_memprot_intr_get_cpuid(void); - -/** - * @brief Clears current interrupt ON flag for given Memory type - * - * Interrupt clearing happens in two steps: - * 1. Interrupt CLR flag is set (to clear the interrupt ON status) - * 2. Interrupt CLR flag is reset (to allow further monitoring) - * This operation is non-atomic by PMS module design - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - */ -void IRAM_ATTR esp_memprot_monitor_clear_intr(mem_type_prot_t mem_type); - -/** - * @brief Returns active PMS violation interrupt (if any) - * - * This function iterates through supported Memory type status registers - * and returns the first interrupt-on flag. If none is found active, - * MEMPROT_NONE is returned. - * Order of checking (in current version): - * 1. MEMPROT_IRAM0_SRAM - * 2. MEMPROT_DRAM0_SRAM - * - * @return mem_type Memory protection type related to active interrupt found (see mem_type_prot_t enum) - */ -mem_type_prot_t IRAM_ATTR esp_memprot_get_active_intr_memtype(void); - -/** - * @brief Checks whether any violation interrupt is active - * - * @return true/false (yes/no) - */ -bool IRAM_ATTR esp_memprot_is_locked_any(void); - -/** - * @brief Checks whether any violation interrupt is enabled - * - * @return true/false (yes/no) - */ -bool IRAM_ATTR esp_memprot_is_intr_ena_any(void); - -/** - * @brief Checks whether any violation interrupt is enabled - * - * @return true/false (yes/no) - */ -bool IRAM_ATTR esp_memprot_get_violate_intr_on(mem_type_prot_t mem_type); - -/** - * @brief Returns the address which caused the violation interrupt (if any) - * - * The address is taken from appropriate PMS violation status register, based given Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return faulting address - */ -uint32_t IRAM_ATTR esp_memprot_get_violate_addr(mem_type_prot_t mem_type); - -/** - * @brief Returns the World identifier of the code causing the violation interrupt (if any) - * - * The value is taken from appropriate PMS violation status register, based given Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return World identifier (see pms_world_t enum) - */ -pms_world_t IRAM_ATTR esp_memprot_get_violate_world(mem_type_prot_t mem_type); - -/** - * @brief Returns Read or Write operation type which caused the violation interrupt (if any) - * - * The value (bit) is taken from appropriate PMS violation status register, based given Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return PMS operation type relevant to mem_type parameter (se pms_operation_type_t) - */ -pms_operation_type_t IRAM_ATTR esp_memprot_get_violate_wr(mem_type_prot_t mem_type); - -/** - * @brief Returns LoadStore flag of the operation type which caused the violation interrupt (if any) - * - * The value (bit) is taken from appropriate PMS violation status register, based given Memory type - * Effective only on IRam0 access - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return true/false (LoadStore bit on/off) - */ -bool IRAM_ATTR esp_memprot_get_violate_loadstore(mem_type_prot_t mem_type); - -/** - * @brief Returns byte-enables for the address which caused the violation interrupt (if any) - * - * The value is taken from appropriate PMS violation status register, based given Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return byte-enables - */ -uint32_t IRAM_ATTR esp_memprot_get_violate_byte_en(mem_type_prot_t mem_type); - -/** - * @brief Returns raw contents of DRam0 status register 1 - * - * @return 32-bit register value - */ -uint32_t IRAM_ATTR esp_memprot_get_dram_status_reg_1(void); - -/** - * @brief Returns raw contents of DRam0 status register 2 - * - * @return 32-bit register value - */ -uint32_t IRAM_ATTR esp_memprot_get_dram_status_reg_2(void); - -/** - * @brief Returns raw contents of IRam0 status register - * - * @return 32-bit register value - */ -uint32_t IRAM_ATTR esp_memprot_get_iram_status_reg(void); - -/** - * @brief Register PMS violation interrupt in global interrupt matrix for given Memory type - * - * Memory protection components uses specific interrupt number, see ETS_MEMPROT_ERR_INUM - * The registration makes the panic-handler routine being called when the interrupt appears - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - */ -void esp_memprot_set_intr_matrix(mem_type_prot_t mem_type); - -/** - * @brief Convenient routine for setting the PMS defaults - * - * Called on application startup, depending on CONFIG_ESP_SYSTEM_MEMPROT_FEATURE Kconfig settings - * For implementation details see 'esp_memprot_set_prot_int' description - * - * @param invoke_panic_handler register all interrupts for panic handling (true/false) - * @param lock_feature lock the defaults to prevent further PMS settings changes (true/false) - * @param mem_type_mask 32-bit field of specific PMS parts to configure (see 'esp_memprot_set_prot_int') - */ -void esp_memprot_set_prot(bool invoke_panic_handler, bool lock_feature, uint32_t *mem_type_mask); - -/** - * @brief Internal routine for setting the PMS defaults - * - * Called on application startup from within 'esp_memprot_set_prot'. Allows setting a specific splitting address - * (main I/D split line) - see the parameter 'split_addr'. If the 'split_addr' equals to NULL, default I/D split line - * is used (&_iram_text_end) and all the remaining lines share the same address. - * The function sets all the split lines and PMS areas to the same space, - * ie there is a single instruction space and single data space at the end. - * The PMS split lines and permission areas scheme described below: - * - * DRam0/DMA IRam0 - * ----------------------------------------------- - * ... | IRam0_PMS_0 | - * DRam0_PMS_0 ----------------------------------------------- IRam0_line1_Split_addr - * ... | IRam0_PMS_1 | - * ... ----------------------------------------------- IRam0_line0_Split_addr - * | IRam0_PMS_2 | - * =============================================== IRam0_DRam0_Split_addr (main I/D) - * | DRam0_PMS_1 | - * DRam0_DMA_line0_Split_addr ----------------------------------------------- ... - * | DRam0_PMS_2 | ... - * DRam0_DMA_line1_Split_addr ----------------------------------------------- IRam0_PMS_3 - * | DRam0_PMS_3 | ... - * ----------------------------------------------- - * - * Default settings provided by 'esp_memprot_set_prot_int' are as follows: - * - * DRam0/DMA IRam0 - * ----------------------------------------------- - * | IRam0_PMS_0 = IRam0_PMS_1 = IRam0_PMS_2 | - * | DRam0_PMS_0 | IRam0_line1_Split_addr - * DRam0_DMA_line0_Split_addr | | = - * = =============================================== IRam0_line0_Split_addr - * DRam0_DMA_line1_Split_addr | | = - * | DRam0_PMS_1 = DRam0_PMS_2 = DRam0_PMS_3 | IRam0_DRam0_Split_addr (main I/D) - * | IRam0_PMS_3 | - * ----------------------------------------------- - * - * Once the memprot feature is locked, it can be unlocked only by digital system reset - * - * @param invoke_panic_handler register all the violation interrupts for panic handling (true/false) - * @param lock_feature lock the defaults to prevent further PMS settings changes (true/false) - * @param split_addr specific main I/D adrees or NULL to use default ($_iram_text_end) - * @param mem_type_mask 32-bit field of specific PMS parts to configure (members of mem_type_prot_t) - */ -void esp_memprot_set_prot_int(bool invoke_panic_handler, bool lock_feature, void *split_addr, uint32_t *mem_type_mask); - -/** - * @brief Returns raw contents of PMS interrupt monitor register for given Memory type - * - * @param mem_type Memory protection type (see mem_type_prot_t enum) - * - * @return 32-bit register value - */ -uint32_t esp_memprot_get_monitor_enable_reg(mem_type_prot_t mem_type); - -#ifdef __cplusplus -} -#endif diff --git a/tools/sdk/esp32s3/include/esp_hw_support/include/soc/esp32s2/memprot.h b/tools/sdk/esp32s3/include/esp_hw_support/include/soc/esp32s2/memprot.h index 0ebd6474578..596633ac7f2 100644 --- a/tools/sdk/esp32s3/include/esp_hw_support/include/soc/esp32s2/memprot.h +++ b/tools/sdk/esp32s3/include/esp_hw_support/include/soc/esp32s2/memprot.h @@ -68,7 +68,7 @@ typedef enum { * The address is given by region-specific global symbol exported from linker script, * it is not read out from related configuration register. */ -uint32_t *IRAM_ATTR esp_memprot_get_split_addr(mem_type_prot_t mem_type); +uint32_t * esp_memprot_get_split_addr(mem_type_prot_t mem_type); /** * @brief Initializes illegal memory access control for required memory section. @@ -116,7 +116,7 @@ esp_err_t esp_memprot_clear_intr(mem_type_prot_t mem_type); * * @return Memory protection area type (see mem_type_prot_t enum) */ -mem_type_prot_t IRAM_ATTR esp_memprot_get_active_intr_memtype(void); +mem_type_prot_t esp_memprot_get_active_intr_memtype(void); /** * @brief Gets interrupt status register contents for specified memory region @@ -141,7 +141,7 @@ esp_err_t esp_memprot_get_fault_reg(mem_type_prot_t mem_type, uint32_t *fault_re * DRAM0: 0 - non-atomic operation, 1 - atomic operation * @return ESP_OK on success, ESP_ERR_INVALID_ARG on failure */ -esp_err_t IRAM_ATTR esp_memprot_get_fault_status(mem_type_prot_t mem_type, uint32_t **faulting_address, uint32_t *op_type, uint32_t *op_subtype); +esp_err_t esp_memprot_get_fault_status(mem_type_prot_t mem_type, uint32_t **faulting_address, uint32_t *op_type, uint32_t *op_subtype); /** * @brief Gets string representation of required memory region identifier @@ -150,7 +150,7 @@ esp_err_t IRAM_ATTR esp_memprot_get_fault_status(mem_type_prot_t mem_type, uint3 * * @return mem_type as string */ -const char *IRAM_ATTR esp_memprot_type_to_str(mem_type_prot_t mem_type); +const char * esp_memprot_type_to_str(mem_type_prot_t mem_type); /** * @brief Detects whether any of the interrupt locks is active (requires digital system reset to unlock) diff --git a/tools/sdk/esp32s3/include/esp_hw_support/port/esp32s3/mspi_timing_tuning_configs.h b/tools/sdk/esp32s3/include/esp_hw_support/port/esp32s3/mspi_timing_tuning_configs.h index 3a538ae387e..274dbd3dec5 100644 --- a/tools/sdk/esp32s3/include/esp_hw_support/port/esp32s3/mspi_timing_tuning_configs.h +++ b/tools/sdk/esp32s3/include/esp_hw_support/port/esp32s3/mspi_timing_tuning_configs.h @@ -128,6 +128,11 @@ #endif #endif //PSRAM 120M STR +//PSRAM 120M STR +#if MSPI_TIMING_PSRAM_DTR_MODE && CONFIG_SPIRAM_SPEED_120M +#define MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ 240 +#endif //PSRAM 120M DTR + //------------------------------------------Determine the Core Clock-----------------------------------------------// /** @@ -233,3 +238,20 @@ ESP_STATIC_ASSERT(CHECK_POWER_OF_2(MSPI_TIMING_CORE_CLOCK_MHZ / MSPI_TIMING_PSRA #define MSPI_TIMING_PSRAM_CONFIG_TABLE_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE {{2, 0, 1}, {0, 0, 0}, {2, 2, 2}, {1, 0, 1}, {2, 0, 2}, {0, 0, 1}, {2, 2, 3}, {1, 0, 2}, {2, 0, 3}, {0, 0, 2}, {2, 2, 4}, {1, 0, 3}} #define MSPI_TIMING_PSRAM_CONFIG_NUM_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE 12 #define MSPI_TIMING_PSRAM_DEFAULT_CONFIG_ID_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE 2 + +//PSRAM: core clock 240M, module clock 120M, DTR mode +#define MSPI_TIMING_PSRAM_CONFIG_TABLE_CORE_CLK_240M_MODULE_CLK_120M_DTR_MODE {{0, 0, 0}, {4, 1, 2}, {1, 0, 1}, {4, 0, 2}, {0, 0, 1}, {4, 1, 3}, {1, 0, 2}, {4, 0, 3}, {0, 0, 2}, {4, 1, 4}, {1, 0, 3}, {4, 0, 4}, {0, 0, 3}, {4, 1, 5}} +#define MSPI_TIMING_PSRAM_CONFIG_NUM_CORE_CLK_240M_MODULE_CLK_120M_DTR_MODE 14 +#define MSPI_TIMING_PSRAM_DEFAULT_CONFIG_ID_CORE_CLK_240M_MODULE_CLK_120M_DTR_MODE 1 + +//------------------------------------------Frequency Scanning Related-----------------------------------------------// +/** + * On ESP32S3, only module clock 120M, DDR mode needs frequency scan. Frequency scanning is to get the max workable PLL + * frequency under each successfull timing tuning configuration. PLL frequency may fluctuate under high temperature, + * this method is to get the tuning configuration that can work under higher PLL frequency. + */ +#define MSPI_TIMING_PLL_FREQ_SCAN_RANGE_MHZ_MIN 440 +#define MSPI_TIMING_PLL_FREQ_SCAN_RANGE_MHZ_MAX 600 +#define MSPI_TIMING_PLL_FREQ_SCAN_THRESH_MHZ_LOW 448 +#define MSPI_TIMING_PLL_FREQ_SCAN_THRESH_MHZ_HIGH 520 +#define MSPI_TIMING_PLL_FREQ_SCAN_STEP_MHZ_MODULE_CLK_120M 8 diff --git a/tools/sdk/esp32s3/include/esp_lcd/include/esp_lcd_panel_commands.h b/tools/sdk/esp32s3/include/esp_lcd/include/esp_lcd_panel_commands.h index 091ef1cffef..5917c3e8774 100644 --- a/tools/sdk/esp32s3/include/esp_lcd/include/esp_lcd_panel_commands.h +++ b/tools/sdk/esp32s3/include/esp_lcd/include/esp_lcd_panel_commands.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -31,7 +31,7 @@ #define LCD_CMD_RAMRD 0x2E // Read frame memory #define LCD_CMD_PTLAR 0x30 // Define the partial area #define LCD_CMD_VSCRDEF 0x33 // Vertical scrolling definition -#define LCD_CMD_TEOFF 0x34 // Turns of tearing effect +#define LCD_CMD_TEOFF 0x34 // Turns off tearing effect #define LCD_CMD_TEON 0x35 // Turns on tearing effect #define LCD_CMD_MADCTL 0x36 // Memory data access control @@ -48,7 +48,7 @@ #define LCD_CMD_COLMOD 0x3A // Defines the format of RGB picture data #define LCD_CMD_RAMWRC 0x3C // Memory write continue #define LCD_CMD_RAMRDC 0x3E // Memory read continue -#define LCD_CMD_STE 0x44 // Set tear scanline, tearing effect output signal when display module reaches line N -#define LCD_CMD_GDCAN 0x45 // Get scanline +#define LCD_CMD_STE 0x44 // Set tear scan line, tearing effect output signal when display module reaches line N +#define LCD_CMD_GDCAN 0x45 // Get scan line #define LCD_CMD_WRDISBV 0x51 // Write display brightness #define LCD_CMD_RDDISBV 0x52 // Read display brightness value diff --git a/tools/sdk/esp32s3/include/esp_lcd/include/esp_lcd_panel_io.h b/tools/sdk/esp32s3/include/esp_lcd/include/esp_lcd_panel_io.h index c01fe3e441f..de7b434b5f8 100644 --- a/tools/sdk/esp32s3/include/esp_lcd/include/esp_lcd_panel_io.h +++ b/tools/sdk/esp32s3/include/esp_lcd/include/esp_lcd_panel_io.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -71,7 +71,7 @@ esp_err_t esp_lcd_panel_io_rx_param(esp_lcd_panel_io_handle_t io, int lcd_cmd, v * this function will wait until they are finished and the queue is empty before sending the command(s). * * @param[in] io LCD panel IO handle, which is created by other factory API like `esp_lcd_new_panel_io_spi()` - * @param[in] lcd_cmd The specific LCD command (set to -1 if no command needed - only in SPI and I2C) + * @param[in] lcd_cmd The specific LCD command, set to -1 if no command needed * @param[in] param Buffer that holds the command specific parameters, set to NULL if no parameter is needed for the command * @param[in] param_size Size of `param` in memory, in bytes, set to zero if no parameter is needed for the command * @return diff --git a/tools/sdk/esp32s3/include/esp_mm/include/esp_cache.h b/tools/sdk/esp32s3/include/esp_mm/include/esp_cache.h index 800e8865695..af51a18ed72 100644 --- a/tools/sdk/esp32s3/include/esp_mm/include/esp_cache.h +++ b/tools/sdk/esp32s3/include/esp_mm/include/esp_cache.h @@ -41,9 +41,9 @@ extern "C" { * @note You should not call this during any Flash operations (e.g. esp_flash APIs, nvs and some other APIs that are based on esp_flash APIs) * @note If XIP_From_PSRAM is enabled (by enabling both CONFIG_SPIRAM_FETCH_INSTRUCTIONS and CONFIG_SPIRAM_RODATA), you can call this API during Flash operations * - * @param[in] Starting address to do the msync - * @param[in] Size to do the msync - * @param[in] Flags, see `ESP_CACHE_MSYNC_FLAG_x` + * @param[in] addr Starting address to do the msync + * @param[in] size Size to do the msync + * @param[in] flags Flags, see `ESP_CACHE_MSYNC_FLAG_x` * * @return * - ESP_OK: diff --git a/tools/sdk/esp32s3/include/esp_mm/include/esp_mmu_map.h b/tools/sdk/esp32s3/include/esp_mm/include/esp_mmu_map.h index 33d3396441d..355b0c97501 100644 --- a/tools/sdk/esp32s3/include/esp_mm/include/esp_mmu_map.h +++ b/tools/sdk/esp32s3/include/esp_mm/include/esp_mmu_map.h @@ -47,7 +47,7 @@ extern "C" { * - the to-be-mapped paddr block is overlapped with an already mapped paddr block. * - the to-be-mapped paddr block encloses an already mapped paddr block. * 2. If the to-be-mapped paddr block is enclosed by an already mapped paddr block, no new mapping will happen, return ESP_ERR_INVALID_STATE. The out pointer will be the already mapped paddr corresponding vaddr. - * 3. If the to-be-mapped paddr block is totally the same as an already mapped paddr block, no new mapping will happen, return ESP_ERR_INVALID_STATE. The out pointer will be the corresponding vaddr. + * 3. If the to-be-mapped paddr block is identical with an already mapped paddr block, no new mapping will happen, return ESP_ERR_INVALID_STATE. The out pointer will be the corresponding vaddr. * * - If this flag isn't set, overlapped, enclosed or same to-be-mapped paddr block will lead to ESP_ERR_INVALID_ARG. */ @@ -77,7 +77,7 @@ typedef uint32_t esp_paddr_t; * - ESP_ERR_NOT_FOUND: No enough size free block to use * - ESP_ERR_NO_MEM: Out of memory, this API will allocate some heap memory for internal usage * - ESP_ERR_INVALID_STATE: Paddr is mapped already, this API will return corresponding vaddr_start of the previously mapped block. - * Only to-be-mapped paddr block is totally enclosed by a previously mapped block will lead to this error: + * Only to-be-mapped paddr block is totally enclosed by a previously mapped block will lead to this error. (Identical scenario will behave similarly) * new_block_start new_block_end * |-------- New Block --------| * |--------------- Block ---------------| @@ -156,6 +156,20 @@ esp_err_t esp_mmu_vaddr_to_paddr(void *vaddr, esp_paddr_t *out_paddr, mmu_target */ esp_err_t esp_mmu_paddr_to_vaddr(esp_paddr_t paddr, mmu_target_t target, mmu_vaddr_t type, void **out_vaddr); +/** + * @brief If the physical address is mapped, this API will provide the capabilities of the virtual address where the physical address is mapped to. + * + * @note: Only return value is ESP_OK(which means physically address is successfully mapped), then caps you get make sense. + * @note This API only check one page (see CONFIG_MMU_PAGE_SIZE), starting from the `paddr` + * + * @param[in] paddr Physical address + * @param[out] out_caps Bitwise OR of MMU_MEM_CAP_* flags indicating the capabilities of a virtual address where the physical address is mapped to. + * @return + * - ESP_OK: Physical address successfully mapped. + * - ESP_ERR_INVALID_ARG: Null pointer + * - ESP_ERR_NOT_FOUND: Physical address is not mapped successfully. + */ +esp_err_t esp_mmu_paddr_find_caps(const esp_paddr_t paddr, mmu_mem_caps_t *out_caps); #ifdef __cplusplus } diff --git a/tools/sdk/esp32s3/include/esp_netif/include/esp_netif.h b/tools/sdk/esp32s3/include/esp_netif/include/esp_netif.h index 9372b6d1506..2510a1eefee 100644 --- a/tools/sdk/esp32s3/include/esp_netif/include/esp_netif.h +++ b/tools/sdk/esp32s3/include/esp_netif/include/esp_netif.h @@ -523,6 +523,34 @@ int esp_netif_get_netif_impl_index(esp_netif_t *esp_netif); */ esp_err_t esp_netif_get_netif_impl_name(esp_netif_t *esp_netif, char* name); +/** + * @brief Enable NAPT on an interface + * + * @note Enable operation can be performed only on one interface at a time. + * NAPT cannot be enabled on multiple interfaces according to this implementation. + * + * @param[in] esp_netif Handle to esp-netif instance + * + * @return + * - ESP_OK + * - ESP_FAIL + * - ESP_ERR_NOT_SUPPORTED +*/ + +esp_err_t esp_netif_napt_enable(esp_netif_t *esp_netif); + +/** + * @brief Disable NAPT on an interface. + * + * @param[in] esp_netif Handle to esp-netif instance + * + * @return + * - ESP_OK + * - ESP_FAIL + * - ESP_ERR_NOT_SUPPORTED +*/ +esp_err_t esp_netif_napt_disable(esp_netif_t *esp_netif); + /** * @} */ diff --git a/tools/sdk/esp32s3/include/esp_phy/include/esp_phy_init.h b/tools/sdk/esp32s3/include/esp_phy/include/esp_phy_init.h index 4f30c7795fc..4813e5bdee6 100644 --- a/tools/sdk/esp32s3/include/esp_phy/include/esp_phy_init.h +++ b/tools/sdk/esp32s3/include/esp_phy/include/esp_phy_init.h @@ -180,6 +180,15 @@ void esp_phy_disable(void); */ void esp_btbb_enable(void); +/** + * @brief Disable BTBB module + * + * Dsiable BTBB module, used by IEEE802154 or Bluetooth. + * Users should not call this API in their application. + * + */ +void esp_btbb_disable(void); + /** * @brief Load calibration data from NVS and initialize PHY and RF module */ diff --git a/tools/sdk/esp32s3/include/esp_rom/include/esp32/rom/ets_sys.h b/tools/sdk/esp32s3/include/esp_rom/include/esp32/rom/ets_sys.h index 6f9688fcf18..549db8ffc63 100644 --- a/tools/sdk/esp32s3/include/esp_rom/include/esp32/rom/ets_sys.h +++ b/tools/sdk/esp32s3/include/esp_rom/include/esp32/rom/ets_sys.h @@ -48,7 +48,10 @@ extern "C" { typedef enum { ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1 /**< return failed in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, } ETS_STATUS; typedef uint32_t ETSSignal; @@ -621,13 +624,16 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); #define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) typedef enum { OK = 0, FAIL, PENDING, BUSY, CANCEL, -} STATUS; +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif /** * @} diff --git a/tools/sdk/esp32s3/include/esp_rom/include/esp32/rom/uart.h b/tools/sdk/esp32s3/include/esp_rom/include/esp32/rom/uart.h index 3eb59f30f96..3bd0d38f484 100644 --- a/tools/sdk/esp32s3/include/esp_rom/include/esp32/rom/uart.h +++ b/tools/sdk/esp32s3/include/esp_rom/include/esp32/rom/uart.h @@ -227,7 +227,7 @@ void uart_buff_switch(uint8_t uart_no); * * @return OK. */ -STATUS uart_tx_one_char(uint8_t TxChar); +ETS_STATUS uart_tx_one_char(uint8_t TxChar); /** * @brief Output a char to message exchange channel, wait until fifo not full. @@ -237,7 +237,7 @@ STATUS uart_tx_one_char(uint8_t TxChar); * * @return OK. */ -STATUS uart_tx_one_char2(uint8_t TxChar); +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); /** * @brief Wait until uart tx full empty. @@ -273,7 +273,7 @@ static inline void IRAM_ATTR uart_tx_wait_idle(uint8_t uart_no) { * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_one_char(uint8_t *pRxChar); +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); /** * @brief Get an input char from message channel, wait until successful. @@ -295,7 +295,7 @@ char uart_rx_one_char_block(void); * * @return OK. */ -STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); /** * @brief Process uart received information in the interrupt handler. @@ -318,7 +318,7 @@ void uart_rx_intr_handler(void *para); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); /** * @brief Get all chars from receive buffer. @@ -329,7 +329,7 @@ STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); * @return OK for successful. * FAIL for failed. */ -STATUS UartGetCmdLn(uint8_t *pCmdLn); +ETS_STATUS UartGetCmdLn(uint8_t *pCmdLn); /** * @brief Get uart configuration struct. @@ -379,7 +379,7 @@ int recv_packet(uint8_t *p, int len, uint8_t is_sync); * @return OK for successful. * FAIL for failed. */ -STATUS SendMsg(uint8_t *pData, uint16_t DataLen); +ETS_STATUS SendMsg(uint8_t *pData, uint16_t DataLen); /** * @brief Receive an packet from download tool, with SLIP escaping. @@ -395,7 +395,7 @@ STATUS SendMsg(uint8_t *pData, uint16_t DataLen); * @return OK for successful. * FAIL for failed. */ -STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync); +ETS_STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync); extern UartDevice UartDev; diff --git a/tools/sdk/esp32s3/include/esp_rom/include/esp32c2/rom/ets_sys.h b/tools/sdk/esp32s3/include/esp_rom/include/esp32c2/rom/ets_sys.h index 6d2e3a4ef4e..ad642fcc460 100644 --- a/tools/sdk/esp32s3/include/esp_rom/include/esp32c2/rom/ets_sys.h +++ b/tools/sdk/esp32s3/include/esp_rom/include/esp32c2/rom/ets_sys.h @@ -43,7 +43,10 @@ extern "C" { typedef enum { ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1 /**< return failed in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, } ETS_STATUS; typedef ETS_STATUS ets_status_t; @@ -438,13 +441,16 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); #define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) typedef enum { OK = 0, FAIL, PENDING, BUSY, CANCEL, -} STATUS; +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif /** * @} diff --git a/tools/sdk/esp32s3/include/esp_rom/include/esp32c2/rom/uart.h b/tools/sdk/esp32s3/include/esp_rom/include/esp32c2/rom/uart.h index 8a4507e8108..454e0d83a11 100644 --- a/tools/sdk/esp32s3/include/esp_rom/include/esp32c2/rom/uart.h +++ b/tools/sdk/esp32s3/include/esp_rom/include/esp32c2/rom/uart.h @@ -205,7 +205,7 @@ void uart_tx_switch(uint8_t uart_no); * * @return OK. */ -STATUS uart_tx_one_char(uint8_t TxChar); +ETS_STATUS uart_tx_one_char(uint8_t TxChar); /** * @brief Output a char to message exchange channel, wait until fifo not full. @@ -215,7 +215,7 @@ STATUS uart_tx_one_char(uint8_t TxChar); * * @return OK. */ -STATUS uart_tx_one_char2(uint8_t TxChar); +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); /** * @brief Wait until uart tx full empty. @@ -245,7 +245,7 @@ void uart_tx_wait_idle(uint8_t uart_no); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_one_char(uint8_t *pRxChar); +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); /** * @brief Get an input char from message channel, wait until successful. @@ -267,7 +267,7 @@ char uart_rx_one_char_block(void); * * @return OK. */ -STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); /** * @brief Get an char from receive buffer. @@ -280,7 +280,7 @@ STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); /** * @brief Get all chars from receive buffer. @@ -291,7 +291,7 @@ STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); * @return OK for successful. * FAIL for failed. */ -STATUS UartGetCmdLn(uint8_t *pCmdLn); +ETS_STATUS UartGetCmdLn(uint8_t *pCmdLn); /** * @brief Get uart configuration struct. diff --git a/tools/sdk/esp32s3/include/esp_rom/include/esp32c3/rom/ets_sys.h b/tools/sdk/esp32s3/include/esp_rom/include/esp32c3/rom/ets_sys.h index d5489bd835d..06b3b47d8c2 100644 --- a/tools/sdk/esp32s3/include/esp_rom/include/esp32c3/rom/ets_sys.h +++ b/tools/sdk/esp32s3/include/esp_rom/include/esp32c3/rom/ets_sys.h @@ -43,7 +43,10 @@ extern "C" { typedef enum { ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1 /**< return failed in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, } ETS_STATUS; typedef ETS_STATUS ets_status_t; @@ -430,13 +433,16 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); #define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) typedef enum { OK = 0, FAIL, PENDING, BUSY, CANCEL, -} STATUS; +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif /** * @} diff --git a/tools/sdk/esp32s3/include/esp_rom/include/esp32c3/rom/uart.h b/tools/sdk/esp32s3/include/esp_rom/include/esp32c3/rom/uart.h index 0cd91b06d57..a4fbd52077f 100644 --- a/tools/sdk/esp32s3/include/esp_rom/include/esp32c3/rom/uart.h +++ b/tools/sdk/esp32s3/include/esp_rom/include/esp32c3/rom/uart.h @@ -195,7 +195,7 @@ void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue); * * @return OK. */ -STATUS uart_tx_one_char(uint8_t TxChar); +ETS_STATUS uart_tx_one_char(uint8_t TxChar); /** * @brief Output a char to message exchange channel, wait until fifo not full. @@ -205,7 +205,7 @@ STATUS uart_tx_one_char(uint8_t TxChar); * * @return OK. */ -STATUS uart_tx_one_char2(uint8_t TxChar); +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); /** * @brief Wait until uart tx full empty. @@ -235,7 +235,7 @@ void uart_tx_wait_idle(uint8_t uart_no); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_one_char(uint8_t *pRxChar); +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); /** * @brief Get an input char from message channel, wait until successful. @@ -257,7 +257,7 @@ char uart_rx_one_char_block(void); * * @return OK. */ -STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); /** * @brief Get an char from receive buffer. @@ -270,7 +270,7 @@ STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); /** * @brief Get uart configuration struct. diff --git a/tools/sdk/esp32s3/include/esp_rom/include/esp32c6/rom/ets_sys.h b/tools/sdk/esp32s3/include/esp_rom/include/esp32c6/rom/ets_sys.h index 48a724d54b8..7c04af3a54c 100644 --- a/tools/sdk/esp32s3/include/esp_rom/include/esp32c6/rom/ets_sys.h +++ b/tools/sdk/esp32s3/include/esp_rom/include/esp32c6/rom/ets_sys.h @@ -43,7 +43,10 @@ extern "C" { typedef enum { ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1 /**< return failed in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, } ETS_STATUS; typedef ETS_STATUS ets_status_t; @@ -407,13 +410,16 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); #define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) typedef enum { OK = 0, FAIL, PENDING, BUSY, CANCEL, -} STATUS; +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif /** * @} diff --git a/tools/sdk/esp32s3/include/esp_rom/include/esp32c6/rom/uart.h b/tools/sdk/esp32s3/include/esp_rom/include/esp32c6/rom/uart.h index 380f19a4e56..9045c42f6f6 100644 --- a/tools/sdk/esp32s3/include/esp_rom/include/esp32c6/rom/uart.h +++ b/tools/sdk/esp32s3/include/esp_rom/include/esp32c6/rom/uart.h @@ -205,7 +205,7 @@ void uart_tx_switch(uint8_t uart_no); * * @return OK. */ -STATUS uart_tx_one_char(uint8_t TxChar); +ETS_STATUS uart_tx_one_char(uint8_t TxChar); /** * @brief Output a char to message exchange channel, wait until fifo not full. @@ -215,7 +215,7 @@ STATUS uart_tx_one_char(uint8_t TxChar); * * @return OK. */ -STATUS uart_tx_one_char2(uint8_t TxChar); +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); /** * @brief Wait until uart tx full empty. @@ -245,7 +245,7 @@ void uart_tx_wait_idle(uint8_t uart_no); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_one_char(uint8_t *pRxChar); +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); /** * @brief Get an input char from message channel, wait until successful. @@ -267,7 +267,7 @@ char uart_rx_one_char_block(void); * * @return OK. */ -STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); /** * @brief Process uart recevied information in the interrupt handler. @@ -290,7 +290,7 @@ void uart_rx_intr_handler(void *para); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); /** * @brief Get all chars from receive buffer. @@ -301,7 +301,7 @@ STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); * @return OK for successful. * FAIL for failed. */ -STATUS UartGetCmdLn(uint8_t *pCmdLn); +ETS_STATUS UartGetCmdLn(uint8_t *pCmdLn); /** * @brief Get uart configuration struct. diff --git a/tools/sdk/esp32s3/include/esp_rom/include/esp32h2/rom/efuse.h b/tools/sdk/esp32s3/include/esp_rom/include/esp32h2/rom/efuse.h index 6cd9f4b377e..dc612dff4b8 100644 --- a/tools/sdk/esp32s3/include/esp_rom/include/esp32h2/rom/efuse.h +++ b/tools/sdk/esp32s3/include/esp_rom/include/esp32h2/rom/efuse.h @@ -27,7 +27,8 @@ extern "C" { typedef enum { ETS_EFUSE_KEY_PURPOSE_USER = 0, - ETS_EFUSE_KEY_PURPOSE_RESERVED = 1, + ETS_EFUSE_KEY_PURPOSE_ECDSA_KEY = 1, + ETS_EFUSE_KEY_PURPOSE_RESERVED = 2, ETS_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, diff --git a/tools/sdk/esp32s3/include/esp_rom/include/esp32h2/rom/ets_sys.h b/tools/sdk/esp32s3/include/esp_rom/include/esp32h2/rom/ets_sys.h index b9ac5a13f41..b9247bc3bdf 100644 --- a/tools/sdk/esp32s3/include/esp_rom/include/esp32h2/rom/ets_sys.h +++ b/tools/sdk/esp32s3/include/esp_rom/include/esp32h2/rom/ets_sys.h @@ -43,7 +43,10 @@ extern "C" { typedef enum { ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1 /**< return failed in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, } ETS_STATUS; typedef ETS_STATUS ets_status_t; @@ -406,13 +409,16 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); #define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) typedef enum { OK = 0, FAIL, PENDING, BUSY, CANCEL, -} STATUS; +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif /** * @} diff --git a/tools/sdk/esp32s3/include/esp_rom/include/esp32h2/rom/uart.h b/tools/sdk/esp32s3/include/esp_rom/include/esp32h2/rom/uart.h index 380f19a4e56..9045c42f6f6 100644 --- a/tools/sdk/esp32s3/include/esp_rom/include/esp32h2/rom/uart.h +++ b/tools/sdk/esp32s3/include/esp_rom/include/esp32h2/rom/uart.h @@ -205,7 +205,7 @@ void uart_tx_switch(uint8_t uart_no); * * @return OK. */ -STATUS uart_tx_one_char(uint8_t TxChar); +ETS_STATUS uart_tx_one_char(uint8_t TxChar); /** * @brief Output a char to message exchange channel, wait until fifo not full. @@ -215,7 +215,7 @@ STATUS uart_tx_one_char(uint8_t TxChar); * * @return OK. */ -STATUS uart_tx_one_char2(uint8_t TxChar); +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); /** * @brief Wait until uart tx full empty. @@ -245,7 +245,7 @@ void uart_tx_wait_idle(uint8_t uart_no); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_one_char(uint8_t *pRxChar); +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); /** * @brief Get an input char from message channel, wait until successful. @@ -267,7 +267,7 @@ char uart_rx_one_char_block(void); * * @return OK. */ -STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); /** * @brief Process uart recevied information in the interrupt handler. @@ -290,7 +290,7 @@ void uart_rx_intr_handler(void *para); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); /** * @brief Get all chars from receive buffer. @@ -301,7 +301,7 @@ STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); * @return OK for successful. * FAIL for failed. */ -STATUS UartGetCmdLn(uint8_t *pCmdLn); +ETS_STATUS UartGetCmdLn(uint8_t *pCmdLn); /** * @brief Get uart configuration struct. diff --git a/tools/sdk/esp32s3/include/esp_rom/include/esp32h4/rom/ets_sys.h b/tools/sdk/esp32s3/include/esp_rom/include/esp32h4/rom/ets_sys.h index 902127abfbb..91544de628a 100644 --- a/tools/sdk/esp32s3/include/esp_rom/include/esp32h4/rom/ets_sys.h +++ b/tools/sdk/esp32s3/include/esp_rom/include/esp32h4/rom/ets_sys.h @@ -43,7 +43,10 @@ extern "C" { typedef enum { ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1 /**< return failed in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, } ETS_STATUS; typedef ETS_STATUS ets_status_t; @@ -441,13 +444,16 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); #define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) typedef enum { OK = 0, FAIL, PENDING, BUSY, CANCEL, -} STATUS; +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif /** * @} diff --git a/tools/sdk/esp32s3/include/esp_rom/include/esp32h4/rom/uart.h b/tools/sdk/esp32s3/include/esp_rom/include/esp32h4/rom/uart.h index d271893d761..28677ac4097 100644 --- a/tools/sdk/esp32s3/include/esp_rom/include/esp32h4/rom/uart.h +++ b/tools/sdk/esp32s3/include/esp_rom/include/esp32h4/rom/uart.h @@ -205,7 +205,7 @@ void uart_tx_switch(uint8_t uart_no); * * @return OK. */ -STATUS uart_tx_one_char(uint8_t TxChar); +ETS_STATUS uart_tx_one_char(uint8_t TxChar); /** * @brief Output a char to message exchange channel, wait until fifo not full. @@ -215,7 +215,7 @@ STATUS uart_tx_one_char(uint8_t TxChar); * * @return OK. */ -STATUS uart_tx_one_char2(uint8_t TxChar); +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); /** * @brief Wait until uart tx full empty. @@ -245,7 +245,7 @@ void uart_tx_wait_idle(uint8_t uart_no); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_one_char(uint8_t *pRxChar); +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); /** * @brief Get an input char from message channel, wait until successful. @@ -267,7 +267,7 @@ char uart_rx_one_char_block(void); * * @return OK. */ -STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); /** * @brief Get an char from receive buffer. @@ -280,7 +280,7 @@ STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); /** * @brief Get all chars from receive buffer. @@ -291,7 +291,7 @@ STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); * @return OK for successful. * FAIL for failed. */ -STATUS UartGetCmdLn(uint8_t *pCmdLn); +ETS_STATUS UartGetCmdLn(uint8_t *pCmdLn); /** * @brief Get uart configuration struct. diff --git a/tools/sdk/esp32s3/include/esp_rom/include/esp32s2/rom/ets_sys.h b/tools/sdk/esp32s3/include/esp_rom/include/esp32s2/rom/ets_sys.h index a2cf1adce34..19c1994de71 100644 --- a/tools/sdk/esp32s3/include/esp_rom/include/esp32s2/rom/ets_sys.h +++ b/tools/sdk/esp32s3/include/esp_rom/include/esp32s2/rom/ets_sys.h @@ -45,7 +45,10 @@ extern "C" { typedef enum { ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1 /**< return failed in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, } ETS_STATUS; typedef ETS_STATUS ets_status_t; @@ -556,13 +559,16 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); #define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) typedef enum { OK = 0, FAIL, PENDING, BUSY, CANCEL, -} STATUS; +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif /** * @} diff --git a/tools/sdk/esp32s3/include/esp_rom/include/esp32s2/rom/uart.h b/tools/sdk/esp32s3/include/esp_rom/include/esp32s2/rom/uart.h index 899413f3171..491d2c28fbe 100644 --- a/tools/sdk/esp32s3/include/esp_rom/include/esp32s2/rom/uart.h +++ b/tools/sdk/esp32s3/include/esp_rom/include/esp32s2/rom/uart.h @@ -1,16 +1,8 @@ -// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _ROM_UART_H_ #define _ROM_UART_H_ @@ -251,7 +243,7 @@ void uart_buff_switch(uint8_t uart_no); * * @return OK. */ -STATUS uart_tx_one_char(uint8_t TxChar); +ETS_STATUS uart_tx_one_char(uint8_t TxChar); /** * @brief Output a char to message exchange channel, wait until fifo not full. @@ -261,7 +253,7 @@ STATUS uart_tx_one_char(uint8_t TxChar); * * @return OK. */ -STATUS uart_tx_one_char2(uint8_t TxChar); +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); /** * @brief Wait until uart tx full empty. @@ -291,7 +283,7 @@ void uart_tx_wait_idle(uint8_t uart_no); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_one_char(uint8_t *pRxChar); +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); /** * @brief Get an input char from message channel, wait until successful. @@ -313,7 +305,7 @@ char uart_rx_one_char_block(void); * * @return OK. */ -STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); /** * @brief Process uart recevied information in the interrupt handler. @@ -336,7 +328,7 @@ void uart_rx_intr_handler(void *para); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); /** * @brief Get all chars from receive buffer. @@ -347,7 +339,7 @@ STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); * @return OK for successful. * FAIL for failed. */ -STATUS UartGetCmdLn(uint8_t *pCmdLn); +ETS_STATUS UartGetCmdLn(uint8_t *pCmdLn); /** * @brief Get uart configuration struct. @@ -397,7 +389,7 @@ int recv_packet(uint8_t *p, int len, uint8_t is_sync); * @return OK for successful. * FAIL for failed. */ -STATUS SendMsg(uint8_t *pData, uint16_t DataLen); +ETS_STATUS SendMsg(uint8_t *pData, uint16_t DataLen); /** * @brief Receive an packet from download tool, with SLIP escaping. @@ -413,7 +405,7 @@ STATUS SendMsg(uint8_t *pData, uint16_t DataLen); * @return OK for successful. * FAIL for failed. */ -STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync); +ETS_STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync); /** * @brief Check if this UART is in download connection. diff --git a/tools/sdk/esp32s3/include/esp_rom/include/esp32s3/rom/ets_sys.h b/tools/sdk/esp32s3/include/esp_rom/include/esp32s3/rom/ets_sys.h index 9047442c36e..83c93b2eb6a 100644 --- a/tools/sdk/esp32s3/include/esp_rom/include/esp32s3/rom/ets_sys.h +++ b/tools/sdk/esp32s3/include/esp_rom/include/esp32s3/rom/ets_sys.h @@ -43,7 +43,10 @@ extern "C" { typedef enum { ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1 /**< return failed in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, } ETS_STATUS; typedef ETS_STATUS ets_status_t; @@ -543,13 +546,16 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); #define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) typedef enum { OK = 0, FAIL, PENDING, BUSY, CANCEL, -} STATUS; +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif /** * @} diff --git a/tools/sdk/esp32s3/include/esp_rom/include/esp32s3/rom/uart.h b/tools/sdk/esp32s3/include/esp_rom/include/esp32s3/rom/uart.h index 3486886ad54..864563f7883 100644 --- a/tools/sdk/esp32s3/include/esp_rom/include/esp32s3/rom/uart.h +++ b/tools/sdk/esp32s3/include/esp_rom/include/esp32s3/rom/uart.h @@ -203,7 +203,7 @@ void uart_tx_switch(uint8_t uart_no); * * @return OK. */ -STATUS uart_tx_one_char(uint8_t TxChar); +ETS_STATUS uart_tx_one_char(uint8_t TxChar); /** * @brief Output a char to message exchange channel, wait until fifo not full. @@ -213,7 +213,7 @@ STATUS uart_tx_one_char(uint8_t TxChar); * * @return OK. */ -STATUS uart_tx_one_char2(uint8_t TxChar); +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); /** * @brief Wait until uart tx full empty. @@ -243,7 +243,7 @@ void uart_tx_wait_idle(uint8_t uart_no); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_one_char(uint8_t *pRxChar); +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); /** * @brief Get an input char from message channel, wait until successful. @@ -265,7 +265,7 @@ char uart_rx_one_char_block(void); * * @return OK. */ -STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); /** * @brief Get an char from receive buffer. @@ -278,7 +278,7 @@ STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); * @return OK for successful. * FAIL for failed. */ -STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); /** * @brief Get uart configuration struct. diff --git a/tools/sdk/esp32s3/include/esp_wifi/include/esp_mesh.h b/tools/sdk/esp32s3/include/esp_wifi/include/esp_mesh.h index 78f65945051..5ba707b527e 100644 --- a/tools/sdk/esp32s3/include/esp_wifi/include/esp_mesh.h +++ b/tools/sdk/esp32s3/include/esp_wifi/include/esp_mesh.h @@ -174,7 +174,8 @@ typedef enum { MESH_EVENT_PARENT_DISCONNECTED, /**< parent is disconnected on station interface */ MESH_EVENT_NO_PARENT_FOUND, /**< no parent found */ MESH_EVENT_LAYER_CHANGE, /**< layer changes over the mesh network */ - MESH_EVENT_TODS_STATE, /**< state represents whether the root is able to access external IP network */ + MESH_EVENT_TODS_STATE, /**< state represents whether the root is able to access external IP network. + This state is a manual event that needs to be triggered with esp_mesh_post_toDS_state(). */ MESH_EVENT_VOTE_STARTED, /**< the process of voting a new root is started either by children or by the root */ MESH_EVENT_VOTE_STOPPED, /**< the process of voting a new root is stopped */ MESH_EVENT_ROOT_ADDRESS, /**< the root address is obtained. It is posted by mesh stack automatically. */ @@ -1175,7 +1176,10 @@ esp_err_t esp_mesh_get_rx_pending(mesh_rx_pending_t *pending); int esp_mesh_available_txupQ_num(const mesh_addr_t *addr, uint32_t *xseqno_in); /** - * @brief Set the number of queue + * @brief Set the number of RX queue for the node, the average number of window allocated to one of + * its child node is: wnd = xon_qsize / (2 * max_connection + 1). + * However, the window of each child node is not strictly equal to the average value, + * it is affected by the traffic also. * * @attention This API shall be called before mesh is started. * diff --git a/tools/sdk/esp32s3/include/esp_wifi/include/esp_wifi.h b/tools/sdk/esp32s3/include/esp_wifi/include/esp_wifi.h index 863ebb7d702..3c0ade914b1 100644 --- a/tools/sdk/esp32s3/include/esp_wifi/include/esp_wifi.h +++ b/tools/sdk/esp32s3/include/esp_wifi/include/esp_wifi.h @@ -660,10 +660,10 @@ esp_err_t esp_wifi_get_country(wifi_country_t *country); /** - * @brief Set MAC address of WiFi station or the soft-AP interface. + * @brief Set MAC address of WiFi station, soft-AP or NAN interface. * * @attention 1. This API can only be called when the interface is disabled - * @attention 2. Soft-AP and station have different MAC addresses, do not set them to be the same. + * @attention 2. Above mentioned interfaces have different MAC addresses, do not set them to be the same. * @attention 3. The bit 0 of the first byte of MAC address can not be 1. For example, the MAC address * can set to be "1a:XX:XX:XX:XX:XX", but can not be "15:XX:XX:XX:XX:XX". * @@ -1151,6 +1151,7 @@ esp_err_t esp_wifi_set_inactive_time(wifi_interface_t ifx, uint16_t sec); * @return * - ESP_OK: succeed * - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init + * - ESP_ERR_WIFI_NOT_STARTED: WiFi is not started by esp_wifi_start * - ESP_ERR_WIFI_ARG: invalid argument */ esp_err_t esp_wifi_get_inactive_time(wifi_interface_t ifx, uint16_t *sec); @@ -1348,6 +1349,19 @@ esp_err_t esp_wifi_sta_get_aid(uint16_t *aid); */ esp_err_t esp_wifi_sta_get_negotiated_phymode(wifi_phy_mode_t *phymode); +/** + * @brief Config dynamic carrier sense + * + * @attention This API should be called after esp_wifi_start(). + * + * @param enabled Dynamic carrier sense is enabled or not. + * + * @return + * - ESP_OK: succeed + * - others: failed + */ +esp_err_t esp_wifi_set_dynamic_cs(bool enabled); + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32s3/include/esp_wifi/include/esp_wifi_types.h b/tools/sdk/esp32s3/include/esp_wifi/include/esp_wifi_types.h index ac12c34b497..614bcd2cb5b 100644 --- a/tools/sdk/esp32s3/include/esp_wifi/include/esp_wifi_types.h +++ b/tools/sdk/esp32s3/include/esp_wifi/include/esp_wifi_types.h @@ -129,6 +129,7 @@ typedef enum { WIFI_REASON_AP_TSF_RESET = 206, WIFI_REASON_ROAMING = 207, WIFI_REASON_ASSOC_COMEBACK_TIME_TOO_LONG = 208, + WIFI_REASON_SA_QUERY_TIMEOUT = 209, } wifi_err_reason_t; typedef enum { diff --git a/tools/sdk/esp32s3/include/esp_wifi/wifi_apps/include/esp_nan.h b/tools/sdk/esp32s3/include/esp_wifi/wifi_apps/include/esp_nan.h index 0fba2bf5f57..9be6bbb6659 100644 --- a/tools/sdk/esp32s3/include/esp_wifi/wifi_apps/include/esp_nan.h +++ b/tools/sdk/esp32s3/include/esp_wifi/wifi_apps/include/esp_nan.h @@ -120,8 +120,8 @@ esp_err_t esp_wifi_nan_cancel_service(uint8_t service_id); * @param req NAN Datapath Request parameters. * * @return - * - non-zero: NAN Datapath Identifier - * - zero: failed + * - non-zero NAN Datapath identifier: If NAN datapath req was accepted by publisher + * - zero: If NAN datapath req was rejected by publisher or a timeout occurs */ uint8_t esp_wifi_nan_datapath_req(wifi_nan_datapath_req_t *req); diff --git a/tools/sdk/esp32s3/include/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/portmacro.h b/tools/sdk/esp32s3/include/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/portmacro.h index a1adffbd4f3..660c48a950e 100644 --- a/tools/sdk/esp32s3/include/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/portmacro.h +++ b/tools/sdk/esp32s3/include/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/portmacro.h @@ -523,6 +523,14 @@ extern void _frxt_setup_switch( void ); //Defined in portasm.S #define portALT_GET_RUN_TIME_COUNTER_VALUE(x) do {x = (uint32_t)esp_timer_get_time();} while(0) #endif +// --------------------- TCB Cleanup ----------------------- + +#if CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP +/* If enabled, users must provide an implementation of vPortCleanUpTCB() */ +extern void vPortCleanUpTCB ( void *pxTCB ); +#define portCLEAN_UP_TCB( pxTCB ) vPortCleanUpTCB( pxTCB ) +#endif /* CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP */ + // -------------- Optimized Task Selection ----------------- #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 @@ -627,7 +635,7 @@ FORCE_INLINE_ATTR BaseType_t xPortGetCoreID(void) /* ------------------------------------------------------ Misc --------------------------------------------------------- * - Miscellaneous porting macros - * - These are not port of the FreeRTOS porting interface, but are used by other FreeRTOS dependent components + * - These are not part of the FreeRTOS porting interface, but are used by other FreeRTOS dependent components * ------------------------------------------------------------------------------------------------------------------ */ // -------------------- Co-Processor ----------------------- diff --git a/tools/sdk/esp32s3/include/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/FreeRTOSConfig_arch.h b/tools/sdk/esp32s3/include/freertos/esp_additions/arch/xtensa/include/freertos/FreeRTOSConfig_arch.h similarity index 50% rename from tools/sdk/esp32s3/include/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/FreeRTOSConfig_arch.h rename to tools/sdk/esp32s3/include/freertos/esp_additions/arch/xtensa/include/freertos/FreeRTOSConfig_arch.h index cb0c78ec1f8..a7ed6d5e4a3 100644 --- a/tools/sdk/esp32s3/include/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/FreeRTOSConfig_arch.h +++ b/tools/sdk/esp32s3/include/freertos/esp_additions/arch/xtensa/include/freertos/FreeRTOSConfig_arch.h @@ -1,18 +1,17 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef FREERTOS_CONFIG_XTENSA_H -#define FREERTOS_CONFIG_XTENSA_H +#pragma once -//Xtensa Archiecture specific configuration. This file is included in the common FreeRTOSConfig.h. +/* Xtensa Architecture specific configuration. This file is included in the common FreeRTOSConfig.h. */ #include "sdkconfig.h" /* Required for configuration-dependent settings. */ -#include "xtensa_config.h" +#include "freertos/xtensa_config.h" /* -------------------------------------------- Xtensa Additional Config ---------------------------------------------- * - Provide Xtensa definitions usually given by -D option when building with xt-make (see readme_xtensa.txt) @@ -27,29 +26,55 @@ * - XT_USE_SWPRI We don't define this (unused) * ------------------------------------------------------------------------------------------------------------------ */ -#define configXT_SIMULATOR 0 -#define configXT_BOARD 1 /* Board mode */ +#define configXT_SIMULATOR 0 +#define configXT_BOARD 1 /* Board mode */ #if CONFIG_FREERTOS_CORETIMER_0 -#define configXT_TIMER_INDEX 0 + #define configXT_TIMER_INDEX 0 #elif CONFIG_FREERTOS_CORETIMER_1 -#define configXT_TIMER_INDEX 1 + #define configXT_TIMER_INDEX 1 #endif -#define configXT_INTEXC_HOOKS 0 +#define configXT_INTEXC_HOOKS 0 -#define configBENCHMARK 0 +#define configBENCHMARK 0 /* ------------------------------------------------- FreeRTOS Config --------------------------------------------------- * - All Vanilla FreeRTOS configuration goes into this section * ------------------------------------------------------------------------------------------------------------------ */ -// ------------------ Scheduler Related -------------------- +/* ------------------ Scheduler Related -------------------- */ +#define configMAX_PRIORITIES ( 25 ) #ifdef CONFIG_FREERTOS_OPTIMIZED_SCHEDULER -#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #else -#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 -#endif -#define configMAX_API_CALL_INTERRUPT_PRIORITY XCHAL_EXCM_LEVEL + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#endif /* CONFIG_FREERTOS_OPTIMIZED_SCHEDULER */ +#define configMINIMAL_STACK_SIZE ( CONFIG_FREERTOS_IDLE_TASK_STACKSIZE + configSTACK_OVERHEAD_TOTAL ) +#define configMAX_API_CALL_INTERRUPT_PRIORITY XCHAL_EXCM_LEVEL + +/* ----------------------- System -------------------------- */ + +#define configUSE_NEWLIB_REENTRANT 1 +#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1 + +/* ----------------------- Memory ------------------------- */ + +/* This isn't used as FreeRTOS will only allocate from internal memory (see + * heap_idf.c). We simply define this macro to span all non-statically-allocated + * shared RAM. */ +#define configTOTAL_HEAP_SIZE ( &_heap_end - &_heap_start ) + +/* ------------------- Run-time Stats ---------------------- */ + +#if CONFIG_FREERTOS_USE_TRACE_FACILITY + /* Used by uxTaskGetSystemState(), and other trace facility functions */ + #define configUSE_TRACE_FACILITY 1 +#endif /* CONFIG_FREERTOS_USE_TRACE_FACILITY */ + +/* -------------------- API Includes ----------------------- */ + +#define INCLUDE_xTaskDelayUntil 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 /* ------------------------------------------------ ESP-IDF Additions -------------------------------------------------- * @@ -60,9 +85,7 @@ * Size needs to be aligned to the stack increment, since the location of * the stack for the 2nd CPU will be calculated using configISR_STACK_SIZE. */ -#define configSTACK_ALIGNMENT 16 +#define configSTACK_ALIGNMENT 16 #ifndef configISR_STACK_SIZE -#define configISR_STACK_SIZE ((CONFIG_FREERTOS_ISR_STACKSIZE + configSTACK_ALIGNMENT - 1) & (~(configSTACK_ALIGNMENT - 1))) + #define configISR_STACK_SIZE ( ( CONFIG_FREERTOS_ISR_STACKSIZE + configSTACK_ALIGNMENT - 1 ) & ( ~( configSTACK_ALIGNMENT - 1 ) ) ) #endif - -#endif // FREERTOS_CONFIG_XTENSA_H diff --git a/tools/sdk/esp32s3/include/freertos/esp_additions/include/esp_private/freertos_idf_additions_priv.h b/tools/sdk/esp32s3/include/freertos/esp_additions/include/esp_private/freertos_idf_additions_priv.h new file mode 100644 index 00000000000..c6e6ba81c08 --- /dev/null +++ b/tools/sdk/esp32s3/include/freertos/esp_additions/include/esp_private/freertos_idf_additions_priv.h @@ -0,0 +1,99 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/* + * This file is like "idf_additions.h" but for private API (i.e., only meant to + * be called by other internally by other + * ESP-IDF components. + */ + +#include "sdkconfig.h" +#include "freertos/FreeRTOS.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/* ----------------------------------------------------------------------------- + * Priority Raise/Restore + * - Special functions to forcefully raise and restore a task's priority + * - Used by cache_utils.c when disabling/enabling the cache + * -------------------------------------------------------------------------- */ + +#if ( INCLUDE_vTaskPrioritySet == 1 ) + + typedef struct + { + UBaseType_t uxPriority; + #if ( configUSE_MUTEXES == 1 ) + UBaseType_t uxBasePriority; + #endif + } prvTaskSavedPriority_t; + +/** + * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be + * available. See the configuration section for more information. + * + * Saves the current priority and current base priority of a task, then + * raises the task's current and base priority to uxNewPriority if + * uxNewPriority is of a higher priority. + * + * Once a task's priority has been raised with this function, the priority + * can be restored by calling prvTaskPriorityRestore() + * + * - Note that this function differs from vTaskPrioritySet() as the task's + * current priority will be modified even if the task has already + * inherited a priority. + * - This function is intended for special circumstance where a task must be + * forced immediately to a higher priority. + * + * For configUSE_MUTEXES == 0: A context switch will occur before the + * function returns if the priority being set is higher than the currently + * executing task. + * + * @note This functions is private and should only be called internally + * within various IDF components. Users should never call this function from + * their application. + * + * @note vTaskPrioritySet() should not be called while a task's priority is + * already raised via this function + * + * @param pxSavedPriority returns base and current priorities + * + * @param uxNewPriority The priority to which the task's priority will be + * set. + */ + void prvTaskPriorityRaise( prvTaskSavedPriority_t * pxSavedPriority, + UBaseType_t uxNewPriority ); + +/** + * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be + * available. + * See the configuration section for more information. + * + * Restore a task's priority that was previously raised by + * prvTaskPriorityRaise(). + * + * For configUSE_MUTEXES == 0: A context switch will occur before the function + * returns if the priority + * being set is higher than the currently executing task. + * + * @note This functions is private and should only be called internally within + * various IDF components. Users should never call this function from their + * application. + * + * @param pxSavedPriority previously saved base and current priorities that need + * to be restored + */ + void prvTaskPriorityRestore( prvTaskSavedPriority_t * pxSavedPriority ); + +#endif // ( INCLUDE_vTaskPrioritySet == 1) + +#ifdef __cplusplus + } +#endif diff --git a/tools/sdk/esp32s3/include/freertos/esp_additions/include/freertos/FreeRTOSConfig.h b/tools/sdk/esp32s3/include/freertos/esp_additions/include/freertos/FreeRTOSConfig.h index 182ca817180..3a3c10ea253 100644 --- a/tools/sdk/esp32s3/include/freertos/esp_additions/include/freertos/FreeRTOSConfig.h +++ b/tools/sdk/esp32s3/include/freertos/esp_additions/include/freertos/FreeRTOSConfig.h @@ -1,293 +1,285 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H +#pragma once #include "sdkconfig.h" -/* -This file gets pulled into assembly sources. Therefore, some includes need to be wrapped in #ifndef __ASSEMBLER__ -*/ +/* This file gets pulled into assembly sources. Therefore, some includes need to + * be wrapped in #ifndef __ASSEMBLER__ */ #ifndef __ASSEMBLER__ -#include //For configASSERT() + /* For configASSERT() */ + #include #endif /* def __ASSEMBLER__ */ -#ifdef CONFIG_FREERTOS_SMP - -// Pull in the SMP configuration -#include "freertos/FreeRTOSConfig_smp.h" - -#else // CONFIG_FREERTOS_SMP - -// The arch-specific FreeRTOSConfig_arch.h in port//include. -#include "freertos/FreeRTOSConfig_arch.h" - -#if !(defined(FREERTOS_CONFIG_XTENSA_H) \ - || defined(FREERTOS_CONFIG_RISCV_H) \ - || defined(FREERTOS_CONFIG_LINUX_H)) -#error "Needs architecture-speific FreeRTOSConfig.h!" -#endif - /* ----------------------------------------------------- Helpers ------------------------------------------------------- * - Macros that the FreeRTOS configuration macros depend on * ------------------------------------------------------------------------------------------------------------------ */ /* Higher stack checker modes cause overhead on each function call */ #if CONFIG_STACK_CHECK_ALL || CONFIG_STACK_CHECK_STRONG -#define STACK_OVERHEAD_CHECKER 256 + #define STACK_OVERHEAD_CHECKER 256 #else -#define STACK_OVERHEAD_CHECKER 0 + #define STACK_OVERHEAD_CHECKER 0 #endif /* with optimizations disabled, scheduler uses additional stack */ #if CONFIG_COMPILER_OPTIMIZATION_NONE -#define STACK_OVERHEAD_OPTIMIZATION 320 + #define STACK_OVERHEAD_OPTIMIZATION 320 #else -#define STACK_OVERHEAD_OPTIMIZATION 0 + #define STACK_OVERHEAD_OPTIMIZATION 0 #endif /* apptrace mdule increases minimum stack usage */ #if CONFIG_APPTRACE_ENABLE -#define STACK_OVERHEAD_APPTRACE 1280 + #define STACK_OVERHEAD_APPTRACE 1280 #else -#define STACK_OVERHEAD_APPTRACE 0 + #define STACK_OVERHEAD_APPTRACE 0 #endif /* Stack watchpoint decreases minimum usable stack size by up to 60 bytes. - See FreeRTOS FREERTOS_WATCHPOINT_END_OF_STACK option in Kconfig. */ + * See FreeRTOS FREERTOS_WATCHPOINT_END_OF_STACK option in Kconfig. */ #if CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK -#define STACK_OVERHEAD_WATCHPOINT 60 + #define STACK_OVERHEAD_WATCHPOINT 60 #else -#define STACK_OVERHEAD_WATCHPOINT 0 + #define STACK_OVERHEAD_WATCHPOINT 0 #endif -#define configSTACK_OVERHEAD_TOTAL ( \ - STACK_OVERHEAD_CHECKER + \ - STACK_OVERHEAD_OPTIMIZATION + \ - STACK_OVERHEAD_APPTRACE + \ - STACK_OVERHEAD_WATCHPOINT \ - ) +#define configSTACK_OVERHEAD_TOTAL \ + ( \ + STACK_OVERHEAD_CHECKER + \ + STACK_OVERHEAD_OPTIMIZATION + \ + STACK_OVERHEAD_APPTRACE + \ + STACK_OVERHEAD_WATCHPOINT \ + ) + +/* The arch-specific FreeRTOSConfig_arch.h in esp_additions/arch_include/. + * Placed here due to configSTACK_OVERHEAD_TOTAL. Todo: IDF-5712. */ +#include "freertos/FreeRTOSConfig_arch.h" /* ------------------------------------------------- FreeRTOS Config --------------------------------------------------- * - All Vanilla FreeRTOS configuration goes into this section * - Keep this section in-sync with the corresponding version of single-core upstream version of FreeRTOS - * - Don't put any SMP or ESP-IDF exclusive FreeRTOS configurations here. Those go into the next section + * - Don't put any Amazon SMP FreeRTOS or IDF FreeRTOS configurations here. Those go into the next section * - Not all FreeRTOS configuration are listed. Some configurations have default values set in FreeRTOS.h thus don't * need to be explicitly defined. * ------------------------------------------------------------------------------------------------------------------ */ /*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - * - * See http://www.freertos.org/a00110.html - *----------------------------------------------------------*/ - -// ------------------ Scheduler Related -------------------- - -#define configUSE_PREEMPTION 1 -#define configUSE_TICKLESS_IDLE CONFIG_FREERTOS_USE_TICKLESS_IDLE +* Application specific definitions. +* +* These definitions should be adjusted for your particular hardware and +* application requirements. +* +* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE +* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. +* +* See http://www.freertos.org/a00110.html +*----------------------------------------------------------*/ + +/* ------------------ Scheduler Related -------------------- */ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE CONFIG_FREERTOS_USE_TICKLESS_IDLE #if configUSE_TICKLESS_IDLE -#define configEXPECTED_IDLE_TIME_BEFORE_SLEEP CONFIG_FREERTOS_IDLE_TIME_BEFORE_SLEEP -#endif //configUSE_TICKLESS_IDLE -#define configCPU_CLOCK_HZ (CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ * 1000000) -#define configTICK_RATE_HZ CONFIG_FREERTOS_HZ -#ifdef CONFIG_IDF_TARGET_LINUX -#define configMAX_PRIORITIES ( 7 ) // Default in upstream simulator -/* The stack allocated by FreeRTOS will be passed to a pthread. - pthread has a minimal stack size which currently is 16KB. - The rest is for additional structures of the POSIX/Linux port. - This is a magic number since PTHREAD_STACK_MIN seems to not be a constant. */ -#define configMINIMAL_STACK_SIZE ( ( unsigned short ) (0x4000 + 40) / sizeof(portSTACK_TYPE) ) -#else -#define configMAX_PRIORITIES ( 25 ) //This has impact on speed of search for highest priority -#define configMINIMAL_STACK_SIZE ( CONFIG_FREERTOS_IDLE_TASK_STACKSIZE + configSTACK_OVERHEAD_TOTAL ) -#endif -#define configUSE_TIME_SLICING 1 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 0 -#define configKERNEL_INTERRUPT_PRIORITY 1 //Todo: This currently isn't used anywhere - -// ------------- Synchronization Primitives ---------------- - -#define configUSE_MUTEXES 1 -#define configUSE_RECURSIVE_MUTEXES 1 -#define configUSE_COUNTING_SEMAPHORES 1 -#define configUSE_QUEUE_SETS 1 -#define configQUEUE_REGISTRY_SIZE CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE -#define configUSE_TASK_NOTIFICATIONS 1 -#define configTASK_NOTIFICATION_ARRAY_ENTRIES CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES - -// ----------------------- System -------------------------- - -#define configMAX_TASK_NAME_LEN CONFIG_FREERTOS_MAX_TASK_NAME_LEN -#define configNUM_THREAD_LOCAL_STORAGE_POINTERS CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS -#define configSTACK_DEPTH_TYPE uint32_t -#ifndef CONFIG_IDF_TARGET_LINUX -#define configUSE_NEWLIB_REENTRANT 1 -#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1 -#else -#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0 // Default in upstream simulator -#endif + #define configEXPECTED_IDLE_TIME_BEFORE_SLEEP CONFIG_FREERTOS_IDLE_TIME_BEFORE_SLEEP +#endif /* configUSE_TICKLESS_IDLE */ +#define configCPU_CLOCK_HZ ( CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ * 1000000 ) +#define configTICK_RATE_HZ CONFIG_FREERTOS_HZ +#define configUSE_TIME_SLICING 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configKERNEL_INTERRUPT_PRIORITY 1 /*Todo: This currently isn't used anywhere */ + +/* ------------- Synchronization Primitives ---------------- */ + +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_QUEUE_SETS 1 +#define configQUEUE_REGISTRY_SIZE CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE +#define configUSE_TASK_NOTIFICATIONS 1 +#define configTASK_NOTIFICATION_ARRAY_ENTRIES CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES + +/* ----------------------- System -------------------------- */ + +#define configMAX_TASK_NAME_LEN CONFIG_FREERTOS_MAX_TASK_NAME_LEN +#if CONFIG_FREERTOS_SMP +/* Number of TLSP is doubled to store TLSP deletion callbacks */ + #define configNUM_THREAD_LOCAL_STORAGE_POINTERS ( CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS * 2 ) +#else /* CONFIG_FREERTOS_SMP */ + #define configNUM_THREAD_LOCAL_STORAGE_POINTERS CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS +#endif /* CONFIG_FREERTOS_SMP */ +#define configSTACK_DEPTH_TYPE uint32_t #if CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY -#define configENABLE_BACKWARD_COMPATIBILITY 1 -#else -#define configENABLE_BACKWARD_COMPATIBILITY 0 -#endif -#define configASSERT(a) assert(a) - -// ----------------------- Memory ------------------------- - -#define configSUPPORT_STATIC_ALLOCATION 1 -#define configSUPPORT_DYNAMIC_ALLOCATION 1 -#ifdef CONFIG_IDF_TARGET_LINUX -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 65 * 1024 ) ) // Default in upstream simulator -#else -//We define the heap to span all of the non-statically-allocated shared RAM. ToDo: Make sure there -//is some space left for the app and main cpu when running outside of a thread. -#define configTOTAL_HEAP_SIZE (&_heap_end - &_heap_start)//( ( size_t ) (64 * 1024) ) -#endif -#define configAPPLICATION_ALLOCATED_HEAP 1 -#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 - -// ------------------------ Hooks -------------------------- - -#define configUSE_IDLE_HOOK CONFIG_FREERTOS_USE_IDLE_HOOK -#define configUSE_TICK_HOOK CONFIG_FREERTOS_USE_TICK_HOOK + #define configENABLE_BACKWARD_COMPATIBILITY 1 +#else /* CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY */ + #define configENABLE_BACKWARD_COMPATIBILITY 0 +#endif /* CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY */ +#define configASSERT( a ) assert( a ) + +/* ----------------------- Memory ------------------------- */ + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configAPPLICATION_ALLOCATED_HEAP 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +/* ------------------------ Hooks -------------------------- */ + +#if CONFIG_FREERTOS_USE_IDLE_HOOK + #define configUSE_IDLE_HOOK 1 +#else /* CONFIG_FREERTOS_USE_IDLE_HOOK */ + #define configUSE_IDLE_HOOK 0 +#endif /* CONFIG_FREERTOS_USE_IDLE_HOOK */ +#if CONFIG_FREERTOS_USE_TICK_HOOK + #define configUSE_TICK_HOOK 1 +#else /* CONFIG_FREERTOS_USE_TICK_HOOK */ + #define configUSE_TICK_HOOK 0 +#endif /* CONFIG_FREERTOS_USE_TICK_HOOK */ #if CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE -#define configCHECK_FOR_STACK_OVERFLOW 0 + #define configCHECK_FOR_STACK_OVERFLOW 0 #elif CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL -#define configCHECK_FOR_STACK_OVERFLOW 1 + #define configCHECK_FOR_STACK_OVERFLOW 1 #elif CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY -#define configCHECK_FOR_STACK_OVERFLOW 2 -#endif -#define configRECORD_STACK_HIGH_ADDRESS 1 // This must be set as the port requires TCB.pxEndOfStack + #define configCHECK_FOR_STACK_OVERFLOW 2 +#endif /* CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE */ +#define configRECORD_STACK_HIGH_ADDRESS 1 /* This must be set as the port requires TCB.pxEndOfStack */ -// ------------------- Run-time Stats ---------------------- +/* ------------------- Run-time Stats ---------------------- */ #ifdef CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS -#define configGENERATE_RUN_TIME_STATS 1 /* Used by vTaskGetRunTimeStats() */ -#endif -#ifdef CONFIG_IDF_TARGET_LINUX -#define configUSE_TRACE_FACILITY 1 -#else -#ifdef CONFIG_FREERTOS_USE_TRACE_FACILITY -#define configUSE_TRACE_FACILITY 1 /* Used by uxTaskGetSystemState(), and other trace facility functions */ -#endif -#endif + #define configGENERATE_RUN_TIME_STATS 1 /* Used by vTaskGetRunTimeStats() */ +#endif /* CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS */ #ifdef CONFIG_FREERTOS_USE_STATS_FORMATTING_FUNCTIONS -#define configUSE_STATS_FORMATTING_FUNCTIONS 1 /* Used by vTaskList() */ -#endif + #define configUSE_STATS_FORMATTING_FUNCTIONS 1 /* Used by vTaskList() */ +#endif /* CONFIG_FREERTOS_USE_STATS_FORMATTING_FUNCTIONS */ -// -------------------- Co-routines ----------------------- +/* -------------------- Co-routines ----------------------- */ -#define configUSE_CO_ROUTINES 0 // CO_ROUTINES are not supported in ESP-IDF -#define configMAX_CO_ROUTINE_PRIORITIES 2 +#define configUSE_CO_ROUTINES 0 /* CO_ROUTINES are not supported in ESP-IDF */ +#define configMAX_CO_ROUTINE_PRIORITIES 2 -// ------------------- Software Timer ---------------------- +/* ------------------- Software Timer ---------------------- */ -#define configUSE_TIMERS 1 -#define configTIMER_TASK_PRIORITY CONFIG_FREERTOS_TIMER_TASK_PRIORITY -#define configTIMER_QUEUE_LENGTH CONFIG_FREERTOS_TIMER_QUEUE_LENGTH -#define configTIMER_TASK_STACK_DEPTH CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY CONFIG_FREERTOS_TIMER_TASK_PRIORITY +#define configTIMER_QUEUE_LENGTH CONFIG_FREERTOS_TIMER_QUEUE_LENGTH +#define configTIMER_TASK_STACK_DEPTH CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH -// -------------------- API Includes ----------------------- +/* -------------------- API Includes ----------------------- */ #if CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY -#define configENABLE_BACKWARD_COMPATIBILITY 1 -#else -#define configENABLE_BACKWARD_COMPATIBILITY 0 -#endif - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelay 1 -#define INCLUDE_xTaskGetIdleTaskHandle 1 -#define INCLUDE_xTaskAbortDelay 1 -#define INCLUDE_xSemaphoreGetMutexHolder 1 -#define INCLUDE_xTaskGetHandle 1 -#define INCLUDE_uxTaskGetStackHighWaterMark 1 -#define INCLUDE_uxTaskGetStackHighWaterMark2 1 -#define INCLUDE_eTaskGetState 1 -#define INCLUDE_xTaskResumeFromISR 1 -#define INCLUDE_xTimerPendFunctionCall 1 -#define INCLUDE_xTaskGetSchedulerState 1 -#ifdef CONFIG_IDF_TARGET_LINUX -#define INCLUDE_xTaskGetCurrentTaskHandle 0 // not defined in POSIX simulator -#define INCLUDE_vTaskDelayUntil 1 -#else -#define INCLUDE_xTaskDelayUntil 1 -#define INCLUDE_xTaskGetCurrentTaskHandle 1 -#endif -//Unlisted -#define INCLUDE_pxTaskGetStackStart 1 - -// -------------------- Trace Macros ----------------------- + #define configENABLE_BACKWARD_COMPATIBILITY 1 +#else /* CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY */ + #define configENABLE_BACKWARD_COMPATIBILITY 0 +#endif /* CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetIdleTaskHandle 1 +#define INCLUDE_xTaskAbortDelay 1 +#define INCLUDE_xSemaphoreGetMutexHolder 1 +#define INCLUDE_xTaskGetHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_uxTaskGetStackHighWaterMark2 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTaskResumeFromISR 1 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskGetSchedulerState 1 +/* Unlisted */ +#define INCLUDE_pxTaskGetStackStart 1 + +/* -------------------- Trace Macros ----------------------- */ /* -For trace macros. -Note: Include trace macros here and not above as trace macros are dependent on some of the FreeRTOS configs -*/ + * For trace macros. + * Note: Include trace macros here and not above as trace macros are dependent on some of the FreeRTOS configs + */ #ifndef __ASSEMBLER__ -#if CONFIG_SYSVIEW_ENABLE -#include "SEGGER_SYSVIEW_FreeRTOS.h" -#undef INLINE // to avoid redefinition -#endif //CONFIG_SYSVIEW_ENABLE + #if CONFIG_SYSVIEW_ENABLE + #include "SEGGER_SYSVIEW_FreeRTOS.h" + #undef INLINE /* to avoid redefinition */ + #endif /* CONFIG_SYSVIEW_ENABLE */ + + #if CONFIG_FREERTOS_SMP + +/* Default values for trace macros added to ESP-IDF implementation of SYSVIEW + * that is not part of Amazon SMP FreeRTOS. */ + #ifndef traceISR_EXIT + #define traceISR_EXIT() + #endif + #ifndef traceISR_ENTER + #define traceISR_ENTER( _n_ ) + #endif + + #ifndef traceQUEUE_GIVE_FROM_ISR + #define traceQUEUE_GIVE_FROM_ISR( pxQueue ) + #endif + + #ifndef traceQUEUE_GIVE_FROM_ISR_FAILED + #define traceQUEUE_GIVE_FROM_ISR_FAILED( pxQueue ) + #endif + + #ifndef traceQUEUE_SEMAPHORE_RECEIVE + #define traceQUEUE_SEMAPHORE_RECEIVE( pxQueue ) + #endif + #endif /* CONFIG_FREERTOS_SMP */ #endif /* def __ASSEMBLER__ */ -/* ------------------------------------------------ ESP-IDF Additions -------------------------------------------------- - * - All FreeRTOS related configurations no part of Vanilla FreeRTOS goes into this section - * - FreeRTOS configurations related to SMP and ESP-IDF additions go into this section +/* ----------------------------------------------- Amazon SMP FreeRTOS ------------------------------------------------- + * - All Amazon SMP FreeRTOS specific configurations * ------------------------------------------------------------------------------------------------------------------ */ -// ------------------------- SMP --------------------------- - -#ifndef CONFIG_FREERTOS_UNICORE -#define portNUM_PROCESSORS 2 -#else -#define portNUM_PROCESSORS 1 -#endif -#define configNUM_CORES portNUM_PROCESSORS -#ifdef CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID -#define configTASKLIST_INCLUDE_COREID 1 -#endif - -// ---------------------- Features ------------------------- - -#ifdef CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS -#define configTHREAD_LOCAL_STORAGE_DELETE_CALLBACKS 1 -#endif - -#if CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER -#define configCHECK_MUTEX_GIVEN_BY_OWNER 1 -#else -#define configCHECK_MUTEX_GIVEN_BY_OWNER 0 -#endif - -#ifndef __ASSEMBLER__ -#if CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP -extern void vPortCleanUpTCB ( void *pxTCB ); -#define portCLEAN_UP_TCB( pxTCB ) vPortCleanUpTCB( pxTCB ) -#endif -#endif - -// -------------------- Compatibility ---------------------- +#if CONFIG_FREERTOS_SMP + #ifdef CONFIG_FREERTOS_UNICORE + #define configNUM_CORES 1 + #else + #define configNUM_CORES 2 + #endif /* CONFIG_FREERTOS_UNICORE */ + #define configUSE_CORE_AFFINITY 1 + #define configRUN_MULTIPLE_PRIORITIES 1 + #define configUSE_TASK_PREEMPTION_DISABLE 1 + +/* This is always enabled to call IDF style idle hooks, by can be "--Wl,--wrap" + * if users enable CONFIG_FREERTOS_USE_MINIMAL_IDLE_HOOK. */ + #define configUSE_MINIMAL_IDLE_HOOK 1 + +/* IDF Newlib supports dynamic reentrancy. We provide our own __getreent() + * function. */ + #define configNEWLIB_REENTRANT_IS_DYNAMIC 1 +#endif /* CONFIG_FREERTOS_SMP */ + +/* -------------------------------------------------- IDF FreeRTOS ----------------------------------------------------- + * - All IDF FreeRTOS specific configurations + * ------------------------------------------------------------------------------------------------------------------ */ -// backward compatibility for 4.4 -#define xTaskRemoveFromUnorderedEventList vTaskRemoveFromUnorderedEventList +#if !CONFIG_FREERTOS_SMP + #ifdef CONFIG_FREERTOS_UNICORE + #define configNUM_CORES 1 + #else + #define configNUM_CORES 2 + #endif /* CONFIG_FREERTOS_UNICORE */ + #ifdef CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID + #define configTASKLIST_INCLUDE_COREID 1 + #endif /* CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID */ + #ifdef CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS + #define configTHREAD_LOCAL_STORAGE_DELETE_CALLBACKS 1 + #endif /* CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS */ + #if CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER + #define configCHECK_MUTEX_GIVEN_BY_OWNER 1 + #endif /* CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER */ +#endif /* !CONFIG_FREERTOS_SMP */ -#endif // CONFIG_FREERTOS_SMP +/* ------------------------------------------------ ESP-IDF Additions -------------------------------------------------- + * - Any other macros required by the rest of ESP-IDF + * ------------------------------------------------------------------------------------------------------------------ */ -#endif /* FREERTOS_CONFIG_H */ +#define portNUM_PROCESSORS configNUM_CORES diff --git a/tools/sdk/esp32s3/include/freertos/esp_additions/include/freertos/idf_additions.h b/tools/sdk/esp32s3/include/freertos/esp_additions/include/freertos/idf_additions.h index 6523575c8da..22aac424b74 100644 --- a/tools/sdk/esp32s3/include/freertos/esp_additions/include/freertos/idf_additions.h +++ b/tools/sdk/esp32s3/include/freertos/esp_additions/include/freertos/idf_additions.h @@ -1,45 +1,65 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ +#pragma once + +/* + * This file contains the function prototypes of ESP-IDF specific API additions + * to the FreeRTOS kernel. These API additions are not part of Vanilla (i.e., + * upstream) FreeRTOS and include things such as.... + * - Various helper functions + * - API for ESP-IDF feature additions to FreeRTOS (such as TSLP deletion + * call backs) + */ + #include "sdkconfig.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" -#include "idf_additions_inc.h" -#if CONFIG_FREERTOS_SMP || __DOXYGEN__ +#ifdef __cplusplus + extern "C" { +#endif -/* ------------------------------------------------ Helper Functions --------------------------------------------------- +/* ----------------------------------------------------------------------------- + * SMP related API additions to FreeRTOS * - * ------------------------------------------------------------------------------------------------------------------ */ + * Todo: Move IDF FreeRTOS SMP related additions to this header as well (see + * IDF-7201) + * -------------------------------------------------------------------------- */ + +#if CONFIG_FREERTOS_SMP || __DOXYGEN__ /** * @brief Create a new task that is pinned to a particular core * - * Helper function to create a task that is pinned to a particular core, or has no affinity. In other wrods, the created - * task will have an affinity mask of: + * Helper function to create a task that is pinned to a particular core, or has + * no affinity. In other wrods, the created task will have an affinity mask of: * - (1 << xCoreID) if it is pinned to a particular core * - Set to tskNO_AFFINITY if it has no affinity * * @param pxTaskCode Pointer to the task entry function. * @param pcName A descriptive name for the task. * @param usStackDepth The size of the task stack. - * @param pvParameters Pointer that will be used as the parameter for the task being created. + * @param pvParameters Pointer that will be used as the parameter for the task + * being created. * @param uxPriority The priority at which the task should run. - * @param pxCreatedTask Used to pass back a handle by which the created task can be referenced. - * @param xCoreID The core to which the task is pinned to, or tskNO_AFFINITY if the task has no core affinity - * @return pdPASS if the task was successfully created and added to a ready list, otherwise an error code defined in the - * file projdefs.h + * @param pxCreatedTask Used to pass back a handle by which the created task can + * be referenced. + * @param xCoreID The core to which the task is pinned to, or tskNO_AFFINITY if + * the task has no core affinity + * @return pdPASS if the task was successfully created and added to a ready + * list, otherwise an error code defined in the file projdefs.h */ -BaseType_t xTaskCreatePinnedToCore( TaskFunction_t pxTaskCode, - const char * const pcName, - const uint32_t usStackDepth, - void * const pvParameters, - UBaseType_t uxPriority, - TaskHandle_t * const pxCreatedTask, - const BaseType_t xCoreID); + BaseType_t xTaskCreatePinnedToCore( TaskFunction_t pxTaskCode, + const char * const pcName, + const uint32_t usStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask, + const BaseType_t xCoreID ); /** @@ -50,142 +70,118 @@ BaseType_t xTaskCreatePinnedToCore( TaskFunction_t pxTaskCode, * @param pxTaskCode Pointer to the task entry function. * @param pcName A descriptive name for the task. * @param ulStackDepth The size of the task stack. - * @param pvParameters Pointer that will be used as the parameter for the task being created. + * @param pvParameters Pointer that will be used as the parameter for the task + * being created. * @param uxPriority The priority at which the task should run. - * @param puxStackBuffer Must point to a StackType_t array that has at least ulStackDepth indexes - * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will then be used to hold the task's data structures, - * @param xCoreID The core to which the task is pinned to, or tskNO_AFFINITY if the task has no core affinity + * @param puxStackBuffer Must point to a StackType_t array that has at least + * ulStackDepth indexes + * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will + * then be used to hold the task's data structures, + * @param xCoreID The core to which the task is pinned to, or tskNO_AFFINITY if + * the task has no core affinity * @return The task handle if the task was created, NULL otherwise. */ -#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) -TaskHandle_t xTaskCreateStaticPinnedToCore( TaskFunction_t pxTaskCode, - const char * const pcName, - const uint32_t ulStackDepth, - void * const pvParameters, - UBaseType_t uxPriority, - StackType_t * const puxStackBuffer, - StaticTask_t * const pxTaskBuffer, - const BaseType_t xCoreID ); -#endif /* configSUPPORT_STATIC_ALLOCATION */ + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + TaskHandle_t xTaskCreateStaticPinnedToCore( TaskFunction_t pxTaskCode, + const char * const pcName, + const uint32_t ulStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer, + const BaseType_t xCoreID ); + #endif /* configSUPPORT_STATIC_ALLOCATION */ /** * @brief Get the handle of the task running on a certain core * - * Because of the nature of SMP processing, there is no guarantee that this value will still be valid on return and - * should only be used for debugging purposes. + * Because of the nature of SMP processing, there is no guarantee that this + * value will still be valid on return and should only be used for debugging + * purposes. * - * [refactor-todo] Mark this function as deprecated, call xTaskGetCurrentTaskHandleCPU() instead + * [refactor-todo] Mark this function as deprecated, call + * xTaskGetCurrentTaskHandleCPU() instead * * @param xCoreID The core to query * @return Handle of the current task running on the queried core */ -TaskHandle_t xTaskGetCurrentTaskHandleForCPU( BaseType_t xCoreID ); + TaskHandle_t xTaskGetCurrentTaskHandleForCPU( BaseType_t xCoreID ); /** * @brief Get the handle of idle task for the given CPU. * - * [refactor-todo] Mark this function as deprecated, call xTaskGetIdleTaskHandle() instead + * [refactor-todo] Mark this function as deprecated, call + * xTaskGetIdleTaskHandle() instead * * @param xCoreID The core to query * @return Handle of the idle task for the queried core */ -TaskHandle_t xTaskGetIdleTaskHandleForCPU( BaseType_t xCoreID ); + TaskHandle_t xTaskGetIdleTaskHandleForCPU( BaseType_t xCoreID ); /** * @brief Get the current core affintiy of a particular task * - * Helper function to get the core affinity of a particular task. If the task is pinned to a particular core, the core - * ID is returned. If the task is not pinned to a particular core, tskNO_AFFINITY is returned. + * Helper function to get the core affinity of a particular task. If the task is + * pinned to a particular core, the core ID is returned. If the task is not + * pinned to a particular core, tskNO_AFFINITY is returned. * - * [refactor-todo] Mark this function as deprecated, call vTaskCoreAffinityGet() instead + * [refactor-todo] Mark this function as deprecated, call vTaskCoreAffinityGet() + * instead * * @param xTask The task to query * @return The tasks coreID or tskNO_AFFINITY */ -BaseType_t xTaskGetAffinity( TaskHandle_t xTask ); - -#if ( CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS ) - - /** - * Prototype of local storage pointer deletion callback. - */ - typedef void (*TlsDeleteCallbackFunction_t)( int, void * ); - - /** - * Set local storage pointer and deletion callback. - * - * Each task contains an array of pointers that is dimensioned by the - * configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h. - * The kernel does not use the pointers itself, so the application writer - * can use the pointers for any purpose they wish. - * - * Local storage pointers set for a task can reference dynamically - * allocated resources. This function is similar to - * vTaskSetThreadLocalStoragePointer, but provides a way to release - * these resources when the task gets deleted. For each pointer, - * a callback function can be set. This function will be called - * when task is deleted, with the local storage pointer index - * and value as arguments. - * - * @param xTaskToSet Task to set thread local storage pointer for - * @param xIndex The index of the pointer to set, from 0 to - * configNUM_THREAD_LOCAL_STORAGE_POINTERS - 1. - * @param pvValue Pointer value to set. - * @param pvDelCallback Function to call to dispose of the local - * storage pointer when the task is deleted. - */ - void vTaskSetThreadLocalStoragePointerAndDelCallback( - TaskHandle_t xTaskToSet, - BaseType_t xIndex, - void *pvValue, - TlsDeleteCallbackFunction_t pvDelCallback); -#endif // CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS + BaseType_t xTaskGetAffinity( TaskHandle_t xTask ); #endif // CONFIG_FREERTOS_SMP || __DOXYGEN__ -#if ( INCLUDE_vTaskPrioritySet == 1 ) +/* ----------------------------------------------------------------------------- + * TLSP Deletion Callback related API additions + * + * Todo: Move IDF FreeRTOS TLSP Deletion Callback related additions to this + * header as well (see IDF-7201) + * -------------------------------------------------------------------------- */ + +#if CONFIG_FREERTOS_SMP || __DOXYGEN__ + + #if ( CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS ) /** - * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Saves the current priority and current base priority of a task, then raises the tasks - * current and base priority to uxNewPriority if uxNewPriority is of a higher priority. - * Once a task's priority has been raised with this function, the priority can be restored - * by calling prvTaskPriorityRestore() - * - Note that this function differs from vTaskPrioritySet() as the task's current priority - * will be modified even if the task has already inherited a priority. - * - This function is intended for special circumstance where a task must be forced immediately - * to a higher priority. - * - * For configUSE_MUTEXES == 0: A context switch will occur before the function returns if the priority - * being set is higher than the currently executing task. - * - * @note This functions is private is only be called internally within various IDF components. - * Users should never call this function from their application. - * - * @note vTaskPrioritySet() should not be called while a task's priority is already raised via this function - * - * @param pxSavedPriority returns base and current priorities - * - * @param uxNewPriority The priority to which the task will be set. + * Prototype of local storage pointer deletion callback. */ -void prvTaskPriorityRaise( prvTaskSavedPriority_t * pxSavedPriority, UBaseType_t uxNewPriority ); + typedef void (* TlsDeleteCallbackFunction_t)( int, + void * ); /** - * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Restore a task's priority that was previously raised by prvTaskPriorityRaise(). - * - * For configUSE_MUTEXES == 0: A context switch will occur before the function returns if the priority - * being set is higher than the currently executing task. - * - * @note This functions is private is only be called internally within various IDF components. - * Users should never call this function from their application. - * - * @param pxSavedPriority previously saved base and current priorities that need to be restored + * Set local storage pointer and deletion callback. + * + * Each task contains an array of pointers that is dimensioned by the + * configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h. The + * kernel does not use the pointers itself, so the application writer can use + * the pointers for any purpose they wish. + * + * Local storage pointers set for a task can reference dynamically allocated + * resources. This function is similar to vTaskSetThreadLocalStoragePointer, but + * provides a way to release these resources when the task gets deleted. For + * each pointer, a callback function can be set. This function will be called + * when task is deleted, with the local storage pointer index and value as + * arguments. + * + * @param xTaskToSet Task to set thread local storage pointer for + * @param xIndex The index of the pointer to set, from 0 to + * configNUM_THREAD_LOCAL_STORAGE_POINTERS - 1. + * @param pvValue Pointer value to set. + * @param pvDelCallback Function to call to dispose of the local storage + * pointer when the task is deleted. */ -void prvTaskPriorityRestore( prvTaskSavedPriority_t * pxSavedPriority ); + void vTaskSetThreadLocalStoragePointerAndDelCallback( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue, + TlsDeleteCallbackFunction_t pvDelCallback ); + #endif // CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS + +#endif // CONFIG_FREERTOS_SMP || __DOXYGEN__ -#endif // ( INCLUDE_vTaskPrioritySet == 1) +#ifdef __cplusplus + } +#endif diff --git a/tools/sdk/esp32s3/include/freertos/esp_additions/include/freertos/idf_additions_inc.h b/tools/sdk/esp32s3/include/freertos/esp_additions/include/freertos/idf_additions_inc.h deleted file mode 100644 index 25b0b6d9a4d..00000000000 --- a/tools/sdk/esp32s3/include/freertos/esp_additions/include/freertos/idf_additions_inc.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - - -#ifndef FREERTOS_ADDITITIONS_INC_H_ -#define FREERTOS_ADDITITIONS_INC_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "sdkconfig.h" -#include "freertos/FreeRTOS.h" - -#if ( INCLUDE_vTaskPrioritySet == 1 ) - -typedef struct { - UBaseType_t uxPriority; -#if ( configUSE_MUTEXES == 1 ) - UBaseType_t uxBasePriority; -#endif -} prvTaskSavedPriority_t; - -#endif // ( INCLUDE_vTaskPrioritySet == 1) - -#ifdef __cplusplus -} -#endif - -#endif //FREERTOS_ADDITITIONS_INC_H_ diff --git a/tools/sdk/esp32s3/include/hal/esp32s3/include/hal/cache_ll.h b/tools/sdk/esp32s3/include/hal/esp32s3/include/hal/cache_ll.h index fa6c6b966eb..9b0ce94b136 100644 --- a/tools/sdk/esp32s3/include/hal/esp32s3/include/hal/cache_ll.h +++ b/tools/sdk/esp32s3/include/hal/esp32s3/include/hal/cache_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -100,6 +100,37 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, dbus_mask); } +/** + * Returns enabled buses for a given core + * + * @param cache_id cache ID (when l1 cache is per core) + * + * @return State of enabled buses + */ +__attribute__((always_inline)) +static inline cache_bus_mask_t cache_ll_l1_get_enabled_bus(uint32_t cache_id) +{ + cache_bus_mask_t mask = 0; + HAL_ASSERT(cache_id == 0 || cache_id == 1); + //On esp32s3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first + + uint32_t ibus_mask = REG_READ(EXTMEM_ICACHE_CTRL1_REG); + if (cache_id == 0) { + mask |= (!(ibus_mask & EXTMEM_ICACHE_SHUT_CORE0_BUS)) ? CACHE_BUS_IBUS0 : 0; + } else { + mask |= (!(ibus_mask & EXTMEM_ICACHE_SHUT_CORE1_BUS)) ? CACHE_BUS_IBUS0 : 0; + } + + uint32_t dbus_mask = REG_READ(EXTMEM_DCACHE_CTRL1_REG); + if (cache_id == 1) { + mask |= (!(dbus_mask & EXTMEM_DCACHE_SHUT_CORE0_BUS)) ? CACHE_BUS_DBUS0 : 0; + } else { + mask |= (!(dbus_mask & EXTMEM_DCACHE_SHUT_CORE1_BUS)) ? CACHE_BUS_DBUS0 : 0; + } + + return mask; +} + /** * Disable the Cache Buses * diff --git a/tools/sdk/esp32s3/include/hal/esp32s3/include/hal/clk_tree_ll.h b/tools/sdk/esp32s3/include/hal/esp32s3/include/hal/clk_tree_ll.h index c2534134a70..c333775d6b4 100644 --- a/tools/sdk/esp32s3/include/hal/esp32s3/include/hal/clk_tree_ll.h +++ b/tools/sdk/esp32s3/include/hal/esp32s3/include/hal/clk_tree_ll.h @@ -12,6 +12,7 @@ #include "soc/rtc.h" #include "soc/system_reg.h" #include "soc/rtc_cntl_reg.h" +#include "soc/regi2c_defs.h" #include "hal/regi2c_ctrl.h" #include "soc/regi2c_bbpll.h" #include "hal/assert.h" @@ -682,6 +683,45 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(v return REG_READ(RTC_SLOW_CLK_CAL_REG); } +/** + * @brief Configure PLL frequency for MSPI timing tuning + * @note Only used by the MSPI Timing tuning driver + * + * @param xtal_freq Xtal frequency + * @param pll_freq PLL frequency + * @param oc_div OC divider + * @param oc_ref_div OC ref divider + */ +static inline __attribute__((always_inline)) +void clk_ll_bbpll_set_frequency_for_mspi_tuning(rtc_xtal_freq_t xtal_freq, int pll_freq, uint8_t oc_div, uint8_t oc_ref_div) +{ + HAL_ASSERT(xtal_freq == RTC_XTAL_FREQ_40M); + uint32_t pll_reg = GET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PD | + RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD); + HAL_ASSERT(pll_reg == 0); + + /* Set this register to let the digital part know 480M PLL is used */ + SET_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL); + uint8_t dr1 = 0; + uint8_t dr3 = 0; + uint8_t dchgp = 5; + uint8_t dcur = 3; + uint8_t dbias = 2; + uint8_t i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | (oc_ref_div); + uint8_t i2c_bbpll_div_7_0 = oc_div; + REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x6B); + + uint8_t i2c_bbpll_dcur = (1 << I2C_BBPLL_OC_DLREF_SEL_LSB ) | (3 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur; + REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref); + REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0); + REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR1, dr1); + REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3); + REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur); + REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_VCO_DBIAS, dbias); + REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DHREF_SEL, 3); + REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DLREF_SEL, 1); +} + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32s3/include/hal/esp32s3/include/hal/efuse_ll.h b/tools/sdk/esp32s3/include/hal/esp32s3/include/hal/efuse_ll.h index 7e2b6bb789c..19bb37734ac 100644 --- a/tools/sdk/esp32s3/include/hal/esp32s3/include/hal/efuse_ll.h +++ b/tools/sdk/esp32s3/include/hal/esp32s3/include/hal/efuse_ll.h @@ -22,32 +22,32 @@ extern "C" { __attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void) { - return EFUSE.rd_repeat_data1.reg_spi_boot_crypt_cnt; + return EFUSE.rd_repeat_data1.spi_boot_crypt_cnt; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void) { - return EFUSE.rd_repeat_data1.reg_wdt_delay_sel; + return EFUSE.rd_repeat_data1.wdt_delay_sel; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_type(void) { - return EFUSE.rd_repeat_data3.reg_flash_type; + return EFUSE.rd_repeat_data3.flash_type; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void) { - return EFUSE.rd_mac_spi_sys_0; + return EFUSE.rd_mac_spi_sys_0.mac_0; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void) { - return EFUSE.rd_mac_spi_sys_1.reg_mac_1; + return EFUSE.rd_mac_spi_sys_1.mac_1; } __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void) { - return EFUSE.rd_repeat_data2.reg_secure_boot_en; + return EFUSE.rd_repeat_data2.secure_boot_en; } // use efuse_hal_get_major_chip_version() to get major chip version @@ -59,7 +59,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_ve // use efuse_hal_get_minor_chip_version() to get minor chip version __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void) { - return (EFUSE.rd_mac_spi_sys_5.wafer_version_minor_high << 3) + EFUSE.rd_mac_spi_sys_3.wafer_version_minor_low; + return (EFUSE.rd_mac_spi_sys_5.wafer_version_minor_hi << 3) + EFUSE.rd_mac_spi_sys_3.wafer_version_minor_lo; } __attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void) @@ -108,7 +108,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_k_dig_ldo(voi __attribute__((always_inline)) static inline uint32_t efuse_ll_get_v_rtc_dbias20(void) { // EFUSE_BLK1, 155, 8, BLOCK1 voltage of rtc dbias20 - return (EFUSE.rd_mac_spi_sys_5.v_rtc_dbias20_hi << 5) + EFUSE.rd_mac_spi_sys_4.v_rtc_dbias20_low; + return (EFUSE.rd_mac_spi_sys_5.v_rtc_dbias20_1 << 5) + EFUSE.rd_mac_spi_sys_4.v_rtc_dbias20; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_v_dig_dbias20(void) diff --git a/tools/sdk/esp32s3/include/hal/esp32s3/include/hal/gdma_ll.h b/tools/sdk/esp32s3/include/hal/esp32s3/include/hal/gdma_ll.h index 2fc70293039..88ca2b91c4c 100644 --- a/tools/sdk/esp32s3/include/hal/esp32s3/include/hal/gdma_ll.h +++ b/tools/sdk/esp32s3/include/hal/esp32s3/include/hal/gdma_ll.h @@ -18,6 +18,8 @@ extern "C" { #define GDMA_LL_GET_HW(id) (((id) == 0) ? (&GDMA) : NULL) +#define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5] + #define GDMA_LL_RX_EVENT_MASK (0x3FF) #define GDMA_LL_TX_EVENT_MASK (0xFF) diff --git a/tools/sdk/esp32s3/include/hal/esp32s3/include/hal/ledc_ll.h b/tools/sdk/esp32s3/include/hal/esp32s3/include/hal/ledc_ll.h index d2543733253..101443a2f02 100644 --- a/tools/sdk/esp32s3/include/hal/esp32s3/include/hal/ledc_ll.h +++ b/tools/sdk/esp32s3/include/hal/esp32s3/include/hal/ledc_ll.h @@ -33,6 +33,9 @@ extern "C" { LEDC_SLOW_CLK_RC_FAST, \ } +#define LEDC_LL_GLOBAL_CLK_DEFAULT LEDC_SLOW_CLK_RC_FAST + + /** * @brief Set LEDC low speed timer clock * diff --git a/tools/sdk/esp32s3/include/hal/esp32s3/include/hal/mspi_timing_tuning_ll.h b/tools/sdk/esp32s3/include/hal/esp32s3/include/hal/mspi_timing_tuning_ll.h index ce400c1c2c0..e1eade89416 100644 --- a/tools/sdk/esp32s3/include/hal/esp32s3/include/hal/mspi_timing_tuning_ll.h +++ b/tools/sdk/esp32s3/include/hal/esp32s3/include/hal/mspi_timing_tuning_ll.h @@ -238,6 +238,7 @@ static inline mspi_timing_ll_flash_mode_t mspi_timing_ll_get_flash_mode(uint8_t return MSPI_TIMING_LL_FLASH_SLOW_MODE; default: HAL_ASSERT(false); + return 0; } } diff --git a/tools/sdk/esp32s3/include/hal/esp32s3/include/hal/spimem_flash_ll.h b/tools/sdk/esp32s3/include/hal/esp32s3/include/hal/spimem_flash_ll.h index 3c325bf8391..4e8d5744f65 100644 --- a/tools/sdk/esp32s3/include/hal/esp32s3/include/hal/spimem_flash_ll.h +++ b/tools/sdk/esp32s3/include/hal/esp32s3/include/hal/spimem_flash_ll.h @@ -575,6 +575,9 @@ static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void) case 2: clock_val = 160; break; + case 3: + clock_val = 240; + break; default: abort(); } diff --git a/tools/sdk/esp32s3/include/hal/include/hal/ecdsa_hal.h b/tools/sdk/esp32s3/include/hal/include/hal/ecdsa_hal.h new file mode 100644 index 00000000000..d7244b3dc05 --- /dev/null +++ b/tools/sdk/esp32s3/include/hal/include/hal/ecdsa_hal.h @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/******************************************************************************* + * NOTICE + * The HAL is not public api, don't use in application code. + * See readme.md in soc/README.md + ******************************************************************************/ + +#pragma once + +#include +#include "hal/ecdsa_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * ECDSA peripheral config structure + */ +typedef struct { + ecdsa_mode_t mode; /* Mode of operation */ + ecdsa_curve_t curve; /* Curve to use for operation */ + ecdsa_k_mode_t k_mode; /* Source of K */ + ecdsa_sha_mode_t sha_mode; /* Source of SHA that needs to be signed */ +} ecdsa_hal_config_t; + +/** + * @brief Generate ECDSA signature + * + * @param conf Configuration for ECDSA operation, see ``ecdsa_hal_config_t`` + * @param k Value of K used internally. Set this to NULL if K is generated by hardware + * @param hash Hash that is to be signed + * @param r_out Buffer that will contain `R` component of ECDSA signature + * @param s_out Buffer that will contain `S` component of ECDSA signature + * @param len Length of the r_out and s_out buffer (32 bytes for SECP256R1, 24 for SECP192R1) + */ +void ecdsa_hal_gen_signature(ecdsa_hal_config_t *conf, const uint8_t *k, const uint8_t *hash, + uint8_t *r_out, uint8_t *s_out, uint16_t len); + +/** + * @brief Verify given ECDSA signature + * + * @param conf Configuration for ECDSA operation, see ``ecdsa_hal_config_t`` + * @param hash Hash that was signed + * @param r `R` component of ECDSA signature + * @param s `S` component of ECDSA signature + * @param pub_x X coordinate of public key + * @param pub_y Y coordinate of public key + * @param len Length of r and s buffer (32 bytes for SECP256R1, 24 for SECP192R1) + * + * @return - 0, if the signature matches + * - -1, if verification fails + */ +int ecdsa_hal_verify_signature(ecdsa_hal_config_t *conf, const uint8_t *hash, const uint8_t *r, const uint8_t *s, + const uint8_t *pub_x, const uint8_t *pub_y, uint16_t len); +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s3/include/hal/include/hal/ecdsa_types.h b/tools/sdk/esp32s3/include/hal/include/hal/ecdsa_types.h new file mode 100644 index 00000000000..fdb2f3d3cf0 --- /dev/null +++ b/tools/sdk/esp32s3/include/hal/include/hal/ecdsa_types.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief ECDSA peripheral work modes + */ +typedef enum { + ECDSA_MODE_SIGN_VERIFY, + ECDSA_MODE_SIGN_GEN, +} ecdsa_mode_t; + +/** + * @brief ECDSA curve options + */ +typedef enum { + ECDSA_CURVE_SECP192R1, + ECDSA_CURVE_SECP256R1, +} ecdsa_curve_t; + +/** + * @brief Source of 'K' used internally for generating signature + */ +typedef enum { + ECDSA_K_USE_TRNG, + ECDSA_K_USER_PROVIDED, +} ecdsa_k_mode_t; + +/** + * @brief Source of SHA message that is to be signed/verified + */ +typedef enum { + ECDSA_Z_USE_SHA_PERI, + ECDSA_Z_USER_PROVIDED, +} ecdsa_sha_mode_t; + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s3/include/hal/include/hal/efuse_hal.h b/tools/sdk/esp32s3/include/hal/include/hal/efuse_hal.h index 2f141b74404..bb11c9ae7b3 100644 --- a/tools/sdk/esp32s3/include/hal/include/hal/efuse_hal.h +++ b/tools/sdk/esp32s3/include/hal/include/hal/efuse_hal.h @@ -26,6 +26,15 @@ void efuse_hal_get_mac(uint8_t *mac); */ uint32_t efuse_hal_chip_revision(void); +/** + * @brief Is flash encryption currently enabled in hardware? + * + * Flash encryption is enabled if the FLASH_CRYPT_CNT efuse has an odd number of bits set. + * + * @return true if flash encryption is enabled. + */ +bool efuse_hal_flash_encryption_enabled(void); + /** * @brief Returns major chip version */ diff --git a/tools/sdk/esp32s3/include/hal/include/hal/modem_clock_hal.h b/tools/sdk/esp32s3/include/hal/include/hal/modem_clock_hal.h new file mode 100644 index 00000000000..9912308f5eb --- /dev/null +++ b/tools/sdk/esp32s3/include/hal/include/hal/modem_clock_hal.h @@ -0,0 +1,48 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The HAL layer for MODEM CLOCK + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc/soc_caps.h" +#include "hal/modem_syscon_ll.h" +#include "hal/modem_lpcon_ll.h" +#include "hal/modem_clock_types.h" + +typedef struct { + modem_syscon_dev_t *syscon_dev; + modem_lpcon_dev_t *lpcon_dev; +} modem_clock_hal_context_t; + +#if MAC_SUPPORT_PMU_MODEM_STATE +void modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain, uint32_t bitmap); +#endif + +void modem_clock_hal_enable_fe_clock(modem_clock_hal_context_t *hal, bool enable); + +#if SOC_BT_SUPPORTED +void modem_clock_hal_set_ble_rtc_timer_divisor_value(modem_clock_hal_context_t *hal, uint32_t divider); +void modem_clock_hal_enable_ble_rtc_timer_clock(modem_clock_hal_context_t *hal, bool enable); +void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src); +void modem_clock_hal_deselect_all_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t *hal); +#endif + +void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src); +void modem_clock_hal_deselect_all_coex_lpclk_source(modem_clock_hal_context_t *hal); + +#if SOC_WIFI_SUPPORTED +void modem_clock_hal_select_wifi_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src); +void modem_clock_hal_deselect_all_wifi_lpclk_source(modem_clock_hal_context_t *hal); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s3/include/hal/include/hal/rmt_types.h b/tools/sdk/esp32s3/include/hal/include/hal/rmt_types.h index 1082761d87a..7650c78bb70 100644 --- a/tools/sdk/esp32s3/include/hal/include/hal/rmt_types.h +++ b/tools/sdk/esp32s3/include/hal/include/hal/rmt_types.h @@ -1,11 +1,12 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once +#include #include "soc/clk_tree_defs.h" #include "soc/soc_caps.h" @@ -28,12 +29,12 @@ typedef int rmt_clock_source_t; */ typedef union { struct { - unsigned int duration0 : 15; /*!< Duration of level0 */ - unsigned int level0 : 1; /*!< Level of the first part */ - unsigned int duration1 : 15; /*!< Duration of level1 */ - unsigned int level1 : 1; /*!< Level of the second part */ + uint16_t duration0 : 15; /*!< Duration of level0 */ + uint16_t level0 : 1; /*!< Level of the first part */ + uint16_t duration1 : 15; /*!< Duration of level1 */ + uint16_t level1 : 1; /*!< Level of the second part */ }; - unsigned int val; /*!< Equivalent unsigned value for the RMT symbol */ + uint32_t val; /*!< Equivalent unsigned value for the RMT symbol */ } rmt_symbol_word_t; #ifdef __cplusplus diff --git a/tools/sdk/esp32s3/include/hal/include/hal/spi_slave_hd_hal.h b/tools/sdk/esp32s3/include/hal/include/hal/spi_slave_hd_hal.h index 099139cc015..d426f97e970 100644 --- a/tools/sdk/esp32s3/include/hal/include/hal/spi_slave_hd_hal.h +++ b/tools/sdk/esp32s3/include/hal/include/hal/spi_slave_hd_hal.h @@ -1,16 +1,8 @@ -// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ /******************************************************************************* * NOTICE @@ -258,8 +250,7 @@ int spi_slave_hd_hal_get_rxlen(spi_slave_hd_hal_context_t *hal); */ int spi_slave_hd_hal_get_last_addr(spi_slave_hd_hal_context_t *hal); -#if CONFIG_IDF_TARGET_ESP32S2 -//Append mode is only supported on ESP32S2 now + //////////////////////////////////////////////////////////////////////////////// // Append Mode //////////////////////////////////////////////////////////////////////////////// @@ -315,4 +306,3 @@ esp_err_t spi_slave_hd_hal_txdma_append(spi_slave_hd_hal_context_t *hal, uint8_t * - ESP_ERR_INVALID_STATE: Function called in invalid state. */ esp_err_t spi_slave_hd_hal_rxdma_append(spi_slave_hd_hal_context_t *hal, uint8_t *data, size_t len, void *arg); -#endif //#if CONFIG_IDF_TARGET_ESP32S2 diff --git a/tools/sdk/esp32s3/include/heap/include/esp_heap_caps.h b/tools/sdk/esp32s3/include/heap/include/esp_heap_caps.h index e5adf162b83..f3d1026c8b5 100644 --- a/tools/sdk/esp32s3/include/heap/include/esp_heap_caps.h +++ b/tools/sdk/esp32s3/include/heap/include/esp_heap_caps.h @@ -11,6 +11,7 @@ #include "multi_heap.h" #include #include "esp_err.h" +#include "esp_attr.h" #ifdef __cplusplus extern "C" { @@ -53,6 +54,26 @@ typedef void (*esp_alloc_failed_hook_t) (size_t size, uint32_t caps, const char */ esp_err_t heap_caps_register_failed_alloc_callback(esp_alloc_failed_hook_t callback); +#ifdef CONFIG_HEAP_USE_HOOKS +/** + * @brief callback called after every allocation + * @param ptr the allocated memory + * @param size in bytes of the allocation + * @param caps Bitwise OR of MALLOC_CAP_* flags indicating the type of memory allocated. + * @note this hook is called on the same thread as the allocation, which may be within a low level operation. + * You should refrain from doing heavy work, logging, flash writes, or any locking. + */ +__attribute__((weak)) IRAM_ATTR void esp_heap_trace_alloc_hook(void* ptr, size_t size, uint32_t caps); + +/** + * @brief callback called after every free + * @param ptr the memory that was freed + * @note this hook is called on the same thread as the allocation, which may be within a low level operation. + * You should refrain from doing heavy work, logging, flash writes, or any locking. + */ +__attribute__((weak)) IRAM_ATTR void esp_heap_trace_free_hook(void* ptr); +#endif + /** * @brief Allocate a chunk of memory which has the given capabilities * diff --git a/tools/sdk/esp32s3/include/heap/include/esp_heap_trace.h b/tools/sdk/esp32s3/include/heap/include/esp_heap_trace.h index b1c5d476e4c..2b0daa2e4c6 100644 --- a/tools/sdk/esp32s3/include/heap/include/esp_heap_trace.h +++ b/tools/sdk/esp32s3/include/heap/include/esp_heap_trace.h @@ -36,8 +36,11 @@ typedef struct heap_trace_record_t { size_t size; ///< Size of the allocation void *alloced_by[CONFIG_HEAP_TRACING_STACK_DEPTH]; ///< Call stack of the caller which allocated the memory. void *freed_by[CONFIG_HEAP_TRACING_STACK_DEPTH]; ///< Call stack of the caller which freed the memory (all zero if not freed.) -#ifdef CONFIG_HEAP_TRACING_STANDALONE - TAILQ_ENTRY(heap_trace_record_t) tailq; ///< Linked list: prev & next records +#if CONFIG_HEAP_TRACING_STANDALONE + TAILQ_ENTRY(heap_trace_record_t) tailq_list; ///< Linked list: prev & next records +#if CONFIG_HEAP_TRACE_HASH_MAP + TAILQ_ENTRY(heap_trace_record_t) tailq_hashmap; ///< Linked list: prev & next in hashmap entry list +#endif // CONFIG_HEAP_TRACE_HASH_MAP #endif // CONFIG_HEAP_TRACING_STANDALONE } heap_trace_record_t; @@ -52,6 +55,10 @@ typedef struct { size_t capacity; ///< The capacity of the internal buffer size_t high_water_mark; ///< The maximum value that 'count' got to size_t has_overflowed; ///< True if the internal buffer overflowed at some point +#if CONFIG_HEAP_TRACE_HASH_MAP + size_t total_hashmap_hits; ///< If hashmap is used, the total number of hits + size_t total_hashmap_miss; ///< If hashmap is used, the total number of misses (possibly due to overflow) +#endif } heap_trace_summary_t; /** diff --git a/tools/sdk/esp32s3/include/mbedtls/port/include/ecdsa/ecdsa_alt.h b/tools/sdk/esp32s3/include/mbedtls/port/include/ecdsa/ecdsa_alt.h new file mode 100644 index 00000000000..9e2620b3126 --- /dev/null +++ b/tools/sdk/esp32s3/include/mbedtls/port/include/ecdsa/ecdsa_alt.h @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "sdkconfig.h" +#include "mbedtls/pk.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef CONFIG_MBEDTLS_HARDWARE_ECDSA_SIGN + +/** + * @brief Initialize MPI to notify mbedtls_ecdsa_sign to use the private key in efuse + * We break the MPI struct of the private key in order to + * differentiate between hardware key and software key + * + * @note Currently, `efuse_blk` is not used internally. + * Hardware will choose the efuse block that has purpose set to ECDSA_KEY. + * In case of multiple ECDSA_KEY burnt in efuse, hardware will choose the + * greater efuse block number as the private key. + * + * @param key The MPI in which this functions stores the hardware context. + * This must be uninitialized + * @param efuse_blk The efuse key block that should be used as the private key. + * The key purpose of this block must be ECDSA_KEY + * + * @return - 0 if successful + * - -1 otherwise + * + */ +int esp_ecdsa_privkey_load_mpi(mbedtls_mpi *key, int efuse_blk); + +/** + * @brief Initialize PK context to notify mbedtls_ecdsa_sign to use the private key in efuse + * We break the MPI struct used to represent the private key `d` in ECP keypair + * in order to differentiate between hardware key and software key + * + * @note Currently, `efuse_blk` is not used internally. + * Hardware will choose the efuse block that has purpose set to ECDSA_KEY. + * In case of multiple ECDSA_KEY burnt in efuse, hardware will choose the + * greater efuse block number as the private key. + * + * @param key_ctx The context in which this functions stores the hardware context. + * This must be uninitialized + * @param efuse_blk The efuse key block that should be used as the private key. + * The key purpose of this block must be ECDSA_KEY + * + * @return - 0 if successful + * - -1 otherwise + */ +int esp_ecdsa_privkey_load_pk_context(mbedtls_pk_context *key_ctx, int efuse_blk); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s3/include/mbedtls/port/include/mbedtls/esp_config.h b/tools/sdk/esp32s3/include/mbedtls/port/include/mbedtls/esp_config.h index 71905d8cb3c..ea2efa243ad 100644 --- a/tools/sdk/esp32s3/include/mbedtls/port/include/mbedtls/esp_config.h +++ b/tools/sdk/esp32s3/include/mbedtls/port/include/mbedtls/esp_config.h @@ -224,6 +224,7 @@ #undef MBEDTLS_ECP_VERIFY_ALT #undef MBEDTLS_ECP_VERIFY_ALT_SOFT_FALLBACK #endif + /** * \def MBEDTLS_ENTROPY_HARDWARE_ALT * diff --git a/tools/sdk/esp32s3/include/pthread/include/semaphore.h b/tools/sdk/esp32s3/include/pthread/include/semaphore.h new file mode 100644 index 00000000000..5a7ef56b971 --- /dev/null +++ b/tools/sdk/esp32s3/include/pthread/include/semaphore.h @@ -0,0 +1,73 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef unsigned int sem_t; + +/** + * This is the maximum value to which any POSIX semaphore can count on ESP chips. + */ +#define SEM_VALUE_MAX 0x7FFF + +/** + * This is a POSIX function, please refer to the POSIX specification for a detailed description. + * + * Must NOT be called if threads are still blocked on semaphore! + */ +int sem_destroy(sem_t *sem); + +/** + * This is a POSIX function, please refer to the POSIX specification for a detailed description. + * + * Note that on ESP chips, pshared is ignored. Semaphores can always be shared between FreeRTOS tasks. + */ +int sem_init(sem_t *sem, int pshared, unsigned value); + +/** + * This is a POSIX function, please refer to the POSIX specification for a detailed description. + * + * Note that, unlike specified in POSIX, this implementation returns -1 and sets errno to + * EAGAIN if the semaphore can not be unlocked (posted) due to its value being SEM_VALUE_MAX. + */ +int sem_post(sem_t *sem); + +/** + * This is a POSIX function, please refer to the POSIX specification for a detailed description. + * + * Note the following three deviations/issues originating from the underlying FreeRTOS implementation: + * * The time value passed by abstime will be rounded up to the next FreeRTOS tick. + * * The actual timeout will happen after the tick the time was rounded to + * and before the following tick. + * * It is possible, though unlikely, that the task is preempted directly after the timeout calculation, + * delaying timeout of the following blocking operating system call by the duration of the preemption. + */ +int sem_timedwait(sem_t * restrict semaphore, const struct timespec *restrict abstime); + +/** + * This is a POSIX function, please refer to the POSIX specification for a detailed description. + */ +int sem_trywait(sem_t *sem); + +/** + * This is a POSIX function, please refer to the POSIX specification for a detailed description. + */ +int sem_wait(sem_t *sem); + +/** + * This is a POSIX function, please refer to the POSIX specification for a detailed description. + */ +int sem_getvalue(sem_t *restrict sem, int *restrict sval); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s3/include/soc/esp32s3/include/soc/efuse_defs.h b/tools/sdk/esp32s3/include/soc/esp32s3/include/soc/efuse_defs.h new file mode 100644 index 00000000000..6c61b202b9e --- /dev/null +++ b/tools/sdk/esp32s3/include/soc/esp32s3/include/soc/efuse_defs.h @@ -0,0 +1,39 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define EFUSE_WRITE_OP_CODE 0x5a5a +#define EFUSE_READ_OP_CODE 0x5aa5 + +/** EFUSE_RD_MAC_SPI_SYS_2_REG register + * BLOCK1 data register 2. + */ +// #define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c) +/* EFUSE_SPI_PAD_CONF_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the first part of SPI_PAD_CONF..*/ +#define EFUSE_SPI_PAD_CONF_1 0xFFFFFFFF +#define EFUSE_SPI_PAD_CONF_1_M ((EFUSE_SPI_PAD_CONF_1_V)<<(EFUSE_SPI_PAD_CONF_1_S)) +#define EFUSE_SPI_PAD_CONF_1_V 0xFFFFFFFF +#define EFUSE_SPI_PAD_CONF_1_S 0 + +/** EFUSE_RD_MAC_SPI_SYS_3_REG register + * BLOCK1 data register 3. + */ +//#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) +/* EFUSE_SPI_PAD_CONF_2 : RO ;bitpos:[17:0] ;default: 18'h0 ; */ +/*description: Stores the second part of SPI_PAD_CONF..*/ +#define EFUSE_SPI_PAD_CONF_2 0x0003FFFF +#define EFUSE_SPI_PAD_CONF_2_M ((EFUSE_SPI_PAD_CONF_2_V)<<(EFUSE_SPI_PAD_CONF_2_S)) +#define EFUSE_SPI_PAD_CONF_2_V 0x3FFFF +#define EFUSE_SPI_PAD_CONF_2_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s3/include/soc/esp32s3/include/soc/efuse_reg.h b/tools/sdk/esp32s3/include/soc/esp32s3/include/soc/efuse_reg.h index 94e6851ae01..6b4119620b0 100644 --- a/tools/sdk/esp32s3/include/soc/esp32s3/include/soc/efuse_reg.h +++ b/tools/sdk/esp32s3/include/soc/esp32s3/include/soc/efuse_reg.h @@ -1,1943 +1,2864 @@ -/* - * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_EFUSE_REG_H_ -#define _SOC_EFUSE_REG_H_ +#pragma once - -#include "soc.h" +#include +#include "soc/soc.h" +#include "efuse_defs.h" #ifdef __cplusplus extern "C" { #endif -#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) -/* EFUSE_PGM_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 0th 32-bit data to be programmed..*/ -#define EFUSE_PGM_DATA_0 0xFFFFFFFF -#define EFUSE_PGM_DATA_0_M ((EFUSE_PGM_DATA_0_V)<<(EFUSE_PGM_DATA_0_S)) -#define EFUSE_PGM_DATA_0_V 0xFFFFFFFF +/** EFUSE_PGM_DATA0_REG register + * Register 0 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) +/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) +#define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_0_S 0 -#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) -/* EFUSE_PGM_DATA_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 1st 32-bit data to be programmed..*/ -#define EFUSE_PGM_DATA_1 0xFFFFFFFF -#define EFUSE_PGM_DATA_1_M ((EFUSE_PGM_DATA_1_V)<<(EFUSE_PGM_DATA_1_S)) -#define EFUSE_PGM_DATA_1_V 0xFFFFFFFF +/** EFUSE_PGM_DATA1_REG register + * Register 1 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) +/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1st 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_1 0xFFFFFFFFU +#define EFUSE_PGM_DATA_1_M (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S) +#define EFUSE_PGM_DATA_1_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_1_S 0 -#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) -/* EFUSE_PGM_DATA_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 2nd 32-bit data to be programmed..*/ -#define EFUSE_PGM_DATA_2 0xFFFFFFFF -#define EFUSE_PGM_DATA_2_M ((EFUSE_PGM_DATA_2_V)<<(EFUSE_PGM_DATA_2_S)) -#define EFUSE_PGM_DATA_2_V 0xFFFFFFFF +/** EFUSE_PGM_DATA2_REG register + * Register 2 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) +/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2nd 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_2 0xFFFFFFFFU +#define EFUSE_PGM_DATA_2_M (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S) +#define EFUSE_PGM_DATA_2_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_2_S 0 -#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xC) -/* EFUSE_PGM_DATA_3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 3rd 32-bit data to be programmed..*/ -#define EFUSE_PGM_DATA_3 0xFFFFFFFF -#define EFUSE_PGM_DATA_3_M ((EFUSE_PGM_DATA_3_V)<<(EFUSE_PGM_DATA_3_S)) -#define EFUSE_PGM_DATA_3_V 0xFFFFFFFF +/** EFUSE_PGM_DATA3_REG register + * Register 3 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc) +/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0; + * The content of the 3rd 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_3 0xFFFFFFFFU +#define EFUSE_PGM_DATA_3_M (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S) +#define EFUSE_PGM_DATA_3_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_3_S 0 -#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) -/* EFUSE_PGM_DATA_4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 4th 32-bit data to be programmed..*/ -#define EFUSE_PGM_DATA_4 0xFFFFFFFF -#define EFUSE_PGM_DATA_4_M ((EFUSE_PGM_DATA_4_V)<<(EFUSE_PGM_DATA_4_S)) -#define EFUSE_PGM_DATA_4_V 0xFFFFFFFF +/** EFUSE_PGM_DATA4_REG register + * Register 4 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) +/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0; + * The content of the 4th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_4 0xFFFFFFFFU +#define EFUSE_PGM_DATA_4_M (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S) +#define EFUSE_PGM_DATA_4_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_4_S 0 -#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) -/* EFUSE_PGM_DATA_5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 5th 32-bit data to be programmed..*/ -#define EFUSE_PGM_DATA_5 0xFFFFFFFF -#define EFUSE_PGM_DATA_5_M ((EFUSE_PGM_DATA_5_V)<<(EFUSE_PGM_DATA_5_S)) -#define EFUSE_PGM_DATA_5_V 0xFFFFFFFF +/** EFUSE_PGM_DATA5_REG register + * Register 5 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) +/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0; + * The content of the 5th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_5 0xFFFFFFFFU +#define EFUSE_PGM_DATA_5_M (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S) +#define EFUSE_PGM_DATA_5_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_5_S 0 -#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) -/* EFUSE_PGM_DATA_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 6th 32-bit data to be programmed..*/ -#define EFUSE_PGM_DATA_6 0xFFFFFFFF -#define EFUSE_PGM_DATA_6_M ((EFUSE_PGM_DATA_6_V)<<(EFUSE_PGM_DATA_6_S)) -#define EFUSE_PGM_DATA_6_V 0xFFFFFFFF +/** EFUSE_PGM_DATA6_REG register + * Register 6 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) +/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0; + * The content of the 6th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_6 0xFFFFFFFFU +#define EFUSE_PGM_DATA_6_M (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S) +#define EFUSE_PGM_DATA_6_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_6_S 0 -#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1C) -/* EFUSE_PGM_DATA_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 7th 32-bit data to be programmed..*/ -#define EFUSE_PGM_DATA_7 0xFFFFFFFF -#define EFUSE_PGM_DATA_7_M ((EFUSE_PGM_DATA_7_V)<<(EFUSE_PGM_DATA_7_S)) -#define EFUSE_PGM_DATA_7_V 0xFFFFFFFF +/** EFUSE_PGM_DATA7_REG register + * Register 7 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c) +/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0; + * The content of the 7th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_7 0xFFFFFFFFU +#define EFUSE_PGM_DATA_7_M (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S) +#define EFUSE_PGM_DATA_7_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_7_S 0 -#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) -/* EFUSE_PGM_RS_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 0th 32-bit RS code to be programmed..*/ -#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_0_M ((EFUSE_PGM_RS_DATA_0_V)<<(EFUSE_PGM_RS_DATA_0_S)) -#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFF +/** EFUSE_PGM_CHECK_VALUE0_REG register + * Register 0 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) +/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) +#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_0_S 0 -#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) -/* EFUSE_PGM_RS_DATA_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 1st 32-bit RS code to be programmed..*/ -#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_1_M ((EFUSE_PGM_RS_DATA_1_V)<<(EFUSE_PGM_RS_DATA_1_S)) -#define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFF +/** EFUSE_PGM_CHECK_VALUE1_REG register + * Register 1 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) +/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1st 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_1_M (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S) +#define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_1_S 0 -#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) -/* EFUSE_PGM_RS_DATA_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 2nd 32-bit RS code to be programmed..*/ -#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_2_M ((EFUSE_PGM_RS_DATA_2_V)<<(EFUSE_PGM_RS_DATA_2_S)) -#define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFF +/** EFUSE_PGM_CHECK_VALUE2_REG register + * Register 2 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) +/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2nd 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_2_M (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S) +#define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_2_S 0 -#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2C) -/* EFUSE_WR_DIS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Disable programming of individual eFuses..*/ -#define EFUSE_WR_DIS 0xFFFFFFFF -#define EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S)) -#define EFUSE_WR_DIS_V 0xFFFFFFFF +/** EFUSE_RD_WR_DIS_REG register + * BLOCK0 data register 0. + */ +#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c) +/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; + * Disable programming of individual eFuses. + */ +#define EFUSE_WR_DIS 0xFFFFFFFFU +#define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) +#define EFUSE_WR_DIS_V 0xFFFFFFFFU #define EFUSE_WR_DIS_S 0 -#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) -/* EFUSE_VDD_SPI_DREFH : RO ;bitpos:[31:30] ;default: 2'h0 ; */ -/*description: SPI regulator high voltage reference..*/ -#define EFUSE_VDD_SPI_DREFH 0x00000003 -#define EFUSE_VDD_SPI_DREFH_M ((EFUSE_VDD_SPI_DREFH_V)<<(EFUSE_VDD_SPI_DREFH_S)) -#define EFUSE_VDD_SPI_DREFH_V 0x3 -#define EFUSE_VDD_SPI_DREFH_S 30 -/* EFUSE_VDD_SPI_MODECURLIM : RO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: SPI regulator switches current limit mode..*/ -#define EFUSE_VDD_SPI_MODECURLIM (BIT(29)) -#define EFUSE_VDD_SPI_MODECURLIM_M (BIT(29)) -#define EFUSE_VDD_SPI_MODECURLIM_V 0x1 -#define EFUSE_VDD_SPI_MODECURLIM_S 29 -/* EFUSE_BTLC_GPIO_ENABLE : RO ;bitpos:[28:27] ;default: 2'h0 ; */ -/*description: Enable btlc gpio..*/ -#define EFUSE_BTLC_GPIO_ENABLE 0x00000003 -#define EFUSE_BTLC_GPIO_ENABLE_M ((EFUSE_BTLC_GPIO_ENABLE_V)<<(EFUSE_BTLC_GPIO_ENABLE_S)) -#define EFUSE_BTLC_GPIO_ENABLE_V 0x3 -#define EFUSE_BTLC_GPIO_ENABLE_S 27 -/* EFUSE_EXT_PHY_ENABLE : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: Set this bit to enable external PHY..*/ -#define EFUSE_EXT_PHY_ENABLE (BIT(26)) -#define EFUSE_EXT_PHY_ENABLE_M (BIT(26)) -#define EFUSE_EXT_PHY_ENABLE_V 0x1 -#define EFUSE_EXT_PHY_ENABLE_S 26 -/* EFUSE_USB_EXCHG_PINS : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: Set this bit to exchange USB D+ and D- pins..*/ -#define EFUSE_USB_EXCHG_PINS (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_M (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_V 0x1 -#define EFUSE_USB_EXCHG_PINS_S 25 -/* EFUSE_USB_DREFL : RO ;bitpos:[24:23] ;default: 2'h0 ; */ -/*description: Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, s -tored in eFuse..*/ -#define EFUSE_USB_DREFL 0x00000003 -#define EFUSE_USB_DREFL_M ((EFUSE_USB_DREFL_V)<<(EFUSE_USB_DREFL_S)) -#define EFUSE_USB_DREFL_V 0x3 -#define EFUSE_USB_DREFL_S 23 -/* EFUSE_USB_DREFH : RO ;bitpos:[22:21] ;default: 2'h0 ; */ -/*description: Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, sto -red in eFuse..*/ -#define EFUSE_USB_DREFH 0x00000003 -#define EFUSE_USB_DREFH_M ((EFUSE_USB_DREFH_V)<<(EFUSE_USB_DREFH_S)) -#define EFUSE_USB_DREFH_V 0x3 -#define EFUSE_USB_DREFH_S 21 -/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Set this bit to disable flash encryption when in download boot modes..*/ -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 -/* EFUSE_DIS_PAD_JTAG : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: Set this bit to disable JTAG in the hard way. JTAG is disabled permanently..*/ -#define EFUSE_DIS_PAD_JTAG (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_M (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_V 0x1 -#define EFUSE_DIS_PAD_JTAG_S 19 -/* EFUSE_SOFT_DIS_JTAG : RO ;bitpos:[18:16] ;default: 3'h0 ; */ -/*description: Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JT -AG can be enabled in HMAC module..*/ -#define EFUSE_SOFT_DIS_JTAG 0x00000007 -#define EFUSE_SOFT_DIS_JTAG_M ((EFUSE_SOFT_DIS_JTAG_V)<<(EFUSE_SOFT_DIS_JTAG_S)) -#define EFUSE_SOFT_DIS_JTAG_V 0x7 -#define EFUSE_SOFT_DIS_JTAG_S 16 -/* EFUSE_DIS_APP_CPU : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Disable app cpu..*/ -#define EFUSE_DIS_APP_CPU (BIT(15)) -#define EFUSE_DIS_APP_CPU_M (BIT(15)) -#define EFUSE_DIS_APP_CPU_V 0x1 -#define EFUSE_DIS_APP_CPU_S 15 -/* EFUSE_DIS_CAN : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Set this bit to disable CAN function..*/ -#define EFUSE_DIS_CAN (BIT(14)) -#define EFUSE_DIS_CAN_M (BIT(14)) -#define EFUSE_DIS_CAN_V 0x1 -#define EFUSE_DIS_CAN_S 14 -/* EFUSE_DIS_USB : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to disable USB function..*/ -#define EFUSE_DIS_USB (BIT(13)) -#define EFUSE_DIS_USB_M (BIT(13)) -#define EFUSE_DIS_USB_V 0x1 -#define EFUSE_DIS_USB_S 13 -/* EFUSE_DIS_FORCE_DOWNLOAD : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to disable the function that forces chip into download mode..*/ -#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_M (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x1 -#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 -/* EFUSE_DIS_DOWNLOAD_DCACHE : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0, 1, 2, 3, -6, 7)..*/ -#define EFUSE_DIS_DOWNLOAD_DCACHE (BIT(11)) -#define EFUSE_DIS_DOWNLOAD_DCACHE_M (BIT(11)) -#define EFUSE_DIS_DOWNLOAD_DCACHE_V 0x1 -#define EFUSE_DIS_DOWNLOAD_DCACHE_S 11 -/* EFUSE_DIS_DOWNLOAD_ICACHE : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6 -, 7)..*/ -#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_M (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x1 -#define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 -/* EFUSE_DIS_DCACHE : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to disable Dcache..*/ -#define EFUSE_DIS_DCACHE (BIT(9)) -#define EFUSE_DIS_DCACHE_M (BIT(9)) -#define EFUSE_DIS_DCACHE_V 0x1 -#define EFUSE_DIS_DCACHE_S 9 -/* EFUSE_DIS_ICACHE : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to disable Icache..*/ +/** EFUSE_RD_REPEAT_DATA0_REG register + * BLOCK0 data register 1. + */ +#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) +/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; + * Set this bit to disable reading from BlOCK4-10. + */ +#define EFUSE_RD_DIS 0x0000007FU +#define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) +#define EFUSE_RD_DIS_V 0x0000007FU +#define EFUSE_RD_DIS_S 0 +/** EFUSE_DIS_RTC_RAM_BOOT : RO; bitpos: [7]; default: 0; + * Set this bit to disable boot from RTC RAM. + */ +#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) +#define EFUSE_DIS_RTC_RAM_BOOT_M (EFUSE_DIS_RTC_RAM_BOOT_V << EFUSE_DIS_RTC_RAM_BOOT_S) +#define EFUSE_DIS_RTC_RAM_BOOT_V 0x00000001U +#define EFUSE_DIS_RTC_RAM_BOOT_S 7 +/** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0; + * Set this bit to disable Icache. + */ #define EFUSE_DIS_ICACHE (BIT(8)) -#define EFUSE_DIS_ICACHE_M (BIT(8)) -#define EFUSE_DIS_ICACHE_V 0x1 +#define EFUSE_DIS_ICACHE_M (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S) +#define EFUSE_DIS_ICACHE_V 0x00000001U #define EFUSE_DIS_ICACHE_S 8 -/* EFUSE_RPT4_RESERVED5 : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Reserved */ -#define EFUSE_RPT4_RESERVED5 (BIT(7)) -#define EFUSE_RPT4_RESERVED5_M (BIT(7)) -#define EFUSE_RPT4_RESERVED5_V 0x1 -#define EFUSE_RPT4_RESERVED5_S 7 -/* EFUSE_RD_DIS : RO ;bitpos:[6:0] ;default: 7'h0 ; */ -/*description: Set this bit to disable reading from BlOCK4-10..*/ -#define EFUSE_RD_DIS 0x0000007F -#define EFUSE_RD_DIS_M ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S)) -#define EFUSE_RD_DIS_V 0x7F -#define EFUSE_RD_DIS_S 0 +/** EFUSE_DIS_DCACHE : RO; bitpos: [9]; default: 0; + * Set this bit to disable Dcache. + */ +#define EFUSE_DIS_DCACHE (BIT(9)) +#define EFUSE_DIS_DCACHE_M (EFUSE_DIS_DCACHE_V << EFUSE_DIS_DCACHE_S) +#define EFUSE_DIS_DCACHE_V 0x00000001U +#define EFUSE_DIS_DCACHE_S 9 +/** EFUSE_DIS_DOWNLOAD_ICACHE : RO; bitpos: [10]; default: 0; + * Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, + * 7). + */ +#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) +#define EFUSE_DIS_DOWNLOAD_ICACHE_M (EFUSE_DIS_DOWNLOAD_ICACHE_V << EFUSE_DIS_DOWNLOAD_ICACHE_S) +#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 +/** EFUSE_DIS_DOWNLOAD_DCACHE : RO; bitpos: [11]; default: 0; + * Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0, 1, 2, 3, 6, + * 7). + */ +#define EFUSE_DIS_DOWNLOAD_DCACHE (BIT(11)) +#define EFUSE_DIS_DOWNLOAD_DCACHE_M (EFUSE_DIS_DOWNLOAD_DCACHE_V << EFUSE_DIS_DOWNLOAD_DCACHE_S) +#define EFUSE_DIS_DOWNLOAD_DCACHE_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_DCACHE_S 11 +/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0; + * Set this bit to disable the function that forces chip into download mode. + */ +#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x00000001U +#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 +/** EFUSE_DIS_USB_OTG : RO; bitpos: [13]; default: 0; + * Set this bit to disable USB function. + */ +#define EFUSE_DIS_USB_OTG (BIT(13)) +#define EFUSE_DIS_USB_OTG_M (EFUSE_DIS_USB_OTG_V << EFUSE_DIS_USB_OTG_S) +#define EFUSE_DIS_USB_OTG_V 0x00000001U +#define EFUSE_DIS_USB_OTG_S 13 +/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0; + * Set this bit to disable CAN function. + */ +#define EFUSE_DIS_TWAI (BIT(14)) +#define EFUSE_DIS_TWAI_M (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S) +#define EFUSE_DIS_TWAI_V 0x00000001U +#define EFUSE_DIS_TWAI_S 14 +/** EFUSE_DIS_APP_CPU : RO; bitpos: [15]; default: 0; + * Disable app cpu. + */ +#define EFUSE_DIS_APP_CPU (BIT(15)) +#define EFUSE_DIS_APP_CPU_M (EFUSE_DIS_APP_CPU_V << EFUSE_DIS_APP_CPU_S) +#define EFUSE_DIS_APP_CPU_V 0x00000001U +#define EFUSE_DIS_APP_CPU_S 15 +/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0; + * Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG + * can be enabled in HMAC module. + */ +#define EFUSE_SOFT_DIS_JTAG 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_M (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S) +#define EFUSE_SOFT_DIS_JTAG_V 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_S 16 +/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0; + * Set this bit to disable JTAG in the hard way. JTAG is disabled permanently. + */ +#define EFUSE_DIS_PAD_JTAG (BIT(19)) +#define EFUSE_DIS_PAD_JTAG_M (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S) +#define EFUSE_DIS_PAD_JTAG_V 0x00000001U +#define EFUSE_DIS_PAD_JTAG_S 19 +/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0; + * Set this bit to disable flash encryption when in download boot modes. + */ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 +/** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0; + * Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored + * in eFuse. + */ +#define EFUSE_USB_DREFH 0x00000003U +#define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S) +#define EFUSE_USB_DREFH_V 0x00000003U +#define EFUSE_USB_DREFH_S 21 +/** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0; + * Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, + * stored in eFuse. + */ +#define EFUSE_USB_DREFL 0x00000003U +#define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S) +#define EFUSE_USB_DREFL_V 0x00000003U +#define EFUSE_USB_DREFL_S 23 +/** EFUSE_USB_EXCHG_PINS : RO; bitpos: [25]; default: 0; + * Set this bit to exchange USB D+ and D- pins. + */ +#define EFUSE_USB_EXCHG_PINS (BIT(25)) +#define EFUSE_USB_EXCHG_PINS_M (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S) +#define EFUSE_USB_EXCHG_PINS_V 0x00000001U +#define EFUSE_USB_EXCHG_PINS_S 25 +/** EFUSE_USB_EXT_PHY_ENABLE : RO; bitpos: [26]; default: 0; + * Set this bit to enable external PHY. + */ +#define EFUSE_USB_EXT_PHY_ENABLE (BIT(26)) +#define EFUSE_USB_EXT_PHY_ENABLE_M (EFUSE_USB_EXT_PHY_ENABLE_V << EFUSE_USB_EXT_PHY_ENABLE_S) +#define EFUSE_USB_EXT_PHY_ENABLE_V 0x00000001U +#define EFUSE_USB_EXT_PHY_ENABLE_S 26 +/** EFUSE_BTLC_GPIO_ENABLE : RO; bitpos: [28:27]; default: 0; + * Bluetooth GPIO signal output security level control. + */ +#define EFUSE_BTLC_GPIO_ENABLE 0x00000003U +#define EFUSE_BTLC_GPIO_ENABLE_M (EFUSE_BTLC_GPIO_ENABLE_V << EFUSE_BTLC_GPIO_ENABLE_S) +#define EFUSE_BTLC_GPIO_ENABLE_V 0x00000003U +#define EFUSE_BTLC_GPIO_ENABLE_S 27 +/** EFUSE_VDD_SPI_MODECURLIM : RO; bitpos: [29]; default: 0; + * SPI regulator switches current limit mode. + */ +#define EFUSE_VDD_SPI_MODECURLIM (BIT(29)) +#define EFUSE_VDD_SPI_MODECURLIM_M (EFUSE_VDD_SPI_MODECURLIM_V << EFUSE_VDD_SPI_MODECURLIM_S) +#define EFUSE_VDD_SPI_MODECURLIM_V 0x00000001U +#define EFUSE_VDD_SPI_MODECURLIM_S 29 +/** EFUSE_VDD_SPI_DREFH : RO; bitpos: [31:30]; default: 0; + * SPI regulator high voltage reference. + */ +#define EFUSE_VDD_SPI_DREFH 0x00000003U +#define EFUSE_VDD_SPI_DREFH_M (EFUSE_VDD_SPI_DREFH_V << EFUSE_VDD_SPI_DREFH_S) +#define EFUSE_VDD_SPI_DREFH_V 0x00000003U +#define EFUSE_VDD_SPI_DREFH_S 30 -#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) -/* EFUSE_KEY_PURPOSE_1 : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: Purpose of Key1..*/ -#define EFUSE_KEY_PURPOSE_1 0x0000000F -#define EFUSE_KEY_PURPOSE_1_M ((EFUSE_KEY_PURPOSE_1_V)<<(EFUSE_KEY_PURPOSE_1_S)) -#define EFUSE_KEY_PURPOSE_1_V 0xF -#define EFUSE_KEY_PURPOSE_1_S 28 -/* EFUSE_KEY_PURPOSE_0 : RO ;bitpos:[27:24] ;default: 4'h0 ; */ -/*description: Purpose of Key0..*/ -#define EFUSE_KEY_PURPOSE_0 0x0000000F -#define EFUSE_KEY_PURPOSE_0_M ((EFUSE_KEY_PURPOSE_0_V)<<(EFUSE_KEY_PURPOSE_0_S)) -#define EFUSE_KEY_PURPOSE_0_V 0xF -#define EFUSE_KEY_PURPOSE_0_S 24 -/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Set this bit to enable revoking third secure boot key..*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 -/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Set this bit to enable revoking second secure boot key..*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 -/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to enable revoking first secure boot key..*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 -/* EFUSE_SPI_BOOT_CRYPT_CNT : RO ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even n -umber of 1: disable..*/ -#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_M ((EFUSE_SPI_BOOT_CRYPT_CNT_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_S)) -#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x7 -#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 -/* EFUSE_WDT_DELAY_SEL : RO ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1 -: 80000. 2: 160000. 3:320000..*/ -#define EFUSE_WDT_DELAY_SEL 0x00000003 -#define EFUSE_WDT_DELAY_SEL_M ((EFUSE_WDT_DELAY_SEL_V)<<(EFUSE_WDT_DELAY_SEL_S)) -#define EFUSE_WDT_DELAY_SEL_V 0x3 -#define EFUSE_WDT_DELAY_SEL_S 16 -/* EFUSE_VDD_SPI_DCAP : RO ;bitpos:[15:14] ;default: 2'h0 ; */ -/*description: Prevents SPI regulator from overshoot..*/ -#define EFUSE_VDD_SPI_DCAP 0x00000003 -#define EFUSE_VDD_SPI_DCAP_M ((EFUSE_VDD_SPI_DCAP_V)<<(EFUSE_VDD_SPI_DCAP_S)) -#define EFUSE_VDD_SPI_DCAP_V 0x3 -#define EFUSE_VDD_SPI_DCAP_S 14 -/* EFUSE_VDD_SPI_INIT : RO ;bitpos:[13:12] ;default: 2'h0 ; */ -/*description: Adds resistor from LDO output to ground. 0: no resistance 1: 6 K 2: 4 K 3: 2 K..*/ -#define EFUSE_VDD_SPI_INIT 0x00000003 -#define EFUSE_VDD_SPI_INIT_M ((EFUSE_VDD_SPI_INIT_V)<<(EFUSE_VDD_SPI_INIT_S)) -#define EFUSE_VDD_SPI_INIT_V 0x3 -#define EFUSE_VDD_SPI_INIT_S 12 -/* EFUSE_VDD_SPI_DCURLIM : RO ;bitpos:[11:9]] ;default: 3'h0 ; */ -/*description: Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+ -d)..*/ -#define EFUSE_VDD_SPI_DCURLIM 0x00000007 -#define EFUSE_VDD_SPI_DCURLIM_M ((EFUSE_VDD_SPI_DCURLIM_V)<<(EFUSE_VDD_SPI_DCURLIM_S)) -#define EFUSE_VDD_SPI_DCURLIM_V 0x7 -#define EFUSE_VDD_SPI_DCURLIM_S 9 -/* EFUSE_VDD_SPI_ENCURLIM : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set SPI regulator to 1 to enable output current limit..*/ -#define EFUSE_VDD_SPI_ENCURLIM (BIT(8)) -#define EFUSE_VDD_SPI_ENCURLIM_M (BIT(8)) -#define EFUSE_VDD_SPI_ENCURLIM_V 0x1 -#define EFUSE_VDD_SPI_ENCURLIM_S 8 -/* EFUSE_VDD_SPI_EN_INIT : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set SPI regulator to 0 to configure init[1:0]=0..*/ -#define EFUSE_VDD_SPI_EN_INIT (BIT(7)) -#define EFUSE_VDD_SPI_EN_INIT_M (BIT(7)) -#define EFUSE_VDD_SPI_EN_INIT_V 0x1 -#define EFUSE_VDD_SPI_EN_INIT_S 7 -/* EFUSE_VDD_SPI_FORCE : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit and force to use the configuration of eFuse to configure VDD_SPI..*/ -#define EFUSE_VDD_SPI_FORCE (BIT(6)) -#define EFUSE_VDD_SPI_FORCE_M (BIT(6)) -#define EFUSE_VDD_SPI_FORCE_V 0x1 -#define EFUSE_VDD_SPI_FORCE_S 6 -/* EFUSE_VDD_SPI_TIEH : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: SPI regulator output is short connected to VDD3P3_RTC_IO..*/ -#define EFUSE_VDD_SPI_TIEH (BIT(5)) -#define EFUSE_VDD_SPI_TIEH_M (BIT(5)) -#define EFUSE_VDD_SPI_TIEH_V 0x1 -#define EFUSE_VDD_SPI_TIEH_S 5 -/* EFUSE_VDD_SPI_XPD : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: SPI regulator power up signal..*/ +/** EFUSE_RD_REPEAT_DATA1_REG register + * BLOCK0 data register 2. + */ +#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) +/** EFUSE_VDD_SPI_DREFM : RO; bitpos: [1:0]; default: 0; + * SPI regulator medium voltage reference. + */ +#define EFUSE_VDD_SPI_DREFM 0x00000003U +#define EFUSE_VDD_SPI_DREFM_M (EFUSE_VDD_SPI_DREFM_V << EFUSE_VDD_SPI_DREFM_S) +#define EFUSE_VDD_SPI_DREFM_V 0x00000003U +#define EFUSE_VDD_SPI_DREFM_S 0 +/** EFUSE_VDD_SPI_DREFL : RO; bitpos: [3:2]; default: 0; + * SPI regulator low voltage reference. + */ +#define EFUSE_VDD_SPI_DREFL 0x00000003U +#define EFUSE_VDD_SPI_DREFL_M (EFUSE_VDD_SPI_DREFL_V << EFUSE_VDD_SPI_DREFL_S) +#define EFUSE_VDD_SPI_DREFL_V 0x00000003U +#define EFUSE_VDD_SPI_DREFL_S 2 +/** EFUSE_VDD_SPI_XPD : RO; bitpos: [4]; default: 0; + * SPI regulator power up signal. + */ #define EFUSE_VDD_SPI_XPD (BIT(4)) -#define EFUSE_VDD_SPI_XPD_M (BIT(4)) -#define EFUSE_VDD_SPI_XPD_V 0x1 +#define EFUSE_VDD_SPI_XPD_M (EFUSE_VDD_SPI_XPD_V << EFUSE_VDD_SPI_XPD_S) +#define EFUSE_VDD_SPI_XPD_V 0x00000001U #define EFUSE_VDD_SPI_XPD_S 4 -/* EFUSE_VDD_SPI_DREFL : RO ;bitpos:[3:2] ;default: 2'h0 ; */ -/*description: SPI regulator low voltage reference..*/ -#define EFUSE_VDD_SPI_DREFL 0x00000003 -#define EFUSE_VDD_SPI_DREFL_M ((EFUSE_VDD_SPI_DREFL_V)<<(EFUSE_VDD_SPI_DREFL_S)) -#define EFUSE_VDD_SPI_DREFL_V 0x3 -#define EFUSE_VDD_SPI_DREFL_S 2 -/* EFUSE_VDD_SPI_DREFM : RO ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: SPI regulator medium voltage reference..*/ -#define EFUSE_VDD_SPI_DREFM 0x00000003 -#define EFUSE_VDD_SPI_DREFM_M ((EFUSE_VDD_SPI_DREFM_V)<<(EFUSE_VDD_SPI_DREFM_S)) -#define EFUSE_VDD_SPI_DREFM_V 0x3 -#define EFUSE_VDD_SPI_DREFM_S 0 +/** EFUSE_VDD_SPI_TIEH : RO; bitpos: [5]; default: 0; + * SPI regulator output is short connected to VDD3P3_RTC_IO. + */ +#define EFUSE_VDD_SPI_TIEH (BIT(5)) +#define EFUSE_VDD_SPI_TIEH_M (EFUSE_VDD_SPI_TIEH_V << EFUSE_VDD_SPI_TIEH_S) +#define EFUSE_VDD_SPI_TIEH_V 0x00000001U +#define EFUSE_VDD_SPI_TIEH_S 5 +/** EFUSE_VDD_SPI_FORCE : RO; bitpos: [6]; default: 0; + * Set this bit and force to use the configuration of eFuse to configure VDD_SPI. + */ +#define EFUSE_VDD_SPI_FORCE (BIT(6)) +#define EFUSE_VDD_SPI_FORCE_M (EFUSE_VDD_SPI_FORCE_V << EFUSE_VDD_SPI_FORCE_S) +#define EFUSE_VDD_SPI_FORCE_V 0x00000001U +#define EFUSE_VDD_SPI_FORCE_S 6 +/** EFUSE_VDD_SPI_EN_INIT : RO; bitpos: [7]; default: 0; + * Set SPI regulator to 0 to configure init[1:0]=0. + */ +#define EFUSE_VDD_SPI_EN_INIT (BIT(7)) +#define EFUSE_VDD_SPI_EN_INIT_M (EFUSE_VDD_SPI_EN_INIT_V << EFUSE_VDD_SPI_EN_INIT_S) +#define EFUSE_VDD_SPI_EN_INIT_V 0x00000001U +#define EFUSE_VDD_SPI_EN_INIT_S 7 +/** EFUSE_VDD_SPI_ENCURLIM : RO; bitpos: [8]; default: 0; + * Set SPI regulator to 1 to enable output current limit. + */ +#define EFUSE_VDD_SPI_ENCURLIM (BIT(8)) +#define EFUSE_VDD_SPI_ENCURLIM_M (EFUSE_VDD_SPI_ENCURLIM_V << EFUSE_VDD_SPI_ENCURLIM_S) +#define EFUSE_VDD_SPI_ENCURLIM_V 0x00000001U +#define EFUSE_VDD_SPI_ENCURLIM_S 8 +/** EFUSE_VDD_SPI_DCURLIM : RO; bitpos: [11:9]; default: 0; + * Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d). + */ +#define EFUSE_VDD_SPI_DCURLIM 0x00000007U +#define EFUSE_VDD_SPI_DCURLIM_M (EFUSE_VDD_SPI_DCURLIM_V << EFUSE_VDD_SPI_DCURLIM_S) +#define EFUSE_VDD_SPI_DCURLIM_V 0x00000007U +#define EFUSE_VDD_SPI_DCURLIM_S 9 +/** EFUSE_VDD_SPI_INIT : RO; bitpos: [13:12]; default: 0; + * Adds resistor from LDO output to ground. 0: no resistance 1: 6 K 2: 4 K 3: 2 K. + */ +#define EFUSE_VDD_SPI_INIT 0x00000003U +#define EFUSE_VDD_SPI_INIT_M (EFUSE_VDD_SPI_INIT_V << EFUSE_VDD_SPI_INIT_S) +#define EFUSE_VDD_SPI_INIT_V 0x00000003U +#define EFUSE_VDD_SPI_INIT_S 12 +/** EFUSE_VDD_SPI_DCAP : RO; bitpos: [15:14]; default: 0; + * Prevents SPI regulator from overshoot. + */ +#define EFUSE_VDD_SPI_DCAP 0x00000003U +#define EFUSE_VDD_SPI_DCAP_M (EFUSE_VDD_SPI_DCAP_V << EFUSE_VDD_SPI_DCAP_S) +#define EFUSE_VDD_SPI_DCAP_V 0x00000003U +#define EFUSE_VDD_SPI_DCAP_S 14 +/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0; + * Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: + * 80000. 2: 160000. 3:320000. + */ +#define EFUSE_WDT_DELAY_SEL 0x00000003U +#define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) +#define EFUSE_WDT_DELAY_SEL_V 0x00000003U +#define EFUSE_WDT_DELAY_SEL_S 16 +/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0; + * Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even + * number of 1: disable. + */ +#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 +/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0; + * Set this bit to enable revoking first secure boot key. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 +/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0; + * Set this bit to enable revoking second secure boot key. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 +/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0; + * Set this bit to enable revoking third secure boot key. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 +/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0; + * Purpose of Key0. + */ +#define EFUSE_KEY_PURPOSE_0 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_M (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S) +#define EFUSE_KEY_PURPOSE_0_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_S 24 +/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0; + * Purpose of Key1. + */ +#define EFUSE_KEY_PURPOSE_1 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_M (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S) +#define EFUSE_KEY_PURPOSE_1_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_S 28 -#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) -/* EFUSE_FLASH_TPUW : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: Configures flash waiting time after power-up, in unit of ms. If the value is les -s than 15, the waiting time is the configurable value; Otherwise, the waiting ti -me is twice the configurable value..*/ -#define EFUSE_FLASH_TPUW 0x0000000F -#define EFUSE_FLASH_TPUW_M ((EFUSE_FLASH_TPUW_V)<<(EFUSE_FLASH_TPUW_S)) -#define EFUSE_FLASH_TPUW_V 0xF -#define EFUSE_FLASH_TPUW_S 28 -/* EFUSE_POWER_GLITCH_DSENSE : RO ;bitpos:[27:26] ;default: 2'h0 ; */ -/*description: Sample delay configuration of power glitch..*/ -#define EFUSE_POWER_GLITCH_DSENSE 0x00000003 -#define EFUSE_POWER_GLITCH_DSENSE_M ((EFUSE_POWER_GLITCH_DSENSE_V)<<(EFUSE_POWER_GLITCH_DSENSE_S)) -#define EFUSE_POWER_GLITCH_DSENSE_V 0x3 -#define EFUSE_POWER_GLITCH_DSENSE_S 26 -/* EFUSE_USB_PHY_SEL : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This bit is used to switch internal PHY and external PHY for USB OTG and USB Dev -ice. 0: internal PHY is assigned to USB Device while external PHY is assigned to - USB OTG. 1: internal PHY is assigned to USB OTG while external PHY is assigned -to USB Device..*/ -#define EFUSE_USB_PHY_SEL (BIT(25)) -#define EFUSE_USB_PHY_SEL_M (BIT(25)) -#define EFUSE_USB_PHY_SEL_V 0x1 -#define EFUSE_USB_PHY_SEL_S 25 -/* EFUSE_STRAP_JTAG_SEL : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: Set this bit to enable selection between usb_to_jtag and pad_to_jtag through str -apping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0..*/ -#define EFUSE_STRAP_JTAG_SEL (BIT(24)) -#define EFUSE_STRAP_JTAG_SEL_M (BIT(24)) -#define EFUSE_STRAP_JTAG_SEL_V 0x1 -#define EFUSE_STRAP_JTAG_SEL_S 24 -/* EFUSE_DIS_USB_DEVICE : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Set this bit to disable usb device..*/ -#define EFUSE_DIS_USB_DEVICE (BIT(23)) -#define EFUSE_DIS_USB_DEVICE_M (BIT(23)) -#define EFUSE_DIS_USB_DEVICE_V 0x1 -#define EFUSE_DIS_USB_DEVICE_S 23 -/* EFUSE_DIS_USB_JTAG : RO ;bitpos:[22] ;default: 6'h0 ; */ -/*description: Set this bit to disable function of usb switch to jtag in module of usb device..*/ -#define EFUSE_DIS_USB_JTAG (BIT(22)) -#define EFUSE_DIS_USB_JTAG_M (BIT(22)) -#define EFUSE_DIS_USB_JTAG_V 0x1 -#define EFUSE_DIS_USB_JTAG_S 22 -/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to enable revoking aggressive secure boot..*/ -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x1 -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 -/* EFUSE_SECURE_BOOT_EN : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Set this bit to enable secure boot..*/ +/** EFUSE_RD_REPEAT_DATA2_REG register + * BLOCK0 data register 3. + */ +#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) +/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0; + * Purpose of Key2. + */ +#define EFUSE_KEY_PURPOSE_2 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_M (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S) +#define EFUSE_KEY_PURPOSE_2_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_S 0 +/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0; + * Purpose of Key3. + */ +#define EFUSE_KEY_PURPOSE_3 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_M (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S) +#define EFUSE_KEY_PURPOSE_3_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_S 4 +/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0; + * Purpose of Key4. + */ +#define EFUSE_KEY_PURPOSE_4 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_M (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S) +#define EFUSE_KEY_PURPOSE_4_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_S 8 +/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0; + * Purpose of Key5. + */ +#define EFUSE_KEY_PURPOSE_5 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S) +#define EFUSE_KEY_PURPOSE_5_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_S 12 +/** EFUSE_RPT4_RESERVED0 : RO; bitpos: [19:16]; default: 0; + * Reserved (used for four backups method). + */ +#define EFUSE_RPT4_RESERVED0 0x0000000FU +#define EFUSE_RPT4_RESERVED0_M (EFUSE_RPT4_RESERVED0_V << EFUSE_RPT4_RESERVED0_S) +#define EFUSE_RPT4_RESERVED0_V 0x0000000FU +#define EFUSE_RPT4_RESERVED0_S 16 +/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0; + * Set this bit to enable secure boot. + */ #define EFUSE_SECURE_BOOT_EN (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_M (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_V 0x1 +#define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) +#define EFUSE_SECURE_BOOT_EN_V 0x00000001U #define EFUSE_SECURE_BOOT_EN_S 20 -/* EFUSE_RPT4_RESERVED0 : RO ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: Reserved (used for four backups method)..*/ -#define EFUSE_RPT4_RESERVED0 0x0000000F -#define EFUSE_RPT4_RESERVED0_M ((EFUSE_RPT4_RESERVED0_V)<<(EFUSE_RPT4_RESERVED0_S)) -#define EFUSE_RPT4_RESERVED0_V 0xF -#define EFUSE_RPT4_RESERVED0_S 16 -/* EFUSE_KEY_PURPOSE_5 : RO ;bitpos:[15:12] ;default: 4'h0 ; */ -/*description: Purpose of Key5..*/ -#define EFUSE_KEY_PURPOSE_5 0x0000000F -#define EFUSE_KEY_PURPOSE_5_M ((EFUSE_KEY_PURPOSE_5_V)<<(EFUSE_KEY_PURPOSE_5_S)) -#define EFUSE_KEY_PURPOSE_5_V 0xF -#define EFUSE_KEY_PURPOSE_5_S 12 -/* EFUSE_KEY_PURPOSE_4 : RO ;bitpos:[11:8] ;default: 4'h0 ; */ -/*description: Purpose of Key4..*/ -#define EFUSE_KEY_PURPOSE_4 0x0000000F -#define EFUSE_KEY_PURPOSE_4_M ((EFUSE_KEY_PURPOSE_4_V)<<(EFUSE_KEY_PURPOSE_4_S)) -#define EFUSE_KEY_PURPOSE_4_V 0xF -#define EFUSE_KEY_PURPOSE_4_S 8 -/* EFUSE_KEY_PURPOSE_3 : RO ;bitpos:[7:4] ;default: 4'h0 ; */ -/*description: Purpose of Key3..*/ -#define EFUSE_KEY_PURPOSE_3 0x0000000F -#define EFUSE_KEY_PURPOSE_3_M ((EFUSE_KEY_PURPOSE_3_V)<<(EFUSE_KEY_PURPOSE_3_S)) -#define EFUSE_KEY_PURPOSE_3_V 0xF -#define EFUSE_KEY_PURPOSE_3_S 4 -/* EFUSE_KEY_PURPOSE_2 : RO ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: Purpose of Key2..*/ -#define EFUSE_KEY_PURPOSE_2 0x0000000F -#define EFUSE_KEY_PURPOSE_2_M ((EFUSE_KEY_PURPOSE_2_V)<<(EFUSE_KEY_PURPOSE_2_S)) -#define EFUSE_KEY_PURPOSE_2_V 0xF -#define EFUSE_KEY_PURPOSE_2_S 0 +/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0; + * Set this bit to enable revoking aggressive secure boot. + */ +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001U +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 +/** EFUSE_DIS_USB_JTAG : RO; bitpos: [22]; default: 0; + * Set this bit to disable function of usb switch to jtag in module of usb device. + */ +#define EFUSE_DIS_USB_JTAG (BIT(22)) +#define EFUSE_DIS_USB_JTAG_M (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S) +#define EFUSE_DIS_USB_JTAG_V 0x00000001U +#define EFUSE_DIS_USB_JTAG_S 22 +/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [23]; default: 0; + * Set this bit to disable usb device. + */ +#define EFUSE_DIS_USB_SERIAL_JTAG (BIT(23)) +#define EFUSE_DIS_USB_SERIAL_JTAG_M (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_S 23 +/** EFUSE_STRAP_JTAG_SEL : RO; bitpos: [24]; default: 0; + * Set this bit to enable selection between usb_to_jtag and pad_to_jtag through + * strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0. + */ +#define EFUSE_STRAP_JTAG_SEL (BIT(24)) +#define EFUSE_STRAP_JTAG_SEL_M (EFUSE_STRAP_JTAG_SEL_V << EFUSE_STRAP_JTAG_SEL_S) +#define EFUSE_STRAP_JTAG_SEL_V 0x00000001U +#define EFUSE_STRAP_JTAG_SEL_S 24 +/** EFUSE_USB_PHY_SEL : RO; bitpos: [25]; default: 0; + * This bit is used to switch internal PHY and external PHY for USB OTG and USB + * Device. 0: internal PHY is assigned to USB Device while external PHY is assigned to + * USB OTG. 1: internal PHY is assigned to USB OTG while external PHY is assigned to + * USB Device. + */ +#define EFUSE_USB_PHY_SEL (BIT(25)) +#define EFUSE_USB_PHY_SEL_M (EFUSE_USB_PHY_SEL_V << EFUSE_USB_PHY_SEL_S) +#define EFUSE_USB_PHY_SEL_V 0x00000001U +#define EFUSE_USB_PHY_SEL_S 25 +/** EFUSE_POWER_GLITCH_DSENSE : RO; bitpos: [27:26]; default: 0; + * Sample delay configuration of power glitch. + */ +#define EFUSE_POWER_GLITCH_DSENSE 0x00000003U +#define EFUSE_POWER_GLITCH_DSENSE_M (EFUSE_POWER_GLITCH_DSENSE_V << EFUSE_POWER_GLITCH_DSENSE_S) +#define EFUSE_POWER_GLITCH_DSENSE_V 0x00000003U +#define EFUSE_POWER_GLITCH_DSENSE_S 26 +/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0; + * Configures flash waiting time after power-up, in unit of ms. If the value is less + * than 15, the waiting time is the configurable value. Otherwise, the waiting time + * is twice the configurable value. + */ +#define EFUSE_FLASH_TPUW 0x0000000FU +#define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S) +#define EFUSE_FLASH_TPUW_V 0x0000000FU +#define EFUSE_FLASH_TPUW_S 28 -#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3C) -/* EFUSE_DIS_USB_OTG_DOWNLOAD_MODE : RO ;bitpos:[31] ;default: 1'h0 ; */ -/*description: Set this bit to disable download through USB-OTG*/ -#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE (BIT(31)) -#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_M (BIT(31)) -#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V 0x1 -#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S 31 -/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[30] ;default: 1'h0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED1 (BIT(30)) -#define EFUSE_RPT4_RESERVED1_M (BIT(30)) -#define EFUSE_RPT4_RESERVED1_V 0x1 -#define EFUSE_RPT4_RESERVED1_S 30 -/* EFUSE_SECURE_VERSION : RO ;bitpos:[29:14] ;default: 16'h0 ; */ -/*description: Secure version (used by ESP-IDF anti-rollback feature)..*/ -#define EFUSE_SECURE_VERSION 0x0000FFFF -#define EFUSE_SECURE_VERSION_M ((EFUSE_SECURE_VERSION_V)<<(EFUSE_SECURE_VERSION_S)) -#define EFUSE_SECURE_VERSION_V 0xFFFF -#define EFUSE_SECURE_VERSION_S 14 -/* EFUSE_FORCE_SEND_RESUME : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to force ROM code to send a resume command during SPI boot..*/ -#define EFUSE_FORCE_SEND_RESUME (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_M (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_V 0x1 -#define EFUSE_FORCE_SEND_RESUME_S 13 -/* EFUSE_FLASH_ECC_EN : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set 1 to enable ECC for flash boot..*/ -#define EFUSE_FLASH_ECC_EN (BIT(12)) -#define EFUSE_FLASH_ECC_EN_M (BIT(12)) -#define EFUSE_FLASH_ECC_EN_V 0x1 -#define EFUSE_FLASH_ECC_EN_S 12 -/* EFUSE_FLASH_PAGE_SIZE : RO ;bitpos:[11:10] ;default: 2'h0 ; */ -/*description: Set Flash page size..*/ -#define EFUSE_FLASH_PAGE_SIZE 0x00000003 -#define EFUSE_FLASH_PAGE_SIZE_M ((EFUSE_FLASH_PAGE_SIZE_V)<<(EFUSE_FLASH_PAGE_SIZE_S)) -#define EFUSE_FLASH_PAGE_SIZE_V 0x3 -#define EFUSE_FLASH_PAGE_SIZE_S 10 -/* EFUSE_FLASH_TYPE : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set the maximum lines of SPI flash. 0: four lines. 1: eight lines..*/ -#define EFUSE_FLASH_TYPE (BIT(9)) -#define EFUSE_FLASH_TYPE_M (BIT(9)) -#define EFUSE_FLASH_TYPE_V 0x1 -#define EFUSE_FLASH_TYPE_S 9 -/* EFUSE_PIN_POWER_SELECTION : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI..*/ -#define EFUSE_PIN_POWER_SELECTION (BIT(8)) -#define EFUSE_PIN_POWER_SELECTION_M (BIT(8)) -#define EFUSE_PIN_POWER_SELECTION_V 0x1 -#define EFUSE_PIN_POWER_SELECTION_S 8 -/* EFUSE_UART_PRINT_CONTROL : RO ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO -8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled..*/ -#define EFUSE_UART_PRINT_CONTROL 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_M ((EFUSE_UART_PRINT_CONTROL_V)<<(EFUSE_UART_PRINT_CONTROL_S)) -#define EFUSE_UART_PRINT_CONTROL_V 0x3 -#define EFUSE_UART_PRINT_CONTROL_S 6 -/* EFUSE_ENABLE_SECURITY_DOWNLOAD : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to enable secure UART download mode..*/ -#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x1 -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 -/* EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to disable download through USB-Seial-JTAG.*/ -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x1 -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 4 -/* EFUSE_FLASH_ECC_MODE : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would - use 16to17 byte mode..*/ -#define EFUSE_FLASH_ECC_MODE (BIT(3)) -#define EFUSE_FLASH_ECC_MODE_M (BIT(3)) -#define EFUSE_FLASH_ECC_MODE_V 0x1 -#define EFUSE_FLASH_ECC_MODE_S 3 -/* EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Disable USB-Serial-JTAG print during rom boot.*/ -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x1 -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 2 -/* EFUSE_DIS_DIRECT_BOOT : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to disable direct boot.*/ -#define EFUSE_DIS_DIRECT_BOOT (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_M (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_V 0x1 -#define EFUSE_DIS_DIRECT_BOOT_S 1 -/* EFUSE_DIS_DOWNLOAD_MODE : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7)..*/ +/** EFUSE_RD_REPEAT_DATA3_REG register + * BLOCK0 data register 4. + */ +#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) +/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; + * Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7). + */ #define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_M (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_V 0x1 +#define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) +#define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MODE_S 0 +/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0; + * Disable direct boot mode + */ +#define EFUSE_DIS_DIRECT_BOOT (BIT(1)) +#define EFUSE_DIS_DIRECT_BOOT_M (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S) +#define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U +#define EFUSE_DIS_DIRECT_BOOT_S 1 +/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0; + * Selectes the default UART print channel. 0: UART0. 1: UART1. + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 2 +/** EFUSE_FLASH_ECC_MODE : RO; bitpos: [3]; default: 0; + * Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would + * use 16to17 byte mode. + */ +#define EFUSE_FLASH_ECC_MODE (BIT(3)) +#define EFUSE_FLASH_ECC_MODE_M (EFUSE_FLASH_ECC_MODE_V << EFUSE_FLASH_ECC_MODE_S) +#define EFUSE_FLASH_ECC_MODE_V 0x00000001U +#define EFUSE_FLASH_ECC_MODE_S 3 +/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0; + * Set this bit to disable UART download mode through USB. + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(4)) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 4 +/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0; + * Set this bit to enable secure UART download mode. + */ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001U +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 +/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0; + * Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 + * is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled. + */ +#define EFUSE_UART_PRINT_CONTROL 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) +#define EFUSE_UART_PRINT_CONTROL_V 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_S 6 +/** EFUSE_PIN_POWER_SELECTION : RO; bitpos: [8]; default: 0; + * GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI. + */ +#define EFUSE_PIN_POWER_SELECTION (BIT(8)) +#define EFUSE_PIN_POWER_SELECTION_M (EFUSE_PIN_POWER_SELECTION_V << EFUSE_PIN_POWER_SELECTION_S) +#define EFUSE_PIN_POWER_SELECTION_V 0x00000001U +#define EFUSE_PIN_POWER_SELECTION_S 8 +/** EFUSE_FLASH_TYPE : RO; bitpos: [9]; default: 0; + * Set the maximum lines of SPI flash. 0: four lines. 1: eight lines. + */ +#define EFUSE_FLASH_TYPE (BIT(9)) +#define EFUSE_FLASH_TYPE_M (EFUSE_FLASH_TYPE_V << EFUSE_FLASH_TYPE_S) +#define EFUSE_FLASH_TYPE_V 0x00000001U +#define EFUSE_FLASH_TYPE_S 9 +/** EFUSE_FLASH_PAGE_SIZE : RO; bitpos: [11:10]; default: 0; + * Set Flash page size. + */ +#define EFUSE_FLASH_PAGE_SIZE 0x00000003U +#define EFUSE_FLASH_PAGE_SIZE_M (EFUSE_FLASH_PAGE_SIZE_V << EFUSE_FLASH_PAGE_SIZE_S) +#define EFUSE_FLASH_PAGE_SIZE_V 0x00000003U +#define EFUSE_FLASH_PAGE_SIZE_S 10 +/** EFUSE_FLASH_ECC_EN : RO; bitpos: [12]; default: 0; + * Set 1 to enable ECC for flash boot. + */ +#define EFUSE_FLASH_ECC_EN (BIT(12)) +#define EFUSE_FLASH_ECC_EN_M (EFUSE_FLASH_ECC_EN_V << EFUSE_FLASH_ECC_EN_S) +#define EFUSE_FLASH_ECC_EN_V 0x00000001U +#define EFUSE_FLASH_ECC_EN_S 12 +/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [13]; default: 0; + * Set this bit to force ROM code to send a resume command during SPI boot. + */ +#define EFUSE_FORCE_SEND_RESUME (BIT(13)) +#define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) +#define EFUSE_FORCE_SEND_RESUME_V 0x00000001U +#define EFUSE_FORCE_SEND_RESUME_S 13 +/** EFUSE_SECURE_VERSION : RO; bitpos: [29:14]; default: 0; + * Secure version (used by ESP-IDF anti-rollback feature). + */ +#define EFUSE_SECURE_VERSION 0x0000FFFFU +#define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) +#define EFUSE_SECURE_VERSION_V 0x0000FFFFU +#define EFUSE_SECURE_VERSION_S 14 +/** EFUSE_POWERGLITCH_EN : RO; bitpos: [30]; default: 0; + * Set this bit to enable power glitch function. + */ +#define EFUSE_POWERGLITCH_EN (BIT(30)) +#define EFUSE_POWERGLITCH_EN_M (EFUSE_POWERGLITCH_EN_V << EFUSE_POWERGLITCH_EN_S) +#define EFUSE_POWERGLITCH_EN_V 0x00000001U +#define EFUSE_POWERGLITCH_EN_S 30 +/** EFUSE_DIS_USB_OTG_DOWNLOAD_MODE : R; bitpos: [31]; default: 0; + * Set this bit to disable download through USB-OTG + */ +#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE (BIT(31)) +#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_M (EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S) +#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V 0x00000001U +#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S 31 + +/** EFUSE_RD_REPEAT_DATA4_REG register + * BLOCK0 data register 5. + */ +#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) +/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [0]; default: 0; + * Disables check of wafer version major + */ +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR (BIT(0)) +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S) +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V 0x00000001U +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S 0 +/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [1]; default: 0; + * Disables check of blk version major + */ +#define EFUSE_DISABLE_BLK_VERSION_MAJOR (BIT(1)) +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S) +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V 0x00000001U +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S 1 +/** EFUSE_RESERVED_0_162 : R; bitpos: [23:2]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_0_162 0x003FFFFFU +#define EFUSE_RESERVED_0_162_M (EFUSE_RESERVED_0_162_V << EFUSE_RESERVED_0_162_S) +#define EFUSE_RESERVED_0_162_V 0x003FFFFFU +#define EFUSE_RESERVED_0_162_S 2 -#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) -/* EFUSE_RPT4_RESERVED2 : RO ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: Reserved (used for four backups method)..*/ -#define EFUSE_RPT4_RESERVED2 0x00FFFFFF -#define EFUSE_RPT4_RESERVED2_M ((EFUSE_RPT4_RESERVED2_V)<<(EFUSE_RPT4_RESERVED2_S)) -#define EFUSE_RPT4_RESERVED2_V 0xFFFFFF -#define EFUSE_RPT4_RESERVED2_S 0 - -#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44) -/* EFUSE_MAC_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the low 32 bits of MAC address..*/ -#define EFUSE_MAC_0 0xFFFFFFFF -#define EFUSE_MAC_0_M ((EFUSE_MAC_0_V)<<(EFUSE_MAC_0_S)) -#define EFUSE_MAC_0_V 0xFFFFFFFF +/** EFUSE_RD_MAC_SPI_SYS_0_REG register + * BLOCK1 data register 0. + */ +#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44) +/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0; + * Stores the low 32 bits of MAC address. + */ +#define EFUSE_MAC_0 0xFFFFFFFFU +#define EFUSE_MAC_0_M (EFUSE_MAC_0_V << EFUSE_MAC_0_S) +#define EFUSE_MAC_0_V 0xFFFFFFFFU #define EFUSE_MAC_0_S 0 -#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48) -/* EFUSE_SPI_PAD_CONF_0 : RO ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: Stores the zeroth part of SPI_PAD_CONF..*/ -#define EFUSE_SPI_PAD_CONF_0 0x0000FFFF -#define EFUSE_SPI_PAD_CONF_0_M ((EFUSE_SPI_PAD_CONF_0_V)<<(EFUSE_SPI_PAD_CONF_0_S)) -#define EFUSE_SPI_PAD_CONF_0_V 0xFFFF -#define EFUSE_SPI_PAD_CONF_0_S 16 -/* EFUSE_MAC_1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: Stores the high 16 bits of MAC address..*/ -#define EFUSE_MAC_1 0x0000FFFF -#define EFUSE_MAC_1_M ((EFUSE_MAC_1_V)<<(EFUSE_MAC_1_S)) -#define EFUSE_MAC_1_V 0xFFFF +/** EFUSE_RD_MAC_SPI_SYS_1_REG register + * BLOCK1 data register 1. + */ +#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48) +/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0; + * Stores the high 16 bits of MAC address. + */ +#define EFUSE_MAC_1 0x0000FFFFU +#define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) +#define EFUSE_MAC_1_V 0x0000FFFFU #define EFUSE_MAC_1_S 0 +/** EFUSE_SPI_PAD_CONFIG_CLK : R; bitpos: [21:16]; default: 0; + * SPI_PAD_configure CLK + */ +#define EFUSE_SPI_PAD_CONFIG_CLK 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_CLK_M (EFUSE_SPI_PAD_CONFIG_CLK_V << EFUSE_SPI_PAD_CONFIG_CLK_S) +#define EFUSE_SPI_PAD_CONFIG_CLK_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_CLK_S 16 +/** EFUSE_SPI_PAD_CONFIG_Q : R; bitpos: [27:22]; default: 0; + * SPI_PAD_configure Q(D1) + */ +#define EFUSE_SPI_PAD_CONFIG_Q 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_Q_M (EFUSE_SPI_PAD_CONFIG_Q_V << EFUSE_SPI_PAD_CONFIG_Q_S) +#define EFUSE_SPI_PAD_CONFIG_Q_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_Q_S 22 +/** EFUSE_SPI_PAD_CONFIG_D : R; bitpos: [31:28]; default: 0; + * SPI_PAD_configure D(D0) + */ +#define EFUSE_SPI_PAD_CONFIG_D 0x0000000FU +#define EFUSE_SPI_PAD_CONFIG_D_M (EFUSE_SPI_PAD_CONFIG_D_V << EFUSE_SPI_PAD_CONFIG_D_S) +#define EFUSE_SPI_PAD_CONFIG_D_V 0x0000000FU +#define EFUSE_SPI_PAD_CONFIG_D_S 28 -#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4C) +/** EFUSE_RD_MAC_SPI_SYS_2_REG register + * BLOCK1 data register 2. + */ +#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c) /* EFUSE_SPI_PAD_CONF_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: Stores the first part of SPI_PAD_CONF..*/ #define EFUSE_SPI_PAD_CONF_1 0xFFFFFFFF #define EFUSE_SPI_PAD_CONF_1_M ((EFUSE_SPI_PAD_CONF_1_V)<<(EFUSE_SPI_PAD_CONF_1_S)) #define EFUSE_SPI_PAD_CONF_1_V 0xFFFFFFFF #define EFUSE_SPI_PAD_CONF_1_S 0 +/** EFUSE_SPI_PAD_CONFIG_D_1 : R; bitpos: [1:0]; default: 0; + * SPI_PAD_configure D(D0) + */ +#define EFUSE_SPI_PAD_CONFIG_D_1 0x00000003U +#define EFUSE_SPI_PAD_CONFIG_D_1_M (EFUSE_SPI_PAD_CONFIG_D_1_V << EFUSE_SPI_PAD_CONFIG_D_1_S) +#define EFUSE_SPI_PAD_CONFIG_D_1_V 0x00000003U +#define EFUSE_SPI_PAD_CONFIG_D_1_S 0 +/** EFUSE_SPI_PAD_CONFIG_CS : R; bitpos: [7:2]; default: 0; + * SPI_PAD_configure CS + */ +#define EFUSE_SPI_PAD_CONFIG_CS 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_CS_M (EFUSE_SPI_PAD_CONFIG_CS_V << EFUSE_SPI_PAD_CONFIG_CS_S) +#define EFUSE_SPI_PAD_CONFIG_CS_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_CS_S 2 +/** EFUSE_SPI_PAD_CONFIG_HD : R; bitpos: [13:8]; default: 0; + * SPI_PAD_configure HD(D3) + */ +#define EFUSE_SPI_PAD_CONFIG_HD 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_HD_M (EFUSE_SPI_PAD_CONFIG_HD_V << EFUSE_SPI_PAD_CONFIG_HD_S) +#define EFUSE_SPI_PAD_CONFIG_HD_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_HD_S 8 +/** EFUSE_SPI_PAD_CONFIG_WP : R; bitpos: [19:14]; default: 0; + * SPI_PAD_configure WP(D2) + */ +#define EFUSE_SPI_PAD_CONFIG_WP 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_WP_M (EFUSE_SPI_PAD_CONFIG_WP_V << EFUSE_SPI_PAD_CONFIG_WP_S) +#define EFUSE_SPI_PAD_CONFIG_WP_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_WP_S 14 +/** EFUSE_SPI_PAD_CONFIG_DQS : R; bitpos: [25:20]; default: 0; + * SPI_PAD_configure DQS + */ +#define EFUSE_SPI_PAD_CONFIG_DQS 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_DQS_M (EFUSE_SPI_PAD_CONFIG_DQS_V << EFUSE_SPI_PAD_CONFIG_DQS_S) +#define EFUSE_SPI_PAD_CONFIG_DQS_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_DQS_S 20 +/** EFUSE_SPI_PAD_CONFIG_D4 : R; bitpos: [31:26]; default: 0; + * SPI_PAD_configure D4 + */ +#define EFUSE_SPI_PAD_CONFIG_D4 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D4_M (EFUSE_SPI_PAD_CONFIG_D4_V << EFUSE_SPI_PAD_CONFIG_D4_S) +#define EFUSE_SPI_PAD_CONFIG_D4_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D4_S 26 + +/** EFUSE_RD_MAC_SPI_SYS_3_REG register + * BLOCK1 data register 3. + */ +#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) +/** EFUSE_SPI_PAD_CONFIG_D5 : R; bitpos: [5:0]; default: 0; + * SPI_PAD_configure D5 + */ +#define EFUSE_SPI_PAD_CONFIG_D5 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D5_M (EFUSE_SPI_PAD_CONFIG_D5_V << EFUSE_SPI_PAD_CONFIG_D5_S) +#define EFUSE_SPI_PAD_CONFIG_D5_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D5_S 0 +/** EFUSE_SPI_PAD_CONFIG_D6 : R; bitpos: [11:6]; default: 0; + * SPI_PAD_configure D6 + */ +#define EFUSE_SPI_PAD_CONFIG_D6 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D6_M (EFUSE_SPI_PAD_CONFIG_D6_V << EFUSE_SPI_PAD_CONFIG_D6_S) +#define EFUSE_SPI_PAD_CONFIG_D6_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D6_S 6 +/** EFUSE_SPI_PAD_CONFIG_D7 : R; bitpos: [17:12]; default: 0; + * SPI_PAD_configure D7 + */ +#define EFUSE_SPI_PAD_CONFIG_D7 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D7_M (EFUSE_SPI_PAD_CONFIG_D7_V << EFUSE_SPI_PAD_CONFIG_D7_S) +#define EFUSE_SPI_PAD_CONFIG_D7_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D7_S 12 +/** EFUSE_WAFER_VERSION_MINOR_LO : R; bitpos: [20:18]; default: 0; + * WAFER_VERSION_MINOR least significant bits + */ +#define EFUSE_WAFER_VERSION_MINOR_LO 0x00000007U +#define EFUSE_WAFER_VERSION_MINOR_LO_M (EFUSE_WAFER_VERSION_MINOR_LO_V << EFUSE_WAFER_VERSION_MINOR_LO_S) +#define EFUSE_WAFER_VERSION_MINOR_LO_V 0x00000007U +#define EFUSE_WAFER_VERSION_MINOR_LO_S 18 +/** EFUSE_PKG_VERSION : R; bitpos: [23:21]; default: 0; + * Package version + */ +#define EFUSE_PKG_VERSION 0x00000007U +#define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S) +#define EFUSE_PKG_VERSION_V 0x00000007U +#define EFUSE_PKG_VERSION_S 21 +/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [26:24]; default: 0; + * BLK_VERSION_MINOR + */ +#define EFUSE_BLK_VERSION_MINOR 0x00000007U +#define EFUSE_BLK_VERSION_MINOR_M (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S) +#define EFUSE_BLK_VERSION_MINOR_V 0x00000007U +#define EFUSE_BLK_VERSION_MINOR_S 24 +/** EFUSE_RESERVED_1_123 : R; bitpos: [31:27]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_1_123 0x0000001FU +#define EFUSE_RESERVED_1_123_M (EFUSE_RESERVED_1_123_V << EFUSE_RESERVED_1_123_S) +#define EFUSE_RESERVED_1_123_V 0x0000001FU +#define EFUSE_RESERVED_1_123_S 27 + +/** EFUSE_RD_MAC_SPI_SYS_4_REG register + * BLOCK1 data register 4. + */ +#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) +/** EFUSE_RESERVED_1_128 : R; bitpos: [12:0]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_1_128 0x00001FFFU +#define EFUSE_RESERVED_1_128_M (EFUSE_RESERVED_1_128_V << EFUSE_RESERVED_1_128_S) +#define EFUSE_RESERVED_1_128_V 0x00001FFFU +#define EFUSE_RESERVED_1_128_S 0 +/** EFUSE_K_RTC_LDO : R; bitpos: [19:13]; default: 0; + * BLOCK1 K_RTC_LDO + */ +#define EFUSE_K_RTC_LDO 0x0000007FU +#define EFUSE_K_RTC_LDO_M (EFUSE_K_RTC_LDO_V << EFUSE_K_RTC_LDO_S) +#define EFUSE_K_RTC_LDO_V 0x0000007FU +#define EFUSE_K_RTC_LDO_S 13 +/** EFUSE_K_DIG_LDO : R; bitpos: [26:20]; default: 0; + * BLOCK1 K_DIG_LDO + */ +#define EFUSE_K_DIG_LDO 0x0000007FU +#define EFUSE_K_DIG_LDO_M (EFUSE_K_DIG_LDO_V << EFUSE_K_DIG_LDO_S) +#define EFUSE_K_DIG_LDO_V 0x0000007FU +#define EFUSE_K_DIG_LDO_S 20 +/** EFUSE_V_RTC_DBIAS20 : R; bitpos: [31:27]; default: 0; + * BLOCK1 voltage of rtc dbias20 + */ +#define EFUSE_V_RTC_DBIAS20 0x0000001FU +#define EFUSE_V_RTC_DBIAS20_M (EFUSE_V_RTC_DBIAS20_V << EFUSE_V_RTC_DBIAS20_S) +#define EFUSE_V_RTC_DBIAS20_V 0x0000001FU +#define EFUSE_V_RTC_DBIAS20_S 27 + +/** EFUSE_RD_MAC_SPI_SYS_5_REG register + * BLOCK1 data register 5. + */ +#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58) +/** EFUSE_V_RTC_DBIAS20_1 : R; bitpos: [2:0]; default: 0; + * BLOCK1 voltage of rtc dbias20 + */ +#define EFUSE_V_RTC_DBIAS20_1 0x00000007U +#define EFUSE_V_RTC_DBIAS20_1_M (EFUSE_V_RTC_DBIAS20_1_V << EFUSE_V_RTC_DBIAS20_1_S) +#define EFUSE_V_RTC_DBIAS20_1_V 0x00000007U +#define EFUSE_V_RTC_DBIAS20_1_S 0 +/** EFUSE_V_DIG_DBIAS20 : R; bitpos: [10:3]; default: 0; + * BLOCK1 voltage of digital dbias20 + */ +#define EFUSE_V_DIG_DBIAS20 0x000000FFU +#define EFUSE_V_DIG_DBIAS20_M (EFUSE_V_DIG_DBIAS20_V << EFUSE_V_DIG_DBIAS20_S) +#define EFUSE_V_DIG_DBIAS20_V 0x000000FFU +#define EFUSE_V_DIG_DBIAS20_S 3 +/** EFUSE_DIG_DBIAS_HVT : R; bitpos: [15:11]; default: 0; + * BLOCK1 digital dbias when hvt + */ +#define EFUSE_DIG_DBIAS_HVT 0x0000001FU +#define EFUSE_DIG_DBIAS_HVT_M (EFUSE_DIG_DBIAS_HVT_V << EFUSE_DIG_DBIAS_HVT_S) +#define EFUSE_DIG_DBIAS_HVT_V 0x0000001FU +#define EFUSE_DIG_DBIAS_HVT_S 11 +/** EFUSE_RESERVED_1_176 : R; bitpos: [22:16]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_1_176 0x0000007FU +#define EFUSE_RESERVED_1_176_M (EFUSE_RESERVED_1_176_V << EFUSE_RESERVED_1_176_S) +#define EFUSE_RESERVED_1_176_V 0x0000007FU +#define EFUSE_RESERVED_1_176_S 16 +/** EFUSE_WAFER_VERSION_MINOR_HI : R; bitpos: [23]; default: 0; + * WAFER_VERSION_MINOR most significant bit + */ +#define EFUSE_WAFER_VERSION_MINOR_HI (BIT(23)) +#define EFUSE_WAFER_VERSION_MINOR_HI_M (EFUSE_WAFER_VERSION_MINOR_HI_V << EFUSE_WAFER_VERSION_MINOR_HI_S) +#define EFUSE_WAFER_VERSION_MINOR_HI_V 0x00000001U +#define EFUSE_WAFER_VERSION_MINOR_HI_S 23 +/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [25:24]; default: 0; + * WAFER_VERSION_MAJOR + */ +#define EFUSE_WAFER_VERSION_MAJOR 0x00000003U +#define EFUSE_WAFER_VERSION_MAJOR_M (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S) +#define EFUSE_WAFER_VERSION_MAJOR_V 0x00000003U +#define EFUSE_WAFER_VERSION_MAJOR_S 24 +/** EFUSE_ADC2_CAL_VOL_ATTEN3 : R; bitpos: [31:26]; default: 0; + * ADC2 calibration voltage at atten3 + */ +#define EFUSE_ADC2_CAL_VOL_ATTEN3 0x0000003FU +#define EFUSE_ADC2_CAL_VOL_ATTEN3_M (EFUSE_ADC2_CAL_VOL_ATTEN3_V << EFUSE_ADC2_CAL_VOL_ATTEN3_S) +#define EFUSE_ADC2_CAL_VOL_ATTEN3_V 0x0000003FU +#define EFUSE_ADC2_CAL_VOL_ATTEN3_S 26 + +/** EFUSE_RD_SYS_PART1_DATA0_REG register + * Register 0 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c) +/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ +#define EFUSE_OPTIONAL_UNIQUE_ID 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_M (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_S 0 + +/** EFUSE_RD_SYS_PART1_DATA1_REG register + * Register 1 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60) +/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ +#define EFUSE_OPTIONAL_UNIQUE_ID_1 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_1_M (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_1_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_1_S 0 + +/** EFUSE_RD_SYS_PART1_DATA2_REG register + * Register 2 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64) +/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ +#define EFUSE_OPTIONAL_UNIQUE_ID_2 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_2_M (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_2_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_2_S 0 + +/** EFUSE_RD_SYS_PART1_DATA3_REG register + * Register 3 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68) +/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ +#define EFUSE_OPTIONAL_UNIQUE_ID_3 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_3_M (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_3_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_3_S 0 + +/** EFUSE_RD_SYS_PART1_DATA4_REG register + * Register 4 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c) +/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [1:0]; default: 0; + * BLK_VERSION_MAJOR of BLOCK2 change of this bit means users need to update firmware + */ +#define EFUSE_BLK_VERSION_MAJOR 0x00000003U +#define EFUSE_BLK_VERSION_MAJOR_M (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S) +#define EFUSE_BLK_VERSION_MAJOR_V 0x00000003U +#define EFUSE_BLK_VERSION_MAJOR_S 0 +/** EFUSE_RESERVED_2_130 : R; bitpos: [3:2]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_2_130 0x00000003U +#define EFUSE_RESERVED_2_130_M (EFUSE_RESERVED_2_130_V << EFUSE_RESERVED_2_130_S) +#define EFUSE_RESERVED_2_130_V 0x00000003U +#define EFUSE_RESERVED_2_130_S 2 +/** EFUSE_TEMP_CALIB : R; bitpos: [12:4]; default: 0; + * Temperature calibration data + */ +#define EFUSE_TEMP_CALIB 0x000001FFU +#define EFUSE_TEMP_CALIB_M (EFUSE_TEMP_CALIB_V << EFUSE_TEMP_CALIB_S) +#define EFUSE_TEMP_CALIB_V 0x000001FFU +#define EFUSE_TEMP_CALIB_S 4 +/** EFUSE_OCODE : R; bitpos: [20:13]; default: 0; + * ADC OCode + */ +#define EFUSE_OCODE 0x000000FFU +#define EFUSE_OCODE_M (EFUSE_OCODE_V << EFUSE_OCODE_S) +#define EFUSE_OCODE_V 0x000000FFU +#define EFUSE_OCODE_S 13 +/** EFUSE_ADC1_INIT_CODE_ATTEN0 : R; bitpos: [28:21]; default: 0; + * ADC1 init code at atten0 + */ +#define EFUSE_ADC1_INIT_CODE_ATTEN0 0x000000FFU +#define EFUSE_ADC1_INIT_CODE_ATTEN0_M (EFUSE_ADC1_INIT_CODE_ATTEN0_V << EFUSE_ADC1_INIT_CODE_ATTEN0_S) +#define EFUSE_ADC1_INIT_CODE_ATTEN0_V 0x000000FFU +#define EFUSE_ADC1_INIT_CODE_ATTEN0_S 21 +/** EFUSE_ADC1_INIT_CODE_ATTEN1 : R; bitpos: [31:29]; default: 0; + * ADC1 init code at atten1 + */ +#define EFUSE_ADC1_INIT_CODE_ATTEN1 0x00000007U +#define EFUSE_ADC1_INIT_CODE_ATTEN1_M (EFUSE_ADC1_INIT_CODE_ATTEN1_V << EFUSE_ADC1_INIT_CODE_ATTEN1_S) +#define EFUSE_ADC1_INIT_CODE_ATTEN1_V 0x00000007U +#define EFUSE_ADC1_INIT_CODE_ATTEN1_S 29 + +/** EFUSE_RD_SYS_PART1_DATA5_REG register + * Register 5 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70) +/** EFUSE_ADC1_INIT_CODE_ATTEN1_1 : R; bitpos: [2:0]; default: 0; + * ADC1 init code at atten1 + */ +#define EFUSE_ADC1_INIT_CODE_ATTEN1_1 0x00000007U +#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_M (EFUSE_ADC1_INIT_CODE_ATTEN1_1_V << EFUSE_ADC1_INIT_CODE_ATTEN1_1_S) +#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_V 0x00000007U +#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_S 0 +/** EFUSE_ADC1_INIT_CODE_ATTEN2 : R; bitpos: [8:3]; default: 0; + * ADC1 init code at atten2 + */ +#define EFUSE_ADC1_INIT_CODE_ATTEN2 0x0000003FU +#define EFUSE_ADC1_INIT_CODE_ATTEN2_M (EFUSE_ADC1_INIT_CODE_ATTEN2_V << EFUSE_ADC1_INIT_CODE_ATTEN2_S) +#define EFUSE_ADC1_INIT_CODE_ATTEN2_V 0x0000003FU +#define EFUSE_ADC1_INIT_CODE_ATTEN2_S 3 +/** EFUSE_ADC1_INIT_CODE_ATTEN3 : R; bitpos: [14:9]; default: 0; + * ADC1 init code at atten3 + */ +#define EFUSE_ADC1_INIT_CODE_ATTEN3 0x0000003FU +#define EFUSE_ADC1_INIT_CODE_ATTEN3_M (EFUSE_ADC1_INIT_CODE_ATTEN3_V << EFUSE_ADC1_INIT_CODE_ATTEN3_S) +#define EFUSE_ADC1_INIT_CODE_ATTEN3_V 0x0000003FU +#define EFUSE_ADC1_INIT_CODE_ATTEN3_S 9 +/** EFUSE_ADC2_INIT_CODE_ATTEN0 : R; bitpos: [22:15]; default: 0; + * ADC2 init code at atten0 + */ +#define EFUSE_ADC2_INIT_CODE_ATTEN0 0x000000FFU +#define EFUSE_ADC2_INIT_CODE_ATTEN0_M (EFUSE_ADC2_INIT_CODE_ATTEN0_V << EFUSE_ADC2_INIT_CODE_ATTEN0_S) +#define EFUSE_ADC2_INIT_CODE_ATTEN0_V 0x000000FFU +#define EFUSE_ADC2_INIT_CODE_ATTEN0_S 15 +/** EFUSE_ADC2_INIT_CODE_ATTEN1 : R; bitpos: [28:23]; default: 0; + * ADC2 init code at atten1 + */ +#define EFUSE_ADC2_INIT_CODE_ATTEN1 0x0000003FU +#define EFUSE_ADC2_INIT_CODE_ATTEN1_M (EFUSE_ADC2_INIT_CODE_ATTEN1_V << EFUSE_ADC2_INIT_CODE_ATTEN1_S) +#define EFUSE_ADC2_INIT_CODE_ATTEN1_V 0x0000003FU +#define EFUSE_ADC2_INIT_CODE_ATTEN1_S 23 +/** EFUSE_ADC2_INIT_CODE_ATTEN2 : R; bitpos: [31:29]; default: 0; + * ADC2 init code at atten2 + */ +#define EFUSE_ADC2_INIT_CODE_ATTEN2 0x00000007U +#define EFUSE_ADC2_INIT_CODE_ATTEN2_M (EFUSE_ADC2_INIT_CODE_ATTEN2_V << EFUSE_ADC2_INIT_CODE_ATTEN2_S) +#define EFUSE_ADC2_INIT_CODE_ATTEN2_V 0x00000007U +#define EFUSE_ADC2_INIT_CODE_ATTEN2_S 29 + +/** EFUSE_RD_SYS_PART1_DATA6_REG register + * Register 6 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74) +/** EFUSE_ADC2_INIT_CODE_ATTEN2_1 : R; bitpos: [2:0]; default: 0; + * ADC2 init code at atten2 + */ +#define EFUSE_ADC2_INIT_CODE_ATTEN2_1 0x00000007U +#define EFUSE_ADC2_INIT_CODE_ATTEN2_1_M (EFUSE_ADC2_INIT_CODE_ATTEN2_1_V << EFUSE_ADC2_INIT_CODE_ATTEN2_1_S) +#define EFUSE_ADC2_INIT_CODE_ATTEN2_1_V 0x00000007U +#define EFUSE_ADC2_INIT_CODE_ATTEN2_1_S 0 +/** EFUSE_ADC2_INIT_CODE_ATTEN3 : R; bitpos: [8:3]; default: 0; + * ADC2 init code at atten3 + */ +#define EFUSE_ADC2_INIT_CODE_ATTEN3 0x0000003FU +#define EFUSE_ADC2_INIT_CODE_ATTEN3_M (EFUSE_ADC2_INIT_CODE_ATTEN3_V << EFUSE_ADC2_INIT_CODE_ATTEN3_S) +#define EFUSE_ADC2_INIT_CODE_ATTEN3_V 0x0000003FU +#define EFUSE_ADC2_INIT_CODE_ATTEN3_S 3 +/** EFUSE_ADC1_CAL_VOL_ATTEN0 : R; bitpos: [16:9]; default: 0; + * ADC1 calibration voltage at atten0 + */ +#define EFUSE_ADC1_CAL_VOL_ATTEN0 0x000000FFU +#define EFUSE_ADC1_CAL_VOL_ATTEN0_M (EFUSE_ADC1_CAL_VOL_ATTEN0_V << EFUSE_ADC1_CAL_VOL_ATTEN0_S) +#define EFUSE_ADC1_CAL_VOL_ATTEN0_V 0x000000FFU +#define EFUSE_ADC1_CAL_VOL_ATTEN0_S 9 +/** EFUSE_ADC1_CAL_VOL_ATTEN1 : R; bitpos: [24:17]; default: 0; + * ADC1 calibration voltage at atten1 + */ +#define EFUSE_ADC1_CAL_VOL_ATTEN1 0x000000FFU +#define EFUSE_ADC1_CAL_VOL_ATTEN1_M (EFUSE_ADC1_CAL_VOL_ATTEN1_V << EFUSE_ADC1_CAL_VOL_ATTEN1_S) +#define EFUSE_ADC1_CAL_VOL_ATTEN1_V 0x000000FFU +#define EFUSE_ADC1_CAL_VOL_ATTEN1_S 17 +/** EFUSE_ADC1_CAL_VOL_ATTEN2 : R; bitpos: [31:25]; default: 0; + * ADC1 calibration voltage at atten2 + */ +#define EFUSE_ADC1_CAL_VOL_ATTEN2 0x0000007FU +#define EFUSE_ADC1_CAL_VOL_ATTEN2_M (EFUSE_ADC1_CAL_VOL_ATTEN2_V << EFUSE_ADC1_CAL_VOL_ATTEN2_S) +#define EFUSE_ADC1_CAL_VOL_ATTEN2_V 0x0000007FU +#define EFUSE_ADC1_CAL_VOL_ATTEN2_S 25 + +/** EFUSE_RD_SYS_PART1_DATA7_REG register + * Register 7 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78) +/** EFUSE_ADC1_CAL_VOL_ATTEN2_1 : R; bitpos: [0]; default: 0; + * ADC1 calibration voltage at atten2 + */ +#define EFUSE_ADC1_CAL_VOL_ATTEN2_1 (BIT(0)) +#define EFUSE_ADC1_CAL_VOL_ATTEN2_1_M (EFUSE_ADC1_CAL_VOL_ATTEN2_1_V << EFUSE_ADC1_CAL_VOL_ATTEN2_1_S) +#define EFUSE_ADC1_CAL_VOL_ATTEN2_1_V 0x00000001U +#define EFUSE_ADC1_CAL_VOL_ATTEN2_1_S 0 +/** EFUSE_ADC1_CAL_VOL_ATTEN3 : R; bitpos: [8:1]; default: 0; + * ADC1 calibration voltage at atten3 + */ +#define EFUSE_ADC1_CAL_VOL_ATTEN3 0x000000FFU +#define EFUSE_ADC1_CAL_VOL_ATTEN3_M (EFUSE_ADC1_CAL_VOL_ATTEN3_V << EFUSE_ADC1_CAL_VOL_ATTEN3_S) +#define EFUSE_ADC1_CAL_VOL_ATTEN3_V 0x000000FFU +#define EFUSE_ADC1_CAL_VOL_ATTEN3_S 1 +/** EFUSE_ADC2_CAL_VOL_ATTEN0 : R; bitpos: [16:9]; default: 0; + * ADC2 calibration voltage at atten0 + */ +#define EFUSE_ADC2_CAL_VOL_ATTEN0 0x000000FFU +#define EFUSE_ADC2_CAL_VOL_ATTEN0_M (EFUSE_ADC2_CAL_VOL_ATTEN0_V << EFUSE_ADC2_CAL_VOL_ATTEN0_S) +#define EFUSE_ADC2_CAL_VOL_ATTEN0_V 0x000000FFU +#define EFUSE_ADC2_CAL_VOL_ATTEN0_S 9 +/** EFUSE_ADC2_CAL_VOL_ATTEN1 : R; bitpos: [23:17]; default: 0; + * ADC2 calibration voltage at atten1 + */ +#define EFUSE_ADC2_CAL_VOL_ATTEN1 0x0000007FU +#define EFUSE_ADC2_CAL_VOL_ATTEN1_M (EFUSE_ADC2_CAL_VOL_ATTEN1_V << EFUSE_ADC2_CAL_VOL_ATTEN1_S) +#define EFUSE_ADC2_CAL_VOL_ATTEN1_V 0x0000007FU +#define EFUSE_ADC2_CAL_VOL_ATTEN1_S 17 +/** EFUSE_ADC2_CAL_VOL_ATTEN2 : R; bitpos: [30:24]; default: 0; + * ADC2 calibration voltage at atten2 + */ +#define EFUSE_ADC2_CAL_VOL_ATTEN2 0x0000007FU +#define EFUSE_ADC2_CAL_VOL_ATTEN2_M (EFUSE_ADC2_CAL_VOL_ATTEN2_V << EFUSE_ADC2_CAL_VOL_ATTEN2_S) +#define EFUSE_ADC2_CAL_VOL_ATTEN2_V 0x0000007FU +#define EFUSE_ADC2_CAL_VOL_ATTEN2_S 24 +/** EFUSE_RESERVED_2_255 : R; bitpos: [31]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_2_255 (BIT(31)) +#define EFUSE_RESERVED_2_255_M (EFUSE_RESERVED_2_255_V << EFUSE_RESERVED_2_255_S) +#define EFUSE_RESERVED_2_255_V 0x00000001U +#define EFUSE_RESERVED_2_255_S 31 -#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) -/* EFUSE_SYS_DATA_PART0_0 : RO ;bitpos:[31:18] ;default: 14'h0 ; */ -/*description: Stores the fist 14 bits of the zeroth part of system data..*/ -#define EFUSE_SYS_DATA_PART0_0 0x00003FFF -#define EFUSE_SYS_DATA_PART0_0_M ((EFUSE_SYS_DATA_PART0_0_V)<<(EFUSE_SYS_DATA_PART0_0_S)) -#define EFUSE_SYS_DATA_PART0_0_V 0x3FFF -#define EFUSE_SYS_DATA_PART0_0_S 18 -/* EFUSE_SPI_PAD_CONF_2 : RO ;bitpos:[17:0] ;default: 18'h0 ; */ -/*description: Stores the second part of SPI_PAD_CONF..*/ -#define EFUSE_SPI_PAD_CONF_2 0x0003FFFF -#define EFUSE_SPI_PAD_CONF_2_M ((EFUSE_SPI_PAD_CONF_2_V)<<(EFUSE_SPI_PAD_CONF_2_S)) -#define EFUSE_SPI_PAD_CONF_2_V 0x3FFFF -#define EFUSE_SPI_PAD_CONF_2_S 0 - -#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) -/* EFUSE_SYS_DATA_PART0_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fist 32 bits of the zeroth part of system data..*/ -#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_1_M ((EFUSE_SYS_DATA_PART0_1_V)<<(EFUSE_SYS_DATA_PART0_1_S)) -#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_1_S 0 - -#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58) -/* EFUSE_SYS_DATA_PART0_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of the zeroth part of system data..*/ -#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_2_M ((EFUSE_SYS_DATA_PART0_2_V)<<(EFUSE_SYS_DATA_PART0_2_S)) -#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_2_S 0 - -#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5C) -/* EFUSE_SYS_DATA_PART1_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of the first part of system data..*/ -#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_0_M ((EFUSE_SYS_DATA_PART1_0_V)<<(EFUSE_SYS_DATA_PART1_0_S)) -#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_0_S 0 - -#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60) -/* EFUSE_SYS_DATA_PART1_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of the first part of system data..*/ -#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_1_M ((EFUSE_SYS_DATA_PART1_1_V)<<(EFUSE_SYS_DATA_PART1_1_S)) -#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_1_S 0 - -#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64) -/* EFUSE_SYS_DATA_PART1_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of the first part of system data..*/ -#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_2_M ((EFUSE_SYS_DATA_PART1_2_V)<<(EFUSE_SYS_DATA_PART1_2_S)) -#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_2_S 0 - -#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68) -/* EFUSE_SYS_DATA_PART1_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of the first part of system data..*/ -#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_3_M ((EFUSE_SYS_DATA_PART1_3_V)<<(EFUSE_SYS_DATA_PART1_3_S)) -#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_3_S 0 - -#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6C) -/* EFUSE_SYS_DATA_PART1_4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of the first part of system data..*/ -#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_4_M ((EFUSE_SYS_DATA_PART1_4_V)<<(EFUSE_SYS_DATA_PART1_4_S)) -#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_4_S 0 - -#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70) -/* EFUSE_SYS_DATA_PART1_5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of the first part of system data..*/ -#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_5_M ((EFUSE_SYS_DATA_PART1_5_V)<<(EFUSE_SYS_DATA_PART1_5_S)) -#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_5_S 0 - -#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74) -/* EFUSE_SYS_DATA_PART1_6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of the first part of system data..*/ -#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_6_M ((EFUSE_SYS_DATA_PART1_6_V)<<(EFUSE_SYS_DATA_PART1_6_S)) -#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_6_S 0 - -#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78) -/* EFUSE_SYS_DATA_PART1_7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of the first part of system data..*/ -#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_7_M ((EFUSE_SYS_DATA_PART1_7_V)<<(EFUSE_SYS_DATA_PART1_7_S)) -#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_7_S 0 - -#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7C) -/* EFUSE_USR_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of BLOCK3 (user)..*/ -#define EFUSE_USR_DATA0 0xFFFFFFFF -#define EFUSE_USR_DATA0_M ((EFUSE_USR_DATA0_V)<<(EFUSE_USR_DATA0_S)) -#define EFUSE_USR_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA0_REG register + * Register 0 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c) +/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA0 0xFFFFFFFFU +#define EFUSE_USR_DATA0_M (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S) +#define EFUSE_USR_DATA0_V 0xFFFFFFFFU #define EFUSE_USR_DATA0_S 0 -#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) -/* EFUSE_USR_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of BLOCK3 (user)..*/ -#define EFUSE_USR_DATA1 0xFFFFFFFF -#define EFUSE_USR_DATA1_M ((EFUSE_USR_DATA1_V)<<(EFUSE_USR_DATA1_S)) -#define EFUSE_USR_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA1_REG register + * Register 1 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) +/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA1 0xFFFFFFFFU +#define EFUSE_USR_DATA1_M (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S) +#define EFUSE_USR_DATA1_V 0xFFFFFFFFU #define EFUSE_USR_DATA1_S 0 -#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) -/* EFUSE_USR_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of BLOCK3 (user)..*/ -#define EFUSE_USR_DATA2 0xFFFFFFFF -#define EFUSE_USR_DATA2_M ((EFUSE_USR_DATA2_V)<<(EFUSE_USR_DATA2_S)) -#define EFUSE_USR_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA2_REG register + * Register 2 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) +/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA2 0xFFFFFFFFU +#define EFUSE_USR_DATA2_M (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S) +#define EFUSE_USR_DATA2_V 0xFFFFFFFFU #define EFUSE_USR_DATA2_S 0 -#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) -/* EFUSE_USR_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of BLOCK3 (user)..*/ -#define EFUSE_USR_DATA3 0xFFFFFFFF -#define EFUSE_USR_DATA3_M ((EFUSE_USR_DATA3_V)<<(EFUSE_USR_DATA3_S)) -#define EFUSE_USR_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA3_REG register + * Register 3 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) +/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA3 0xFFFFFFFFU +#define EFUSE_USR_DATA3_M (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S) +#define EFUSE_USR_DATA3_V 0xFFFFFFFFU #define EFUSE_USR_DATA3_S 0 -#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8C) -/* EFUSE_USR_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of BLOCK3 (user)..*/ -#define EFUSE_USR_DATA4 0xFFFFFFFF -#define EFUSE_USR_DATA4_M ((EFUSE_USR_DATA4_V)<<(EFUSE_USR_DATA4_S)) -#define EFUSE_USR_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA4_REG register + * Register 4 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c) +/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA4 0xFFFFFFFFU +#define EFUSE_USR_DATA4_M (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S) +#define EFUSE_USR_DATA4_V 0xFFFFFFFFU #define EFUSE_USR_DATA4_S 0 -#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) -/* EFUSE_USR_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of BLOCK3 (user)..*/ -#define EFUSE_USR_DATA5 0xFFFFFFFF -#define EFUSE_USR_DATA5_M ((EFUSE_USR_DATA5_V)<<(EFUSE_USR_DATA5_S)) -#define EFUSE_USR_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA5_REG register + * Register 5 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) +/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA5 0xFFFFFFFFU +#define EFUSE_USR_DATA5_M (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S) +#define EFUSE_USR_DATA5_V 0xFFFFFFFFU #define EFUSE_USR_DATA5_S 0 -#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) -/* EFUSE_USR_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of BLOCK3 (user)..*/ -#define EFUSE_USR_DATA6 0xFFFFFFFF -#define EFUSE_USR_DATA6_M ((EFUSE_USR_DATA6_V)<<(EFUSE_USR_DATA6_S)) -#define EFUSE_USR_DATA6_V 0xFFFFFFFF -#define EFUSE_USR_DATA6_S 0 - -#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) -/* EFUSE_USR_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of BLOCK3 (user)..*/ -#define EFUSE_USR_DATA7 0xFFFFFFFF -#define EFUSE_USR_DATA7_M ((EFUSE_USR_DATA7_V)<<(EFUSE_USR_DATA7_S)) -#define EFUSE_USR_DATA7_V 0xFFFFFFFF -#define EFUSE_USR_DATA7_S 0 - -#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9C) -/* EFUSE_KEY0_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY0..*/ -#define EFUSE_KEY0_DATA0 0xFFFFFFFF -#define EFUSE_KEY0_DATA0_M ((EFUSE_KEY0_DATA0_V)<<(EFUSE_KEY0_DATA0_S)) -#define EFUSE_KEY0_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA6_REG register + * Register 6 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) +/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_3_192 0x000000FFU +#define EFUSE_RESERVED_3_192_M (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S) +#define EFUSE_RESERVED_3_192_V 0x000000FFU +#define EFUSE_RESERVED_3_192_S 0 +/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0; + * Custom MAC + */ +#define EFUSE_CUSTOM_MAC 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_M (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S) +#define EFUSE_CUSTOM_MAC_V 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_S 8 + +/** EFUSE_RD_USR_DATA7_REG register + * Register 7 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) +/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0; + * Custom MAC + */ +#define EFUSE_CUSTOM_MAC_1 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_1_M (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S) +#define EFUSE_CUSTOM_MAC_1_V 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_1_S 0 +/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_3_248 0x000000FFU +#define EFUSE_RESERVED_3_248_M (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S) +#define EFUSE_RESERVED_3_248_V 0x000000FFU +#define EFUSE_RESERVED_3_248_S 24 + +/** EFUSE_RD_KEY0_DATA0_REG register + * Register 0 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c) +/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA0 0xFFFFFFFFU +#define EFUSE_KEY0_DATA0_M (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S) +#define EFUSE_KEY0_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA0_S 0 -#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xA0) -/* EFUSE_KEY0_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY0..*/ -#define EFUSE_KEY0_DATA1 0xFFFFFFFF -#define EFUSE_KEY0_DATA1_M ((EFUSE_KEY0_DATA1_V)<<(EFUSE_KEY0_DATA1_S)) -#define EFUSE_KEY0_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA1_REG register + * Register 1 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0) +/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA1 0xFFFFFFFFU +#define EFUSE_KEY0_DATA1_M (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S) +#define EFUSE_KEY0_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA1_S 0 -#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xA4) -/* EFUSE_KEY0_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY0..*/ -#define EFUSE_KEY0_DATA2 0xFFFFFFFF -#define EFUSE_KEY0_DATA2_M ((EFUSE_KEY0_DATA2_V)<<(EFUSE_KEY0_DATA2_S)) -#define EFUSE_KEY0_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA2_REG register + * Register 2 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4) +/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA2 0xFFFFFFFFU +#define EFUSE_KEY0_DATA2_M (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S) +#define EFUSE_KEY0_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA2_S 0 -#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xA8) -/* EFUSE_KEY0_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY0..*/ -#define EFUSE_KEY0_DATA3 0xFFFFFFFF -#define EFUSE_KEY0_DATA3_M ((EFUSE_KEY0_DATA3_V)<<(EFUSE_KEY0_DATA3_S)) -#define EFUSE_KEY0_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA3_REG register + * Register 3 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8) +/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA3 0xFFFFFFFFU +#define EFUSE_KEY0_DATA3_M (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S) +#define EFUSE_KEY0_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA3_S 0 -#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xAC) -/* EFUSE_KEY0_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY0..*/ -#define EFUSE_KEY0_DATA4 0xFFFFFFFF -#define EFUSE_KEY0_DATA4_M ((EFUSE_KEY0_DATA4_V)<<(EFUSE_KEY0_DATA4_S)) -#define EFUSE_KEY0_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA4_REG register + * Register 4 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac) +/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA4 0xFFFFFFFFU +#define EFUSE_KEY0_DATA4_M (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S) +#define EFUSE_KEY0_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA4_S 0 -#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xB0) -/* EFUSE_KEY0_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY0..*/ -#define EFUSE_KEY0_DATA5 0xFFFFFFFF -#define EFUSE_KEY0_DATA5_M ((EFUSE_KEY0_DATA5_V)<<(EFUSE_KEY0_DATA5_S)) -#define EFUSE_KEY0_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA5_REG register + * Register 5 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0) +/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA5 0xFFFFFFFFU +#define EFUSE_KEY0_DATA5_M (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S) +#define EFUSE_KEY0_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA5_S 0 -#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xB4) -/* EFUSE_KEY0_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY0..*/ -#define EFUSE_KEY0_DATA6 0xFFFFFFFF -#define EFUSE_KEY0_DATA6_M ((EFUSE_KEY0_DATA6_V)<<(EFUSE_KEY0_DATA6_S)) -#define EFUSE_KEY0_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA6_REG register + * Register 6 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4) +/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA6 0xFFFFFFFFU +#define EFUSE_KEY0_DATA6_M (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S) +#define EFUSE_KEY0_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA6_S 0 -#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xB8) -/* EFUSE_KEY0_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY0..*/ -#define EFUSE_KEY0_DATA7 0xFFFFFFFF -#define EFUSE_KEY0_DATA7_M ((EFUSE_KEY0_DATA7_V)<<(EFUSE_KEY0_DATA7_S)) -#define EFUSE_KEY0_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA7_REG register + * Register 7 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8) +/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA7 0xFFFFFFFFU +#define EFUSE_KEY0_DATA7_M (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S) +#define EFUSE_KEY0_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA7_S 0 -#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xBC) -/* EFUSE_KEY1_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY1..*/ -#define EFUSE_KEY1_DATA0 0xFFFFFFFF -#define EFUSE_KEY1_DATA0_M ((EFUSE_KEY1_DATA0_V)<<(EFUSE_KEY1_DATA0_S)) -#define EFUSE_KEY1_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA0_REG register + * Register 0 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc) +/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA0 0xFFFFFFFFU +#define EFUSE_KEY1_DATA0_M (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S) +#define EFUSE_KEY1_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA0_S 0 -#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xC0) -/* EFUSE_KEY1_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY1..*/ -#define EFUSE_KEY1_DATA1 0xFFFFFFFF -#define EFUSE_KEY1_DATA1_M ((EFUSE_KEY1_DATA1_V)<<(EFUSE_KEY1_DATA1_S)) -#define EFUSE_KEY1_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA1_REG register + * Register 1 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0) +/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA1 0xFFFFFFFFU +#define EFUSE_KEY1_DATA1_M (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S) +#define EFUSE_KEY1_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA1_S 0 -#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xC4) -/* EFUSE_KEY1_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY1..*/ -#define EFUSE_KEY1_DATA2 0xFFFFFFFF -#define EFUSE_KEY1_DATA2_M ((EFUSE_KEY1_DATA2_V)<<(EFUSE_KEY1_DATA2_S)) -#define EFUSE_KEY1_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA2_REG register + * Register 2 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4) +/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA2 0xFFFFFFFFU +#define EFUSE_KEY1_DATA2_M (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S) +#define EFUSE_KEY1_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA2_S 0 -#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xC8) -/* EFUSE_KEY1_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY1..*/ -#define EFUSE_KEY1_DATA3 0xFFFFFFFF -#define EFUSE_KEY1_DATA3_M ((EFUSE_KEY1_DATA3_V)<<(EFUSE_KEY1_DATA3_S)) -#define EFUSE_KEY1_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA3_REG register + * Register 3 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8) +/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA3 0xFFFFFFFFU +#define EFUSE_KEY1_DATA3_M (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S) +#define EFUSE_KEY1_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA3_S 0 -#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xCC) -/* EFUSE_KEY1_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY1..*/ -#define EFUSE_KEY1_DATA4 0xFFFFFFFF -#define EFUSE_KEY1_DATA4_M ((EFUSE_KEY1_DATA4_V)<<(EFUSE_KEY1_DATA4_S)) -#define EFUSE_KEY1_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA4_REG register + * Register 4 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc) +/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA4 0xFFFFFFFFU +#define EFUSE_KEY1_DATA4_M (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S) +#define EFUSE_KEY1_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA4_S 0 -#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xD0) -/* EFUSE_KEY1_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY1..*/ -#define EFUSE_KEY1_DATA5 0xFFFFFFFF -#define EFUSE_KEY1_DATA5_M ((EFUSE_KEY1_DATA5_V)<<(EFUSE_KEY1_DATA5_S)) -#define EFUSE_KEY1_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA5_REG register + * Register 5 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0) +/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA5 0xFFFFFFFFU +#define EFUSE_KEY1_DATA5_M (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S) +#define EFUSE_KEY1_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA5_S 0 -#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xD4) -/* EFUSE_KEY1_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY1..*/ -#define EFUSE_KEY1_DATA6 0xFFFFFFFF -#define EFUSE_KEY1_DATA6_M ((EFUSE_KEY1_DATA6_V)<<(EFUSE_KEY1_DATA6_S)) -#define EFUSE_KEY1_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA6_REG register + * Register 6 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4) +/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA6 0xFFFFFFFFU +#define EFUSE_KEY1_DATA6_M (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S) +#define EFUSE_KEY1_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA6_S 0 -#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xD8) -/* EFUSE_KEY1_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY1..*/ -#define EFUSE_KEY1_DATA7 0xFFFFFFFF -#define EFUSE_KEY1_DATA7_M ((EFUSE_KEY1_DATA7_V)<<(EFUSE_KEY1_DATA7_S)) -#define EFUSE_KEY1_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA7_REG register + * Register 7 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8) +/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA7 0xFFFFFFFFU +#define EFUSE_KEY1_DATA7_M (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S) +#define EFUSE_KEY1_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA7_S 0 -#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xDC) -/* EFUSE_KEY2_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY2..*/ -#define EFUSE_KEY2_DATA0 0xFFFFFFFF -#define EFUSE_KEY2_DATA0_M ((EFUSE_KEY2_DATA0_V)<<(EFUSE_KEY2_DATA0_S)) -#define EFUSE_KEY2_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA0_REG register + * Register 0 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc) +/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA0 0xFFFFFFFFU +#define EFUSE_KEY2_DATA0_M (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S) +#define EFUSE_KEY2_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA0_S 0 -#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xE0) -/* EFUSE_KEY2_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY2..*/ -#define EFUSE_KEY2_DATA1 0xFFFFFFFF -#define EFUSE_KEY2_DATA1_M ((EFUSE_KEY2_DATA1_V)<<(EFUSE_KEY2_DATA1_S)) -#define EFUSE_KEY2_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA1_REG register + * Register 1 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0) +/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA1 0xFFFFFFFFU +#define EFUSE_KEY2_DATA1_M (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S) +#define EFUSE_KEY2_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA1_S 0 -#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xE4) -/* EFUSE_KEY2_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY2..*/ -#define EFUSE_KEY2_DATA2 0xFFFFFFFF -#define EFUSE_KEY2_DATA2_M ((EFUSE_KEY2_DATA2_V)<<(EFUSE_KEY2_DATA2_S)) -#define EFUSE_KEY2_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA2_REG register + * Register 2 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4) +/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA2 0xFFFFFFFFU +#define EFUSE_KEY2_DATA2_M (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S) +#define EFUSE_KEY2_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA2_S 0 -#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xE8) -/* EFUSE_KEY2_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY2..*/ -#define EFUSE_KEY2_DATA3 0xFFFFFFFF -#define EFUSE_KEY2_DATA3_M ((EFUSE_KEY2_DATA3_V)<<(EFUSE_KEY2_DATA3_S)) -#define EFUSE_KEY2_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA3_REG register + * Register 3 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8) +/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA3 0xFFFFFFFFU +#define EFUSE_KEY2_DATA3_M (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S) +#define EFUSE_KEY2_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA3_S 0 -#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xEC) -/* EFUSE_KEY2_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY2..*/ -#define EFUSE_KEY2_DATA4 0xFFFFFFFF -#define EFUSE_KEY2_DATA4_M ((EFUSE_KEY2_DATA4_V)<<(EFUSE_KEY2_DATA4_S)) -#define EFUSE_KEY2_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA4_REG register + * Register 4 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec) +/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA4 0xFFFFFFFFU +#define EFUSE_KEY2_DATA4_M (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S) +#define EFUSE_KEY2_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA4_S 0 -#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xF0) -/* EFUSE_KEY2_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY2..*/ -#define EFUSE_KEY2_DATA5 0xFFFFFFFF -#define EFUSE_KEY2_DATA5_M ((EFUSE_KEY2_DATA5_V)<<(EFUSE_KEY2_DATA5_S)) -#define EFUSE_KEY2_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA5_REG register + * Register 5 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0) +/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA5 0xFFFFFFFFU +#define EFUSE_KEY2_DATA5_M (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S) +#define EFUSE_KEY2_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA5_S 0 -#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xF4) -/* EFUSE_KEY2_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY2..*/ -#define EFUSE_KEY2_DATA6 0xFFFFFFFF -#define EFUSE_KEY2_DATA6_M ((EFUSE_KEY2_DATA6_V)<<(EFUSE_KEY2_DATA6_S)) -#define EFUSE_KEY2_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA6_REG register + * Register 6 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4) +/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA6 0xFFFFFFFFU +#define EFUSE_KEY2_DATA6_M (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S) +#define EFUSE_KEY2_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA6_S 0 -#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xF8) -/* EFUSE_KEY2_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY2..*/ -#define EFUSE_KEY2_DATA7 0xFFFFFFFF -#define EFUSE_KEY2_DATA7_M ((EFUSE_KEY2_DATA7_V)<<(EFUSE_KEY2_DATA7_S)) -#define EFUSE_KEY2_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA7_REG register + * Register 7 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8) +/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA7 0xFFFFFFFFU +#define EFUSE_KEY2_DATA7_M (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S) +#define EFUSE_KEY2_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA7_S 0 -#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xFC) -/* EFUSE_KEY3_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY3..*/ -#define EFUSE_KEY3_DATA0 0xFFFFFFFF -#define EFUSE_KEY3_DATA0_M ((EFUSE_KEY3_DATA0_V)<<(EFUSE_KEY3_DATA0_S)) -#define EFUSE_KEY3_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA0_REG register + * Register 0 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc) +/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA0 0xFFFFFFFFU +#define EFUSE_KEY3_DATA0_M (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S) +#define EFUSE_KEY3_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA0_S 0 -#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) -/* EFUSE_KEY3_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY3..*/ -#define EFUSE_KEY3_DATA1 0xFFFFFFFF -#define EFUSE_KEY3_DATA1_M ((EFUSE_KEY3_DATA1_V)<<(EFUSE_KEY3_DATA1_S)) -#define EFUSE_KEY3_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA1_REG register + * Register 1 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) +/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA1 0xFFFFFFFFU +#define EFUSE_KEY3_DATA1_M (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S) +#define EFUSE_KEY3_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA1_S 0 -#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) -/* EFUSE_KEY3_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY3..*/ -#define EFUSE_KEY3_DATA2 0xFFFFFFFF -#define EFUSE_KEY3_DATA2_M ((EFUSE_KEY3_DATA2_V)<<(EFUSE_KEY3_DATA2_S)) -#define EFUSE_KEY3_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA2_REG register + * Register 2 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) +/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA2 0xFFFFFFFFU +#define EFUSE_KEY3_DATA2_M (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S) +#define EFUSE_KEY3_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA2_S 0 -#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) -/* EFUSE_KEY3_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY3..*/ -#define EFUSE_KEY3_DATA3 0xFFFFFFFF -#define EFUSE_KEY3_DATA3_M ((EFUSE_KEY3_DATA3_V)<<(EFUSE_KEY3_DATA3_S)) -#define EFUSE_KEY3_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA3_REG register + * Register 3 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) +/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA3 0xFFFFFFFFU +#define EFUSE_KEY3_DATA3_M (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S) +#define EFUSE_KEY3_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA3_S 0 -#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10C) -/* EFUSE_KEY3_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY3..*/ -#define EFUSE_KEY3_DATA4 0xFFFFFFFF -#define EFUSE_KEY3_DATA4_M ((EFUSE_KEY3_DATA4_V)<<(EFUSE_KEY3_DATA4_S)) -#define EFUSE_KEY3_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA4_REG register + * Register 4 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c) +/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA4 0xFFFFFFFFU +#define EFUSE_KEY3_DATA4_M (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S) +#define EFUSE_KEY3_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA4_S 0 -#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) -/* EFUSE_KEY3_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY3..*/ -#define EFUSE_KEY3_DATA5 0xFFFFFFFF -#define EFUSE_KEY3_DATA5_M ((EFUSE_KEY3_DATA5_V)<<(EFUSE_KEY3_DATA5_S)) -#define EFUSE_KEY3_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA5_REG register + * Register 5 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) +/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA5 0xFFFFFFFFU +#define EFUSE_KEY3_DATA5_M (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S) +#define EFUSE_KEY3_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA5_S 0 -#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) -/* EFUSE_KEY3_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY3..*/ -#define EFUSE_KEY3_DATA6 0xFFFFFFFF -#define EFUSE_KEY3_DATA6_M ((EFUSE_KEY3_DATA6_V)<<(EFUSE_KEY3_DATA6_S)) -#define EFUSE_KEY3_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA6_REG register + * Register 6 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) +/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA6 0xFFFFFFFFU +#define EFUSE_KEY3_DATA6_M (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S) +#define EFUSE_KEY3_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA6_S 0 -#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) -/* EFUSE_KEY3_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY3..*/ -#define EFUSE_KEY3_DATA7 0xFFFFFFFF -#define EFUSE_KEY3_DATA7_M ((EFUSE_KEY3_DATA7_V)<<(EFUSE_KEY3_DATA7_S)) -#define EFUSE_KEY3_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA7_REG register + * Register 7 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) +/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA7 0xFFFFFFFFU +#define EFUSE_KEY3_DATA7_M (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S) +#define EFUSE_KEY3_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA7_S 0 -#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11C) -/* EFUSE_KEY4_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY4..*/ -#define EFUSE_KEY4_DATA0 0xFFFFFFFF -#define EFUSE_KEY4_DATA0_M ((EFUSE_KEY4_DATA0_V)<<(EFUSE_KEY4_DATA0_S)) -#define EFUSE_KEY4_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA0_REG register + * Register 0 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c) +/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA0 0xFFFFFFFFU +#define EFUSE_KEY4_DATA0_M (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S) +#define EFUSE_KEY4_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA0_S 0 -#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) -/* EFUSE_KEY4_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY4..*/ -#define EFUSE_KEY4_DATA1 0xFFFFFFFF -#define EFUSE_KEY4_DATA1_M ((EFUSE_KEY4_DATA1_V)<<(EFUSE_KEY4_DATA1_S)) -#define EFUSE_KEY4_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA1_REG register + * Register 1 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) +/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA1 0xFFFFFFFFU +#define EFUSE_KEY4_DATA1_M (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S) +#define EFUSE_KEY4_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA1_S 0 -#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) -/* EFUSE_KEY4_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY4..*/ -#define EFUSE_KEY4_DATA2 0xFFFFFFFF -#define EFUSE_KEY4_DATA2_M ((EFUSE_KEY4_DATA2_V)<<(EFUSE_KEY4_DATA2_S)) -#define EFUSE_KEY4_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA2_REG register + * Register 2 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) +/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA2 0xFFFFFFFFU +#define EFUSE_KEY4_DATA2_M (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S) +#define EFUSE_KEY4_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA2_S 0 -#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) -/* EFUSE_KEY4_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY4..*/ -#define EFUSE_KEY4_DATA3 0xFFFFFFFF -#define EFUSE_KEY4_DATA3_M ((EFUSE_KEY4_DATA3_V)<<(EFUSE_KEY4_DATA3_S)) -#define EFUSE_KEY4_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA3_REG register + * Register 3 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) +/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA3 0xFFFFFFFFU +#define EFUSE_KEY4_DATA3_M (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S) +#define EFUSE_KEY4_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA3_S 0 -#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12C) -/* EFUSE_KEY4_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY4..*/ -#define EFUSE_KEY4_DATA4 0xFFFFFFFF -#define EFUSE_KEY4_DATA4_M ((EFUSE_KEY4_DATA4_V)<<(EFUSE_KEY4_DATA4_S)) -#define EFUSE_KEY4_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA4_REG register + * Register 4 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c) +/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA4 0xFFFFFFFFU +#define EFUSE_KEY4_DATA4_M (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S) +#define EFUSE_KEY4_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA4_S 0 -#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) -/* EFUSE_KEY4_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY4..*/ -#define EFUSE_KEY4_DATA5 0xFFFFFFFF -#define EFUSE_KEY4_DATA5_M ((EFUSE_KEY4_DATA5_V)<<(EFUSE_KEY4_DATA5_S)) -#define EFUSE_KEY4_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA5_REG register + * Register 5 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) +/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA5 0xFFFFFFFFU +#define EFUSE_KEY4_DATA5_M (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S) +#define EFUSE_KEY4_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA5_S 0 -#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) -/* EFUSE_KEY4_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY4..*/ -#define EFUSE_KEY4_DATA6 0xFFFFFFFF -#define EFUSE_KEY4_DATA6_M ((EFUSE_KEY4_DATA6_V)<<(EFUSE_KEY4_DATA6_S)) -#define EFUSE_KEY4_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA6_REG register + * Register 6 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) +/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA6 0xFFFFFFFFU +#define EFUSE_KEY4_DATA6_M (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S) +#define EFUSE_KEY4_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA6_S 0 -#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) -/* EFUSE_KEY4_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY4..*/ -#define EFUSE_KEY4_DATA7 0xFFFFFFFF -#define EFUSE_KEY4_DATA7_M ((EFUSE_KEY4_DATA7_V)<<(EFUSE_KEY4_DATA7_S)) -#define EFUSE_KEY4_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA7_REG register + * Register 7 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) +/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA7 0xFFFFFFFFU +#define EFUSE_KEY4_DATA7_M (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S) +#define EFUSE_KEY4_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA7_S 0 -#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13C) -/* EFUSE_KEY5_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY5..*/ -#define EFUSE_KEY5_DATA0 0xFFFFFFFF -#define EFUSE_KEY5_DATA0_M ((EFUSE_KEY5_DATA0_V)<<(EFUSE_KEY5_DATA0_S)) -#define EFUSE_KEY5_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA0_REG register + * Register 0 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c) +/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA0 0xFFFFFFFFU +#define EFUSE_KEY5_DATA0_M (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S) +#define EFUSE_KEY5_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA0_S 0 -#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) -/* EFUSE_KEY5_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY5..*/ -#define EFUSE_KEY5_DATA1 0xFFFFFFFF -#define EFUSE_KEY5_DATA1_M ((EFUSE_KEY5_DATA1_V)<<(EFUSE_KEY5_DATA1_S)) -#define EFUSE_KEY5_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA1_REG register + * Register 1 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) +/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA1 0xFFFFFFFFU +#define EFUSE_KEY5_DATA1_M (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S) +#define EFUSE_KEY5_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA1_S 0 -#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) -/* EFUSE_KEY5_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY5..*/ -#define EFUSE_KEY5_DATA2 0xFFFFFFFF -#define EFUSE_KEY5_DATA2_M ((EFUSE_KEY5_DATA2_V)<<(EFUSE_KEY5_DATA2_S)) -#define EFUSE_KEY5_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA2_REG register + * Register 2 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) +/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA2 0xFFFFFFFFU +#define EFUSE_KEY5_DATA2_M (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S) +#define EFUSE_KEY5_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA2_S 0 -#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) -/* EFUSE_KEY5_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY5..*/ -#define EFUSE_KEY5_DATA3 0xFFFFFFFF -#define EFUSE_KEY5_DATA3_M ((EFUSE_KEY5_DATA3_V)<<(EFUSE_KEY5_DATA3_S)) -#define EFUSE_KEY5_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA3_REG register + * Register 3 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) +/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA3 0xFFFFFFFFU +#define EFUSE_KEY5_DATA3_M (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S) +#define EFUSE_KEY5_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA3_S 0 -#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14C) -/* EFUSE_KEY5_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY5..*/ -#define EFUSE_KEY5_DATA4 0xFFFFFFFF -#define EFUSE_KEY5_DATA4_M ((EFUSE_KEY5_DATA4_V)<<(EFUSE_KEY5_DATA4_S)) -#define EFUSE_KEY5_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA4_REG register + * Register 4 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c) +/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA4 0xFFFFFFFFU +#define EFUSE_KEY5_DATA4_M (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S) +#define EFUSE_KEY5_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA4_S 0 -#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) -/* EFUSE_KEY5_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY5..*/ -#define EFUSE_KEY5_DATA5 0xFFFFFFFF -#define EFUSE_KEY5_DATA5_M ((EFUSE_KEY5_DATA5_V)<<(EFUSE_KEY5_DATA5_S)) -#define EFUSE_KEY5_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA5_REG register + * Register 5 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) +/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA5 0xFFFFFFFFU +#define EFUSE_KEY5_DATA5_M (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S) +#define EFUSE_KEY5_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA5_S 0 -#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) -/* EFUSE_KEY5_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY5..*/ -#define EFUSE_KEY5_DATA6 0xFFFFFFFF -#define EFUSE_KEY5_DATA6_M ((EFUSE_KEY5_DATA6_V)<<(EFUSE_KEY5_DATA6_S)) -#define EFUSE_KEY5_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA6_REG register + * Register 6 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) +/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA6 0xFFFFFFFFU +#define EFUSE_KEY5_DATA6_M (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S) +#define EFUSE_KEY5_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA6_S 0 -#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) -/* EFUSE_KEY5_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY5..*/ -#define EFUSE_KEY5_DATA7 0xFFFFFFFF -#define EFUSE_KEY5_DATA7_M ((EFUSE_KEY5_DATA7_V)<<(EFUSE_KEY5_DATA7_S)) -#define EFUSE_KEY5_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA7_REG register + * Register 7 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) +/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA7 0xFFFFFFFFU +#define EFUSE_KEY5_DATA7_M (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S) +#define EFUSE_KEY5_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA7_S 0 -#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15C) -/* EFUSE_SYS_DATA_PART2_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the 0th 32 bits of the 2nd part of system data..*/ -#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_0_M ((EFUSE_SYS_DATA_PART2_0_V)<<(EFUSE_SYS_DATA_PART2_0_S)) -#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA0_REG register + * Register 0 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c) +/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S) +#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_0_S 0 -#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) -/* EFUSE_SYS_DATA_PART2_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the 1st 32 bits of the 2nd part of system data..*/ -#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_1_M ((EFUSE_SYS_DATA_PART2_1_V)<<(EFUSE_SYS_DATA_PART2_1_S)) -#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA1_REG register + * Register 1 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) +/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1st 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S) +#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_1_S 0 -#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) -/* EFUSE_SYS_DATA_PART2_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the 2nd 32 bits of the 2nd part of system data..*/ -#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_2_M ((EFUSE_SYS_DATA_PART2_2_V)<<(EFUSE_SYS_DATA_PART2_2_S)) -#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA2_REG register + * Register 2 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) +/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2nd 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S) +#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_2_S 0 -#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) -/* EFUSE_SYS_DATA_PART2_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the 3rd 32 bits of the 2nd part of system data..*/ -#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_3_M ((EFUSE_SYS_DATA_PART2_3_V)<<(EFUSE_SYS_DATA_PART2_3_S)) -#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA3_REG register + * Register 3 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) +/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3rd 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S) +#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_3_S 0 -#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16C) -/* EFUSE_SYS_DATA_PART2_4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the 4th 32 bits of the 2nd part of system data..*/ -#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_4_M ((EFUSE_SYS_DATA_PART2_4_V)<<(EFUSE_SYS_DATA_PART2_4_S)) -#define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA4_REG register + * Register 4 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c) +/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_4_M (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S) +#define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_4_S 0 -#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) -/* EFUSE_SYS_DATA_PART2_5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the 5th 32 bits of the 2nd part of system data..*/ -#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_5_M ((EFUSE_SYS_DATA_PART2_5_V)<<(EFUSE_SYS_DATA_PART2_5_S)) -#define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA5_REG register + * Register 5 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) +/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_5_M (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S) +#define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_5_S 0 -#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) -/* EFUSE_SYS_DATA_PART2_6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the 6th 32 bits of the 2nd part of system data..*/ -#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_6_M ((EFUSE_SYS_DATA_PART2_6_V)<<(EFUSE_SYS_DATA_PART2_6_S)) -#define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA6_REG register + * Register 6 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) +/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_6_M (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S) +#define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_6_S 0 -#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) -/* EFUSE_SYS_DATA_PART2_7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the 7th 32 bits of the 2nd part of system data..*/ -#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_7_M ((EFUSE_SYS_DATA_PART2_7_V)<<(EFUSE_SYS_DATA_PART2_7_S)) -#define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA7_REG register + * Register 7 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) +/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_7_M (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S) +#define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_7_S 0 -#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17C) -/* EFUSE_VDD_SPI_DREFH_ERR : RO ;bitpos:[31:30] ;default: 2'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_VDD_SPI_DREFH_ERR 0x00000003 -#define EFUSE_VDD_SPI_DREFH_ERR_M ((EFUSE_VDD_SPI_DREFH_ERR_V)<<(EFUSE_VDD_SPI_DREFH_ERR_S)) -#define EFUSE_VDD_SPI_DREFH_ERR_V 0x3 -#define EFUSE_VDD_SPI_DREFH_ERR_S 30 -/* EFUSE_VDD_SPI_MODECURLIM_ERR : RO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_VDD_SPI_MODECURLIM_ERR (BIT(29)) -#define EFUSE_VDD_SPI_MODECURLIM_ERR_M (BIT(29)) -#define EFUSE_VDD_SPI_MODECURLIM_ERR_V 0x1 -#define EFUSE_VDD_SPI_MODECURLIM_ERR_S 29 -/* EFUSE_BTLC_GPIO_ENABLE_ERR : RO ;bitpos:[28:27] ;default: 2'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_BTLC_GPIO_ENABLE_ERR 0x00000003 -#define EFUSE_BTLC_GPIO_ENABLE_ERR_M ((EFUSE_BTLC_GPIO_ENABLE_ERR_V)<<(EFUSE_BTLC_GPIO_ENABLE_ERR_S)) -#define EFUSE_BTLC_GPIO_ENABLE_ERR_V 0x3 -#define EFUSE_BTLC_GPIO_ENABLE_ERR_S 27 -/* EFUSE_EXT_PHY_ENABLE_ERR : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_EXT_PHY_ENABLE_ERR (BIT(26)) -#define EFUSE_EXT_PHY_ENABLE_ERR_M (BIT(26)) -#define EFUSE_EXT_PHY_ENABLE_ERR_V 0x1 -#define EFUSE_EXT_PHY_ENABLE_ERR_S 26 -/* EFUSE_USB_EXCHG_PINS_ERR : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_USB_EXCHG_PINS_ERR (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_ERR_M (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_ERR_V 0x1 -#define EFUSE_USB_EXCHG_PINS_ERR_S 25 -/* EFUSE_USB_DREFL_ERR : RO ;bitpos:[24:23] ;default: 2'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_USB_DREFL_ERR 0x00000003 -#define EFUSE_USB_DREFL_ERR_M ((EFUSE_USB_DREFL_ERR_V)<<(EFUSE_USB_DREFL_ERR_S)) -#define EFUSE_USB_DREFL_ERR_V 0x3 -#define EFUSE_USB_DREFL_ERR_S 23 -/* EFUSE_USB_DREFH_ERR : RO ;bitpos:[22:21] ;default: 2'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_USB_DREFH_ERR 0x00000003 -#define EFUSE_USB_DREFH_ERR_M ((EFUSE_USB_DREFH_ERR_V)<<(EFUSE_USB_DREFH_ERR_S)) -#define EFUSE_USB_DREFH_ERR_V 0x3 -#define EFUSE_USB_DREFH_ERR_S 21 -/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20 -/* EFUSE_DIS_PAD_JTAG_ERR : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_DIS_PAD_JTAG_ERR (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_ERR_M (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_ERR_V 0x1 -#define EFUSE_DIS_PAD_JTAG_ERR_S 19 -/* EFUSE_SOFT_DIS_JTAG_ERR : RO ;bitpos:[18:16] ;default: 3'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_SOFT_DIS_JTAG_ERR 0x00000007 -#define EFUSE_SOFT_DIS_JTAG_ERR_M ((EFUSE_SOFT_DIS_JTAG_ERR_V)<<(EFUSE_SOFT_DIS_JTAG_ERR_S)) -#define EFUSE_SOFT_DIS_JTAG_ERR_V 0x7 -#define EFUSE_SOFT_DIS_JTAG_ERR_S 16 -/* EFUSE_DIS_APP_CPU_ERR : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_DIS_APP_CPU_ERR (BIT(15)) -#define EFUSE_DIS_APP_CPU_ERR_M (BIT(15)) -#define EFUSE_DIS_APP_CPU_ERR_V 0x1 -#define EFUSE_DIS_APP_CPU_ERR_S 15 -/* EFUSE_DIS_CAN_ERR : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_DIS_CAN_ERR (BIT(14)) -#define EFUSE_DIS_CAN_ERR_M (BIT(14)) -#define EFUSE_DIS_CAN_ERR_V 0x1 -#define EFUSE_DIS_CAN_ERR_S 14 -/* EFUSE_DIS_USB_ERR : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_DIS_USB_ERR (BIT(13)) -#define EFUSE_DIS_USB_ERR_M (BIT(13)) -#define EFUSE_DIS_USB_ERR_V 0x1 -#define EFUSE_DIS_USB_ERR_S 13 -/* EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x1 -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 -/* EFUSE_DIS_DOWNLOAD_DCACHE_ERR : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR (BIT(11)) -#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_M (BIT(11)) -#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V 0x1 -#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S 11 -/* EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V 0x1 -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S 10 -/* EFUSE_DIS_DCACHE_ERR : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_DIS_DCACHE_ERR (BIT(9)) -#define EFUSE_DIS_DCACHE_ERR_M (BIT(9)) -#define EFUSE_DIS_DCACHE_ERR_V 0x1 -#define EFUSE_DIS_DCACHE_ERR_S 9 -/* EFUSE_DIS_ICACHE_ERR : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +/** EFUSE_RD_REPEAT_ERR0_REG register + * Programming error record register 0 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) +/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_RD_DIS_ERR 0x0000007FU +#define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S) +#define EFUSE_RD_DIS_ERR_V 0x0000007FU +#define EFUSE_RD_DIS_ERR_S 0 +/** EFUSE_DIS_RTC_RAM_BOOT_ERR : RO; bitpos: [7]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_DIS_RTC_RAM_BOOT_ERR (BIT(7)) +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_M (EFUSE_DIS_RTC_RAM_BOOT_ERR_V << EFUSE_DIS_RTC_RAM_BOOT_ERR_S) +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_V 0x00000001U +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_S 7 +/** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ #define EFUSE_DIS_ICACHE_ERR (BIT(8)) -#define EFUSE_DIS_ICACHE_ERR_M (BIT(8)) -#define EFUSE_DIS_ICACHE_ERR_V 0x1 +#define EFUSE_DIS_ICACHE_ERR_M (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S) +#define EFUSE_DIS_ICACHE_ERR_V 0x00000001U #define EFUSE_DIS_ICACHE_ERR_S 8 -/* EFUSE_RPT4_RESERVED5_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Reserved*/ -#define EFUSE_RPT4_RESERVED5_ERR (BIT(7)) -#define EFUSE_RPT4_RESERVED5_ERR_M (BIT(7)) -#define EFUSE_RPT4_RESERVED5_ERR_V 0x1 -#define EFUSE_RPT4_RESERVED5_ERR_S 7 -/* EFUSE_RD_DIS_ERR : RO ;bitpos:[6:0] ;default: 7'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_RD_DIS_ERR 0x0000007F -#define EFUSE_RD_DIS_ERR_M ((EFUSE_RD_DIS_ERR_V)<<(EFUSE_RD_DIS_ERR_S)) -#define EFUSE_RD_DIS_ERR_V 0x7F -#define EFUSE_RD_DIS_ERR_S 0 +/** EFUSE_DIS_DCACHE_ERR : RO; bitpos: [9]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_DIS_DCACHE_ERR (BIT(9)) +#define EFUSE_DIS_DCACHE_ERR_M (EFUSE_DIS_DCACHE_ERR_V << EFUSE_DIS_DCACHE_ERR_S) +#define EFUSE_DIS_DCACHE_ERR_V 0x00000001U +#define EFUSE_DIS_DCACHE_ERR_S 9 +/** EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO; bitpos: [10]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR (BIT(10)) +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M (EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V << EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S 10 +/** EFUSE_DIS_DOWNLOAD_DCACHE_ERR : RO; bitpos: [11]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR (BIT(11)) +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_M (EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V << EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S 11 +/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x00000001U +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 +/** EFUSE_DIS_USB_ERR : RO; bitpos: [13]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_DIS_USB_ERR (BIT(13)) +#define EFUSE_DIS_USB_ERR_M (EFUSE_DIS_USB_ERR_V << EFUSE_DIS_USB_ERR_S) +#define EFUSE_DIS_USB_ERR_V 0x00000001U +#define EFUSE_DIS_USB_ERR_S 13 +/** EFUSE_DIS_CAN_ERR : RO; bitpos: [14]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_DIS_CAN_ERR (BIT(14)) +#define EFUSE_DIS_CAN_ERR_M (EFUSE_DIS_CAN_ERR_V << EFUSE_DIS_CAN_ERR_S) +#define EFUSE_DIS_CAN_ERR_V 0x00000001U +#define EFUSE_DIS_CAN_ERR_S 14 +/** EFUSE_DIS_APP_CPU_ERR : RO; bitpos: [15]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_DIS_APP_CPU_ERR (BIT(15)) +#define EFUSE_DIS_APP_CPU_ERR_M (EFUSE_DIS_APP_CPU_ERR_V << EFUSE_DIS_APP_CPU_ERR_S) +#define EFUSE_DIS_APP_CPU_ERR_V 0x00000001U +#define EFUSE_DIS_APP_CPU_ERR_S 15 +/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_SOFT_DIS_JTAG_ERR 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_ERR_M (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S) +#define EFUSE_SOFT_DIS_JTAG_ERR_V 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_ERR_S 16 +/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_DIS_PAD_JTAG_ERR (BIT(19)) +#define EFUSE_DIS_PAD_JTAG_ERR_M (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S) +#define EFUSE_DIS_PAD_JTAG_ERR_V 0x00000001U +#define EFUSE_DIS_PAD_JTAG_ERR_S 19 +/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(20)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20 +/** EFUSE_USB_DREFH_ERR : RO; bitpos: [22:21]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_USB_DREFH_ERR 0x00000003U +#define EFUSE_USB_DREFH_ERR_M (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S) +#define EFUSE_USB_DREFH_ERR_V 0x00000003U +#define EFUSE_USB_DREFH_ERR_S 21 +/** EFUSE_USB_DREFL_ERR : RO; bitpos: [24:23]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_USB_DREFL_ERR 0x00000003U +#define EFUSE_USB_DREFL_ERR_M (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S) +#define EFUSE_USB_DREFL_ERR_V 0x00000003U +#define EFUSE_USB_DREFL_ERR_S 23 +/** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [25]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_USB_EXCHG_PINS_ERR (BIT(25)) +#define EFUSE_USB_EXCHG_PINS_ERR_M (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S) +#define EFUSE_USB_EXCHG_PINS_ERR_V 0x00000001U +#define EFUSE_USB_EXCHG_PINS_ERR_S 25 +/** EFUSE_EXT_PHY_ENABLE_ERR : RO; bitpos: [26]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_EXT_PHY_ENABLE_ERR (BIT(26)) +#define EFUSE_EXT_PHY_ENABLE_ERR_M (EFUSE_EXT_PHY_ENABLE_ERR_V << EFUSE_EXT_PHY_ENABLE_ERR_S) +#define EFUSE_EXT_PHY_ENABLE_ERR_V 0x00000001U +#define EFUSE_EXT_PHY_ENABLE_ERR_S 26 +/** EFUSE_BTLC_GPIO_ENABLE_ERR : RO; bitpos: [28:27]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_BTLC_GPIO_ENABLE_ERR 0x00000003U +#define EFUSE_BTLC_GPIO_ENABLE_ERR_M (EFUSE_BTLC_GPIO_ENABLE_ERR_V << EFUSE_BTLC_GPIO_ENABLE_ERR_S) +#define EFUSE_BTLC_GPIO_ENABLE_ERR_V 0x00000003U +#define EFUSE_BTLC_GPIO_ENABLE_ERR_S 27 +/** EFUSE_VDD_SPI_MODECURLIM_ERR : RO; bitpos: [29]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_VDD_SPI_MODECURLIM_ERR (BIT(29)) +#define EFUSE_VDD_SPI_MODECURLIM_ERR_M (EFUSE_VDD_SPI_MODECURLIM_ERR_V << EFUSE_VDD_SPI_MODECURLIM_ERR_S) +#define EFUSE_VDD_SPI_MODECURLIM_ERR_V 0x00000001U +#define EFUSE_VDD_SPI_MODECURLIM_ERR_S 29 +/** EFUSE_VDD_SPI_DREFH_ERR : RO; bitpos: [31:30]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_VDD_SPI_DREFH_ERR 0x00000003U +#define EFUSE_VDD_SPI_DREFH_ERR_M (EFUSE_VDD_SPI_DREFH_ERR_V << EFUSE_VDD_SPI_DREFH_ERR_S) +#define EFUSE_VDD_SPI_DREFH_ERR_V 0x00000003U +#define EFUSE_VDD_SPI_DREFH_ERR_S 30 -#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) -/* EFUSE_KEY_PURPOSE_1_ERR : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_1_ERR_M ((EFUSE_KEY_PURPOSE_1_ERR_V)<<(EFUSE_KEY_PURPOSE_1_ERR_S)) -#define EFUSE_KEY_PURPOSE_1_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_1_ERR_S 28 -/* EFUSE_KEY_PURPOSE_0_ERR : RO ;bitpos:[27:24] ;default: 4'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_0_ERR_M ((EFUSE_KEY_PURPOSE_0_ERR_V)<<(EFUSE_KEY_PURPOSE_0_ERR_S)) -#define EFUSE_KEY_PURPOSE_0_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_0_ERR_S 24 -/* EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 -/* EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 -/* EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 -/* EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M ((EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)) -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x7 -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 -/* EFUSE_WDT_DELAY_SEL_ERR : RO ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003 -#define EFUSE_WDT_DELAY_SEL_ERR_M ((EFUSE_WDT_DELAY_SEL_ERR_V)<<(EFUSE_WDT_DELAY_SEL_ERR_S)) -#define EFUSE_WDT_DELAY_SEL_ERR_V 0x3 -#define EFUSE_WDT_DELAY_SEL_ERR_S 16 -/* EFUSE_VDD_SPI_DCAP_ERR : RO ;bitpos:[15:14] ;default: 2'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_VDD_SPI_DCAP_ERR 0x00000003 -#define EFUSE_VDD_SPI_DCAP_ERR_M ((EFUSE_VDD_SPI_DCAP_ERR_V)<<(EFUSE_VDD_SPI_DCAP_ERR_S)) -#define EFUSE_VDD_SPI_DCAP_ERR_V 0x3 -#define EFUSE_VDD_SPI_DCAP_ERR_S 14 -/* EFUSE_VDD_SPI_INIT_ERR : RO ;bitpos:[13:12] ;default: 2'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_VDD_SPI_INIT_ERR 0x00000003 -#define EFUSE_VDD_SPI_INIT_ERR_M ((EFUSE_VDD_SPI_INIT_ERR_V)<<(EFUSE_VDD_SPI_INIT_ERR_S)) -#define EFUSE_VDD_SPI_INIT_ERR_V 0x3 -#define EFUSE_VDD_SPI_INIT_ERR_S 12 -/* EFUSE_VDD_SPI_DCURLIM_ERR : RO ;bitpos:[11:9]] ;default: 3'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_VDD_SPI_DCURLIM_ERR 0x00000007 -#define EFUSE_VDD_SPI_DCURLIM_ERR_M ((EFUSE_VDD_SPI_DCURLIM_ERR_V)<<(EFUSE_VDD_SPI_DCURLIM_ERR_S)) -#define EFUSE_VDD_SPI_DCURLIM_ERR_V 0x7 -#define EFUSE_VDD_SPI_DCURLIM_ERR_S 9 -/* EFUSE_VDD_SPI_ENCURLIM_ERR : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_VDD_SPI_ENCURLIM_ERR (BIT(8)) -#define EFUSE_VDD_SPI_ENCURLIM_ERR_M (BIT(8)) -#define EFUSE_VDD_SPI_ENCURLIM_ERR_V 0x1 -#define EFUSE_VDD_SPI_ENCURLIM_ERR_S 8 -/* EFUSE_VDD_SPI_EN_INIT_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_VDD_SPI_EN_INIT_ERR (BIT(7)) -#define EFUSE_VDD_SPI_EN_INIT_ERR_M (BIT(7)) -#define EFUSE_VDD_SPI_EN_INIT_ERR_V 0x1 -#define EFUSE_VDD_SPI_EN_INIT_ERR_S 7 -/* EFUSE_VDD_SPI_FORCE_ERR : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_VDD_SPI_FORCE_ERR (BIT(6)) -#define EFUSE_VDD_SPI_FORCE_ERR_M (BIT(6)) -#define EFUSE_VDD_SPI_FORCE_ERR_V 0x1 -#define EFUSE_VDD_SPI_FORCE_ERR_S 6 -/* EFUSE_VDD_SPI_TIEH_ERR : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_VDD_SPI_TIEH_ERR (BIT(5)) -#define EFUSE_VDD_SPI_TIEH_ERR_M (BIT(5)) -#define EFUSE_VDD_SPI_TIEH_ERR_V 0x1 -#define EFUSE_VDD_SPI_TIEH_ERR_S 5 -/* EFUSE_VDD_SPI_XPD_ERR : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +/** EFUSE_RD_REPEAT_ERR1_REG register + * Programming error record register 1 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) +/** EFUSE_VDD_SPI_DREFM_ERR : RO; bitpos: [1:0]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_VDD_SPI_DREFM_ERR 0x00000003U +#define EFUSE_VDD_SPI_DREFM_ERR_M (EFUSE_VDD_SPI_DREFM_ERR_V << EFUSE_VDD_SPI_DREFM_ERR_S) +#define EFUSE_VDD_SPI_DREFM_ERR_V 0x00000003U +#define EFUSE_VDD_SPI_DREFM_ERR_S 0 +/** EFUSE_VDD_SPI_DREFL_ERR : RO; bitpos: [3:2]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_VDD_SPI_DREFL_ERR 0x00000003U +#define EFUSE_VDD_SPI_DREFL_ERR_M (EFUSE_VDD_SPI_DREFL_ERR_V << EFUSE_VDD_SPI_DREFL_ERR_S) +#define EFUSE_VDD_SPI_DREFL_ERR_V 0x00000003U +#define EFUSE_VDD_SPI_DREFL_ERR_S 2 +/** EFUSE_VDD_SPI_XPD_ERR : RO; bitpos: [4]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ #define EFUSE_VDD_SPI_XPD_ERR (BIT(4)) -#define EFUSE_VDD_SPI_XPD_ERR_M (BIT(4)) -#define EFUSE_VDD_SPI_XPD_ERR_V 0x1 +#define EFUSE_VDD_SPI_XPD_ERR_M (EFUSE_VDD_SPI_XPD_ERR_V << EFUSE_VDD_SPI_XPD_ERR_S) +#define EFUSE_VDD_SPI_XPD_ERR_V 0x00000001U #define EFUSE_VDD_SPI_XPD_ERR_S 4 -/* EFUSE_VDD_SPI_DREFL_ERR : RO ;bitpos:[3:2] ;default: 2'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_VDD_SPI_DREFL_ERR 0x00000003 -#define EFUSE_VDD_SPI_DREFL_ERR_M ((EFUSE_VDD_SPI_DREFL_ERR_V)<<(EFUSE_VDD_SPI_DREFL_ERR_S)) -#define EFUSE_VDD_SPI_DREFL_ERR_V 0x3 -#define EFUSE_VDD_SPI_DREFL_ERR_S 2 -/* EFUSE_VDD_SPI_DREFM_ERR : RO ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_VDD_SPI_DREFM_ERR 0x00000003 -#define EFUSE_VDD_SPI_DREFM_ERR_M ((EFUSE_VDD_SPI_DREFM_ERR_V)<<(EFUSE_VDD_SPI_DREFM_ERR_S)) -#define EFUSE_VDD_SPI_DREFM_ERR_V 0x3 -#define EFUSE_VDD_SPI_DREFM_ERR_S 0 +/** EFUSE_VDD_SPI_TIEH_ERR : RO; bitpos: [5]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_VDD_SPI_TIEH_ERR (BIT(5)) +#define EFUSE_VDD_SPI_TIEH_ERR_M (EFUSE_VDD_SPI_TIEH_ERR_V << EFUSE_VDD_SPI_TIEH_ERR_S) +#define EFUSE_VDD_SPI_TIEH_ERR_V 0x00000001U +#define EFUSE_VDD_SPI_TIEH_ERR_S 5 +/** EFUSE_VDD_SPI_FORCE_ERR : RO; bitpos: [6]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_VDD_SPI_FORCE_ERR (BIT(6)) +#define EFUSE_VDD_SPI_FORCE_ERR_M (EFUSE_VDD_SPI_FORCE_ERR_V << EFUSE_VDD_SPI_FORCE_ERR_S) +#define EFUSE_VDD_SPI_FORCE_ERR_V 0x00000001U +#define EFUSE_VDD_SPI_FORCE_ERR_S 6 +/** EFUSE_VDD_SPI_EN_INIT_ERR : RO; bitpos: [7]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_VDD_SPI_EN_INIT_ERR (BIT(7)) +#define EFUSE_VDD_SPI_EN_INIT_ERR_M (EFUSE_VDD_SPI_EN_INIT_ERR_V << EFUSE_VDD_SPI_EN_INIT_ERR_S) +#define EFUSE_VDD_SPI_EN_INIT_ERR_V 0x00000001U +#define EFUSE_VDD_SPI_EN_INIT_ERR_S 7 +/** EFUSE_VDD_SPI_ENCURLIM_ERR : RO; bitpos: [8]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_VDD_SPI_ENCURLIM_ERR (BIT(8)) +#define EFUSE_VDD_SPI_ENCURLIM_ERR_M (EFUSE_VDD_SPI_ENCURLIM_ERR_V << EFUSE_VDD_SPI_ENCURLIM_ERR_S) +#define EFUSE_VDD_SPI_ENCURLIM_ERR_V 0x00000001U +#define EFUSE_VDD_SPI_ENCURLIM_ERR_S 8 +/** EFUSE_VDD_SPI_DCURLIM_ERR : RO; bitpos: [11:9]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_VDD_SPI_DCURLIM_ERR 0x00000007U +#define EFUSE_VDD_SPI_DCURLIM_ERR_M (EFUSE_VDD_SPI_DCURLIM_ERR_V << EFUSE_VDD_SPI_DCURLIM_ERR_S) +#define EFUSE_VDD_SPI_DCURLIM_ERR_V 0x00000007U +#define EFUSE_VDD_SPI_DCURLIM_ERR_S 9 +/** EFUSE_VDD_SPI_INIT_ERR : RO; bitpos: [13:12]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_VDD_SPI_INIT_ERR 0x00000003U +#define EFUSE_VDD_SPI_INIT_ERR_M (EFUSE_VDD_SPI_INIT_ERR_V << EFUSE_VDD_SPI_INIT_ERR_S) +#define EFUSE_VDD_SPI_INIT_ERR_V 0x00000003U +#define EFUSE_VDD_SPI_INIT_ERR_S 12 +/** EFUSE_VDD_SPI_DCAP_ERR : RO; bitpos: [15:14]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_VDD_SPI_DCAP_ERR 0x00000003U +#define EFUSE_VDD_SPI_DCAP_ERR_M (EFUSE_VDD_SPI_DCAP_ERR_V << EFUSE_VDD_SPI_DCAP_ERR_S) +#define EFUSE_VDD_SPI_DCAP_ERR_V 0x00000003U +#define EFUSE_VDD_SPI_DCAP_ERR_S 14 +/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003U +#define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) +#define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003U +#define EFUSE_WDT_DELAY_SEL_ERR_S 16 +/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 +/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 +/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 +/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 +/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_ERR_M (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S) +#define EFUSE_KEY_PURPOSE_0_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_ERR_S 24 +/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_ERR_M (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S) +#define EFUSE_KEY_PURPOSE_1_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_ERR_S 28 -#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) -/* EFUSE_FLASH_TPUW_ERR : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_FLASH_TPUW_ERR 0x0000000F -#define EFUSE_FLASH_TPUW_ERR_M ((EFUSE_FLASH_TPUW_ERR_V)<<(EFUSE_FLASH_TPUW_ERR_S)) -#define EFUSE_FLASH_TPUW_ERR_V 0xF -#define EFUSE_FLASH_TPUW_ERR_S 28 -/* EFUSE_POWER_GLITCH_DSENSE_ERR : RO ;bitpos:[27:26] ;default: 2'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_POWER_GLITCH_DSENSE_ERR 0x00000003 -#define EFUSE_POWER_GLITCH_DSENSE_ERR_M ((EFUSE_POWER_GLITCH_DSENSE_ERR_V)<<(EFUSE_POWER_GLITCH_DSENSE_ERR_S)) -#define EFUSE_POWER_GLITCH_DSENSE_ERR_V 0x3 -#define EFUSE_POWER_GLITCH_DSENSE_ERR_S 26 -/* EFUSE_USB_PHY_SEL_ERR : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_USB_PHY_SEL_ERR (BIT(25)) -#define EFUSE_USB_PHY_SEL_ERR_M (BIT(25)) -#define EFUSE_USB_PHY_SEL_ERR_V 0x1 -#define EFUSE_USB_PHY_SEL_ERR_S 25 -/* EFUSE_STRAP_JTAG_SEL_ERR : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_STRAP_JTAG_SEL_ERR (BIT(24)) -#define EFUSE_STRAP_JTAG_SEL_ERR_M (BIT(24)) -#define EFUSE_STRAP_JTAG_SEL_ERR_V 0x1 -#define EFUSE_STRAP_JTAG_SEL_ERR_S 24 -/* EFUSE_DIS_USB_DEVICE_ERR : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_DIS_USB_DEVICE_ERR (BIT(23)) -#define EFUSE_DIS_USB_DEVICE_ERR_M (BIT(23)) -#define EFUSE_DIS_USB_DEVICE_ERR_V 0x1 -#define EFUSE_DIS_USB_DEVICE_ERR_S 23 -/* EFUSE_DIS_USB_JTAG_ERR : RO ;bitpos:[22] ;default: 6'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_DIS_USB_JTAG_ERR (BIT(22)) -#define EFUSE_DIS_USB_JTAG_ERR_M (BIT(22)) -#define EFUSE_DIS_USB_JTAG_ERR_V 0x1 -#define EFUSE_DIS_USB_JTAG_ERR_S 22 -/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 -/* EFUSE_SECURE_BOOT_EN_ERR : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +/** EFUSE_RD_REPEAT_ERR2_REG register + * Programming error record register 2 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) +/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_ERR_M (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S) +#define EFUSE_KEY_PURPOSE_2_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_ERR_S 0 +/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_ERR_M (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S) +#define EFUSE_KEY_PURPOSE_3_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_ERR_S 4 +/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_ERR_M (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S) +#define EFUSE_KEY_PURPOSE_4_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_ERR_S 8 +/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_ERR_M (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S) +#define EFUSE_KEY_PURPOSE_5_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_ERR_S 12 +/** EFUSE_RPT4_RESERVED0_ERR : RO; bitpos: [19:16]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_RPT4_RESERVED0_ERR 0x0000000FU +#define EFUSE_RPT4_RESERVED0_ERR_M (EFUSE_RPT4_RESERVED0_ERR_V << EFUSE_RPT4_RESERVED0_ERR_S) +#define EFUSE_RPT4_RESERVED0_ERR_V 0x0000000FU +#define EFUSE_RPT4_RESERVED0_ERR_S 16 +/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ #define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_ERR_M (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_ERR_V 0x1 +#define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S) +#define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001U #define EFUSE_SECURE_BOOT_EN_ERR_S 20 -/* EFUSE_RPT4_RESERVED0_ERR : RO ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_RPT4_RESERVED0_ERR 0x0000000F -#define EFUSE_RPT4_RESERVED0_ERR_M ((EFUSE_RPT4_RESERVED0_ERR_V)<<(EFUSE_RPT4_RESERVED0_ERR_S)) -#define EFUSE_RPT4_RESERVED0_ERR_V 0xF -#define EFUSE_RPT4_RESERVED0_ERR_S 16 -/* EFUSE_KEY_PURPOSE_5_ERR : RO ;bitpos:[15:12] ;default: 4'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_5_ERR_M ((EFUSE_KEY_PURPOSE_5_ERR_V)<<(EFUSE_KEY_PURPOSE_5_ERR_S)) -#define EFUSE_KEY_PURPOSE_5_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_5_ERR_S 12 -/* EFUSE_KEY_PURPOSE_4_ERR : RO ;bitpos:[11:8] ;default: 4'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_4_ERR_M ((EFUSE_KEY_PURPOSE_4_ERR_V)<<(EFUSE_KEY_PURPOSE_4_ERR_S)) -#define EFUSE_KEY_PURPOSE_4_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_4_ERR_S 8 -/* EFUSE_KEY_PURPOSE_3_ERR : RO ;bitpos:[7:4] ;default: 4'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_3_ERR_M ((EFUSE_KEY_PURPOSE_3_ERR_V)<<(EFUSE_KEY_PURPOSE_3_ERR_S)) -#define EFUSE_KEY_PURPOSE_3_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_3_ERR_S 4 -/* EFUSE_KEY_PURPOSE_2_ERR : RO ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_2_ERR_M ((EFUSE_KEY_PURPOSE_2_ERR_V)<<(EFUSE_KEY_PURPOSE_2_ERR_S)) -#define EFUSE_KEY_PURPOSE_2_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_2_ERR_S 0 +/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 +/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [22]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_DIS_USB_JTAG_ERR (BIT(22)) +#define EFUSE_DIS_USB_JTAG_ERR_M (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S) +#define EFUSE_DIS_USB_JTAG_ERR_V 0x00000001U +#define EFUSE_DIS_USB_JTAG_ERR_S 22 +/** EFUSE_DIS_USB_DEVICE_ERR : RO; bitpos: [23]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_DIS_USB_DEVICE_ERR (BIT(23)) +#define EFUSE_DIS_USB_DEVICE_ERR_M (EFUSE_DIS_USB_DEVICE_ERR_V << EFUSE_DIS_USB_DEVICE_ERR_S) +#define EFUSE_DIS_USB_DEVICE_ERR_V 0x00000001U +#define EFUSE_DIS_USB_DEVICE_ERR_S 23 +/** EFUSE_STRAP_JTAG_SEL_ERR : RO; bitpos: [24]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_STRAP_JTAG_SEL_ERR (BIT(24)) +#define EFUSE_STRAP_JTAG_SEL_ERR_M (EFUSE_STRAP_JTAG_SEL_ERR_V << EFUSE_STRAP_JTAG_SEL_ERR_S) +#define EFUSE_STRAP_JTAG_SEL_ERR_V 0x00000001U +#define EFUSE_STRAP_JTAG_SEL_ERR_S 24 +/** EFUSE_USB_PHY_SEL_ERR : RO; bitpos: [25]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_USB_PHY_SEL_ERR (BIT(25)) +#define EFUSE_USB_PHY_SEL_ERR_M (EFUSE_USB_PHY_SEL_ERR_V << EFUSE_USB_PHY_SEL_ERR_S) +#define EFUSE_USB_PHY_SEL_ERR_V 0x00000001U +#define EFUSE_USB_PHY_SEL_ERR_S 25 +/** EFUSE_POWER_GLITCH_DSENSE_ERR : RO; bitpos: [27:26]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_POWER_GLITCH_DSENSE_ERR 0x00000003U +#define EFUSE_POWER_GLITCH_DSENSE_ERR_M (EFUSE_POWER_GLITCH_DSENSE_ERR_V << EFUSE_POWER_GLITCH_DSENSE_ERR_S) +#define EFUSE_POWER_GLITCH_DSENSE_ERR_V 0x00000003U +#define EFUSE_POWER_GLITCH_DSENSE_ERR_S 26 +/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_FLASH_TPUW_ERR 0x0000000FU +#define EFUSE_FLASH_TPUW_ERR_M (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S) +#define EFUSE_FLASH_TPUW_ERR_V 0x0000000FU +#define EFUSE_FLASH_TPUW_ERR_S 28 -#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) -/* EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR : RO ;bitpos:[31] ;default: 1'h0 ; */ -/*description: Set this bit to disable download through USB-OTG.*/ -#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR (BIT(31)) -#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_M (BIT(31)) -#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_V 0x1 -#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_S 31 -/* EFUSE_RPT4_RESERVED1_ERR : RO ;bitpos:[30] ;default: 1'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED1_ERR (BIT(30)) -#define EFUSE_RPT4_RESERVED1_ERR_M (BIT(30)) -#define EFUSE_RPT4_RESERVED1_ERR_V 0x1 -#define EFUSE_RPT4_RESERVED1_ERR_S 30 -/* EFUSE_SECURE_VERSION_ERR : RO ;bitpos:[29:14] ;default: 16'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_SECURE_VERSION_ERR 0x0000FFFF -#define EFUSE_SECURE_VERSION_ERR_M ((EFUSE_SECURE_VERSION_ERR_V)<<(EFUSE_SECURE_VERSION_ERR_S)) -#define EFUSE_SECURE_VERSION_ERR_V 0xFFFF -#define EFUSE_SECURE_VERSION_ERR_S 14 -/* EFUSE_FORCE_SEND_RESUME_ERR : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_ERR_M (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x1 -#define EFUSE_FORCE_SEND_RESUME_ERR_S 13 -/* EFUSE_FLASH_ECC_EN_ERR : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_FLASH_ECC_EN_ERR (BIT(12)) -#define EFUSE_FLASH_ECC_EN_ERR_M (BIT(12)) -#define EFUSE_FLASH_ECC_EN_ERR_V 0x1 -#define EFUSE_FLASH_ECC_EN_ERR_S 12 -/* EFUSE_FLASH_PAGE_SIZE_ERR : RO ;bitpos:[11:10] ;default: 2'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_FLASH_PAGE_SIZE_ERR 0x00000003 -#define EFUSE_FLASH_PAGE_SIZE_ERR_M ((EFUSE_FLASH_PAGE_SIZE_ERR_V)<<(EFUSE_FLASH_PAGE_SIZE_ERR_S)) -#define EFUSE_FLASH_PAGE_SIZE_ERR_V 0x3 -#define EFUSE_FLASH_PAGE_SIZE_ERR_S 10 -/* EFUSE_FLASH_TYPE_ERR : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_FLASH_TYPE_ERR (BIT(9)) -#define EFUSE_FLASH_TYPE_ERR_M (BIT(9)) -#define EFUSE_FLASH_TYPE_ERR_V 0x1 -#define EFUSE_FLASH_TYPE_ERR_S 9 -/* EFUSE_PIN_POWER_SELECTION_ERR : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_PIN_POWER_SELECTION_ERR (BIT(8)) -#define EFUSE_PIN_POWER_SELECTION_ERR_M (BIT(8)) -#define EFUSE_PIN_POWER_SELECTION_ERR_V 0x1 -#define EFUSE_PIN_POWER_SELECTION_ERR_S 8 -/* EFUSE_UART_PRINT_CONTROL_ERR : RO ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_ERR_M ((EFUSE_UART_PRINT_CONTROL_ERR_V)<<(EFUSE_UART_PRINT_CONTROL_ERR_S)) -#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x3 -#define EFUSE_UART_PRINT_CONTROL_ERR_S 6 -/* EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x1 -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 -/* EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V 0x1 -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S 4 -/* EFUSE_FLASH_ECC_MODE_ERR : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_FLASH_ECC_MODE_ERR (BIT(3)) -#define EFUSE_FLASH_ECC_MODE_ERR_M (BIT(3)) -#define EFUSE_FLASH_ECC_MODE_ERR_V 0x1 -#define EFUSE_FLASH_ECC_MODE_ERR_S 3 -/* EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_M (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V 0x1 -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S 2 -/* EFUSE_DIS_DIRECT_BOOT_ERR : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_DIS_DIRECT_BOOT_ERR (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_ERR_M (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_ERR_V 0x1 -#define EFUSE_DIS_DIRECT_BOOT_ERR_S 1 -/* EFUSE_DIS_DOWNLOAD_MODE_ERR : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +/** EFUSE_RD_REPEAT_ERR3_REG register + * Programming error record register 3 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) +/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ #define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x1 +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 +/** EFUSE_DIS_LEGACY_SPI_BOOT_ERR : RO; bitpos: [1]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR (BIT(1)) +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_M (EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V << EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S) +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V 0x00000001U +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S 1 +/** EFUSE_UART_PRINT_CHANNEL_ERR : RO; bitpos: [2]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_UART_PRINT_CHANNEL_ERR (BIT(2)) +#define EFUSE_UART_PRINT_CHANNEL_ERR_M (EFUSE_UART_PRINT_CHANNEL_ERR_V << EFUSE_UART_PRINT_CHANNEL_ERR_S) +#define EFUSE_UART_PRINT_CHANNEL_ERR_V 0x00000001U +#define EFUSE_UART_PRINT_CHANNEL_ERR_S 2 +/** EFUSE_FLASH_ECC_MODE_ERR : RO; bitpos: [3]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_FLASH_ECC_MODE_ERR (BIT(3)) +#define EFUSE_FLASH_ECC_MODE_ERR_M (EFUSE_FLASH_ECC_MODE_ERR_V << EFUSE_FLASH_ECC_MODE_ERR_S) +#define EFUSE_FLASH_ECC_MODE_ERR_V 0x00000001U +#define EFUSE_FLASH_ECC_MODE_ERR_S 3 +/** EFUSE_DIS_USB_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR (BIT(4)) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V 0x00000001U +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S 4 +/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x00000001U +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 +/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_ERR_M (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S) +#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_ERR_S 6 +/** EFUSE_PIN_POWER_SELECTION_ERR : RO; bitpos: [8]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_PIN_POWER_SELECTION_ERR (BIT(8)) +#define EFUSE_PIN_POWER_SELECTION_ERR_M (EFUSE_PIN_POWER_SELECTION_ERR_V << EFUSE_PIN_POWER_SELECTION_ERR_S) +#define EFUSE_PIN_POWER_SELECTION_ERR_V 0x00000001U +#define EFUSE_PIN_POWER_SELECTION_ERR_S 8 +/** EFUSE_FLASH_TYPE_ERR : RO; bitpos: [9]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_FLASH_TYPE_ERR (BIT(9)) +#define EFUSE_FLASH_TYPE_ERR_M (EFUSE_FLASH_TYPE_ERR_V << EFUSE_FLASH_TYPE_ERR_S) +#define EFUSE_FLASH_TYPE_ERR_V 0x00000001U +#define EFUSE_FLASH_TYPE_ERR_S 9 +/** EFUSE_FLASH_PAGE_SIZE_ERR : RO; bitpos: [11:10]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_FLASH_PAGE_SIZE_ERR 0x00000003U +#define EFUSE_FLASH_PAGE_SIZE_ERR_M (EFUSE_FLASH_PAGE_SIZE_ERR_V << EFUSE_FLASH_PAGE_SIZE_ERR_S) +#define EFUSE_FLASH_PAGE_SIZE_ERR_V 0x00000003U +#define EFUSE_FLASH_PAGE_SIZE_ERR_S 10 +/** EFUSE_FLASH_ECC_EN_ERR : RO; bitpos: [12]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_FLASH_ECC_EN_ERR (BIT(12)) +#define EFUSE_FLASH_ECC_EN_ERR_M (EFUSE_FLASH_ECC_EN_ERR_V << EFUSE_FLASH_ECC_EN_ERR_S) +#define EFUSE_FLASH_ECC_EN_ERR_V 0x00000001U +#define EFUSE_FLASH_ECC_EN_ERR_S 12 +/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [13]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(13)) +#define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S) +#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001U +#define EFUSE_FORCE_SEND_RESUME_ERR_S 13 +/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [29:14]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_SECURE_VERSION_ERR 0x0000FFFFU +#define EFUSE_SECURE_VERSION_ERR_M (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S) +#define EFUSE_SECURE_VERSION_ERR_V 0x0000FFFFU +#define EFUSE_SECURE_VERSION_ERR_S 14 +/** EFUSE_POWERGLITCH_EN_ERR : RO; bitpos: [30]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_POWERGLITCH_EN_ERR (BIT(30)) +#define EFUSE_POWERGLITCH_EN_ERR_M (EFUSE_POWERGLITCH_EN_ERR_V << EFUSE_POWERGLITCH_EN_ERR_S) +#define EFUSE_POWERGLITCH_EN_ERR_V 0x00000001U +#define EFUSE_POWERGLITCH_EN_ERR_S 30 +/** EFUSE_RPT4_RESERVED1_ERR : RO; bitpos: [31]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED1_ERR (BIT(31)) +#define EFUSE_RPT4_RESERVED1_ERR_M (EFUSE_RPT4_RESERVED1_ERR_V << EFUSE_RPT4_RESERVED1_ERR_S) +#define EFUSE_RPT4_RESERVED1_ERR_V 0x00000001U +#define EFUSE_RPT4_RESERVED1_ERR_S 31 -#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x18C) -/* EFUSE_RPT4_RESERVED2_ERR : RO ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_RPT4_RESERVED2_ERR 0x00FFFFFF -#define EFUSE_RPT4_RESERVED2_ERR_M ((EFUSE_RPT4_RESERVED2_ERR_V)<<(EFUSE_RPT4_RESERVED2_ERR_S)) -#define EFUSE_RPT4_RESERVED2_ERR_V 0xFFFFFF +/** EFUSE_RD_REPEAT_ERR4_REG register + * Programming error record register 4 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x190) +/** EFUSE_RPT4_RESERVED2_ERR : RO; bitpos: [23:0]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_RPT4_RESERVED2_ERR 0x00FFFFFFU +#define EFUSE_RPT4_RESERVED2_ERR_M (EFUSE_RPT4_RESERVED2_ERR_V << EFUSE_RPT4_RESERVED2_ERR_S) +#define EFUSE_RPT4_RESERVED2_ERR_V 0x00FFFFFFU #define EFUSE_RPT4_RESERVED2_ERR_S 0 -#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1C0) -/* EFUSE_KEY4_FAIL : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key4 is reliable 1: Means that programm -ing key4 failed and the number of error bytes is over 6..*/ -#define EFUSE_KEY4_FAIL (BIT(31)) -#define EFUSE_KEY4_FAIL_M (BIT(31)) -#define EFUSE_KEY4_FAIL_V 0x1 -#define EFUSE_KEY4_FAIL_S 31 -/* EFUSE_KEY4_ERR_NUM : RO ;bitpos:[30:28] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes..*/ -#define EFUSE_KEY4_ERR_NUM 0x00000007 -#define EFUSE_KEY4_ERR_NUM_M ((EFUSE_KEY4_ERR_NUM_V)<<(EFUSE_KEY4_ERR_NUM_S)) -#define EFUSE_KEY4_ERR_NUM_V 0x7 -#define EFUSE_KEY4_ERR_NUM_S 28 -/* EFUSE_KEY3_FAIL : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key3 is reliable 1: Means that programm -ing key3 failed and the number of error bytes is over 6..*/ -#define EFUSE_KEY3_FAIL (BIT(27)) -#define EFUSE_KEY3_FAIL_M (BIT(27)) -#define EFUSE_KEY3_FAIL_V 0x1 -#define EFUSE_KEY3_FAIL_S 27 -/* EFUSE_KEY3_ERR_NUM : RO ;bitpos:[26:24] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes..*/ -#define EFUSE_KEY3_ERR_NUM 0x00000007 -#define EFUSE_KEY3_ERR_NUM_M ((EFUSE_KEY3_ERR_NUM_V)<<(EFUSE_KEY3_ERR_NUM_S)) -#define EFUSE_KEY3_ERR_NUM_V 0x7 -#define EFUSE_KEY3_ERR_NUM_S 24 -/* EFUSE_KEY2_FAIL : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key2 is reliable 1: Means that programm -ing key2 failed and the number of error bytes is over 6..*/ -#define EFUSE_KEY2_FAIL (BIT(23)) -#define EFUSE_KEY2_FAIL_M (BIT(23)) -#define EFUSE_KEY2_FAIL_V 0x1 -#define EFUSE_KEY2_FAIL_S 23 -/* EFUSE_KEY2_ERR_NUM : RO ;bitpos:[22:20] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes..*/ -#define EFUSE_KEY2_ERR_NUM 0x00000007 -#define EFUSE_KEY2_ERR_NUM_M ((EFUSE_KEY2_ERR_NUM_V)<<(EFUSE_KEY2_ERR_NUM_S)) -#define EFUSE_KEY2_ERR_NUM_V 0x7 -#define EFUSE_KEY2_ERR_NUM_S 20 -/* EFUSE_KEY1_FAIL : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key1 is reliable 1: Means that programm -ing key1 failed and the number of error bytes is over 6..*/ -#define EFUSE_KEY1_FAIL (BIT(19)) -#define EFUSE_KEY1_FAIL_M (BIT(19)) -#define EFUSE_KEY1_FAIL_V 0x1 -#define EFUSE_KEY1_FAIL_S 19 -/* EFUSE_KEY1_ERR_NUM : RO ;bitpos:[18:16] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes..*/ -#define EFUSE_KEY1_ERR_NUM 0x00000007 -#define EFUSE_KEY1_ERR_NUM_M ((EFUSE_KEY1_ERR_NUM_V)<<(EFUSE_KEY1_ERR_NUM_S)) -#define EFUSE_KEY1_ERR_NUM_V 0x7 -#define EFUSE_KEY1_ERR_NUM_S 16 -/* EFUSE_KEY0_FAIL : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key0 is reliable 1: Means that programm -ing key0 failed and the number of error bytes is over 6..*/ -#define EFUSE_KEY0_FAIL (BIT(15)) -#define EFUSE_KEY0_FAIL_M (BIT(15)) -#define EFUSE_KEY0_FAIL_V 0x1 -#define EFUSE_KEY0_FAIL_S 15 -/* EFUSE_KEY0_ERR_NUM : RO ;bitpos:[14:12] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes..*/ -#define EFUSE_KEY0_ERR_NUM 0x00000007 -#define EFUSE_KEY0_ERR_NUM_M ((EFUSE_KEY0_ERR_NUM_V)<<(EFUSE_KEY0_ERR_NUM_S)) -#define EFUSE_KEY0_ERR_NUM_V 0x7 -#define EFUSE_KEY0_ERR_NUM_S 12 -/* EFUSE_USR_DATA_FAIL : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the user data is reliable 1: Means that programming - user data failed and the number of error bytes is over 6..*/ -#define EFUSE_USR_DATA_FAIL (BIT(11)) -#define EFUSE_USR_DATA_FAIL_M (BIT(11)) -#define EFUSE_USR_DATA_FAIL_V 0x1 -#define EFUSE_USR_DATA_FAIL_S 11 -/* EFUSE_USR_DATA_ERR_NUM : RO ;bitpos:[10:8] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes..*/ -#define EFUSE_USR_DATA_ERR_NUM 0x00000007 -#define EFUSE_USR_DATA_ERR_NUM_M ((EFUSE_USR_DATA_ERR_NUM_V)<<(EFUSE_USR_DATA_ERR_NUM_S)) -#define EFUSE_USR_DATA_ERR_NUM_V 0x7 -#define EFUSE_USR_DATA_ERR_NUM_S 8 -/* EFUSE_SYS_PART1_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of system part1 is reliable 1: Means that -programming user data failed and the number of error bytes is over 6..*/ -#define EFUSE_SYS_PART1_FAIL (BIT(7)) -#define EFUSE_SYS_PART1_FAIL_M (BIT(7)) -#define EFUSE_SYS_PART1_FAIL_V 0x1 -#define EFUSE_SYS_PART1_FAIL_S 7 -/* EFUSE_SYS_PART1_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes..*/ -#define EFUSE_SYS_PART1_NUM 0x00000007 -#define EFUSE_SYS_PART1_NUM_M ((EFUSE_SYS_PART1_NUM_V)<<(EFUSE_SYS_PART1_NUM_S)) -#define EFUSE_SYS_PART1_NUM_V 0x7 -#define EFUSE_SYS_PART1_NUM_S 4 -/* EFUSE_MAC_SPI_8M_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that pr -ogramming user data failed and the number of error bytes is over 6..*/ +/** EFUSE_RD_RS_ERR0_REG register + * Programming error record register 0 of BLOCK1-10. + */ +#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0) +/** EFUSE_MAC_SPI_8M_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_MAC_SPI_8M_ERR_NUM 0x00000007U +#define EFUSE_MAC_SPI_8M_ERR_NUM_M (EFUSE_MAC_SPI_8M_ERR_NUM_V << EFUSE_MAC_SPI_8M_ERR_NUM_S) +#define EFUSE_MAC_SPI_8M_ERR_NUM_V 0x00000007U +#define EFUSE_MAC_SPI_8M_ERR_NUM_S 0 +/** EFUSE_MAC_SPI_8M_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ #define EFUSE_MAC_SPI_8M_FAIL (BIT(3)) -#define EFUSE_MAC_SPI_8M_FAIL_M (BIT(3)) -#define EFUSE_MAC_SPI_8M_FAIL_V 0x1 +#define EFUSE_MAC_SPI_8M_FAIL_M (EFUSE_MAC_SPI_8M_FAIL_V << EFUSE_MAC_SPI_8M_FAIL_S) +#define EFUSE_MAC_SPI_8M_FAIL_V 0x00000001U #define EFUSE_MAC_SPI_8M_FAIL_S 3 -/* EFUSE_MAC_SPI_8M_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes..*/ -#define EFUSE_MAC_SPI_8M_ERR_NUM 0x00000007 -#define EFUSE_MAC_SPI_8M_ERR_NUM_M ((EFUSE_MAC_SPI_8M_ERR_NUM_V)<<(EFUSE_MAC_SPI_8M_ERR_NUM_S)) -#define EFUSE_MAC_SPI_8M_ERR_NUM_V 0x7 -#define EFUSE_MAC_SPI_8M_ERR_NUM_S 0 +/** EFUSE_SYS_PART1_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_SYS_PART1_NUM 0x00000007U +#define EFUSE_SYS_PART1_NUM_M (EFUSE_SYS_PART1_NUM_V << EFUSE_SYS_PART1_NUM_S) +#define EFUSE_SYS_PART1_NUM_V 0x00000007U +#define EFUSE_SYS_PART1_NUM_S 4 +/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part1 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ +#define EFUSE_SYS_PART1_FAIL (BIT(7)) +#define EFUSE_SYS_PART1_FAIL_M (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S) +#define EFUSE_SYS_PART1_FAIL_V 0x00000001U +#define EFUSE_SYS_PART1_FAIL_S 7 +/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_USR_DATA_ERR_NUM 0x00000007U +#define EFUSE_USR_DATA_ERR_NUM_M (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S) +#define EFUSE_USR_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_USR_DATA_ERR_NUM_S 8 +/** EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; + * 0: Means no failure and that the user data is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. + */ +#define EFUSE_USR_DATA_FAIL (BIT(11)) +#define EFUSE_USR_DATA_FAIL_M (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S) +#define EFUSE_USR_DATA_FAIL_V 0x00000001U +#define EFUSE_USR_DATA_FAIL_S 11 +/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY0_ERR_NUM 0x00000007U +#define EFUSE_KEY0_ERR_NUM_M (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S) +#define EFUSE_KEY0_ERR_NUM_V 0x00000007U +#define EFUSE_KEY0_ERR_NUM_S 12 +/** EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0; + * 0: Means no failure and that the data of key0 is reliable 1: Means that programming + * key0 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY0_FAIL (BIT(15)) +#define EFUSE_KEY0_FAIL_M (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S) +#define EFUSE_KEY0_FAIL_V 0x00000001U +#define EFUSE_KEY0_FAIL_S 15 +/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY1_ERR_NUM 0x00000007U +#define EFUSE_KEY1_ERR_NUM_M (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S) +#define EFUSE_KEY1_ERR_NUM_V 0x00000007U +#define EFUSE_KEY1_ERR_NUM_S 16 +/** EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0; + * 0: Means no failure and that the data of key1 is reliable 1: Means that programming + * key1 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY1_FAIL (BIT(19)) +#define EFUSE_KEY1_FAIL_M (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S) +#define EFUSE_KEY1_FAIL_V 0x00000001U +#define EFUSE_KEY1_FAIL_S 19 +/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY2_ERR_NUM 0x00000007U +#define EFUSE_KEY2_ERR_NUM_M (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S) +#define EFUSE_KEY2_ERR_NUM_V 0x00000007U +#define EFUSE_KEY2_ERR_NUM_S 20 +/** EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0; + * 0: Means no failure and that the data of key2 is reliable 1: Means that programming + * key2 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY2_FAIL (BIT(23)) +#define EFUSE_KEY2_FAIL_M (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S) +#define EFUSE_KEY2_FAIL_V 0x00000001U +#define EFUSE_KEY2_FAIL_S 23 +/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY3_ERR_NUM 0x00000007U +#define EFUSE_KEY3_ERR_NUM_M (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S) +#define EFUSE_KEY3_ERR_NUM_V 0x00000007U +#define EFUSE_KEY3_ERR_NUM_S 24 +/** EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0; + * 0: Means no failure and that the data of key3 is reliable 1: Means that programming + * key3 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY3_FAIL (BIT(27)) +#define EFUSE_KEY3_FAIL_M (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S) +#define EFUSE_KEY3_FAIL_V 0x00000001U +#define EFUSE_KEY3_FAIL_S 27 +/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY4_ERR_NUM 0x00000007U +#define EFUSE_KEY4_ERR_NUM_M (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S) +#define EFUSE_KEY4_ERR_NUM_V 0x00000007U +#define EFUSE_KEY4_ERR_NUM_S 28 +/** EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0; + * 0: Means no failure and that the data of key4 is reliable 1: Means that programming + * key4 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY4_FAIL (BIT(31)) +#define EFUSE_KEY4_FAIL_M (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S) +#define EFUSE_KEY4_FAIL_V 0x00000001U +#define EFUSE_KEY4_FAIL_S 31 -#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1C4) -/* EFUSE_SYS_PART2_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of system part2 is reliable 1: Means that -programming user data failed and the number of error bytes is over 6..*/ -#define EFUSE_SYS_PART2_FAIL (BIT(7)) -#define EFUSE_SYS_PART2_FAIL_M (BIT(7)) -#define EFUSE_SYS_PART2_FAIL_V 0x1 -#define EFUSE_SYS_PART2_FAIL_S 7 -/* EFUSE_SYS_PART2_ERR_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes..*/ -#define EFUSE_SYS_PART2_ERR_NUM 0x00000007 -#define EFUSE_SYS_PART2_ERR_NUM_M ((EFUSE_SYS_PART2_ERR_NUM_V)<<(EFUSE_SYS_PART2_ERR_NUM_S)) -#define EFUSE_SYS_PART2_ERR_NUM_V 0x7 -#define EFUSE_SYS_PART2_ERR_NUM_S 4 -/* EFUSE_KEY5_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of KEY5 is reliable 1: Means that programm -ing user data failed and the number of error bytes is over 6..*/ +/** EFUSE_RD_RS_ERR1_REG register + * Programming error record register 1 of BLOCK1-10. + */ +#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4) +/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY5_ERR_NUM 0x00000007U +#define EFUSE_KEY5_ERR_NUM_M (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S) +#define EFUSE_KEY5_ERR_NUM_V 0x00000007U +#define EFUSE_KEY5_ERR_NUM_S 0 +/** EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of KEY5 is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. + */ #define EFUSE_KEY5_FAIL (BIT(3)) -#define EFUSE_KEY5_FAIL_M (BIT(3)) -#define EFUSE_KEY5_FAIL_V 0x1 +#define EFUSE_KEY5_FAIL_M (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S) +#define EFUSE_KEY5_FAIL_V 0x00000001U #define EFUSE_KEY5_FAIL_S 3 -/* EFUSE_KEY5_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes..*/ -#define EFUSE_KEY5_ERR_NUM 0x00000007 -#define EFUSE_KEY5_ERR_NUM_M ((EFUSE_KEY5_ERR_NUM_V)<<(EFUSE_KEY5_ERR_NUM_S)) -#define EFUSE_KEY5_ERR_NUM_V 0x7 -#define EFUSE_KEY5_ERR_NUM_S 0 +/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_SYS_PART2_ERR_NUM 0x00000007U +#define EFUSE_SYS_PART2_ERR_NUM_M (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S) +#define EFUSE_SYS_PART2_ERR_NUM_V 0x00000007U +#define EFUSE_SYS_PART2_ERR_NUM_S 4 +/** EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part2 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ +#define EFUSE_SYS_PART2_FAIL (BIT(7)) +#define EFUSE_SYS_PART2_FAIL_M (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S) +#define EFUSE_SYS_PART2_FAIL_V 0x00000001U +#define EFUSE_SYS_PART2_FAIL_S 7 -#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1C8) -/* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Set this bit and force to enable clock signal of eFuse memory..*/ -#define EFUSE_CLK_EN (BIT(16)) -#define EFUSE_CLK_EN_M (BIT(16)) -#define EFUSE_CLK_EN_V 0x1 -#define EFUSE_CLK_EN_S 16 -/* EFUSE_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to force eFuse SRAM into working mode..*/ -#define EFUSE_MEM_FORCE_PU (BIT(2)) -#define EFUSE_MEM_FORCE_PU_M (BIT(2)) -#define EFUSE_MEM_FORCE_PU_V 0x1 -#define EFUSE_MEM_FORCE_PU_S 2 -/* EFUSE_MEM_CLK_FORCE_ON : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: Set this bit and force to activate clock signal of eFuse SRAM..*/ +/** EFUSE_CLK_REG register + * eFuse clcok configuration register. + */ +#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) +/** EFUSE_EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; + * Set this bit to force eFuse SRAM into power-saving mode. + */ +#define EFUSE_EFUSE_MEM_FORCE_PD (BIT(0)) +#define EFUSE_EFUSE_MEM_FORCE_PD_M (EFUSE_EFUSE_MEM_FORCE_PD_V << EFUSE_EFUSE_MEM_FORCE_PD_S) +#define EFUSE_EFUSE_MEM_FORCE_PD_V 0x00000001U +#define EFUSE_EFUSE_MEM_FORCE_PD_S 0 +/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1; + * Set this bit and force to activate clock signal of eFuse SRAM. + */ #define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) -#define EFUSE_MEM_CLK_FORCE_ON_M (BIT(1)) -#define EFUSE_MEM_CLK_FORCE_ON_V 0x1 +#define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) +#define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001U #define EFUSE_MEM_CLK_FORCE_ON_S 1 -/* EFUSE_MEM_FORCE_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to force eFuse SRAM into power-saving mode..*/ -#define EFUSE_MEM_FORCE_PD (BIT(0)) -#define EFUSE_MEM_FORCE_PD_M (BIT(0)) -#define EFUSE_MEM_FORCE_PD_V 0x1 -#define EFUSE_MEM_FORCE_PD_S 0 - -#define EFUSE_WRITE_OP_CODE 0x5a5a -#define EFUSE_READ_OP_CODE 0x5aa5 - -#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1CC) -/* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: 0x5A5A: Operate programming command 0x5AA5: Operate read command..*/ -#define EFUSE_OP_CODE 0x0000FFFF -#define EFUSE_OP_CODE_M ((EFUSE_OP_CODE_V)<<(EFUSE_OP_CODE_S)) -#define EFUSE_OP_CODE_V 0xFFFF -#define EFUSE_OP_CODE_S 0 +/** EFUSE_EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; + * Set this bit to force eFuse SRAM into working mode. + */ +#define EFUSE_EFUSE_MEM_FORCE_PU (BIT(2)) +#define EFUSE_EFUSE_MEM_FORCE_PU_M (EFUSE_EFUSE_MEM_FORCE_PU_V << EFUSE_EFUSE_MEM_FORCE_PU_S) +#define EFUSE_EFUSE_MEM_FORCE_PU_V 0x00000001U +#define EFUSE_EFUSE_MEM_FORCE_PU_S 2 +/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; + * Set this bit and force to enable clock signal of eFuse memory. + */ +#define EFUSE_CLK_EN (BIT(16)) +#define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) +#define EFUSE_CLK_EN_V 0x00000001U +#define EFUSE_CLK_EN_S 16 -#define EFUSE_WRITE_OP_CODE 0x5a5a -#define EFUSE_READ_OP_CODE 0x5aa5 +/** EFUSE_CONF_REG register + * eFuse operation mode configuraiton register + */ +#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) +/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; + * 0x5A5A: Operate programming command 0x5AA5: Operate read command. + */ +#define EFUSE_OP_CODE 0x0000FFFFU +#define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) +#define EFUSE_OP_CODE_V 0x0000FFFFU +#define EFUSE_OP_CODE_S 0 -#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1D0) -/* EFUSE_REPEAT_ERR_CNT : RO ;bitpos:[17:10] ;default: 8'h0 ; */ -/*description: Indicates the number of error bits during programming BLOCK0..*/ -#define EFUSE_REPEAT_ERR_CNT 0x000000FF -#define EFUSE_REPEAT_ERR_CNT_M ((EFUSE_REPEAT_ERR_CNT_V)<<(EFUSE_REPEAT_ERR_CNT_S)) -#define EFUSE_REPEAT_ERR_CNT_V 0xFF -#define EFUSE_REPEAT_ERR_CNT_S 10 -/* EFUSE_OTP_VDDQ_IS_SW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The value of OTP_VDDQ_IS_SW..*/ -#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) -#define EFUSE_OTP_VDDQ_IS_SW_M (BIT(9)) -#define EFUSE_OTP_VDDQ_IS_SW_V 0x1 -#define EFUSE_OTP_VDDQ_IS_SW_S 9 -/* EFUSE_OTP_PGENB_SW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The value of OTP_PGENB_SW..*/ -#define EFUSE_OTP_PGENB_SW (BIT(8)) -#define EFUSE_OTP_PGENB_SW_M (BIT(8)) -#define EFUSE_OTP_PGENB_SW_V 0x1 -#define EFUSE_OTP_PGENB_SW_S 8 -/* EFUSE_OTP_CSB_SW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The value of OTP_CSB_SW..*/ -#define EFUSE_OTP_CSB_SW (BIT(7)) -#define EFUSE_OTP_CSB_SW_M (BIT(7)) -#define EFUSE_OTP_CSB_SW_V 0x1 -#define EFUSE_OTP_CSB_SW_S 7 -/* EFUSE_OTP_STROBE_SW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The value of OTP_STROBE_SW..*/ -#define EFUSE_OTP_STROBE_SW (BIT(6)) -#define EFUSE_OTP_STROBE_SW_M (BIT(6)) -#define EFUSE_OTP_STROBE_SW_V 0x1 -#define EFUSE_OTP_STROBE_SW_S 6 -/* EFUSE_OTP_VDDQ_C_SYNC2 : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The value of OTP_VDDQ_C_SYNC2..*/ -#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) -#define EFUSE_OTP_VDDQ_C_SYNC2_M (BIT(5)) -#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x1 -#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 -/* EFUSE_OTP_LOAD_SW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The value of OTP_LOAD_SW..*/ +/** EFUSE_STATUS_REG register + * eFuse status register. + */ +#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0) +/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0; + * Indicates the state of the eFuse state machine. + */ +#define EFUSE_STATE 0x0000000FU +#define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) +#define EFUSE_STATE_V 0x0000000FU +#define EFUSE_STATE_S 0 +/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0; + * The value of OTP_LOAD_SW. + */ #define EFUSE_OTP_LOAD_SW (BIT(4)) -#define EFUSE_OTP_LOAD_SW_M (BIT(4)) -#define EFUSE_OTP_LOAD_SW_V 0x1 +#define EFUSE_OTP_LOAD_SW_M (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S) +#define EFUSE_OTP_LOAD_SW_V 0x00000001U #define EFUSE_OTP_LOAD_SW_S 4 -/* EFUSE_STATE : RO ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: Indicates the state of the eFuse state machine..*/ -#define EFUSE_STATE 0x0000000F -#define EFUSE_STATE_M ((EFUSE_STATE_V)<<(EFUSE_STATE_S)) -#define EFUSE_STATE_V 0xF -#define EFUSE_STATE_S 0 +/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0; + * The value of OTP_VDDQ_C_SYNC2. + */ +#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) +#define EFUSE_OTP_VDDQ_C_SYNC2_M (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S) +#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x00000001U +#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 +/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0; + * The value of OTP_STROBE_SW. + */ +#define EFUSE_OTP_STROBE_SW (BIT(6)) +#define EFUSE_OTP_STROBE_SW_M (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S) +#define EFUSE_OTP_STROBE_SW_V 0x00000001U +#define EFUSE_OTP_STROBE_SW_S 6 +/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0; + * The value of OTP_CSB_SW. + */ +#define EFUSE_OTP_CSB_SW (BIT(7)) +#define EFUSE_OTP_CSB_SW_M (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S) +#define EFUSE_OTP_CSB_SW_V 0x00000001U +#define EFUSE_OTP_CSB_SW_S 7 +/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0; + * The value of OTP_PGENB_SW. + */ +#define EFUSE_OTP_PGENB_SW (BIT(8)) +#define EFUSE_OTP_PGENB_SW_M (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S) +#define EFUSE_OTP_PGENB_SW_V 0x00000001U +#define EFUSE_OTP_PGENB_SW_S 8 +/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0; + * The value of OTP_VDDQ_IS_SW. + */ +#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) +#define EFUSE_OTP_VDDQ_IS_SW_M (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S) +#define EFUSE_OTP_VDDQ_IS_SW_V 0x00000001U +#define EFUSE_OTP_VDDQ_IS_SW_S 9 +/** EFUSE_REPEAT_ERR_CNT : RO; bitpos: [17:10]; default: 0; + * Indicates the number of error bits during programming BLOCK0. + */ +#define EFUSE_REPEAT_ERR_CNT 0x000000FFU +#define EFUSE_REPEAT_ERR_CNT_M (EFUSE_REPEAT_ERR_CNT_V << EFUSE_REPEAT_ERR_CNT_S) +#define EFUSE_REPEAT_ERR_CNT_V 0x000000FFU +#define EFUSE_REPEAT_ERR_CNT_S 10 -#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1D4) -/* EFUSE_BLK_NUM : R/W ;bitpos:[5:2] ;default: 4'h0 ; */ -/*description: The serial number of the block to be programmed. Value 0-10 corresponds to block - number 0-10, respectively..*/ -#define EFUSE_BLK_NUM 0x0000000F -#define EFUSE_BLK_NUM_M ((EFUSE_BLK_NUM_V)<<(EFUSE_BLK_NUM_S)) -#define EFUSE_BLK_NUM_V 0xF -#define EFUSE_BLK_NUM_S 2 -/* EFUSE_PGM_CMD : R/WS/SC ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to send programming command..*/ -#define EFUSE_PGM_CMD (BIT(1)) -#define EFUSE_PGM_CMD_M (BIT(1)) -#define EFUSE_PGM_CMD_V 0x1 -#define EFUSE_PGM_CMD_S 1 -/* EFUSE_READ_CMD : R/WS/SC ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to send read command..*/ +/** EFUSE_CMD_REG register + * eFuse command register. + */ +#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4) +/** EFUSE_READ_CMD : R/WS/SC; bitpos: [0]; default: 0; + * Set this bit to send read command. + */ #define EFUSE_READ_CMD (BIT(0)) -#define EFUSE_READ_CMD_M (BIT(0)) -#define EFUSE_READ_CMD_V 0x1 +#define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) +#define EFUSE_READ_CMD_V 0x00000001U #define EFUSE_READ_CMD_S 0 +/** EFUSE_PGM_CMD : R/WS/SC; bitpos: [1]; default: 0; + * Set this bit to send programming command. + */ +#define EFUSE_PGM_CMD (BIT(1)) +#define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) +#define EFUSE_PGM_CMD_V 0x00000001U +#define EFUSE_PGM_CMD_S 1 +/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0; + * The serial number of the block to be programmed. Value 0-10 corresponds to block + * number 0-10, respectively. + */ +#define EFUSE_BLK_NUM 0x0000000FU +#define EFUSE_BLK_NUM_M (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S) +#define EFUSE_BLK_NUM_V 0x0000000FU +#define EFUSE_BLK_NUM_S 2 -#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1D8) -/* EFUSE_PGM_DONE_INT_RAW : R/WC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw bit signal for pgm_done interrupt..*/ -#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) -#define EFUSE_PGM_DONE_INT_RAW_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_RAW_V 0x1 -#define EFUSE_PGM_DONE_INT_RAW_S 1 -/* EFUSE_READ_DONE_INT_RAW : R/WC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw bit signal for read_done interrupt..*/ +/** EFUSE_INT_RAW_REG register + * eFuse raw interrupt register. + */ +#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8) +/** EFUSE_READ_DONE_INT_RAW : R/WC/SS; bitpos: [0]; default: 0; + * The raw bit signal for read_done interrupt. + */ #define EFUSE_READ_DONE_INT_RAW (BIT(0)) -#define EFUSE_READ_DONE_INT_RAW_M (BIT(0)) -#define EFUSE_READ_DONE_INT_RAW_V 0x1 +#define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) +#define EFUSE_READ_DONE_INT_RAW_V 0x00000001U #define EFUSE_READ_DONE_INT_RAW_S 0 +/** EFUSE_PGM_DONE_INT_RAW : R/WC/SS; bitpos: [1]; default: 0; + * The raw bit signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) +#define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) +#define EFUSE_PGM_DONE_INT_RAW_V 0x00000001U +#define EFUSE_PGM_DONE_INT_RAW_S 1 -#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1DC) -/* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The status signal for pgm_done interrupt..*/ -#define EFUSE_PGM_DONE_INT_ST (BIT(1)) -#define EFUSE_PGM_DONE_INT_ST_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_ST_V 0x1 -#define EFUSE_PGM_DONE_INT_ST_S 1 -/* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The status signal for read_done interrupt..*/ +/** EFUSE_INT_ST_REG register + * eFuse interrupt status register. + */ +#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc) +/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The status signal for read_done interrupt. + */ #define EFUSE_READ_DONE_INT_ST (BIT(0)) -#define EFUSE_READ_DONE_INT_ST_M (BIT(0)) -#define EFUSE_READ_DONE_INT_ST_V 0x1 +#define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) +#define EFUSE_READ_DONE_INT_ST_V 0x00000001U #define EFUSE_READ_DONE_INT_ST_S 0 +/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The status signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_ST (BIT(1)) +#define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) +#define EFUSE_PGM_DONE_INT_ST_V 0x00000001U +#define EFUSE_PGM_DONE_INT_ST_S 1 -#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1E0) -/* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The enable signal for pgm_done interrupt..*/ -#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) -#define EFUSE_PGM_DONE_INT_ENA_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_ENA_V 0x1 -#define EFUSE_PGM_DONE_INT_ENA_S 1 -/* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The enable signal for read_done interrupt..*/ +/** EFUSE_INT_ENA_REG register + * eFuse interrupt enable register. + */ +#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0) +/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable signal for read_done interrupt. + */ #define EFUSE_READ_DONE_INT_ENA (BIT(0)) -#define EFUSE_READ_DONE_INT_ENA_M (BIT(0)) -#define EFUSE_READ_DONE_INT_ENA_V 0x1 +#define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) +#define EFUSE_READ_DONE_INT_ENA_V 0x00000001U #define EFUSE_READ_DONE_INT_ENA_S 0 +/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) +#define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) +#define EFUSE_PGM_DONE_INT_ENA_V 0x00000001U +#define EFUSE_PGM_DONE_INT_ENA_S 1 -#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1E4) -/* EFUSE_PGM_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The clear signal for pgm_done interrupt..*/ -#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) -#define EFUSE_PGM_DONE_INT_CLR_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_CLR_V 0x1 -#define EFUSE_PGM_DONE_INT_CLR_S 1 -/* EFUSE_READ_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The clear signal for read_done interrupt..*/ +/** EFUSE_INT_CLR_REG register + * eFuse interrupt clear register. + */ +#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4) +/** EFUSE_READ_DONE_INT_CLR : WO; bitpos: [0]; default: 0; + * The clear signal for read_done interrupt. + */ #define EFUSE_READ_DONE_INT_CLR (BIT(0)) -#define EFUSE_READ_DONE_INT_CLR_M (BIT(0)) -#define EFUSE_READ_DONE_INT_CLR_V 0x1 +#define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) +#define EFUSE_READ_DONE_INT_CLR_V 0x00000001U #define EFUSE_READ_DONE_INT_CLR_S 0 +/** EFUSE_PGM_DONE_INT_CLR : WO; bitpos: [1]; default: 0; + * The clear signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) +#define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) +#define EFUSE_PGM_DONE_INT_CLR_V 0x00000001U +#define EFUSE_PGM_DONE_INT_CLR_S 1 -#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1E8) -/* EFUSE_OE_CLR : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: Reduces the power supply of the programming voltage..*/ -#define EFUSE_OE_CLR (BIT(17)) -#define EFUSE_OE_CLR_M (BIT(17)) -#define EFUSE_OE_CLR_V 0x1 -#define EFUSE_OE_CLR_S 17 -/* EFUSE_DAC_NUM : R/W ;bitpos:[16:9] ;default: 8'd255 ; */ -/*description: Controls the rising period of the programming voltage..*/ -#define EFUSE_DAC_NUM 0x000000FF -#define EFUSE_DAC_NUM_M ((EFUSE_DAC_NUM_V)<<(EFUSE_DAC_NUM_S)) -#define EFUSE_DAC_NUM_V 0xFF -#define EFUSE_DAC_NUM_S 9 -/* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Don't care..*/ +/** EFUSE_DAC_CONF_REG register + * Controls the eFuse programming voltage. + */ +#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8) +/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 28; + * Controls the division factor of the rising clock of the programming voltage. + */ +#define EFUSE_DAC_CLK_DIV 0x000000FFU +#define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) +#define EFUSE_DAC_CLK_DIV_V 0x000000FFU +#define EFUSE_DAC_CLK_DIV_S 0 +/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0; + * Don't care. + */ #define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) -#define EFUSE_DAC_CLK_PAD_SEL_M (BIT(8)) -#define EFUSE_DAC_CLK_PAD_SEL_V 0x1 +#define EFUSE_DAC_CLK_PAD_SEL_M (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S) +#define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001U #define EFUSE_DAC_CLK_PAD_SEL_S 8 -/* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd28 ; */ -/*description: Controls the division factor of the rising clock of the programming voltage..*/ -#define EFUSE_DAC_CLK_DIV 0x000000FF -#define EFUSE_DAC_CLK_DIV_M ((EFUSE_DAC_CLK_DIV_V)<<(EFUSE_DAC_CLK_DIV_S)) -#define EFUSE_DAC_CLK_DIV_V 0xFF -#define EFUSE_DAC_CLK_DIV_S 0 +/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ +#define EFUSE_DAC_NUM 0x000000FFU +#define EFUSE_DAC_NUM_M (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S) +#define EFUSE_DAC_NUM_V 0x000000FFU +#define EFUSE_DAC_NUM_S 9 +/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ +#define EFUSE_OE_CLR (BIT(17)) +#define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) +#define EFUSE_OE_CLR_V 0x00000001U +#define EFUSE_OE_CLR_S 17 -#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1EC) -/* EFUSE_READ_INIT_NUM : R/W ;bitpos:[31:24] ;default: 8'h12 ; */ -/*description: Configures the initial read time of eFuse..*/ -#define EFUSE_READ_INIT_NUM 0x000000FF -#define EFUSE_READ_INIT_NUM_M ((EFUSE_READ_INIT_NUM_V)<<(EFUSE_READ_INIT_NUM_S)) -#define EFUSE_READ_INIT_NUM_V 0xFF +/** EFUSE_RD_TIM_CONF_REG register + * Configures read timing parameters. + */ +#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) +/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18; + * Configures the initial read time of eFuse. + */ +#define EFUSE_READ_INIT_NUM 0x000000FFU +#define EFUSE_READ_INIT_NUM_M (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S) +#define EFUSE_READ_INIT_NUM_V 0x000000FFU #define EFUSE_READ_INIT_NUM_S 24 -#define EFUSE_WR_TIM_CONF0_REG (DR_REG_EFUSE_BASE + 0x1F0) - -#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1F4) -/* EFUSE_PWR_ON_NUM : R/W ;bitpos:[23:8] ;default: 16'h2880 ; */ -/*description: Configures the power up time for VDDQ..*/ -#define EFUSE_PWR_ON_NUM 0x0000FFFF -#define EFUSE_PWR_ON_NUM_M ((EFUSE_PWR_ON_NUM_V)<<(EFUSE_PWR_ON_NUM_S)) -#define EFUSE_PWR_ON_NUM_V 0xFFFF +/** EFUSE_WR_TIM_CONF1_REG register + * Configurarion register 1 of eFuse programming timing parameters. + */ +#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f4) +/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 10368; + * Configures the power up time for VDDQ. + */ +#define EFUSE_PWR_ON_NUM 0x0000FFFFU +#define EFUSE_PWR_ON_NUM_M (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S) +#define EFUSE_PWR_ON_NUM_V 0x0000FFFFU #define EFUSE_PWR_ON_NUM_S 8 -#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1F8) -/* EFUSE_PWR_OFF_NUM : R/W ;bitpos:[15:0] ;default: 16'h190 ; */ -/*description: Configures the power outage time for VDDQ..*/ -#define EFUSE_PWR_OFF_NUM 0x0000FFFF -#define EFUSE_PWR_OFF_NUM_M ((EFUSE_PWR_OFF_NUM_V)<<(EFUSE_PWR_OFF_NUM_S)) -#define EFUSE_PWR_OFF_NUM_V 0xFFFF +/** EFUSE_WR_TIM_CONF2_REG register + * Configurarion register 2 of eFuse programming timing parameters. + */ +#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f8) +/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400; + * Configures the power outage time for VDDQ. + */ +#define EFUSE_PWR_OFF_NUM 0x0000FFFFU +#define EFUSE_PWR_OFF_NUM_M (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S) +#define EFUSE_PWR_OFF_NUM_V 0x0000FFFFU #define EFUSE_PWR_OFF_NUM_S 0 -#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1FC) -/* EFUSE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101180 ; */ -/*description: Stores eFuse version..*/ -#define EFUSE_DATE 0x0FFFFFFF -#define EFUSE_DATE_M ((EFUSE_DATE_V)<<(EFUSE_DATE_S)) -#define EFUSE_DATE_V 0xFFFFFFF +/** EFUSE_DATE_REG register + * eFuse version register. + */ +#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) +/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 34607760; + * Stores eFuse version. + */ +#define EFUSE_DATE 0x0FFFFFFFU +#define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S) +#define EFUSE_DATE_V 0x0FFFFFFFU #define EFUSE_DATE_S 0 - #ifdef __cplusplus } #endif - - - -#endif /*_SOC_EFUSE_REG_H_ */ diff --git a/tools/sdk/esp32s3/include/soc/esp32s3/include/soc/efuse_struct.h b/tools/sdk/esp32s3/include/soc/esp32s3/include/soc/efuse_struct.h index 78d797a3d15..c5f811d94e5 100644 --- a/tools/sdk/esp32s3/include/soc/esp32s3/include/soc/efuse_struct.h +++ b/tools/sdk/esp32s3/include/soc/esp32s3/include/soc/efuse_struct.h @@ -1,500 +1,2515 @@ -/* - * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_EFUSE_STRUCT_H_ -#define _SOC_EFUSE_STRUCT_H_ - +#pragma once #include #ifdef __cplusplus extern "C" { #endif -typedef volatile struct efuse_dev_s { - uint32_t pgm_data0; - uint32_t pgm_data1; - uint32_t pgm_data2; - uint32_t pgm_data3; - uint32_t pgm_data4; - uint32_t pgm_data5; - uint32_t pgm_data6; - uint32_t pgm_data7; - uint32_t pgm_check_value0; - uint32_t pgm_check_value1; - uint32_t pgm_check_value2; - uint32_t rd_wr_dis; - union { - struct { - uint32_t reg_rd_dis : 7; /*Set this bit to disable reading from BlOCK4-10.*/ - uint32_t reg_rpt4_reserved5 : 1; /*Reserved*/ - uint32_t reg_dis_icache : 1; /*Set this bit to disable Icache.*/ - uint32_t reg_dis_dcache : 1; /*Set this bit to disable Dcache.*/ - uint32_t reg_dis_download_icache : 1; /*Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, 7).*/ - uint32_t reg_dis_download_dcache : 1; /*Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0, 1, 2, 3, 6, 7).*/ - uint32_t reg_dis_force_download : 1; /*Set this bit to disable the function that forces chip into download mode.*/ - uint32_t reg_dis_usb : 1; /*Set this bit to disable USB function.*/ - uint32_t reg_dis_can : 1; /*Set this bit to disable CAN function.*/ - uint32_t reg_dis_app_cpu : 1; /*Disable app cpu.*/ - uint32_t reg_soft_dis_jtag : 3; /*Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module.*/ - uint32_t reg_dis_pad_jtag : 1; /*Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.*/ - uint32_t reg_dis_download_manual_encrypt: 1; /*Set this bit to disable flash encryption when in download boot modes.*/ - uint32_t reg_usb_drefh : 2; /*Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored in eFuse.*/ - uint32_t reg_usb_drefl : 2; /*Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, stored in eFuse.*/ - uint32_t reg_usb_exchg_pins : 1; /*Set this bit to exchange USB D+ and D- pins.*/ - uint32_t reg_ext_phy_enable : 1; /*Set this bit to enable external PHY.*/ - uint32_t reg_btlc_gpio_enable : 2; /*Enable btlc gpio.*/ - uint32_t reg_vdd_spi_modecurlim : 1; /*SPI regulator switches current limit mode.*/ - uint32_t reg_vdd_spi_drefh : 2; /*SPI regulator high voltage reference.*/ - }; - uint32_t val; - } rd_repeat_data0; - union { - struct { - uint32_t reg_vdd_spi_drefm : 2; /*SPI regulator medium voltage reference.*/ - uint32_t reg_vdd_spi_drefl : 2; /*SPI regulator low voltage reference.*/ - uint32_t reg_vdd_spi_xpd : 1; /*SPI regulator power up signal.*/ - uint32_t reg_vdd_spi_tieh : 1; /*SPI regulator output is short connected to VDD3P3_RTC_IO.*/ - uint32_t reg_vdd_spi_force : 1; /*Set this bit and force to use the configuration of eFuse to configure VDD_SPI.*/ - uint32_t reg_vdd_spi_en_init : 1; /*Set SPI regulator to 0 to configure init[1:0]=0.*/ - uint32_t reg_vdd_spi_encurlim : 1; /*Set SPI regulator to 1 to enable output current limit.*/ - uint32_t reg_vdd_spi_dcurlim : 3; /*Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d).*/ - uint32_t reg_vdd_spi_init : 2; /*Adds resistor from LDO output to ground. 0: no resistance 1: 6 K 2: 4 K 3: 2 K.*/ - uint32_t reg_vdd_spi_dcap : 2; /*Prevents SPI regulator from overshoot.*/ - uint32_t reg_wdt_delay_sel : 2; /*Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.*/ - uint32_t reg_spi_boot_crypt_cnt : 3; /*Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable.*/ - uint32_t reg_secure_boot_key_revoke0 : 1; /*Set this bit to enable revoking first secure boot key.*/ - uint32_t reg_secure_boot_key_revoke1 : 1; /*Set this bit to enable revoking second secure boot key.*/ - uint32_t reg_secure_boot_key_revoke2 : 1; /*Set this bit to enable revoking third secure boot key.*/ - uint32_t reg_key_purpose_0 : 4; /*Purpose of Key0.*/ - uint32_t reg_key_purpose_1 : 4; /*Purpose of Key1.*/ - }; - uint32_t val; - } rd_repeat_data1; - union { - struct { - uint32_t reg_key_purpose_2 : 4; /*Purpose of Key2.*/ - uint32_t reg_key_purpose_3 : 4; /*Purpose of Key3.*/ - uint32_t reg_key_purpose_4 : 4; /*Purpose of Key4.*/ - uint32_t reg_key_purpose_5 : 4; /*Purpose of Key5.*/ - uint32_t reg_rpt4_reserved0 : 4; /*Reserved (used for four backups method).*/ - uint32_t reg_secure_boot_en : 1; /*Set this bit to enable secure boot.*/ - uint32_t reg_secure_boot_aggressive_revoke: 1; /*Set this bit to enable revoking aggressive secure boot.*/ - uint32_t reg_dis_usb_jtag : 1; /*Set this bit to disable function of usb switch to jtag in module of usb device.*/ - uint32_t reg_dis_usb_device : 1; /*Set this bit to disable usb device.*/ - uint32_t reg_strap_jtag_sel : 1; /*Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.*/ - uint32_t reg_usb_phy_sel : 1; /*This bit is used to switch internal PHY and external PHY for USB OTG and USB Device. 0: internal PHY is assigned to USB Device while external PHY is assigned to USB OTG. 1: internal PHY is assigned to USB OTG while external PHY is assigned to USB Device.*/ - uint32_t reg_power_glitch_dsense : 2; /*Sample delay configuration of power glitch.*/ - uint32_t reg_flash_tpuw : 4; /*Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value; Otherwise, the waiting time is twice the configurable value.*/ - }; - uint32_t val; - } rd_repeat_data2; - union { - struct { - uint32_t reg_dis_download_mode : 1; /*Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7).*/ - uint32_t reg_dis_direct_boot : 1; /*Set this bit to disable direct boot..*/ - uint32_t dis_usb_serial_jtag_rom_print : 1; /*Set this bit to disable USB-Serial-JTAG print during rom boot*/ - uint32_t reg_flash_ecc_mode : 1; /*Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would use 16to17 byte mode.*/ - uint32_t reg_dis_usb_serial_jtag_download_mode: 1; /*Set this bit to disable download through USB-Serial-JTAG.*/ - uint32_t reg_enable_security_download : 1; /*Set this bit to enable secure UART download mode.*/ - uint32_t reg_uart_print_control : 2; /*Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.*/ - uint32_t reg_pin_power_selection : 1; /*GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.*/ - uint32_t reg_flash_type : 1; /*Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.*/ - uint32_t reg_flash_page_size : 2; /*Set Flash page size.*/ - uint32_t reg_flash_ecc_en : 1; /*Set 1 to enable ECC for flash boot.*/ - uint32_t reg_force_send_resume : 1; /*Set this bit to force ROM code to send a resume command during SPI boot.*/ - uint32_t reg_secure_version : 16; /*Secure version (used by ESP-IDF anti-rollback feature).*/ - uint32_t reg_rpt4_reserved1 : 1; /*Reserved (used for four backups method).*/ - uint32_t reg_dis_usb_otg_download_mode : 1; /*Set this bit to disable download through USB-OTG*/ - }; - uint32_t val; - } rd_repeat_data3; - union { - struct { - uint32_t disable_wafer_version_major : 1; - uint32_t disable_blk_version_major : 1; - uint32_t reg_rpt4_reserved2 : 22; /*Reserved.*/ - uint32_t reserved24 : 8; /*Reserved.*/ - }; - uint32_t val; - } rd_repeat_data4; - uint32_t rd_mac_spi_sys_0; - union { - struct { - uint32_t reg_mac_1 : 16; /*Stores the high 16 bits of MAC address.*/ - uint32_t reg_spi_pad_conf_0 : 16; /*Stores the zeroth part of SPI_PAD_CONF.*/ - }; - uint32_t val; - } rd_mac_spi_sys_1; - uint32_t rd_mac_spi_sys_2; - union { - struct { - uint32_t spi_pad_conf_2: 18; /*Stores the second part of SPI_PAD_CONF.*/ - uint32_t wafer_version_minor_low: 3; - uint32_t pkg_version: 3; - uint32_t blk_version_minor:3; - uint32_t reg_sys_data_part0_0: 5; - }; - uint32_t val; - } rd_mac_spi_sys_3; - union { - struct { - uint32_t reserved1: 13; - uint32_t k_rtc_ldo: 7; - uint32_t k_dig_ldo: 7; - uint32_t v_rtc_dbias20_low: 5; - }; - uint32_t val; - } rd_mac_spi_sys_4; - union { - struct { - uint32_t v_rtc_dbias20_hi: 3; - uint32_t v_dig_dbias20: 8; - uint32_t dig_dbias_hvt: 5; - uint32_t reserved1: 7; - uint32_t wafer_version_minor_high: 1; - uint32_t wafer_version_major: 2; - uint32_t reserved2: 6; - }; - uint32_t val; - } rd_mac_spi_sys_5; - uint32_t rd_sys_part1_data0; - uint32_t rd_sys_part1_data1; - uint32_t rd_sys_part1_data2; - uint32_t rd_sys_part1_data3; - union { - struct { - uint32_t blk_version_major: 2; - uint32_t reserved1: 11; - uint32_t ocode: 8; /*ADC OCode*/ - uint32_t reserved2: 11; - }; - uint32_t val; - } rd_sys_part1_data4; - uint32_t rd_sys_part1_data5; - uint32_t rd_sys_part1_data6; - uint32_t rd_sys_part1_data7; - uint32_t rd_usr_data0; - uint32_t rd_usr_data1; - uint32_t rd_usr_data2; - uint32_t rd_usr_data3; - uint32_t rd_usr_data4; - uint32_t rd_usr_data5; - uint32_t rd_usr_data6; - uint32_t rd_usr_data7; - uint32_t rd_key0_data0; - uint32_t rd_key0_data1; - uint32_t rd_key0_data2; - uint32_t rd_key0_data3; - uint32_t rd_key0_data4; - uint32_t rd_key0_data5; - uint32_t rd_key0_data6; - uint32_t rd_key0_data7; - uint32_t rd_key1_data0; - uint32_t rd_key1_data1; - uint32_t rd_key1_data2; - uint32_t rd_key1_data3; - uint32_t rd_key1_data4; - uint32_t rd_key1_data5; - uint32_t rd_key1_data6; - uint32_t rd_key1_data7; - uint32_t rd_key2_data0; - uint32_t rd_key2_data1; - uint32_t rd_key2_data2; - uint32_t rd_key2_data3; - uint32_t rd_key2_data4; - uint32_t rd_key2_data5; - uint32_t rd_key2_data6; - uint32_t rd_key2_data7; - uint32_t rd_key3_data0; - uint32_t rd_key3_data1; - uint32_t rd_key3_data2; - uint32_t rd_key3_data3; - uint32_t rd_key3_data4; - uint32_t rd_key3_data5; - uint32_t rd_key3_data6; - uint32_t rd_key3_data7; - uint32_t rd_key4_data0; - uint32_t rd_key4_data1; - uint32_t rd_key4_data2; - uint32_t rd_key4_data3; - uint32_t rd_key4_data4; - uint32_t rd_key4_data5; - uint32_t rd_key4_data6; - uint32_t rd_key4_data7; - uint32_t rd_key5_data0; - uint32_t rd_key5_data1; - uint32_t rd_key5_data2; - uint32_t rd_key5_data3; - uint32_t rd_key5_data4; - uint32_t rd_key5_data5; - uint32_t rd_key5_data6; - uint32_t rd_key5_data7; - uint32_t rd_sys_part2_data0; - uint32_t rd_sys_part2_data1; - uint32_t rd_sys_part2_data2; - uint32_t rd_sys_part2_data3; - uint32_t rd_sys_part2_data4; - uint32_t rd_sys_part2_data5; - uint32_t rd_sys_part2_data6; - uint32_t rd_sys_part2_data7; - union { - struct { - uint32_t reg_rd_dis_err : 7; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_rpt4_reserved5_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_icache_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_dcache_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_download_icache_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_download_dcache_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_force_download_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_usb_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_can_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_app_cpu_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_soft_dis_jtag_err : 3; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_pad_jtag_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_download_manual_encrypt_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_usb_drefh_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_usb_drefl_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_usb_exchg_pins_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_ext_phy_enable_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_btlc_gpio_enable_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_vdd_spi_modecurlim_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_vdd_spi_drefh_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - }; - uint32_t val; - } rd_repeat_err0; - union { - struct { - uint32_t reg_vdd_spi_drefm_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_vdd_spi_drefl_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_vdd_spi_xpd_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_vdd_spi_tieh_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_vdd_spi_force_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_vdd_spi_en_init_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_vdd_spi_encurlim_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_vdd_spi_dcurlim_err : 3; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_vdd_spi_init_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_vdd_spi_dcap_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_wdt_delay_sel_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_spi_boot_crypt_cnt_err : 3; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_secure_boot_key_revoke0_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_secure_boot_key_revoke1_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_secure_boot_key_revoke2_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_key_purpose_0_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_key_purpose_1_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ - }; - uint32_t val; - } rd_repeat_err1; - union { - struct { - uint32_t reg_key_purpose_2_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_key_purpose_3_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_key_purpose_4_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_key_purpose_5_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_rpt4_reserved0_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_secure_boot_en_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_secure_boot_aggressive_revoke_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_usb_jtag_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_usb_device_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_strap_jtag_sel_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_usb_phy_sel_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_power_glitch_dsense_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_flash_tpuw_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ - }; - uint32_t val; - } rd_repeat_err2; - union { - struct { - uint32_t reg_dis_download_mode_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_direct_boot_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_usb_serial_jtag_rom_print_err:1;/*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_flash_ecc_mode_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_usb_serial_jtag_download_mode_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_enable_security_download_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_uart_print_control_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_pin_power_selection_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_flash_type_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_flash_page_size_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_flash_ecc_en_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_force_send_resume_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_secure_version_err : 16; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_rpt4_reserved1_err : 1; /*Reserved.*/ - uint32_t reg_dis_usb_otg_download_mode_err: 1; /*Set this bit to disable download through USB-OTG*/ - }; - uint32_t val; - } rd_repeat_err3; - union { - struct { - uint32_t reg_rpt4_reserved2_err : 24; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reserved24 : 8; /*Reserved.*/ - }; - uint32_t val; - } rd_repeat_err4; - uint32_t reserved_190; - uint32_t reserved_194; - uint32_t reserved_198; - uint32_t reserved_19c; - uint32_t reserved_1a0; - uint32_t reserved_1a4; - uint32_t reserved_1a8; - uint32_t reserved_1ac; - uint32_t reserved_1b0; - uint32_t reserved_1b4; - uint32_t reserved_1b8; - uint32_t reserved_1bc; - union { - struct { - uint32_t rd_mac_spi_8m_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t rd_mac_spi_8m_fail: 1; /*0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ - uint32_t rd_sys_part1_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t rd_sys_part1_fail: 1; /*0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ - uint32_t rd_usr_data_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t rd_usr_data_fail: 1; /*0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ - uint32_t rd_key0_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t rd_key0_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ - uint32_t rd_key1_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t rd_key1_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ - uint32_t rd_key2_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t rd_key2_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ - uint32_t rd_key3_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t rd_key3_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ - uint32_t rd_key4_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t rd_key4_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ - }; - uint32_t val; - } rd_rs_err0; - union { - struct { - uint32_t rd_key5_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t rd_key5_fail: 1; /*0: Means no failure and that the data of KEY5 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ - uint32_t rd_sys_part2_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t rd_sys_part2_fail: 1; /*0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ - uint32_t reserved8: 24; /*Reserved.*/ - }; - uint32_t val; - } rd_rs_err1; - union { - struct { - uint32_t mem_force_pd: 1; /*Set this bit to force eFuse SRAM into power-saving mode.*/ - uint32_t mem_clk_force_on: 1; /*Set this bit and force to activate clock signal of eFuse SRAM.*/ - uint32_t mem_force_pu: 1; /*Set this bit to force eFuse SRAM into working mode.*/ - uint32_t reserved3: 13; /*Reserved.*/ - uint32_t clk_en: 1; /*Set this bit and force to enable clock signal of eFuse memory.*/ - uint32_t reserved17: 15; /*Reserved.*/ - }; - uint32_t val; - } clk; - union { - struct { - uint32_t op_code: 16; /*0x5A5A: Operate programming command 0x5AA5: Operate read command.*/ - uint32_t reserved16: 16; /*Reserved.*/ - }; - uint32_t val; - } conf; - union { - struct { - uint32_t state: 4; /*Indicates the state of the eFuse state machine.*/ - uint32_t otp_load_sw: 1; /*The value of OTP_LOAD_SW.*/ - uint32_t otp_vddq_c_sync2: 1; /*The value of OTP_VDDQ_C_SYNC2.*/ - uint32_t otp_strobe_sw: 1; /*The value of OTP_STROBE_SW.*/ - uint32_t otp_csb_sw: 1; /*The value of OTP_CSB_SW.*/ - uint32_t otp_pgenb_sw: 1; /*The value of OTP_PGENB_SW.*/ - uint32_t otp_vddq_is_sw: 1; /*The value of OTP_VDDQ_IS_SW.*/ - uint32_t repeat_err_cnt: 8; /*Indicates the number of error bits during programming BLOCK0.*/ - uint32_t reserved18: 14; /*Reserved.*/ - }; - uint32_t val; - } status; - union { - struct { - uint32_t read_cmd: 1; /*Set this bit to send read command.*/ - uint32_t pgm_cmd: 1; /*Set this bit to send programming command.*/ - uint32_t blk_num: 4; /*The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10 respectively.*/ - uint32_t reserved6: 26; /*Reserved.*/ - }; - uint32_t val; - } cmd; - union { - struct { - uint32_t read_done: 1; /*The raw bit signal for read_done interrupt.*/ - uint32_t pgm_done: 1; /*The raw bit signal for pgm_done interrupt.*/ - uint32_t reserved2: 30; /*Reserved.*/ - }; - uint32_t val; - } int_raw; - union { - struct { - uint32_t read_done: 1; /*The status signal for read_done interrupt.*/ - uint32_t pgm_done: 1; /*The status signal for pgm_done interrupt.*/ - uint32_t reserved2: 30; /*Reserved.*/ - }; - uint32_t val; - } int_st; - union { - struct { - uint32_t read_done: 1; /*The enable signal for read_done interrupt.*/ - uint32_t pgm_done: 1; /*The enable signal for pgm_done interrupt.*/ - uint32_t reserved2: 30; /*Reserved.*/ - }; - uint32_t val; - } int_ena; - union { - struct { - uint32_t read_done: 1; /*The clear signal for read_done interrupt.*/ - uint32_t pgm_done: 1; /*The clear signal for pgm_done interrupt.*/ - uint32_t reserved2: 30; /*Reserved.*/ - }; - uint32_t val; - } int_clr; - union { - struct { - uint32_t dac_clk_div: 8; /*Controls the division factor of the rising clock of the programming voltage.*/ - uint32_t dac_clk_pad_sel: 1; /*Don't care.*/ - uint32_t dac_num: 8; /*Controls the rising period of the programming voltage.*/ - uint32_t oe_clr: 1; /*Reduces the power supply of the programming voltage.*/ - uint32_t reserved18: 14; /*Reserved.*/ - }; - uint32_t val; - } dac_conf; - union { - struct { - uint32_t reserved0 : 24; /*Reserved. (Default read timing parameter)*/ - uint32_t reg_read_init_num : 8; /*Configures the initial read time of eFuse.*/ - }; - uint32_t val; - } rd_tim_conf; - uint32_t wr_tim_conf0; - union { - struct { - uint32_t tsup_a: 8; /*Configures the setup time of programming operation.*/ - uint32_t pwr_on_num: 16; /*Configures the power up time for VDDQ.*/ - uint32_t reserved24: 8; /*Reserved.*/ - }; - uint32_t val; - } wr_tim_conf1; - union { - struct { - uint32_t pwr_off_num: 16; /*Configures the power outage time for VDDQ.*/ - uint32_t reserved16: 16; /*Reserved.*/ - }; - uint32_t val; - } wr_tim_conf2; - union { - struct { - uint32_t date: 28; /*Stores eFuse version.*/ - uint32_t reserved28: 4; /*Reserved.*/ - }; - uint32_t val; - } date; +/** Group: PGM Data Register */ +/** Type of pgm_data0 register + * Register 0 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit data to be programmed. + */ + uint32_t pgm_data_0:32; + }; + uint32_t val; +} efuse_pgm_data0_reg_t; + +/** Type of pgm_data1 register + * Register 1 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1st 32-bit data to be programmed. + */ + uint32_t pgm_data_1:32; + }; + uint32_t val; +} efuse_pgm_data1_reg_t; + +/** Type of pgm_data2 register + * Register 2 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2nd 32-bit data to be programmed. + */ + uint32_t pgm_data_2:32; + }; + uint32_t val; +} efuse_pgm_data2_reg_t; + +/** Type of pgm_data3 register + * Register 3 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0; + * The content of the 3rd 32-bit data to be programmed. + */ + uint32_t pgm_data_3:32; + }; + uint32_t val; +} efuse_pgm_data3_reg_t; + +/** Type of pgm_data4 register + * Register 4 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0; + * The content of the 4th 32-bit data to be programmed. + */ + uint32_t pgm_data_4:32; + }; + uint32_t val; +} efuse_pgm_data4_reg_t; + +/** Type of pgm_data5 register + * Register 5 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0; + * The content of the 5th 32-bit data to be programmed. + */ + uint32_t pgm_data_5:32; + }; + uint32_t val; +} efuse_pgm_data5_reg_t; + +/** Type of pgm_data6 register + * Register 6 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0; + * The content of the 6th 32-bit data to be programmed. + */ + uint32_t pgm_data_6:32; + }; + uint32_t val; +} efuse_pgm_data6_reg_t; + +/** Type of pgm_data7 register + * Register 7 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0; + * The content of the 7th 32-bit data to be programmed. + */ + uint32_t pgm_data_7:32; + }; + uint32_t val; +} efuse_pgm_data7_reg_t; + +/** Type of pgm_check_value0 register + * Register 0 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_0:32; + }; + uint32_t val; +} efuse_pgm_check_value0_reg_t; + +/** Type of pgm_check_value1 register + * Register 1 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1st 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_1:32; + }; + uint32_t val; +} efuse_pgm_check_value1_reg_t; + +/** Type of pgm_check_value2 register + * Register 2 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2nd 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_2:32; + }; + uint32_t val; +} efuse_pgm_check_value2_reg_t; + + +/** Group: Read Data Register */ +/** Type of rd_wr_dis register + * BLOCK0 data register 0. + */ +typedef union { + struct { + /** wr_dis : RO; bitpos: [31:0]; default: 0; + * Disable programming of individual eFuses. + */ + uint32_t wr_dis:32; + }; + uint32_t val; +} efuse_rd_wr_dis_reg_t; + +/** Type of rd_repeat_data0 register + * BLOCK0 data register 1. + */ +typedef union { + struct { + /** rd_dis : RO; bitpos: [6:0]; default: 0; + * Set this bit to disable reading from BlOCK4-10. + */ + uint32_t rd_dis:7; + /** dis_rtc_ram_boot : RO; bitpos: [7]; default: 0; + * Set this bit to disable boot from RTC RAM. + */ + uint32_t dis_rtc_ram_boot:1; + /** dis_icache : RO; bitpos: [8]; default: 0; + * Set this bit to disable Icache. + */ + uint32_t dis_icache:1; + /** dis_dcache : RO; bitpos: [9]; default: 0; + * Set this bit to disable Dcache. + */ + uint32_t dis_dcache:1; + /** dis_download_icache : RO; bitpos: [10]; default: 0; + * Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, + * 7). + */ + uint32_t dis_download_icache:1; + /** dis_download_dcache : RO; bitpos: [11]; default: 0; + * Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0, 1, 2, 3, 6, + * 7). + */ + uint32_t dis_download_dcache:1; + /** dis_force_download : RO; bitpos: [12]; default: 0; + * Set this bit to disable the function that forces chip into download mode. + */ + uint32_t dis_force_download:1; + /** dis_usb_otg : RO; bitpos: [13]; default: 0; + * Set this bit to disable USB function. + */ + uint32_t dis_usb_otg:1; + /** dis_twai : RO; bitpos: [14]; default: 0; + * Set this bit to disable CAN function. + */ + uint32_t dis_twai:1; + /** dis_app_cpu : RO; bitpos: [15]; default: 0; + * Disable app cpu. + */ + uint32_t dis_app_cpu:1; + /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0; + * Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG + * can be enabled in HMAC module. + */ + uint32_t soft_dis_jtag:3; + /** dis_pad_jtag : RO; bitpos: [19]; default: 0; + * Set this bit to disable JTAG in the hard way. JTAG is disabled permanently. + */ + uint32_t dis_pad_jtag:1; + /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0; + * Set this bit to disable flash encryption when in download boot modes. + */ + uint32_t dis_download_manual_encrypt:1; + /** usb_drefh : RO; bitpos: [22:21]; default: 0; + * Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored + * in eFuse. + */ + uint32_t usb_drefh:2; + /** usb_drefl : RO; bitpos: [24:23]; default: 0; + * Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, + * stored in eFuse. + */ + uint32_t usb_drefl:2; + /** usb_exchg_pins : RO; bitpos: [25]; default: 0; + * Set this bit to exchange USB D+ and D- pins. + */ + uint32_t usb_exchg_pins:1; + /** usb_ext_phy_enable : RO; bitpos: [26]; default: 0; + * Set this bit to enable external PHY. + */ + uint32_t usb_ext_phy_enable:1; + /** btlc_gpio_enable : RO; bitpos: [28:27]; default: 0; + * Bluetooth GPIO signal output security level control. + */ + uint32_t btlc_gpio_enable:2; + /** vdd_spi_modecurlim : RO; bitpos: [29]; default: 0; + * SPI regulator switches current limit mode. + */ + uint32_t vdd_spi_modecurlim:1; + /** vdd_spi_drefh : RO; bitpos: [31:30]; default: 0; + * SPI regulator high voltage reference. + */ + uint32_t vdd_spi_drefh:2; + }; + uint32_t val; +} efuse_rd_repeat_data0_reg_t; + +/** Type of rd_repeat_data1 register + * BLOCK0 data register 2. + */ +typedef union { + struct { + /** vdd_spi_drefm : RO; bitpos: [1:0]; default: 0; + * SPI regulator medium voltage reference. + */ + uint32_t vdd_spi_drefm:2; + /** vdd_spi_drefl : RO; bitpos: [3:2]; default: 0; + * SPI regulator low voltage reference. + */ + uint32_t vdd_spi_drefl:2; + /** vdd_spi_xpd : RO; bitpos: [4]; default: 0; + * SPI regulator power up signal. + */ + uint32_t vdd_spi_xpd:1; + /** vdd_spi_tieh : RO; bitpos: [5]; default: 0; + * SPI regulator output is short connected to VDD3P3_RTC_IO. + */ + uint32_t vdd_spi_tieh:1; + /** vdd_spi_force : RO; bitpos: [6]; default: 0; + * Set this bit and force to use the configuration of eFuse to configure VDD_SPI. + */ + uint32_t vdd_spi_force:1; + /** vdd_spi_en_init : RO; bitpos: [7]; default: 0; + * Set SPI regulator to 0 to configure init[1:0]=0. + */ + uint32_t vdd_spi_en_init:1; + /** vdd_spi_encurlim : RO; bitpos: [8]; default: 0; + * Set SPI regulator to 1 to enable output current limit. + */ + uint32_t vdd_spi_encurlim:1; + /** vdd_spi_dcurlim : RO; bitpos: [11:9]; default: 0; + * Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d). + */ + uint32_t vdd_spi_dcurlim:3; + /** vdd_spi_init : RO; bitpos: [13:12]; default: 0; + * Adds resistor from LDO output to ground. 0: no resistance 1: 6 K 2: 4 K 3: 2 K. + */ + uint32_t vdd_spi_init:2; + /** vdd_spi_dcap : RO; bitpos: [15:14]; default: 0; + * Prevents SPI regulator from overshoot. + */ + uint32_t vdd_spi_dcap:2; + /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0; + * Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: + * 80000. 2: 160000. 3:320000. + */ + uint32_t wdt_delay_sel:2; + /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0; + * Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even + * number of 1: disable. + */ + uint32_t spi_boot_crypt_cnt:3; + /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0; + * Set this bit to enable revoking first secure boot key. + */ + uint32_t secure_boot_key_revoke0:1; + /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0; + * Set this bit to enable revoking second secure boot key. + */ + uint32_t secure_boot_key_revoke1:1; + /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0; + * Set this bit to enable revoking third secure boot key. + */ + uint32_t secure_boot_key_revoke2:1; + /** key_purpose_0 : RO; bitpos: [27:24]; default: 0; + * Purpose of Key0. + */ + uint32_t key_purpose_0:4; + /** key_purpose_1 : RO; bitpos: [31:28]; default: 0; + * Purpose of Key1. + */ + uint32_t key_purpose_1:4; + }; + uint32_t val; +} efuse_rd_repeat_data1_reg_t; + +/** Type of rd_repeat_data2 register + * BLOCK0 data register 3. + */ +typedef union { + struct { + /** key_purpose_2 : RO; bitpos: [3:0]; default: 0; + * Purpose of Key2. + */ + uint32_t key_purpose_2:4; + /** key_purpose_3 : RO; bitpos: [7:4]; default: 0; + * Purpose of Key3. + */ + uint32_t key_purpose_3:4; + /** key_purpose_4 : RO; bitpos: [11:8]; default: 0; + * Purpose of Key4. + */ + uint32_t key_purpose_4:4; + /** key_purpose_5 : RO; bitpos: [15:12]; default: 0; + * Purpose of Key5. + */ + uint32_t key_purpose_5:4; + /** rpt4_reserved0 : RO; bitpos: [19:16]; default: 0; + * Reserved (used for four backups method). + */ + uint32_t rpt4_reserved0:4; + /** secure_boot_en : RO; bitpos: [20]; default: 0; + * Set this bit to enable secure boot. + */ + uint32_t secure_boot_en:1; + /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0; + * Set this bit to enable revoking aggressive secure boot. + */ + uint32_t secure_boot_aggressive_revoke:1; + /** dis_usb_jtag : RO; bitpos: [22]; default: 0; + * Set this bit to disable function of usb switch to jtag in module of usb device. + */ + uint32_t dis_usb_jtag:1; + /** dis_usb_serial_jtag : RO; bitpos: [23]; default: 0; + * Set this bit to disable usb device. + */ + uint32_t dis_usb_serial_jtag:1; + /** strap_jtag_sel : RO; bitpos: [24]; default: 0; + * Set this bit to enable selection between usb_to_jtag and pad_to_jtag through + * strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0. + */ + uint32_t strap_jtag_sel:1; + /** usb_phy_sel : RO; bitpos: [25]; default: 0; + * This bit is used to switch internal PHY and external PHY for USB OTG and USB + * Device. 0: internal PHY is assigned to USB Device while external PHY is assigned to + * USB OTG. 1: internal PHY is assigned to USB OTG while external PHY is assigned to + * USB Device. + */ + uint32_t usb_phy_sel:1; + /** power_glitch_dsense : RO; bitpos: [27:26]; default: 0; + * Sample delay configuration of power glitch. + */ + uint32_t power_glitch_dsense:2; + /** flash_tpuw : RO; bitpos: [31:28]; default: 0; + * Configures flash waiting time after power-up, in unit of ms. If the value is less + * than 15, the waiting time is the configurable value. Otherwise, the waiting time + * is twice the configurable value. + */ + uint32_t flash_tpuw:4; + }; + uint32_t val; +} efuse_rd_repeat_data2_reg_t; + +/** Type of rd_repeat_data3 register + * BLOCK0 data register 4. + */ +typedef union { + struct { + /** dis_download_mode : RO; bitpos: [0]; default: 0; + * Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7). + */ + uint32_t dis_download_mode:1; + /** dis_direct_boot : RO; bitpos: [1]; default: 0; + * Disable direct boot mode + */ + uint32_t dis_direct_boot:1; + /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0; + * Selectes the default UART print channel. 0: UART0. 1: UART1. + */ + uint32_t dis_usb_serial_jtag_rom_print:1; + /** flash_ecc_mode : RO; bitpos: [3]; default: 0; + * Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would + * use 16to17 byte mode. + */ + uint32_t flash_ecc_mode:1; + /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0; + * Set this bit to disable UART download mode through USB. + */ + uint32_t dis_usb_serial_jtag_download_mode:1; + /** enable_security_download : RO; bitpos: [5]; default: 0; + * Set this bit to enable secure UART download mode. + */ + uint32_t enable_security_download:1; + /** uart_print_control : RO; bitpos: [7:6]; default: 0; + * Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 + * is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled. + */ + uint32_t uart_print_control:2; + /** pin_power_selection : RO; bitpos: [8]; default: 0; + * GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI. + */ + uint32_t pin_power_selection:1; + /** flash_type : RO; bitpos: [9]; default: 0; + * Set the maximum lines of SPI flash. 0: four lines. 1: eight lines. + */ + uint32_t flash_type:1; + /** flash_page_size : RO; bitpos: [11:10]; default: 0; + * Set Flash page size. + */ + uint32_t flash_page_size:2; + /** flash_ecc_en : RO; bitpos: [12]; default: 0; + * Set 1 to enable ECC for flash boot. + */ + uint32_t flash_ecc_en:1; + /** force_send_resume : RO; bitpos: [13]; default: 0; + * Set this bit to force ROM code to send a resume command during SPI boot. + */ + uint32_t force_send_resume:1; + /** secure_version : RO; bitpos: [29:14]; default: 0; + * Secure version (used by ESP-IDF anti-rollback feature). + */ + uint32_t secure_version:16; + /** powerglitch_en : RO; bitpos: [30]; default: 0; + * Set this bit to enable power glitch function. + */ + uint32_t powerglitch_en:1; + /** dis_usb_otg_download_mode : R; bitpos: [31]; default: 0; + * Set this bit to disable download through USB-OTG + */ + uint32_t dis_usb_otg_download_mode:1; + }; + uint32_t val; +} efuse_rd_repeat_data3_reg_t; + +/** Type of rd_repeat_data4 register + * BLOCK0 data register 5. + */ +typedef union { + struct { + /** disable_wafer_version_major : R; bitpos: [0]; default: 0; + * Disables check of wafer version major + */ + uint32_t disable_wafer_version_major:1; + /** disable_blk_version_major : R; bitpos: [1]; default: 0; + * Disables check of blk version major + */ + uint32_t disable_blk_version_major:1; + /** reserved_0_162 : R; bitpos: [23:2]; default: 0; + * reserved + */ + uint32_t reserved_0_162:22; + uint32_t reserved_24:8; + }; + uint32_t val; +} efuse_rd_repeat_data4_reg_t; + +/** Type of rd_mac_spi_sys_0 register + * BLOCK1 data register 0. + */ +typedef union { + struct { + /** mac_0 : RO; bitpos: [31:0]; default: 0; + * Stores the low 32 bits of MAC address. + */ + uint32_t mac_0:32; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_0_reg_t; + +/** Type of rd_mac_spi_sys_1 register + * BLOCK1 data register 1. + */ +typedef union { + struct { + /** mac_1 : RO; bitpos: [15:0]; default: 0; + * Stores the high 16 bits of MAC address. + */ + uint32_t mac_1:16; + /** spi_pad_config_clk : R; bitpos: [21:16]; default: 0; + * SPI_PAD_configure CLK + */ + uint32_t spi_pad_config_clk:6; + /** spi_pad_config_q : R; bitpos: [27:22]; default: 0; + * SPI_PAD_configure Q(D1) + */ + uint32_t spi_pad_config_q:6; + /** spi_pad_config_d : R; bitpos: [31:28]; default: 0; + * SPI_PAD_configure D(D0) + */ + uint32_t spi_pad_config_d:4; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_1_reg_t; + +/** Type of rd_mac_spi_sys_2 register + * BLOCK1 data register 2. + */ +typedef union { + struct { + /** spi_pad_config_d_1 : R; bitpos: [1:0]; default: 0; + * SPI_PAD_configure D(D0) + */ + uint32_t spi_pad_config_d_1:2; + /** spi_pad_config_cs : R; bitpos: [7:2]; default: 0; + * SPI_PAD_configure CS + */ + uint32_t spi_pad_config_cs:6; + /** spi_pad_config_hd : R; bitpos: [13:8]; default: 0; + * SPI_PAD_configure HD(D3) + */ + uint32_t spi_pad_config_hd:6; + /** spi_pad_config_wp : R; bitpos: [19:14]; default: 0; + * SPI_PAD_configure WP(D2) + */ + uint32_t spi_pad_config_wp:6; + /** spi_pad_config_dqs : R; bitpos: [25:20]; default: 0; + * SPI_PAD_configure DQS + */ + uint32_t spi_pad_config_dqs:6; + /** spi_pad_config_d4 : R; bitpos: [31:26]; default: 0; + * SPI_PAD_configure D4 + */ + uint32_t spi_pad_config_d4:6; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_2_reg_t; + +/** Type of rd_mac_spi_sys_3 register + * BLOCK1 data register 3. + */ +typedef union { + struct { + /** spi_pad_config_d5 : R; bitpos: [5:0]; default: 0; + * SPI_PAD_configure D5 + */ + uint32_t spi_pad_config_d5:6; + /** spi_pad_config_d6 : R; bitpos: [11:6]; default: 0; + * SPI_PAD_configure D6 + */ + uint32_t spi_pad_config_d6:6; + /** spi_pad_config_d7 : R; bitpos: [17:12]; default: 0; + * SPI_PAD_configure D7 + */ + uint32_t spi_pad_config_d7:6; + /** wafer_version_minor_lo : R; bitpos: [20:18]; default: 0; + * WAFER_VERSION_MINOR least significant bits + */ + uint32_t wafer_version_minor_lo:3; + /** pkg_version : R; bitpos: [23:21]; default: 0; + * Package version + */ + uint32_t pkg_version:3; + /** blk_version_minor : R; bitpos: [26:24]; default: 0; + * BLK_VERSION_MINOR + */ + uint32_t blk_version_minor:3; + /** reserved_1_123 : R; bitpos: [31:27]; default: 0; + * reserved + */ + uint32_t reserved_1_123:5; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_3_reg_t; + +/** Type of rd_mac_spi_sys_4 register + * BLOCK1 data register 4. + */ +typedef union { + struct { + /** reserved_1_128 : R; bitpos: [12:0]; default: 0; + * reserved + */ + uint32_t reserved_1_128:13; + /** k_rtc_ldo : R; bitpos: [19:13]; default: 0; + * BLOCK1 K_RTC_LDO + */ + uint32_t k_rtc_ldo:7; + /** k_dig_ldo : R; bitpos: [26:20]; default: 0; + * BLOCK1 K_DIG_LDO + */ + uint32_t k_dig_ldo:7; + /** v_rtc_dbias20 : R; bitpos: [31:27]; default: 0; + * BLOCK1 voltage of rtc dbias20 + */ + uint32_t v_rtc_dbias20:5; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_4_reg_t; + +/** Type of rd_mac_spi_sys_5 register + * BLOCK1 data register 5. + */ +typedef union { + struct { + /** v_rtc_dbias20_1 : R; bitpos: [2:0]; default: 0; + * BLOCK1 voltage of rtc dbias20 + */ + uint32_t v_rtc_dbias20_1:3; + /** v_dig_dbias20 : R; bitpos: [10:3]; default: 0; + * BLOCK1 voltage of digital dbias20 + */ + uint32_t v_dig_dbias20:8; + /** dig_dbias_hvt : R; bitpos: [15:11]; default: 0; + * BLOCK1 digital dbias when hvt + */ + uint32_t dig_dbias_hvt:5; + /** reserved_1_176 : R; bitpos: [22:16]; default: 0; + * reserved + */ + uint32_t reserved_1_176:7; + /** wafer_version_minor_hi : R; bitpos: [23]; default: 0; + * WAFER_VERSION_MINOR most significant bit + */ + uint32_t wafer_version_minor_hi:1; + /** wafer_version_major : R; bitpos: [25:24]; default: 0; + * WAFER_VERSION_MAJOR + */ + uint32_t wafer_version_major:2; + /** adc2_cal_vol_atten3 : R; bitpos: [31:26]; default: 0; + * ADC2 calibration voltage at atten3 + */ + uint32_t adc2_cal_vol_atten3:6; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_5_reg_t; + +/** Type of rd_sys_part1_data0 register + * Register 0 of BLOCK2 (system). + */ +typedef union { + struct { + /** optional_unique_id : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data0_reg_t; + +/** Type of rd_sys_part1_data1 register + * Register 1 of BLOCK2 (system). + */ +typedef union { + struct { + /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id_1:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data1_reg_t; + +/** Type of rd_sys_part1_data2 register + * Register 2 of BLOCK2 (system). + */ +typedef union { + struct { + /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id_2:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data2_reg_t; + +/** Type of rd_sys_part1_data3 register + * Register 3 of BLOCK2 (system). + */ +typedef union { + struct { + /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id_3:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data3_reg_t; + +/** Type of rd_sys_part1_data4 register + * Register 4 of BLOCK2 (system). + */ +typedef union { + struct { + /** blk_version_major : R; bitpos: [1:0]; default: 0; + * BLK_VERSION_MAJOR of BLOCK2 change of this bit means users need to update firmware + */ + uint32_t blk_version_major:2; + /** reserved_2_130 : R; bitpos: [3:2]; default: 0; + * reserved + */ + uint32_t reserved_2_130:2; + /** temp_calib : R; bitpos: [12:4]; default: 0; + * Temperature calibration data + */ + uint32_t temp_calib:9; + /** ocode : R; bitpos: [20:13]; default: 0; + * ADC OCode + */ + uint32_t ocode:8; + /** adc1_init_code_atten0 : R; bitpos: [28:21]; default: 0; + * ADC1 init code at atten0 + */ + uint32_t adc1_init_code_atten0:8; + /** adc1_init_code_atten1 : R; bitpos: [31:29]; default: 0; + * ADC1 init code at atten1 + */ + uint32_t adc1_init_code_atten1:3; + }; + uint32_t val; +} efuse_rd_sys_part1_data4_reg_t; + +/** Type of rd_sys_part1_data5 register + * Register 5 of BLOCK2 (system). + */ +typedef union { + struct { + /** adc1_init_code_atten1_1 : R; bitpos: [2:0]; default: 0; + * ADC1 init code at atten1 + */ + uint32_t adc1_init_code_atten1_1:3; + /** adc1_init_code_atten2 : R; bitpos: [8:3]; default: 0; + * ADC1 init code at atten2 + */ + uint32_t adc1_init_code_atten2:6; + /** adc1_init_code_atten3 : R; bitpos: [14:9]; default: 0; + * ADC1 init code at atten3 + */ + uint32_t adc1_init_code_atten3:6; + /** adc2_init_code_atten0 : R; bitpos: [22:15]; default: 0; + * ADC2 init code at atten0 + */ + uint32_t adc2_init_code_atten0:8; + /** adc2_init_code_atten1 : R; bitpos: [28:23]; default: 0; + * ADC2 init code at atten1 + */ + uint32_t adc2_init_code_atten1:6; + /** adc2_init_code_atten2 : R; bitpos: [31:29]; default: 0; + * ADC2 init code at atten2 + */ + uint32_t adc2_init_code_atten2:3; + }; + uint32_t val; +} efuse_rd_sys_part1_data5_reg_t; + +/** Type of rd_sys_part1_data6 register + * Register 6 of BLOCK2 (system). + */ +typedef union { + struct { + /** adc2_init_code_atten2_1 : R; bitpos: [2:0]; default: 0; + * ADC2 init code at atten2 + */ + uint32_t adc2_init_code_atten2_1:3; + /** adc2_init_code_atten3 : R; bitpos: [8:3]; default: 0; + * ADC2 init code at atten3 + */ + uint32_t adc2_init_code_atten3:6; + /** adc1_cal_vol_atten0 : R; bitpos: [16:9]; default: 0; + * ADC1 calibration voltage at atten0 + */ + uint32_t adc1_cal_vol_atten0:8; + /** adc1_cal_vol_atten1 : R; bitpos: [24:17]; default: 0; + * ADC1 calibration voltage at atten1 + */ + uint32_t adc1_cal_vol_atten1:8; + /** adc1_cal_vol_atten2 : R; bitpos: [31:25]; default: 0; + * ADC1 calibration voltage at atten2 + */ + uint32_t adc1_cal_vol_atten2:7; + }; + uint32_t val; +} efuse_rd_sys_part1_data6_reg_t; + +/** Type of rd_sys_part1_data7 register + * Register 7 of BLOCK2 (system). + */ +typedef union { + struct { + /** adc1_cal_vol_atten2_1 : R; bitpos: [0]; default: 0; + * ADC1 calibration voltage at atten2 + */ + uint32_t adc1_cal_vol_atten2_1:1; + /** adc1_cal_vol_atten3 : R; bitpos: [8:1]; default: 0; + * ADC1 calibration voltage at atten3 + */ + uint32_t adc1_cal_vol_atten3:8; + /** adc2_cal_vol_atten0 : R; bitpos: [16:9]; default: 0; + * ADC2 calibration voltage at atten0 + */ + uint32_t adc2_cal_vol_atten0:8; + /** adc2_cal_vol_atten1 : R; bitpos: [23:17]; default: 0; + * ADC2 calibration voltage at atten1 + */ + uint32_t adc2_cal_vol_atten1:7; + /** adc2_cal_vol_atten2 : R; bitpos: [30:24]; default: 0; + * ADC2 calibration voltage at atten2 + */ + uint32_t adc2_cal_vol_atten2:7; + /** reserved_2_255 : R; bitpos: [31]; default: 0; + * reserved + */ + uint32_t reserved_2_255:1; + }; + uint32_t val; +} efuse_rd_sys_part1_data7_reg_t; + +/** Type of rd_usr_data0 register + * Register 0 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data0:32; + }; + uint32_t val; +} efuse_rd_usr_data0_reg_t; + +/** Type of rd_usr_data1 register + * Register 1 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of BLOCK3 (user). + */ + uint32_t usr_data1:32; + }; + uint32_t val; +} efuse_rd_usr_data1_reg_t; + +/** Type of rd_usr_data2 register + * Register 2 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of BLOCK3 (user). + */ + uint32_t usr_data2:32; + }; + uint32_t val; +} efuse_rd_usr_data2_reg_t; + +/** Type of rd_usr_data3 register + * Register 3 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of BLOCK3 (user). + */ + uint32_t usr_data3:32; + }; + uint32_t val; +} efuse_rd_usr_data3_reg_t; + +/** Type of rd_usr_data4 register + * Register 4 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data4:32; + }; + uint32_t val; +} efuse_rd_usr_data4_reg_t; + +/** Type of rd_usr_data5 register + * Register 5 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data5:32; + }; + uint32_t val; +} efuse_rd_usr_data5_reg_t; + +/** Type of rd_usr_data6 register + * Register 6 of BLOCK3 (user). + */ +typedef union { + struct { + /** reserved_3_192 : R; bitpos: [7:0]; default: 0; + * reserved + */ + uint32_t reserved_3_192:8; + /** custom_mac : R; bitpos: [31:8]; default: 0; + * Custom MAC + */ + uint32_t custom_mac:24; + }; + uint32_t val; +} efuse_rd_usr_data6_reg_t; + +/** Type of rd_usr_data7 register + * Register 7 of BLOCK3 (user). + */ +typedef union { + struct { + /** custom_mac_1 : R; bitpos: [23:0]; default: 0; + * Custom MAC + */ + uint32_t custom_mac_1:24; + /** reserved_3_248 : R; bitpos: [31:24]; default: 0; + * reserved + */ + uint32_t reserved_3_248:8; + }; + uint32_t val; +} efuse_rd_usr_data7_reg_t; + +/** Type of rd_key0_data0 register + * Register 0 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY0. + */ + uint32_t key0_data0:32; + }; + uint32_t val; +} efuse_rd_key0_data0_reg_t; + +/** Type of rd_key0_data1 register + * Register 1 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY0. + */ + uint32_t key0_data1:32; + }; + uint32_t val; +} efuse_rd_key0_data1_reg_t; + +/** Type of rd_key0_data2 register + * Register 2 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY0. + */ + uint32_t key0_data2:32; + }; + uint32_t val; +} efuse_rd_key0_data2_reg_t; + +/** Type of rd_key0_data3 register + * Register 3 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY0. + */ + uint32_t key0_data3:32; + }; + uint32_t val; +} efuse_rd_key0_data3_reg_t; + +/** Type of rd_key0_data4 register + * Register 4 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY0. + */ + uint32_t key0_data4:32; + }; + uint32_t val; +} efuse_rd_key0_data4_reg_t; + +/** Type of rd_key0_data5 register + * Register 5 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY0. + */ + uint32_t key0_data5:32; + }; + uint32_t val; +} efuse_rd_key0_data5_reg_t; + +/** Type of rd_key0_data6 register + * Register 6 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY0. + */ + uint32_t key0_data6:32; + }; + uint32_t val; +} efuse_rd_key0_data6_reg_t; + +/** Type of rd_key0_data7 register + * Register 7 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY0. + */ + uint32_t key0_data7:32; + }; + uint32_t val; +} efuse_rd_key0_data7_reg_t; + +/** Type of rd_key1_data0 register + * Register 0 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY1. + */ + uint32_t key1_data0:32; + }; + uint32_t val; +} efuse_rd_key1_data0_reg_t; + +/** Type of rd_key1_data1 register + * Register 1 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY1. + */ + uint32_t key1_data1:32; + }; + uint32_t val; +} efuse_rd_key1_data1_reg_t; + +/** Type of rd_key1_data2 register + * Register 2 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY1. + */ + uint32_t key1_data2:32; + }; + uint32_t val; +} efuse_rd_key1_data2_reg_t; + +/** Type of rd_key1_data3 register + * Register 3 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY1. + */ + uint32_t key1_data3:32; + }; + uint32_t val; +} efuse_rd_key1_data3_reg_t; + +/** Type of rd_key1_data4 register + * Register 4 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY1. + */ + uint32_t key1_data4:32; + }; + uint32_t val; +} efuse_rd_key1_data4_reg_t; + +/** Type of rd_key1_data5 register + * Register 5 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY1. + */ + uint32_t key1_data5:32; + }; + uint32_t val; +} efuse_rd_key1_data5_reg_t; + +/** Type of rd_key1_data6 register + * Register 6 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY1. + */ + uint32_t key1_data6:32; + }; + uint32_t val; +} efuse_rd_key1_data6_reg_t; + +/** Type of rd_key1_data7 register + * Register 7 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY1. + */ + uint32_t key1_data7:32; + }; + uint32_t val; +} efuse_rd_key1_data7_reg_t; + +/** Type of rd_key2_data0 register + * Register 0 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY2. + */ + uint32_t key2_data0:32; + }; + uint32_t val; +} efuse_rd_key2_data0_reg_t; + +/** Type of rd_key2_data1 register + * Register 1 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY2. + */ + uint32_t key2_data1:32; + }; + uint32_t val; +} efuse_rd_key2_data1_reg_t; + +/** Type of rd_key2_data2 register + * Register 2 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY2. + */ + uint32_t key2_data2:32; + }; + uint32_t val; +} efuse_rd_key2_data2_reg_t; + +/** Type of rd_key2_data3 register + * Register 3 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY2. + */ + uint32_t key2_data3:32; + }; + uint32_t val; +} efuse_rd_key2_data3_reg_t; + +/** Type of rd_key2_data4 register + * Register 4 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY2. + */ + uint32_t key2_data4:32; + }; + uint32_t val; +} efuse_rd_key2_data4_reg_t; + +/** Type of rd_key2_data5 register + * Register 5 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY2. + */ + uint32_t key2_data5:32; + }; + uint32_t val; +} efuse_rd_key2_data5_reg_t; + +/** Type of rd_key2_data6 register + * Register 6 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY2. + */ + uint32_t key2_data6:32; + }; + uint32_t val; +} efuse_rd_key2_data6_reg_t; + +/** Type of rd_key2_data7 register + * Register 7 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY2. + */ + uint32_t key2_data7:32; + }; + uint32_t val; +} efuse_rd_key2_data7_reg_t; + +/** Type of rd_key3_data0 register + * Register 0 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY3. + */ + uint32_t key3_data0:32; + }; + uint32_t val; +} efuse_rd_key3_data0_reg_t; + +/** Type of rd_key3_data1 register + * Register 1 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY3. + */ + uint32_t key3_data1:32; + }; + uint32_t val; +} efuse_rd_key3_data1_reg_t; + +/** Type of rd_key3_data2 register + * Register 2 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY3. + */ + uint32_t key3_data2:32; + }; + uint32_t val; +} efuse_rd_key3_data2_reg_t; + +/** Type of rd_key3_data3 register + * Register 3 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY3. + */ + uint32_t key3_data3:32; + }; + uint32_t val; +} efuse_rd_key3_data3_reg_t; + +/** Type of rd_key3_data4 register + * Register 4 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY3. + */ + uint32_t key3_data4:32; + }; + uint32_t val; +} efuse_rd_key3_data4_reg_t; + +/** Type of rd_key3_data5 register + * Register 5 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY3. + */ + uint32_t key3_data5:32; + }; + uint32_t val; +} efuse_rd_key3_data5_reg_t; + +/** Type of rd_key3_data6 register + * Register 6 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY3. + */ + uint32_t key3_data6:32; + }; + uint32_t val; +} efuse_rd_key3_data6_reg_t; + +/** Type of rd_key3_data7 register + * Register 7 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY3. + */ + uint32_t key3_data7:32; + }; + uint32_t val; +} efuse_rd_key3_data7_reg_t; + +/** Type of rd_key4_data0 register + * Register 0 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY4. + */ + uint32_t key4_data0:32; + }; + uint32_t val; +} efuse_rd_key4_data0_reg_t; + +/** Type of rd_key4_data1 register + * Register 1 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY4. + */ + uint32_t key4_data1:32; + }; + uint32_t val; +} efuse_rd_key4_data1_reg_t; + +/** Type of rd_key4_data2 register + * Register 2 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY4. + */ + uint32_t key4_data2:32; + }; + uint32_t val; +} efuse_rd_key4_data2_reg_t; + +/** Type of rd_key4_data3 register + * Register 3 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY4. + */ + uint32_t key4_data3:32; + }; + uint32_t val; +} efuse_rd_key4_data3_reg_t; + +/** Type of rd_key4_data4 register + * Register 4 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY4. + */ + uint32_t key4_data4:32; + }; + uint32_t val; +} efuse_rd_key4_data4_reg_t; + +/** Type of rd_key4_data5 register + * Register 5 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY4. + */ + uint32_t key4_data5:32; + }; + uint32_t val; +} efuse_rd_key4_data5_reg_t; + +/** Type of rd_key4_data6 register + * Register 6 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY4. + */ + uint32_t key4_data6:32; + }; + uint32_t val; +} efuse_rd_key4_data6_reg_t; + +/** Type of rd_key4_data7 register + * Register 7 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY4. + */ + uint32_t key4_data7:32; + }; + uint32_t val; +} efuse_rd_key4_data7_reg_t; + +/** Type of rd_key5_data0 register + * Register 0 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY5. + */ + uint32_t key5_data0:32; + }; + uint32_t val; +} efuse_rd_key5_data0_reg_t; + +/** Type of rd_key5_data1 register + * Register 1 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY5. + */ + uint32_t key5_data1:32; + }; + uint32_t val; +} efuse_rd_key5_data1_reg_t; + +/** Type of rd_key5_data2 register + * Register 2 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY5. + */ + uint32_t key5_data2:32; + }; + uint32_t val; +} efuse_rd_key5_data2_reg_t; + +/** Type of rd_key5_data3 register + * Register 3 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY5. + */ + uint32_t key5_data3:32; + }; + uint32_t val; +} efuse_rd_key5_data3_reg_t; + +/** Type of rd_key5_data4 register + * Register 4 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY5. + */ + uint32_t key5_data4:32; + }; + uint32_t val; +} efuse_rd_key5_data4_reg_t; + +/** Type of rd_key5_data5 register + * Register 5 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY5. + */ + uint32_t key5_data5:32; + }; + uint32_t val; +} efuse_rd_key5_data5_reg_t; + +/** Type of rd_key5_data6 register + * Register 6 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY5. + */ + uint32_t key5_data6:32; + }; + uint32_t val; +} efuse_rd_key5_data6_reg_t; + +/** Type of rd_key5_data7 register + * Register 7 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY5. + */ + uint32_t key5_data7:32; + }; + uint32_t val; +} efuse_rd_key5_data7_reg_t; + +/** Type of rd_sys_part2_data0 register + * Register 0 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_0:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data0_reg_t; + +/** Type of rd_sys_part2_data1 register + * Register 1 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1st 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_1:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data1_reg_t; + +/** Type of rd_sys_part2_data2 register + * Register 2 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2nd 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_2:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data2_reg_t; + +/** Type of rd_sys_part2_data3 register + * Register 3 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3rd 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_3:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data3_reg_t; + +/** Type of rd_sys_part2_data4 register + * Register 4 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_4:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data4_reg_t; + +/** Type of rd_sys_part2_data5 register + * Register 5 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_5:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data5_reg_t; + +/** Type of rd_sys_part2_data6 register + * Register 6 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_6:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data6_reg_t; + +/** Type of rd_sys_part2_data7 register + * Register 7 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_7:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data7_reg_t; + + +/** Group: Report Register */ +/** Type of rd_repeat_err0 register + * Programming error record register 0 of BLOCK0. + */ +typedef union { + struct { + /** rd_dis_err : RO; bitpos: [6:0]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t rd_dis_err:7; + /** dis_rtc_ram_boot_err : RO; bitpos: [7]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_rtc_ram_boot_err:1; + /** dis_icache_err : RO; bitpos: [8]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_icache_err:1; + /** dis_dcache_err : RO; bitpos: [9]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_dcache_err:1; + /** dis_download_icache_err : RO; bitpos: [10]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_download_icache_err:1; + /** dis_download_dcache_err : RO; bitpos: [11]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_download_dcache_err:1; + /** dis_force_download_err : RO; bitpos: [12]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_force_download_err:1; + /** dis_usb_err : RO; bitpos: [13]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_usb_err:1; + /** dis_can_err : RO; bitpos: [14]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_can_err:1; + /** dis_app_cpu_err : RO; bitpos: [15]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_app_cpu_err:1; + /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t soft_dis_jtag_err:3; + /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_pad_jtag_err:1; + /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_download_manual_encrypt_err:1; + /** usb_drefh_err : RO; bitpos: [22:21]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t usb_drefh_err:2; + /** usb_drefl_err : RO; bitpos: [24:23]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t usb_drefl_err:2; + /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t usb_exchg_pins_err:1; + /** ext_phy_enable_err : RO; bitpos: [26]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t ext_phy_enable_err:1; + /** btlc_gpio_enable_err : RO; bitpos: [28:27]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t btlc_gpio_enable_err:2; + /** vdd_spi_modecurlim_err : RO; bitpos: [29]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_modecurlim_err:1; + /** vdd_spi_drefh_err : RO; bitpos: [31:30]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_drefh_err:2; + }; + uint32_t val; +} efuse_rd_repeat_err0_reg_t; + +/** Type of rd_repeat_err1 register + * Programming error record register 1 of BLOCK0. + */ +typedef union { + struct { + /** vdd_spi_drefm_err : RO; bitpos: [1:0]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_drefm_err:2; + /** vdd_spi_drefl_err : RO; bitpos: [3:2]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_drefl_err:2; + /** vdd_spi_xpd_err : RO; bitpos: [4]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_xpd_err:1; + /** vdd_spi_tieh_err : RO; bitpos: [5]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_tieh_err:1; + /** vdd_spi_force_err : RO; bitpos: [6]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_force_err:1; + /** vdd_spi_en_init_err : RO; bitpos: [7]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_en_init_err:1; + /** vdd_spi_encurlim_err : RO; bitpos: [8]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_encurlim_err:1; + /** vdd_spi_dcurlim_err : RO; bitpos: [11:9]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_dcurlim_err:3; + /** vdd_spi_init_err : RO; bitpos: [13:12]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_init_err:2; + /** vdd_spi_dcap_err : RO; bitpos: [15:14]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_dcap_err:2; + /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t wdt_delay_sel_err:2; + /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t spi_boot_crypt_cnt_err:3; + /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t secure_boot_key_revoke0_err:1; + /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t secure_boot_key_revoke1_err:1; + /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t secure_boot_key_revoke2_err:1; + /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t key_purpose_0_err:4; + /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t key_purpose_1_err:4; + }; + uint32_t val; +} efuse_rd_repeat_err1_reg_t; + +/** Type of rd_repeat_err2 register + * Programming error record register 2 of BLOCK0. + */ +typedef union { + struct { + /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t key_purpose_2_err:4; + /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t key_purpose_3_err:4; + /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t key_purpose_4_err:4; + /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t key_purpose_5_err:4; + /** rpt4_reserved0_err : RO; bitpos: [19:16]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t rpt4_reserved0_err:4; + /** secure_boot_en_err : RO; bitpos: [20]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t secure_boot_en_err:1; + /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t secure_boot_aggressive_revoke_err:1; + /** dis_usb_jtag_err : RO; bitpos: [22]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_usb_jtag_err:1; + /** dis_usb_device_err : RO; bitpos: [23]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_usb_device_err:1; + /** strap_jtag_sel_err : RO; bitpos: [24]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t strap_jtag_sel_err:1; + /** usb_phy_sel_err : RO; bitpos: [25]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t usb_phy_sel_err:1; + /** power_glitch_dsense_err : RO; bitpos: [27:26]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t power_glitch_dsense_err:2; + /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t flash_tpuw_err:4; + }; + uint32_t val; +} efuse_rd_repeat_err2_reg_t; + +/** Type of rd_repeat_err3 register + * Programming error record register 3 of BLOCK0. + */ +typedef union { + struct { + /** dis_download_mode_err : RO; bitpos: [0]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_download_mode_err:1; + /** dis_legacy_spi_boot_err : RO; bitpos: [1]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_legacy_spi_boot_err:1; + /** uart_print_channel_err : RO; bitpos: [2]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t uart_print_channel_err:1; + /** flash_ecc_mode_err : RO; bitpos: [3]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t flash_ecc_mode_err:1; + /** dis_usb_download_mode_err : RO; bitpos: [4]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_usb_download_mode_err:1; + /** enable_security_download_err : RO; bitpos: [5]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t enable_security_download_err:1; + /** uart_print_control_err : RO; bitpos: [7:6]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t uart_print_control_err:2; + /** pin_power_selection_err : RO; bitpos: [8]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t pin_power_selection_err:1; + /** flash_type_err : RO; bitpos: [9]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t flash_type_err:1; + /** flash_page_size_err : RO; bitpos: [11:10]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t flash_page_size_err:2; + /** flash_ecc_en_err : RO; bitpos: [12]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t flash_ecc_en_err:1; + /** force_send_resume_err : RO; bitpos: [13]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t force_send_resume_err:1; + /** secure_version_err : RO; bitpos: [29:14]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t secure_version_err:16; + /** powerglitch_en_err : RO; bitpos: [30]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t powerglitch_en_err:1; + /** rpt4_reserved1_err : RO; bitpos: [31]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved1_err:1; + }; + uint32_t val; +} efuse_rd_repeat_err3_reg_t; + +/** Type of rd_repeat_err4 register + * Programming error record register 4 of BLOCK0. + */ +typedef union { + struct { + /** rpt4_reserved2_err : RO; bitpos: [23:0]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t rpt4_reserved2_err:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} efuse_rd_repeat_err4_reg_t; + +/** Type of rd_rs_err0 register + * Programming error record register 0 of BLOCK1-10. + */ +typedef union { + struct { + /** mac_spi_8m_err_num : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t mac_spi_8m_err_num:3; + /** mac_spi_8m_fail : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t mac_spi_8m_fail:1; + /** sys_part1_num : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t sys_part1_num:3; + /** sys_part1_fail : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part1 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t sys_part1_fail:1; + /** usr_data_err_num : RO; bitpos: [10:8]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t usr_data_err_num:3; + /** usr_data_fail : RO; bitpos: [11]; default: 0; + * 0: Means no failure and that the user data is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. + */ + uint32_t usr_data_fail:1; + /** key0_err_num : RO; bitpos: [14:12]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key0_err_num:3; + /** key0_fail : RO; bitpos: [15]; default: 0; + * 0: Means no failure and that the data of key0 is reliable 1: Means that programming + * key0 failed and the number of error bytes is over 6. + */ + uint32_t key0_fail:1; + /** key1_err_num : RO; bitpos: [18:16]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key1_err_num:3; + /** key1_fail : RO; bitpos: [19]; default: 0; + * 0: Means no failure and that the data of key1 is reliable 1: Means that programming + * key1 failed and the number of error bytes is over 6. + */ + uint32_t key1_fail:1; + /** key2_err_num : RO; bitpos: [22:20]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key2_err_num:3; + /** key2_fail : RO; bitpos: [23]; default: 0; + * 0: Means no failure and that the data of key2 is reliable 1: Means that programming + * key2 failed and the number of error bytes is over 6. + */ + uint32_t key2_fail:1; + /** key3_err_num : RO; bitpos: [26:24]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key3_err_num:3; + /** key3_fail : RO; bitpos: [27]; default: 0; + * 0: Means no failure and that the data of key3 is reliable 1: Means that programming + * key3 failed and the number of error bytes is over 6. + */ + uint32_t key3_fail:1; + /** key4_err_num : RO; bitpos: [30:28]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key4_err_num:3; + /** key4_fail : RO; bitpos: [31]; default: 0; + * 0: Means no failure and that the data of key4 is reliable 1: Means that programming + * key4 failed and the number of error bytes is over 6. + */ + uint32_t key4_fail:1; + }; + uint32_t val; +} efuse_rd_rs_err0_reg_t; + +/** Type of rd_rs_err1 register + * Programming error record register 1 of BLOCK1-10. + */ +typedef union { + struct { + /** key5_err_num : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key5_err_num:3; + /** key5_fail : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of KEY5 is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. + */ + uint32_t key5_fail:1; + /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t sys_part2_err_num:3; + /** sys_part2_fail : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part2 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t sys_part2_fail:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} efuse_rd_rs_err1_reg_t; + + +/** Group: Configuration Register */ +/** Type of clk register + * eFuse clcok configuration register. + */ +typedef union { + struct { + /** efuse_mem_force_pd : R/W; bitpos: [0]; default: 0; + * Set this bit to force eFuse SRAM into power-saving mode. + */ + uint32_t efuse_mem_force_pd:1; + /** mem_clk_force_on : R/W; bitpos: [1]; default: 1; + * Set this bit and force to activate clock signal of eFuse SRAM. + */ + uint32_t mem_clk_force_on:1; + /** efuse_mem_force_pu : R/W; bitpos: [2]; default: 0; + * Set this bit to force eFuse SRAM into working mode. + */ + uint32_t efuse_mem_force_pu:1; + uint32_t reserved_3:13; + /** clk_en : R/W; bitpos: [16]; default: 0; + * Set this bit and force to enable clock signal of eFuse memory. + */ + uint32_t clk_en:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} efuse_clk_reg_t; + +/** Type of conf register + * eFuse operation mode configuraiton register + */ +typedef union { + struct { + /** op_code : R/W; bitpos: [15:0]; default: 0; + * 0x5A5A: Operate programming command 0x5AA5: Operate read command. + */ + uint32_t op_code:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} efuse_conf_reg_t; + +/** Type of cmd register + * eFuse command register. + */ +typedef union { + struct { + /** read_cmd : R/WS/SC; bitpos: [0]; default: 0; + * Set this bit to send read command. + */ + uint32_t read_cmd:1; + /** pgm_cmd : R/WS/SC; bitpos: [1]; default: 0; + * Set this bit to send programming command. + */ + uint32_t pgm_cmd:1; + /** blk_num : R/W; bitpos: [5:2]; default: 0; + * The serial number of the block to be programmed. Value 0-10 corresponds to block + * number 0-10, respectively. + */ + uint32_t blk_num:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} efuse_cmd_reg_t; + +/** Type of dac_conf register + * Controls the eFuse programming voltage. + */ +typedef union { + struct { + /** dac_clk_div : R/W; bitpos: [7:0]; default: 28; + * Controls the division factor of the rising clock of the programming voltage. + */ + uint32_t dac_clk_div:8; + /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; + * Don't care. + */ + uint32_t dac_clk_pad_sel:1; + /** dac_num : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ + uint32_t dac_num:8; + /** oe_clr : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ + uint32_t oe_clr:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} efuse_dac_conf_reg_t; + +/** Type of rd_tim_conf register + * Configures read timing parameters. + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** read_init_num : R/W; bitpos: [31:24]; default: 18; + * Configures the initial read time of eFuse. + */ + uint32_t read_init_num:8; + }; + uint32_t val; +} efuse_rd_tim_conf_reg_t; + +/** Type of wr_tim_conf1 register + * Configurarion register 1 of eFuse programming timing parameters. + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** pwr_on_num : R/W; bitpos: [23:8]; default: 10368; + * Configures the power up time for VDDQ. + */ + uint32_t pwr_on_num:16; + uint32_t reserved_24:8; + }; + uint32_t val; +} efuse_wr_tim_conf1_reg_t; + +/** Type of wr_tim_conf2 register + * Configurarion register 2 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** pwr_off_num : R/W; bitpos: [15:0]; default: 400; + * Configures the power outage time for VDDQ. + */ + uint32_t pwr_off_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} efuse_wr_tim_conf2_reg_t; + + +/** Group: Status Register */ +/** Type of status register + * eFuse status register. + */ +typedef union { + struct { + /** state : RO; bitpos: [3:0]; default: 0; + * Indicates the state of the eFuse state machine. + */ + uint32_t state:4; + /** otp_load_sw : RO; bitpos: [4]; default: 0; + * The value of OTP_LOAD_SW. + */ + uint32_t otp_load_sw:1; + /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0; + * The value of OTP_VDDQ_C_SYNC2. + */ + uint32_t otp_vddq_c_sync2:1; + /** otp_strobe_sw : RO; bitpos: [6]; default: 0; + * The value of OTP_STROBE_SW. + */ + uint32_t otp_strobe_sw:1; + /** otp_csb_sw : RO; bitpos: [7]; default: 0; + * The value of OTP_CSB_SW. + */ + uint32_t otp_csb_sw:1; + /** otp_pgenb_sw : RO; bitpos: [8]; default: 0; + * The value of OTP_PGENB_SW. + */ + uint32_t otp_pgenb_sw:1; + /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0; + * The value of OTP_VDDQ_IS_SW. + */ + uint32_t otp_vddq_is_sw:1; + /** repeat_err_cnt : RO; bitpos: [17:10]; default: 0; + * Indicates the number of error bits during programming BLOCK0. + */ + uint32_t repeat_err_cnt:8; + uint32_t reserved_18:14; + }; + uint32_t val; +} efuse_status_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * eFuse raw interrupt register. + */ +typedef union { + struct { + /** read_done_int_raw : R/WC/SS; bitpos: [0]; default: 0; + * The raw bit signal for read_done interrupt. + */ + uint32_t read_done_int_raw:1; + /** pgm_done_int_raw : R/WC/SS; bitpos: [1]; default: 0; + * The raw bit signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_raw_reg_t; + +/** Type of int_st register + * eFuse interrupt status register. + */ +typedef union { + struct { + /** read_done_int_st : RO; bitpos: [0]; default: 0; + * The status signal for read_done interrupt. + */ + uint32_t read_done_int_st:1; + /** pgm_done_int_st : RO; bitpos: [1]; default: 0; + * The status signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_st:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_st_reg_t; + +/** Type of int_ena register + * eFuse interrupt enable register. + */ +typedef union { + struct { + /** read_done_int_ena : R/W; bitpos: [0]; default: 0; + * The enable signal for read_done interrupt. + */ + uint32_t read_done_int_ena:1; + /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0; + * The enable signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_ena_reg_t; + +/** Type of int_clr register + * eFuse interrupt clear register. + */ +typedef union { + struct { + /** read_done_int_clr : WO; bitpos: [0]; default: 0; + * The clear signal for read_done interrupt. + */ + uint32_t read_done_int_clr:1; + /** pgm_done_int_clr : WO; bitpos: [1]; default: 0; + * The clear signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_clr_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * eFuse version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 34607760; + * Stores eFuse version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} efuse_date_reg_t; + + +typedef struct { + volatile efuse_pgm_data0_reg_t pgm_data0; + volatile efuse_pgm_data1_reg_t pgm_data1; + volatile efuse_pgm_data2_reg_t pgm_data2; + volatile efuse_pgm_data3_reg_t pgm_data3; + volatile efuse_pgm_data4_reg_t pgm_data4; + volatile efuse_pgm_data5_reg_t pgm_data5; + volatile efuse_pgm_data6_reg_t pgm_data6; + volatile efuse_pgm_data7_reg_t pgm_data7; + volatile efuse_pgm_check_value0_reg_t pgm_check_value0; + volatile efuse_pgm_check_value1_reg_t pgm_check_value1; + volatile efuse_pgm_check_value2_reg_t pgm_check_value2; + volatile efuse_rd_wr_dis_reg_t rd_wr_dis; + volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; + volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1; + volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2; + volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3; + volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4; + volatile efuse_rd_mac_spi_sys_0_reg_t rd_mac_spi_sys_0; + volatile efuse_rd_mac_spi_sys_1_reg_t rd_mac_spi_sys_1; + volatile efuse_rd_mac_spi_sys_2_reg_t rd_mac_spi_sys_2; + volatile efuse_rd_mac_spi_sys_3_reg_t rd_mac_spi_sys_3; + volatile efuse_rd_mac_spi_sys_4_reg_t rd_mac_spi_sys_4; + volatile efuse_rd_mac_spi_sys_5_reg_t rd_mac_spi_sys_5; + volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0; + volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1; + volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2; + volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3; + volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4; + volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5; + volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6; + volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7; + volatile efuse_rd_usr_data0_reg_t rd_usr_data0; + volatile efuse_rd_usr_data1_reg_t rd_usr_data1; + volatile efuse_rd_usr_data2_reg_t rd_usr_data2; + volatile efuse_rd_usr_data3_reg_t rd_usr_data3; + volatile efuse_rd_usr_data4_reg_t rd_usr_data4; + volatile efuse_rd_usr_data5_reg_t rd_usr_data5; + volatile efuse_rd_usr_data6_reg_t rd_usr_data6; + volatile efuse_rd_usr_data7_reg_t rd_usr_data7; + volatile efuse_rd_key0_data0_reg_t rd_key0_data0; + volatile efuse_rd_key0_data1_reg_t rd_key0_data1; + volatile efuse_rd_key0_data2_reg_t rd_key0_data2; + volatile efuse_rd_key0_data3_reg_t rd_key0_data3; + volatile efuse_rd_key0_data4_reg_t rd_key0_data4; + volatile efuse_rd_key0_data5_reg_t rd_key0_data5; + volatile efuse_rd_key0_data6_reg_t rd_key0_data6; + volatile efuse_rd_key0_data7_reg_t rd_key0_data7; + volatile efuse_rd_key1_data0_reg_t rd_key1_data0; + volatile efuse_rd_key1_data1_reg_t rd_key1_data1; + volatile efuse_rd_key1_data2_reg_t rd_key1_data2; + volatile efuse_rd_key1_data3_reg_t rd_key1_data3; + volatile efuse_rd_key1_data4_reg_t rd_key1_data4; + volatile efuse_rd_key1_data5_reg_t rd_key1_data5; + volatile efuse_rd_key1_data6_reg_t rd_key1_data6; + volatile efuse_rd_key1_data7_reg_t rd_key1_data7; + volatile efuse_rd_key2_data0_reg_t rd_key2_data0; + volatile efuse_rd_key2_data1_reg_t rd_key2_data1; + volatile efuse_rd_key2_data2_reg_t rd_key2_data2; + volatile efuse_rd_key2_data3_reg_t rd_key2_data3; + volatile efuse_rd_key2_data4_reg_t rd_key2_data4; + volatile efuse_rd_key2_data5_reg_t rd_key2_data5; + volatile efuse_rd_key2_data6_reg_t rd_key2_data6; + volatile efuse_rd_key2_data7_reg_t rd_key2_data7; + volatile efuse_rd_key3_data0_reg_t rd_key3_data0; + volatile efuse_rd_key3_data1_reg_t rd_key3_data1; + volatile efuse_rd_key3_data2_reg_t rd_key3_data2; + volatile efuse_rd_key3_data3_reg_t rd_key3_data3; + volatile efuse_rd_key3_data4_reg_t rd_key3_data4; + volatile efuse_rd_key3_data5_reg_t rd_key3_data5; + volatile efuse_rd_key3_data6_reg_t rd_key3_data6; + volatile efuse_rd_key3_data7_reg_t rd_key3_data7; + volatile efuse_rd_key4_data0_reg_t rd_key4_data0; + volatile efuse_rd_key4_data1_reg_t rd_key4_data1; + volatile efuse_rd_key4_data2_reg_t rd_key4_data2; + volatile efuse_rd_key4_data3_reg_t rd_key4_data3; + volatile efuse_rd_key4_data4_reg_t rd_key4_data4; + volatile efuse_rd_key4_data5_reg_t rd_key4_data5; + volatile efuse_rd_key4_data6_reg_t rd_key4_data6; + volatile efuse_rd_key4_data7_reg_t rd_key4_data7; + volatile efuse_rd_key5_data0_reg_t rd_key5_data0; + volatile efuse_rd_key5_data1_reg_t rd_key5_data1; + volatile efuse_rd_key5_data2_reg_t rd_key5_data2; + volatile efuse_rd_key5_data3_reg_t rd_key5_data3; + volatile efuse_rd_key5_data4_reg_t rd_key5_data4; + volatile efuse_rd_key5_data5_reg_t rd_key5_data5; + volatile efuse_rd_key5_data6_reg_t rd_key5_data6; + volatile efuse_rd_key5_data7_reg_t rd_key5_data7; + volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0; + volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1; + volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2; + volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3; + volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4; + volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5; + volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6; + volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7; + volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0; + volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1; + volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2; + volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3; + uint32_t reserved_18c; + volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4; + uint32_t reserved_194[11]; + volatile efuse_rd_rs_err0_reg_t rd_rs_err0; + volatile efuse_rd_rs_err1_reg_t rd_rs_err1; + volatile efuse_clk_reg_t clk; + volatile efuse_conf_reg_t conf; + volatile efuse_status_reg_t status; + volatile efuse_cmd_reg_t cmd; + volatile efuse_int_raw_reg_t int_raw; + volatile efuse_int_st_reg_t int_st; + volatile efuse_int_ena_reg_t int_ena; + volatile efuse_int_clr_reg_t int_clr; + volatile efuse_dac_conf_reg_t dac_conf; + volatile efuse_rd_tim_conf_reg_t rd_tim_conf; + uint32_t reserved_1f0; + volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1; + volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2; + volatile efuse_date_reg_t date; } efuse_dev_t; extern efuse_dev_t EFUSE; +#ifndef __cplusplus +_Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure"); +#endif + #ifdef __cplusplus } #endif - - - -#endif /*_SOC_EFUSE_STRUCT_H_ */ diff --git a/tools/sdk/esp32s3/include/soc/esp32s3/include/soc/soc_caps.h b/tools/sdk/esp32s3/include/soc/esp32s3/include/soc/soc_caps.h index 5d69e0eae4a..2d954d0baef 100644 --- a/tools/sdk/esp32s3/include/soc/esp32s3/include/soc/soc_caps.h +++ b/tools/sdk/esp32s3/include/soc/esp32s3/include/soc/soc_caps.h @@ -439,6 +439,8 @@ #define SOC_EFUSE_DIS_USB_JTAG 1 #define SOC_EFUSE_SOFT_DIS_JTAG 1 #define SOC_EFUSE_DIS_DIRECT_BOOT 1 +#define SOC_EFUSE_DIS_ICACHE 1 +#define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // AES-XTS key purpose not supported for this block /*-------------------------- Secure Boot CAPS----------------------------*/ #define SOC_SECURE_BOOT_V2_RSA 1 @@ -503,3 +505,4 @@ #define SOC_BLE_SUPPORTED (1) /*!< Support Bluetooth Low Energy hardware */ #define SOC_BLE_MESH_SUPPORTED (1) /*!< Support BLE MESH */ #define SOC_BLE_50_SUPPORTED (1) /*!< Support Bluetooth 5.0 */ +#define SOC_BLE_DEVICE_PRIVACY_SUPPORTED (1) /*!< Support BLE device privacy mode */ diff --git a/tools/sdk/esp32s3/include/soc/esp32s3/include/soc/usb_reg.h b/tools/sdk/esp32s3/include/soc/esp32s3/include/soc/usb_reg.h index db5087600e0..90bc61d71ac 100644 --- a/tools/sdk/esp32s3/include/soc/esp32s3/include/soc/usb_reg.h +++ b/tools/sdk/esp32s3/include/soc/esp32s3/include/soc/usb_reg.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -1492,6 +1484,17 @@ extern "C" { #define USB_NZSTSOUTHSHK_M (USB_NZSTSOUTHSHK_V << USB_NZSTSOUTHSHK_S) #define USB_NZSTSOUTHSHK_V 0x00000001 #define USB_NZSTSOUTHSHK_S 2 +/** USB_ENA32KHZSUSP : R/W; bitpos: [3]; default: 0; + * This bit can be set only if FS PHY interface is selected. + * Otherwise, this bit needs to be set to zero. + * 1'b0: USB 1.1 Full-Speed Serial transiver not selected + * 1'b1: If FS PHY interface is choosen and this bit is set, the PHY clock during Suspend + * must be switched from 48 MHz to 32 KHz + */ +#define USB_ENA32KHZSUSP (BIT(3)) +#define USB_ENA32KHZSUSP_M (USB_ENA32KHZSUSP_V << USB_ENA32KHZSUSP_S) +#define USB_ENA32KHZSUSP_V 0x00000001 +#define USB_ENA32KHZSUSP_S 3 /** USB_DEVADDR : R/W; bitpos: [11:4]; default: 0; * Device Address. */ diff --git a/tools/sdk/esp32s3/include/spi_flash/include/esp_spi_flash_counters.h b/tools/sdk/esp32s3/include/spi_flash/include/esp_spi_flash_counters.h index ab8157c256d..3355ee16bc2 100644 --- a/tools/sdk/esp32s3/include/spi_flash/include/esp_spi_flash_counters.h +++ b/tools/sdk/esp32s3/include/spi_flash/include/esp_spi_flash_counters.h @@ -1,16 +1,8 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -32,31 +24,38 @@ typedef struct { uint32_t count; // number of times operation was executed uint32_t time; // total time taken, in microseconds uint32_t bytes; // total number of bytes -} spi_flash_counter_t; +} esp_flash_counter_t; typedef struct { - spi_flash_counter_t read; - spi_flash_counter_t write; - spi_flash_counter_t erase; -} spi_flash_counters_t; + esp_flash_counter_t read; + esp_flash_counter_t write; + esp_flash_counter_t erase; +} esp_flash_counters_t; + +// for deprecate old api +typedef esp_flash_counter_t spi_flash_counter_t; +typedef esp_flash_counters_t spi_flash_counters_t; /** * @brief Reset SPI flash operation counters */ -void spi_flash_reset_counters(void); +void esp_flash_reset_counters(void); +void spi_flash_reset_counters(void) __attribute__((deprecated("Please use 'esp_flash_reset_counters' instead"))); /** * @brief Print SPI flash operation counters */ -void spi_flash_dump_counters(void); +void esp_flash_dump_counters(FILE* stream); +void spi_flash_dump_counters(void) __attribute__((deprecated("Please use 'esp_flash_dump_counters' instead"))); /** * @brief Return current SPI flash operation counters * - * @return pointer to the spi_flash_counters_t structure holding values + * @return pointer to the esp_flash_counters_t structure holding values * of the operation counters */ -const spi_flash_counters_t* spi_flash_get_counters(void); +const esp_flash_counters_t* esp_flash_get_counters(void); +const spi_flash_counters_t* spi_flash_get_counters(void) __attribute__((deprecated("Please use 'esp_flash_get_counters' instead"))); #ifdef __cplusplus } diff --git a/tools/sdk/esp32s3/include/tcp_transport/include/esp_transport_socks_proxy.h b/tools/sdk/esp32s3/include/tcp_transport/include/esp_transport_socks_proxy.h new file mode 100644 index 00000000000..566ed9a6de6 --- /dev/null +++ b/tools/sdk/esp32s3/include/tcp_transport/include/esp_transport_socks_proxy.h @@ -0,0 +1,61 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "esp_transport.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum socks_version_t {SOCKS4 = 4} socks_version_t; + +typedef enum socks_transport_response_t { + // The following values correspond to transport operation + SOCKS_RESPONSE_TARGET_NOT_FOUND = 0xF0, + SOCKS_RESPONSE_PROXY_UNREACHABLE = 0xF1, + SOCKS_TIMEOUT = 0xF2, + // The following values are defined by the SOCKS4 protocol + SOCKS_RESPONSE_SUCCESS = 0x5a, + SOCKS_RESPONSE_REQUEST_REJECTED = 0x5B, + SOCKS_RESPONSE_NOT_RUNNING_IDENTD = 0x5c, + SOCKS_RESPONSE_COULD_NOT_CONFIRM_ID = 0x5d, +} socks_transport_error_t; + +/* + * Socks configuration structure + */ +typedef struct esp_transport_socks_proxy_config_t { + const socks_version_t version; /*!< Socks protocol version.*/ + const char *address;/*!< Proxy address*/ + const int port; /*< Proxy port*/ +} esp_transport_socks_proxy_config_t; + +/** +* @brief Create a proxy transport +* @param parent_handle Handle for the parent transport +* @param config Pointer to the configuration structure to use +* +* @return +* - transport Handler for the created transport. +* - NULL in case of failure +*/ +esp_transport_handle_t esp_transport_socks_proxy_init(esp_transport_handle_t parent_handle, const esp_transport_socks_proxy_config_t *config); + +/** +* @brief Changes the configuration of the proxy +* @param socks_transport Handle for the transport +* @param config Pointer to the configuration structure to use +* +* @return +* - ESP_OK on success +*/ +esp_err_t esp_transport_socks_proxy_set_config(esp_transport_handle_t socks_transport, const esp_transport_socks_proxy_config_t *config); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s3/ld/esp32s3.rom.ld b/tools/sdk/esp32s3/ld/esp32s3.rom.ld index 106134fa765..4fff5ccc763 100644 --- a/tools/sdk/esp32s3/ld/esp32s3.rom.ld +++ b/tools/sdk/esp32s3/ld/esp32s3.rom.ld @@ -1997,7 +1997,7 @@ rcClearCurStat = 0x40005760; rcGetSched = 0x4000576c; rcLowerSched = 0x40005778; rcSetTxAmpduLimit = 0x40005784; -rcTxUpdatePer = 0x40005790; +/* rcTxUpdatePer = 0x40005790;*/ rcUpdateAckSnr = 0x4000579c; rcUpdateRate = 0x400057a8; /* rcUpdateTxDone = 0x400057b4; */ diff --git a/tools/sdk/esp32s3/ld/libbtbb.a b/tools/sdk/esp32s3/ld/libbtbb.a index 80da899242b..8c190ed7b09 100644 Binary files a/tools/sdk/esp32s3/ld/libbtbb.a and b/tools/sdk/esp32s3/ld/libbtbb.a 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b/tools/sdk/esp32s3/lib/libwpa_supplicant.a index 159ea13ad20..41fd070edac 100644 Binary files a/tools/sdk/esp32s3/lib/libwpa_supplicant.a and b/tools/sdk/esp32s3/lib/libwpa_supplicant.a differ diff --git a/tools/sdk/esp32s3/lib/libws2812_led.a b/tools/sdk/esp32s3/lib/libws2812_led.a index 8ebdb908c8e..45faaa45093 100644 Binary files a/tools/sdk/esp32s3/lib/libws2812_led.a and b/tools/sdk/esp32s3/lib/libws2812_led.a differ diff --git a/tools/sdk/esp32s3/lib/libxtensa.a b/tools/sdk/esp32s3/lib/libxtensa.a index 6280e145961..7fefbe8d401 100644 Binary files a/tools/sdk/esp32s3/lib/libxtensa.a and b/tools/sdk/esp32s3/lib/libxtensa.a differ diff --git a/tools/sdk/esp32s3/opi_opi/include/sdkconfig.h b/tools/sdk/esp32s3/opi_opi/include/sdkconfig.h index 344f75a3248..558c3c7954f 100644 --- a/tools/sdk/esp32s3/opi_opi/include/sdkconfig.h +++ b/tools/sdk/esp32s3/opi_opi/include/sdkconfig.h @@ -272,6 +272,8 @@ #define CONFIG_SOC_EFUSE_DIS_USB_JTAG 1 #define CONFIG_SOC_EFUSE_SOFT_DIS_JTAG 1 #define CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT 1 +#define CONFIG_SOC_EFUSE_DIS_ICACHE 1 +#define CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 #define CONFIG_SOC_SECURE_BOOT_V2_RSA 1 #define CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 #define CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 @@ -309,6 +311,7 @@ #define CONFIG_SOC_BLE_SUPPORTED 1 #define CONFIG_SOC_BLE_MESH_SUPPORTED 1 #define CONFIG_SOC_BLE_50_SUPPORTED 1 +#define CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED 1 #define CONFIG_IDF_CMAKE 1 #define CONFIG_IDF_TARGET_ARCH_XTENSA 1 #define CONFIG_IDF_TARGET_ARCH "xtensa" @@ -330,6 +333,7 @@ #define CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE 1 #define CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP 1 #define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x10 +#define CONFIG_BOOTLOADER_RESERVE_RTC_MEM 1 #define CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT 1 #define CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED 1 #define CONFIG_SECURE_BOOT_V2_PREFERRED 1 @@ -734,13 +738,12 @@ #define CONFIG_BT_SMP_ENABLE 1 #define CONFIG_BT_BLE_ESTAB_LINK_CONN_TOUT 30 #define CONFIG_BT_MAX_DEVICE_NAME_LEN 32 -#define CONFIG_BT_BLE_RPA_SUPPORTED 1 #define CONFIG_BT_BLE_RPA_TIMEOUT 900 #define CONFIG_BT_BLE_50_FEATURES_SUPPORTED 1 #define CONFIG_BT_BLE_42_FEATURES_SUPPORTED 1 #define CONFIG_BT_CTRL_MODE_EFF 1 -#define CONFIG_BT_CTRL_BLE_MAX_ACT 10 -#define CONFIG_BT_CTRL_BLE_MAX_ACT_EFF 10 +#define CONFIG_BT_CTRL_BLE_MAX_ACT 6 +#define CONFIG_BT_CTRL_BLE_MAX_ACT_EFF 6 #define CONFIG_BT_CTRL_BLE_STATIC_ACL_TX_BUF_NB 0 #define CONFIG_BT_CTRL_PINNED_TO_CORE_0 1 #define CONFIG_BT_CTRL_PINNED_TO_CORE 0 @@ -1462,5 +1465,5 @@ #define CONFIG_WARN_WRITE_STRINGS CONFIG_COMPILER_WARN_WRITE_STRINGS #define CONFIG_WPA_MBEDTLS_CRYPTO CONFIG_ESP_WIFI_MBEDTLS_CRYPTO #define CONFIG_WPA_MBEDTLS_TLS_CLIENT CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT -#define CONFIG_ARDUINO_IDF_COMMIT "" +#define CONFIG_ARDUINO_IDF_COMMIT "420ebd208a" #define CONFIG_ARDUINO_IDF_BRANCH "release/v5.1" diff --git a/tools/sdk/esp32s3/opi_opi/libbootloader_support.a b/tools/sdk/esp32s3/opi_opi/libbootloader_support.a index 4ef2c2f9ab0..02f7340d42a 100644 Binary files a/tools/sdk/esp32s3/opi_opi/libbootloader_support.a and b/tools/sdk/esp32s3/opi_opi/libbootloader_support.a differ diff --git a/tools/sdk/esp32s3/opi_opi/libesp_hw_support.a b/tools/sdk/esp32s3/opi_opi/libesp_hw_support.a index cda5dc197ff..382fe8e198d 100644 Binary files a/tools/sdk/esp32s3/opi_opi/libesp_hw_support.a and b/tools/sdk/esp32s3/opi_opi/libesp_hw_support.a differ diff --git a/tools/sdk/esp32s3/opi_opi/libesp_psram.a b/tools/sdk/esp32s3/opi_opi/libesp_psram.a index 73fe240d808..df8f936f060 100644 Binary files a/tools/sdk/esp32s3/opi_opi/libesp_psram.a and b/tools/sdk/esp32s3/opi_opi/libesp_psram.a differ diff --git a/tools/sdk/esp32s3/opi_opi/libesp_system.a b/tools/sdk/esp32s3/opi_opi/libesp_system.a index ae68e467a34..bea899d256e 100644 Binary files a/tools/sdk/esp32s3/opi_opi/libesp_system.a and b/tools/sdk/esp32s3/opi_opi/libesp_system.a differ diff --git a/tools/sdk/esp32s3/opi_opi/libfreertos.a b/tools/sdk/esp32s3/opi_opi/libfreertos.a index cea0d5580d5..3ee1893d659 100644 Binary files a/tools/sdk/esp32s3/opi_opi/libfreertos.a and b/tools/sdk/esp32s3/opi_opi/libfreertos.a differ diff --git a/tools/sdk/esp32s3/opi_opi/libspi_flash.a b/tools/sdk/esp32s3/opi_opi/libspi_flash.a index ff14a7e23be..e14646fd1a4 100644 Binary files a/tools/sdk/esp32s3/opi_opi/libspi_flash.a and b/tools/sdk/esp32s3/opi_opi/libspi_flash.a differ diff --git a/tools/sdk/esp32s3/opi_opi/sections.ld b/tools/sdk/esp32s3/opi_opi/sections.ld index 715a6161a7f..c55ecc8bf85 100644 --- a/tools/sdk/esp32s3/opi_opi/sections.ld +++ b/tools/sdk/esp32s3/opi_opi/sections.ld @@ -1,6 +1,6 @@ /* Automatically generated file; DO NOT EDIT */ /* Espressif IoT Development Framework Linker Script */ -/* Generated from: /Users/ficeto/Desktop/ESP32/ESP-IDF-5/esp32-arduino-lib-builder/esp-idf/components/esp_system/ld/esp32s3/sections.ld.in */ +/* Generated from: /home/runner/work/esp32-arduino-lib-builder/esp32-arduino-lib-builder/esp-idf/components/esp_system/ld/esp32s3/sections.ld.in */ /* * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD @@ -496,7 +496,7 @@ SECTIONS *libesp_system.a:esp_system_chip.*(.literal.esp_get_free_heap_size .literal.esp_get_free_internal_heap_size .literal.esp_get_idf_version .literal.esp_get_minimum_free_heap_size .text .text.esp_get_free_heap_size .text.esp_get_free_internal_heap_size .text.esp_get_idf_version .text.esp_get_minimum_free_heap_size) *libfreertos.a:app_startup.*(.literal .literal.* .text .text.*) *libheap.a:multi_heap.*(.literal.multi_heap_check .literal.multi_heap_dump .literal.multi_heap_dump_tlsf .literal.multi_heap_get_info_impl .literal.multi_heap_register_impl .literal.tlsf_check_hook .text .text.multi_heap_check .text.multi_heap_dump .text.multi_heap_dump_tlsf .text.multi_heap_free_size_impl .text.multi_heap_get_info_impl .text.multi_heap_get_info_tlsf .text.multi_heap_minimum_free_size_impl .text.multi_heap_register_impl .text.tlsf_check_hook) - *libheap.a:multi_heap_poisoning.*(.literal.multi_heap_free_size .literal.multi_heap_get_info .literal.multi_heap_minimum_free_size .literal.multi_heap_register .text .text.multi_heap_free_size .text.multi_heap_get_info .text.multi_heap_minimum_free_size .text.multi_heap_register .text.subtract_poison_overhead) + *libheap.a:multi_heap_poisoning.*(.literal.multi_heap_free_size .literal.multi_heap_get_info .literal.multi_heap_minimum_free_size .literal.multi_heap_register .text .text.multi_heap_free_size .text.multi_heap_get_info .text.multi_heap_minimum_free_size .text.multi_heap_register) *libheap.a:tlsf.*(.literal.default_walker .literal.tlsf_add_pool .literal.tlsf_check .literal.tlsf_check_pool .literal.tlsf_create .literal.tlsf_create_with_pool .literal.tlsf_remove_pool .literal.tlsf_walk_pool .text .text.default_walker .text.integrity_walker .text.tlsf_add_pool .text.tlsf_check .text.tlsf_check_pool .text.tlsf_create .text.tlsf_create_with_pool .text.tlsf_destroy .text.tlsf_fit_size .text.tlsf_pool_overhead .text.tlsf_remove_pool .text.tlsf_walk_pool) *liblog.a:log.*(.literal.esp_log_level_get .literal.esp_log_level_set .literal.esp_log_set_vprintf .literal.esp_log_writev .literal.heap_bubble_down .literal.s_log_level_get_and_unlock .text .text.esp_log_level_get .text.esp_log_level_set .text.esp_log_set_vprintf .text.esp_log_writev .text.heap_bubble_down .text.s_log_level_get_and_unlock) *liblog.a:log_freertos.*(.literal.esp_log_system_timestamp .text .text.esp_log_system_timestamp) diff --git a/tools/sdk/esp32s3/opi_qspi/include/sdkconfig.h b/tools/sdk/esp32s3/opi_qspi/include/sdkconfig.h index f70140b7eb4..43236adb2b4 100644 --- a/tools/sdk/esp32s3/opi_qspi/include/sdkconfig.h +++ b/tools/sdk/esp32s3/opi_qspi/include/sdkconfig.h @@ -272,6 +272,8 @@ #define CONFIG_SOC_EFUSE_DIS_USB_JTAG 1 #define CONFIG_SOC_EFUSE_SOFT_DIS_JTAG 1 #define CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT 1 +#define CONFIG_SOC_EFUSE_DIS_ICACHE 1 +#define CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 #define CONFIG_SOC_SECURE_BOOT_V2_RSA 1 #define CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 #define CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 @@ -309,6 +311,7 @@ #define CONFIG_SOC_BLE_SUPPORTED 1 #define CONFIG_SOC_BLE_MESH_SUPPORTED 1 #define CONFIG_SOC_BLE_50_SUPPORTED 1 +#define CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED 1 #define CONFIG_IDF_CMAKE 1 #define CONFIG_IDF_TARGET_ARCH_XTENSA 1 #define CONFIG_IDF_TARGET_ARCH "xtensa" @@ -330,6 +333,7 @@ #define CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE 1 #define CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP 1 #define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x10 +#define CONFIG_BOOTLOADER_RESERVE_RTC_MEM 1 #define CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT 1 #define CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED 1 #define CONFIG_SECURE_BOOT_V2_PREFERRED 1 @@ -734,13 +738,12 @@ #define CONFIG_BT_SMP_ENABLE 1 #define CONFIG_BT_BLE_ESTAB_LINK_CONN_TOUT 30 #define CONFIG_BT_MAX_DEVICE_NAME_LEN 32 -#define CONFIG_BT_BLE_RPA_SUPPORTED 1 #define CONFIG_BT_BLE_RPA_TIMEOUT 900 #define CONFIG_BT_BLE_50_FEATURES_SUPPORTED 1 #define CONFIG_BT_BLE_42_FEATURES_SUPPORTED 1 #define CONFIG_BT_CTRL_MODE_EFF 1 -#define CONFIG_BT_CTRL_BLE_MAX_ACT 10 -#define CONFIG_BT_CTRL_BLE_MAX_ACT_EFF 10 +#define CONFIG_BT_CTRL_BLE_MAX_ACT 6 +#define CONFIG_BT_CTRL_BLE_MAX_ACT_EFF 6 #define CONFIG_BT_CTRL_BLE_STATIC_ACL_TX_BUF_NB 0 #define CONFIG_BT_CTRL_PINNED_TO_CORE_0 1 #define CONFIG_BT_CTRL_PINNED_TO_CORE 0 @@ -1460,5 +1463,5 @@ #define CONFIG_WARN_WRITE_STRINGS CONFIG_COMPILER_WARN_WRITE_STRINGS #define CONFIG_WPA_MBEDTLS_CRYPTO CONFIG_ESP_WIFI_MBEDTLS_CRYPTO #define CONFIG_WPA_MBEDTLS_TLS_CLIENT CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT -#define CONFIG_ARDUINO_IDF_COMMIT "" +#define CONFIG_ARDUINO_IDF_COMMIT "420ebd208a" #define CONFIG_ARDUINO_IDF_BRANCH "release/v5.1" diff --git a/tools/sdk/esp32s3/opi_qspi/libbootloader_support.a b/tools/sdk/esp32s3/opi_qspi/libbootloader_support.a index 4ef2c2f9ab0..02f7340d42a 100644 Binary files a/tools/sdk/esp32s3/opi_qspi/libbootloader_support.a and b/tools/sdk/esp32s3/opi_qspi/libbootloader_support.a differ diff --git a/tools/sdk/esp32s3/opi_qspi/libesp_hw_support.a b/tools/sdk/esp32s3/opi_qspi/libesp_hw_support.a index f8c0fb9488e..5dcd2200692 100644 Binary files a/tools/sdk/esp32s3/opi_qspi/libesp_hw_support.a and b/tools/sdk/esp32s3/opi_qspi/libesp_hw_support.a differ diff --git a/tools/sdk/esp32s3/opi_qspi/libesp_psram.a b/tools/sdk/esp32s3/opi_qspi/libesp_psram.a index b2a666db3b1..2bb493b5051 100644 Binary files a/tools/sdk/esp32s3/opi_qspi/libesp_psram.a and b/tools/sdk/esp32s3/opi_qspi/libesp_psram.a differ diff --git a/tools/sdk/esp32s3/opi_qspi/libesp_system.a b/tools/sdk/esp32s3/opi_qspi/libesp_system.a index 11d60225e4b..1e70838e0e0 100644 Binary files a/tools/sdk/esp32s3/opi_qspi/libesp_system.a and b/tools/sdk/esp32s3/opi_qspi/libesp_system.a differ diff --git a/tools/sdk/esp32s3/opi_qspi/libfreertos.a b/tools/sdk/esp32s3/opi_qspi/libfreertos.a index cea0d5580d5..3ee1893d659 100644 Binary files a/tools/sdk/esp32s3/opi_qspi/libfreertos.a and b/tools/sdk/esp32s3/opi_qspi/libfreertos.a differ diff --git a/tools/sdk/esp32s3/opi_qspi/libspi_flash.a b/tools/sdk/esp32s3/opi_qspi/libspi_flash.a index 653432a38a4..f145aca36ee 100644 Binary files a/tools/sdk/esp32s3/opi_qspi/libspi_flash.a and b/tools/sdk/esp32s3/opi_qspi/libspi_flash.a differ diff --git a/tools/sdk/esp32s3/opi_qspi/sections.ld b/tools/sdk/esp32s3/opi_qspi/sections.ld index 04b403f89cb..bad0471018f 100644 --- a/tools/sdk/esp32s3/opi_qspi/sections.ld +++ b/tools/sdk/esp32s3/opi_qspi/sections.ld @@ -1,6 +1,6 @@ /* Automatically generated file; DO NOT EDIT */ /* Espressif IoT Development Framework Linker Script */ -/* Generated from: /Users/ficeto/Desktop/ESP32/ESP-IDF-5/esp32-arduino-lib-builder/esp-idf/components/esp_system/ld/esp32s3/sections.ld.in */ +/* Generated from: /home/runner/work/esp32-arduino-lib-builder/esp32-arduino-lib-builder/esp-idf/components/esp_system/ld/esp32s3/sections.ld.in */ /* * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD @@ -496,7 +496,7 @@ SECTIONS *libesp_system.a:esp_system_chip.*(.literal.esp_get_free_heap_size .literal.esp_get_free_internal_heap_size .literal.esp_get_idf_version .literal.esp_get_minimum_free_heap_size .text .text.esp_get_free_heap_size .text.esp_get_free_internal_heap_size .text.esp_get_idf_version .text.esp_get_minimum_free_heap_size) *libfreertos.a:app_startup.*(.literal .literal.* .text .text.*) *libheap.a:multi_heap.*(.literal.multi_heap_check .literal.multi_heap_dump .literal.multi_heap_dump_tlsf .literal.multi_heap_get_info_impl .literal.multi_heap_register_impl .literal.tlsf_check_hook .text .text.multi_heap_check .text.multi_heap_dump .text.multi_heap_dump_tlsf .text.multi_heap_free_size_impl .text.multi_heap_get_info_impl .text.multi_heap_get_info_tlsf .text.multi_heap_minimum_free_size_impl .text.multi_heap_register_impl .text.tlsf_check_hook) - *libheap.a:multi_heap_poisoning.*(.literal.multi_heap_free_size .literal.multi_heap_get_info .literal.multi_heap_minimum_free_size .literal.multi_heap_register .text .text.multi_heap_free_size .text.multi_heap_get_info .text.multi_heap_minimum_free_size .text.multi_heap_register .text.subtract_poison_overhead) + *libheap.a:multi_heap_poisoning.*(.literal.multi_heap_free_size .literal.multi_heap_get_info .literal.multi_heap_minimum_free_size .literal.multi_heap_register .text .text.multi_heap_free_size .text.multi_heap_get_info .text.multi_heap_minimum_free_size .text.multi_heap_register) *libheap.a:tlsf.*(.literal.default_walker .literal.tlsf_add_pool .literal.tlsf_check .literal.tlsf_check_pool .literal.tlsf_create .literal.tlsf_create_with_pool .literal.tlsf_remove_pool .literal.tlsf_walk_pool .text .text.default_walker .text.integrity_walker .text.tlsf_add_pool .text.tlsf_check .text.tlsf_check_pool .text.tlsf_create .text.tlsf_create_with_pool .text.tlsf_destroy .text.tlsf_fit_size .text.tlsf_pool_overhead .text.tlsf_remove_pool .text.tlsf_walk_pool) *liblog.a:log.*(.literal.esp_log_level_get .literal.esp_log_level_set .literal.esp_log_set_vprintf .literal.esp_log_writev .literal.heap_bubble_down .literal.s_log_level_get_and_unlock .text .text.esp_log_level_get .text.esp_log_level_set .text.esp_log_set_vprintf .text.esp_log_writev .text.heap_bubble_down .text.s_log_level_get_and_unlock) *liblog.a:log_freertos.*(.literal.esp_log_system_timestamp .text .text.esp_log_system_timestamp) diff --git a/tools/sdk/esp32s3/platformio-build.py b/tools/sdk/esp32s3/platformio-build.py index 1aca96e1109..dd68b1a2cb2 100644 --- a/tools/sdk/esp32s3/platformio-build.py +++ b/tools/sdk/esp32s3/platformio-build.py @@ -105,6 +105,7 @@ "-u", "pthread_include_pthread_cond_impl", "-u", "pthread_include_pthread_local_storage_impl", "-u", "pthread_include_pthread_rwlock_impl", + "-u", "pthread_include_pthread_semaphore_impl", "-u", "ld_include_highint_hdl", "-u", "start_app", "-u", "start_app_other_cores", @@ -127,6 +128,7 @@ join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "freertos", "FreeRTOS-Kernel", "portable", "xtensa", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "freertos", "esp_additions", "include", "freertos"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "freertos", "esp_additions", "include"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "freertos", "esp_additions", "arch", "xtensa", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "esp_hw_support", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "esp_hw_support", "include", "soc"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "esp_hw_support", "include", "soc", "esp32s3"), @@ -250,6 +252,7 @@ join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "esp_http_server", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "esp_https_ota", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "esp_https_server", "include"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "esp_psram", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "esp_lcd", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "esp_lcd", "interface"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "protobuf-c", "protobuf-c"), @@ -257,7 +260,6 @@ join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "protocomm", "include", "security"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "protocomm", "include", "transports"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "esp_local_ctrl", "include"), - join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "esp_psram", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "espcoredump", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "espcoredump", "include", "port", "xtensa"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "wear_levelling", "include"), @@ -304,11 +306,6 @@ join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "esp-dl", "include", "layer"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "esp-dl", "include", "detect"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "esp-dl", "include", "model_zoo"), - join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "esp-sr", "src", "include"), - join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "esp-sr", "esp-tts", "esp_tts_chinese", "include"), - join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "esp-sr", "include", "esp32s3"), - join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "esp32-camera", "driver", "include"), - join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "esp32-camera", "conversions", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "espressif__esp-dsp", "modules", "dotprod", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "espressif__esp-dsp", "modules", "support", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "espressif__esp-dsp", "modules", "windows", "include"), @@ -334,6 +331,11 @@ join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "espressif__esp-dsp", "modules", "common", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "espressif__esp-dsp", "modules", "kalman", "ekf", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "espressif__esp-dsp", "modules", "kalman", "ekf_imu13states", "include"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "esp-sr", "src", "include"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "esp-sr", "esp-tts", "esp_tts_chinese", "include"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "esp-sr", "include", "esp32s3"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "esp32-camera", "driver", "include"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "esp32-camera", "conversions", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "include", "fb_gfx", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", env.BoardConfig().get("build.arduino.memory_type", (env.BoardConfig().get("build.flash_mode", "dio") + "_qspi")), "include"), join(FRAMEWORK_DIR, "cores", env.BoardConfig().get("build.core")) @@ -346,12 +348,12 @@ ], LIBS=[ - "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lapp_trace", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lbt", "-lunity", "-lcmock", "-lconsole", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-lesp_hid", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_https_server", "-lesp_lcd", "-lprotobuf-c", "-lprotocomm", "-lesp_local_ctrl", "-lesp_psram", "-lespcoredump", "-lwear_levelling", "-lsdmmc", "-lfatfs", "-ljson", "-lmqtt", "-lperfmon", "-lspiffs", "-ltouch_element", "-lulp", "-lusb", "-lwifi_provisioning", "-lespressif__mdns", "-lcbor", "-lrmaker_common", "-lesp_diagnostics", "-lrtc_store", "-lesp_insights", "-ljson_parser", "-ljson_generator", "-lesp_schedule", "-lespressif__esp_secure_cert_mgr", "-lesp_rainmaker", "-lgpio_button", "-lqrcode", "-lws2812_led", "-larduino_tinyusb", "-lesp-sr", "-lesp32-camera", "-lesp_littlefs", "-lespressif__esp-dsp", "-lfb_gfx", "-lapp_trace", "-lapp_trace", "-lcmock", "-lunity", "-lesp_lcd", "-lperfmon", "-ltouch_element", "-lusb", "-lesp_hid", "-lfatfs", "-lwear_levelling", "-lsdmmc", "-lesp_insights", "-lcbor", "-lesp_diagnostics", "-lrtc_store", "-lesp_rainmaker", "-lesp_local_ctrl", "-lesp_https_server", "-lwifi_provisioning", "-lprotocomm", "-lbt", "-lbtdm_app", "-lprotobuf-c", "-lespressif__mdns", "-ljson_parser", "-ljson_generator", "-lesp_schedule", "-lespressif__esp_secure_cert_mgr", "-lqrcode", "-lrmaker_common", "-lconsole", "-lmqtt", "-lcat_face_detect", "-lhuman_face_detect", "-lcolor_detect", "-lmfn", "-ldl", "-lhufzip", "-lesp_audio_front_end", "-lesp_audio_processor", "-lmultinet", "-lwakenet", "-lesp-sr", "-lhufzip", "-lesp_audio_front_end", "-lesp_audio_processor", "-lmultinet", "-lwakenet", "-ljson", "-lspiffs", "-ldl_lib", "-lfst", "-lc_speech_features", "-lespressif__esp-dsp", "-lesp_tts_chinese", "-lvoice_set_xiaole", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxt_hal", "-lc", "-lm", "-lnewlib", "-lstdc++", "-lpthread", "-lgcc", "-lcxx", "-lphy", "-lbtbb", "-lesp_phy", "-lphy", "-lbtbb", "-lesp_phy", "-lphy", "-lbtbb" + "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lapp_trace", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lbt", "-lunity", "-lcmock", "-lconsole", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-lesp_hid", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_https_server", "-lesp_psram", "-lesp_lcd", "-lprotobuf-c", "-lprotocomm", "-lesp_local_ctrl", "-lespcoredump", "-lwear_levelling", "-lsdmmc", "-lfatfs", "-ljson", "-lmqtt", "-lperfmon", "-lspiffs", "-ltouch_element", "-lulp", "-lusb", "-lwifi_provisioning", "-lespressif__mdns", "-lcbor", "-lrmaker_common", "-lesp_diagnostics", "-lrtc_store", "-lesp_insights", "-ljson_parser", "-ljson_generator", "-lesp_schedule", "-lespressif__esp_secure_cert_mgr", "-lesp_rainmaker", "-lgpio_button", "-lqrcode", "-lws2812_led", "-larduino_tinyusb", "-lespressif__esp-dsp", "-lesp-sr", "-lesp32-camera", "-lesp_littlefs", "-lfb_gfx", "-lapp_trace", "-lapp_trace", "-lcmock", "-lunity", "-lesp_lcd", "-lperfmon", "-ltouch_element", "-lusb", "-lesp_hid", "-lfatfs", "-lwear_levelling", "-lsdmmc", "-lesp_insights", "-lcbor", "-lesp_diagnostics", "-lrtc_store", "-lesp_rainmaker", "-lesp_local_ctrl", "-lesp_https_server", "-lwifi_provisioning", "-lprotocomm", "-lbt", "-lbtdm_app", "-lprotobuf-c", "-lespressif__mdns", "-ljson_parser", "-ljson_generator", "-lesp_schedule", "-lespressif__esp_secure_cert_mgr", "-lqrcode", "-lrmaker_common", "-lconsole", "-lmqtt", "-lcat_face_detect", "-lhuman_face_detect", "-lcolor_detect", "-lmfn", "-ldl", "-lhufzip", "-lesp_audio_front_end", "-lesp_audio_processor", "-lmultinet", "-lwakenet", "-lesp-sr", "-lhufzip", "-lesp_audio_front_end", "-lesp_audio_processor", "-lmultinet", "-lwakenet", "-ljson", "-lspiffs", "-lespressif__esp-dsp", "-ldl_lib", "-lfst", "-lc_speech_features", "-lespressif__esp-dsp", "-lesp_tts_chinese", "-lvoice_set_xiaole", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxtensa", "-lesp_ringbuf", "-lefuse", "-ldriver", "-lesp_pm", "-lmbedtls", "-lesp_app_format", "-lbootloader_support", "-lesp_partition", "-lapp_update", "-lesp_mm", "-lspi_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-llog", "-lheap", "-lsoc", "-lesp_hw_support", "-lfreertos", "-lnewlib", "-lcxx", "-lesp_common", "-lesp_timer", "-lesp_event", "-lnvs_flash", "-lesp_phy", "-lvfs", "-llwip", "-lesp_netif", "-lwpa_supplicant", "-lesp_coex", "-lesp_wifi", "-lhttp_parser", "-lesp-tls", "-lesp_adc", "-lesp_eth", "-lesp_gdbstub", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_psram", "-lespcoredump", "-lulp", "-lmbedtls_2", "-lmbedcrypto", "-lmbedx509", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lsmartconfig", "-lwapi", "-lxt_hal", "-lc", "-lm", "-lnewlib", "-lstdc++", "-lpthread", "-lgcc", "-lcxx", "-lphy", "-lbtbb", "-lesp_phy", "-lphy", "-lbtbb", "-lesp_phy", "-lphy", "-lbtbb" ], CPPDEFINES=[ "ESP_PLATFORM", - ("IDF_VER", '\\"v5.1-dev-4124-gbb9200acec\\"'), + ("IDF_VER", '\\"v5.1-dev-4528-g420ebd208a\\"'), ("MBEDTLS_CONFIG_FILE", '\\"mbedtls/esp_config.h\\"'), ("SOC_MMU_PAGE_SIZE", 'CONFIG_MMU_PAGE_SIZE'), "UNITY_INCLUDE_CONFIG_H", diff --git a/tools/sdk/esp32s3/qio_opi/include/sdkconfig.h b/tools/sdk/esp32s3/qio_opi/include/sdkconfig.h index ece1adbbdeb..12810b13086 100644 --- a/tools/sdk/esp32s3/qio_opi/include/sdkconfig.h +++ b/tools/sdk/esp32s3/qio_opi/include/sdkconfig.h @@ -272,6 +272,8 @@ #define CONFIG_SOC_EFUSE_DIS_USB_JTAG 1 #define CONFIG_SOC_EFUSE_SOFT_DIS_JTAG 1 #define CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT 1 +#define CONFIG_SOC_EFUSE_DIS_ICACHE 1 +#define CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 #define CONFIG_SOC_SECURE_BOOT_V2_RSA 1 #define CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 #define CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 @@ -309,6 +311,7 @@ #define CONFIG_SOC_BLE_SUPPORTED 1 #define CONFIG_SOC_BLE_MESH_SUPPORTED 1 #define CONFIG_SOC_BLE_50_SUPPORTED 1 +#define CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED 1 #define CONFIG_IDF_CMAKE 1 #define CONFIG_IDF_TARGET_ARCH_XTENSA 1 #define CONFIG_IDF_TARGET_ARCH "xtensa" @@ -330,6 +333,7 @@ #define CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE 1 #define CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP 1 #define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x10 +#define CONFIG_BOOTLOADER_RESERVE_RTC_MEM 1 #define CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT 1 #define CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED 1 #define CONFIG_SECURE_BOOT_V2_PREFERRED 1 @@ -733,13 +737,12 @@ #define CONFIG_BT_SMP_ENABLE 1 #define CONFIG_BT_BLE_ESTAB_LINK_CONN_TOUT 30 #define CONFIG_BT_MAX_DEVICE_NAME_LEN 32 -#define CONFIG_BT_BLE_RPA_SUPPORTED 1 #define CONFIG_BT_BLE_RPA_TIMEOUT 900 #define CONFIG_BT_BLE_50_FEATURES_SUPPORTED 1 #define CONFIG_BT_BLE_42_FEATURES_SUPPORTED 1 #define CONFIG_BT_CTRL_MODE_EFF 1 -#define CONFIG_BT_CTRL_BLE_MAX_ACT 10 -#define CONFIG_BT_CTRL_BLE_MAX_ACT_EFF 10 +#define CONFIG_BT_CTRL_BLE_MAX_ACT 6 +#define CONFIG_BT_CTRL_BLE_MAX_ACT_EFF 6 #define CONFIG_BT_CTRL_BLE_STATIC_ACL_TX_BUF_NB 0 #define CONFIG_BT_CTRL_PINNED_TO_CORE_0 1 #define CONFIG_BT_CTRL_PINNED_TO_CORE 0 @@ -1462,5 +1465,5 @@ #define CONFIG_WARN_WRITE_STRINGS CONFIG_COMPILER_WARN_WRITE_STRINGS #define CONFIG_WPA_MBEDTLS_CRYPTO CONFIG_ESP_WIFI_MBEDTLS_CRYPTO #define CONFIG_WPA_MBEDTLS_TLS_CLIENT CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT -#define CONFIG_ARDUINO_IDF_COMMIT "" +#define CONFIG_ARDUINO_IDF_COMMIT "420ebd208a" #define CONFIG_ARDUINO_IDF_BRANCH "release/v5.1" diff --git a/tools/sdk/esp32s3/qio_opi/libbootloader_support.a b/tools/sdk/esp32s3/qio_opi/libbootloader_support.a index 86a0624e56f..9e5dddd8387 100644 Binary files a/tools/sdk/esp32s3/qio_opi/libbootloader_support.a and b/tools/sdk/esp32s3/qio_opi/libbootloader_support.a differ diff --git a/tools/sdk/esp32s3/qio_opi/libesp_hw_support.a b/tools/sdk/esp32s3/qio_opi/libesp_hw_support.a index 43e2bd42f02..45caf3ad046 100644 Binary files a/tools/sdk/esp32s3/qio_opi/libesp_hw_support.a and b/tools/sdk/esp32s3/qio_opi/libesp_hw_support.a differ diff --git a/tools/sdk/esp32s3/qio_opi/libesp_psram.a b/tools/sdk/esp32s3/qio_opi/libesp_psram.a index 73fe240d808..df8f936f060 100644 Binary files a/tools/sdk/esp32s3/qio_opi/libesp_psram.a and b/tools/sdk/esp32s3/qio_opi/libesp_psram.a differ diff --git a/tools/sdk/esp32s3/qio_opi/libesp_system.a b/tools/sdk/esp32s3/qio_opi/libesp_system.a index ae68e467a34..bea899d256e 100644 Binary files a/tools/sdk/esp32s3/qio_opi/libesp_system.a and b/tools/sdk/esp32s3/qio_opi/libesp_system.a differ diff --git a/tools/sdk/esp32s3/qio_opi/libfreertos.a b/tools/sdk/esp32s3/qio_opi/libfreertos.a index cea0d5580d5..3ee1893d659 100644 Binary files a/tools/sdk/esp32s3/qio_opi/libfreertos.a and b/tools/sdk/esp32s3/qio_opi/libfreertos.a differ diff --git a/tools/sdk/esp32s3/qio_opi/libspi_flash.a b/tools/sdk/esp32s3/qio_opi/libspi_flash.a index d7a1a54e539..59d470d4263 100644 Binary files a/tools/sdk/esp32s3/qio_opi/libspi_flash.a and b/tools/sdk/esp32s3/qio_opi/libspi_flash.a differ diff --git a/tools/sdk/esp32s3/qio_opi/sections.ld b/tools/sdk/esp32s3/qio_opi/sections.ld index 715a6161a7f..c55ecc8bf85 100644 --- a/tools/sdk/esp32s3/qio_opi/sections.ld +++ b/tools/sdk/esp32s3/qio_opi/sections.ld @@ -1,6 +1,6 @@ /* Automatically generated file; DO NOT EDIT */ /* Espressif IoT Development Framework Linker Script */ -/* Generated from: /Users/ficeto/Desktop/ESP32/ESP-IDF-5/esp32-arduino-lib-builder/esp-idf/components/esp_system/ld/esp32s3/sections.ld.in */ +/* Generated from: /home/runner/work/esp32-arduino-lib-builder/esp32-arduino-lib-builder/esp-idf/components/esp_system/ld/esp32s3/sections.ld.in */ /* * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD @@ -496,7 +496,7 @@ SECTIONS *libesp_system.a:esp_system_chip.*(.literal.esp_get_free_heap_size .literal.esp_get_free_internal_heap_size .literal.esp_get_idf_version .literal.esp_get_minimum_free_heap_size .text .text.esp_get_free_heap_size .text.esp_get_free_internal_heap_size .text.esp_get_idf_version .text.esp_get_minimum_free_heap_size) *libfreertos.a:app_startup.*(.literal .literal.* .text .text.*) *libheap.a:multi_heap.*(.literal.multi_heap_check .literal.multi_heap_dump .literal.multi_heap_dump_tlsf .literal.multi_heap_get_info_impl .literal.multi_heap_register_impl .literal.tlsf_check_hook .text .text.multi_heap_check .text.multi_heap_dump .text.multi_heap_dump_tlsf .text.multi_heap_free_size_impl .text.multi_heap_get_info_impl .text.multi_heap_get_info_tlsf .text.multi_heap_minimum_free_size_impl .text.multi_heap_register_impl .text.tlsf_check_hook) - *libheap.a:multi_heap_poisoning.*(.literal.multi_heap_free_size .literal.multi_heap_get_info .literal.multi_heap_minimum_free_size .literal.multi_heap_register .text .text.multi_heap_free_size .text.multi_heap_get_info .text.multi_heap_minimum_free_size .text.multi_heap_register .text.subtract_poison_overhead) + *libheap.a:multi_heap_poisoning.*(.literal.multi_heap_free_size .literal.multi_heap_get_info .literal.multi_heap_minimum_free_size .literal.multi_heap_register .text .text.multi_heap_free_size .text.multi_heap_get_info .text.multi_heap_minimum_free_size .text.multi_heap_register) *libheap.a:tlsf.*(.literal.default_walker .literal.tlsf_add_pool .literal.tlsf_check .literal.tlsf_check_pool .literal.tlsf_create .literal.tlsf_create_with_pool .literal.tlsf_remove_pool .literal.tlsf_walk_pool .text .text.default_walker .text.integrity_walker .text.tlsf_add_pool .text.tlsf_check .text.tlsf_check_pool .text.tlsf_create .text.tlsf_create_with_pool .text.tlsf_destroy .text.tlsf_fit_size .text.tlsf_pool_overhead .text.tlsf_remove_pool .text.tlsf_walk_pool) *liblog.a:log.*(.literal.esp_log_level_get .literal.esp_log_level_set .literal.esp_log_set_vprintf .literal.esp_log_writev .literal.heap_bubble_down .literal.s_log_level_get_and_unlock .text .text.esp_log_level_get .text.esp_log_level_set .text.esp_log_set_vprintf .text.esp_log_writev .text.heap_bubble_down .text.s_log_level_get_and_unlock) *liblog.a:log_freertos.*(.literal.esp_log_system_timestamp .text .text.esp_log_system_timestamp) diff --git a/tools/sdk/esp32s3/qio_qspi/include/sdkconfig.h b/tools/sdk/esp32s3/qio_qspi/include/sdkconfig.h index 4b9873805c4..e942859f492 100644 --- a/tools/sdk/esp32s3/qio_qspi/include/sdkconfig.h +++ b/tools/sdk/esp32s3/qio_qspi/include/sdkconfig.h @@ -272,6 +272,8 @@ #define CONFIG_SOC_EFUSE_DIS_USB_JTAG 1 #define CONFIG_SOC_EFUSE_SOFT_DIS_JTAG 1 #define CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT 1 +#define CONFIG_SOC_EFUSE_DIS_ICACHE 1 +#define CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 #define CONFIG_SOC_SECURE_BOOT_V2_RSA 1 #define CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 #define CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 @@ -309,6 +311,7 @@ #define CONFIG_SOC_BLE_SUPPORTED 1 #define CONFIG_SOC_BLE_MESH_SUPPORTED 1 #define CONFIG_SOC_BLE_50_SUPPORTED 1 +#define CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED 1 #define CONFIG_IDF_CMAKE 1 #define CONFIG_IDF_TARGET_ARCH_XTENSA 1 #define CONFIG_IDF_TARGET_ARCH "xtensa" @@ -330,6 +333,7 @@ #define CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE 1 #define CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP 1 #define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x10 +#define CONFIG_BOOTLOADER_RESERVE_RTC_MEM 1 #define CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT 1 #define CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED 1 #define CONFIG_SECURE_BOOT_V2_PREFERRED 1 @@ -733,13 +737,12 @@ #define CONFIG_BT_SMP_ENABLE 1 #define CONFIG_BT_BLE_ESTAB_LINK_CONN_TOUT 30 #define CONFIG_BT_MAX_DEVICE_NAME_LEN 32 -#define CONFIG_BT_BLE_RPA_SUPPORTED 1 #define CONFIG_BT_BLE_RPA_TIMEOUT 900 #define CONFIG_BT_BLE_50_FEATURES_SUPPORTED 1 #define CONFIG_BT_BLE_42_FEATURES_SUPPORTED 1 #define CONFIG_BT_CTRL_MODE_EFF 1 -#define CONFIG_BT_CTRL_BLE_MAX_ACT 10 -#define CONFIG_BT_CTRL_BLE_MAX_ACT_EFF 10 +#define CONFIG_BT_CTRL_BLE_MAX_ACT 6 +#define CONFIG_BT_CTRL_BLE_MAX_ACT_EFF 6 #define CONFIG_BT_CTRL_BLE_STATIC_ACL_TX_BUF_NB 0 #define CONFIG_BT_CTRL_PINNED_TO_CORE_0 1 #define CONFIG_BT_CTRL_PINNED_TO_CORE 0 @@ -1460,5 +1463,5 @@ #define CONFIG_WARN_WRITE_STRINGS CONFIG_COMPILER_WARN_WRITE_STRINGS #define CONFIG_WPA_MBEDTLS_CRYPTO CONFIG_ESP_WIFI_MBEDTLS_CRYPTO #define CONFIG_WPA_MBEDTLS_TLS_CLIENT CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT -#define CONFIG_ARDUINO_IDF_COMMIT "" +#define CONFIG_ARDUINO_IDF_COMMIT "420ebd208a" #define CONFIG_ARDUINO_IDF_BRANCH "release/v5.1" diff --git a/tools/sdk/esp32s3/qio_qspi/libbootloader_support.a b/tools/sdk/esp32s3/qio_qspi/libbootloader_support.a index 86a0624e56f..9e5dddd8387 100644 Binary files a/tools/sdk/esp32s3/qio_qspi/libbootloader_support.a and b/tools/sdk/esp32s3/qio_qspi/libbootloader_support.a differ diff --git a/tools/sdk/esp32s3/qio_qspi/libesp_hw_support.a b/tools/sdk/esp32s3/qio_qspi/libesp_hw_support.a index 5c9dbd1f4d9..ae06a8d8da3 100644 Binary files a/tools/sdk/esp32s3/qio_qspi/libesp_hw_support.a and b/tools/sdk/esp32s3/qio_qspi/libesp_hw_support.a differ diff --git a/tools/sdk/esp32s3/qio_qspi/libesp_psram.a b/tools/sdk/esp32s3/qio_qspi/libesp_psram.a index b2a666db3b1..2bb493b5051 100644 Binary files a/tools/sdk/esp32s3/qio_qspi/libesp_psram.a and b/tools/sdk/esp32s3/qio_qspi/libesp_psram.a differ diff --git a/tools/sdk/esp32s3/qio_qspi/libesp_system.a b/tools/sdk/esp32s3/qio_qspi/libesp_system.a index 11d60225e4b..1e70838e0e0 100644 Binary files a/tools/sdk/esp32s3/qio_qspi/libesp_system.a and b/tools/sdk/esp32s3/qio_qspi/libesp_system.a differ diff --git a/tools/sdk/esp32s3/qio_qspi/libfreertos.a b/tools/sdk/esp32s3/qio_qspi/libfreertos.a index cea0d5580d5..3ee1893d659 100644 Binary files a/tools/sdk/esp32s3/qio_qspi/libfreertos.a and b/tools/sdk/esp32s3/qio_qspi/libfreertos.a differ diff --git a/tools/sdk/esp32s3/qio_qspi/libspi_flash.a b/tools/sdk/esp32s3/qio_qspi/libspi_flash.a index a7fccaf646f..765b3100b61 100644 Binary files a/tools/sdk/esp32s3/qio_qspi/libspi_flash.a and b/tools/sdk/esp32s3/qio_qspi/libspi_flash.a differ diff --git a/tools/sdk/esp32s3/qio_qspi/sections.ld b/tools/sdk/esp32s3/qio_qspi/sections.ld index 04b403f89cb..bad0471018f 100644 --- a/tools/sdk/esp32s3/qio_qspi/sections.ld +++ b/tools/sdk/esp32s3/qio_qspi/sections.ld @@ -1,6 +1,6 @@ /* Automatically generated file; DO NOT EDIT */ /* Espressif IoT Development Framework Linker Script */ -/* Generated from: /Users/ficeto/Desktop/ESP32/ESP-IDF-5/esp32-arduino-lib-builder/esp-idf/components/esp_system/ld/esp32s3/sections.ld.in */ +/* Generated from: /home/runner/work/esp32-arduino-lib-builder/esp32-arduino-lib-builder/esp-idf/components/esp_system/ld/esp32s3/sections.ld.in */ /* * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD @@ -496,7 +496,7 @@ SECTIONS *libesp_system.a:esp_system_chip.*(.literal.esp_get_free_heap_size .literal.esp_get_free_internal_heap_size .literal.esp_get_idf_version .literal.esp_get_minimum_free_heap_size .text .text.esp_get_free_heap_size .text.esp_get_free_internal_heap_size .text.esp_get_idf_version .text.esp_get_minimum_free_heap_size) *libfreertos.a:app_startup.*(.literal .literal.* .text .text.*) *libheap.a:multi_heap.*(.literal.multi_heap_check .literal.multi_heap_dump .literal.multi_heap_dump_tlsf .literal.multi_heap_get_info_impl .literal.multi_heap_register_impl .literal.tlsf_check_hook .text .text.multi_heap_check .text.multi_heap_dump .text.multi_heap_dump_tlsf .text.multi_heap_free_size_impl .text.multi_heap_get_info_impl .text.multi_heap_get_info_tlsf .text.multi_heap_minimum_free_size_impl .text.multi_heap_register_impl .text.tlsf_check_hook) - *libheap.a:multi_heap_poisoning.*(.literal.multi_heap_free_size .literal.multi_heap_get_info .literal.multi_heap_minimum_free_size .literal.multi_heap_register .text .text.multi_heap_free_size .text.multi_heap_get_info .text.multi_heap_minimum_free_size .text.multi_heap_register .text.subtract_poison_overhead) + *libheap.a:multi_heap_poisoning.*(.literal.multi_heap_free_size .literal.multi_heap_get_info .literal.multi_heap_minimum_free_size .literal.multi_heap_register .text .text.multi_heap_free_size .text.multi_heap_get_info .text.multi_heap_minimum_free_size .text.multi_heap_register) *libheap.a:tlsf.*(.literal.default_walker .literal.tlsf_add_pool .literal.tlsf_check .literal.tlsf_check_pool .literal.tlsf_create .literal.tlsf_create_with_pool .literal.tlsf_remove_pool .literal.tlsf_walk_pool .text .text.default_walker .text.integrity_walker .text.tlsf_add_pool .text.tlsf_check .text.tlsf_check_pool .text.tlsf_create .text.tlsf_create_with_pool .text.tlsf_destroy .text.tlsf_fit_size .text.tlsf_pool_overhead .text.tlsf_remove_pool .text.tlsf_walk_pool) *liblog.a:log.*(.literal.esp_log_level_get .literal.esp_log_level_set .literal.esp_log_set_vprintf .literal.esp_log_writev .literal.heap_bubble_down .literal.s_log_level_get_and_unlock .text .text.esp_log_level_get .text.esp_log_level_set .text.esp_log_set_vprintf .text.esp_log_writev .text.heap_bubble_down .text.s_log_level_get_and_unlock) *liblog.a:log_freertos.*(.literal.esp_log_system_timestamp .text .text.esp_log_system_timestamp) diff --git a/tools/sdk/esp32s3/sdkconfig b/tools/sdk/esp32s3/sdkconfig index a6a5ca20621..40be6529d50 100644 --- a/tools/sdk/esp32s3/sdkconfig +++ b/tools/sdk/esp32s3/sdkconfig @@ -271,6 +271,8 @@ CONFIG_SOC_EFUSE_HARD_DIS_JTAG=y CONFIG_SOC_EFUSE_DIS_USB_JTAG=y CONFIG_SOC_EFUSE_SOFT_DIS_JTAG=y CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT=y +CONFIG_SOC_EFUSE_DIS_ICACHE=y +CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK=y CONFIG_SOC_SECURE_BOOT_V2_RSA=y CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS=3 CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS=y @@ -308,6 +310,7 @@ CONFIG_SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW=y CONFIG_SOC_BLE_SUPPORTED=y CONFIG_SOC_BLE_MESH_SUPPORTED=y CONFIG_SOC_BLE_50_SUPPORTED=y +CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED=y CONFIG_IDF_CMAKE=y CONFIG_IDF_TARGET_ARCH_XTENSA=y CONFIG_IDF_TARGET_ARCH="xtensa" @@ -356,6 +359,7 @@ CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP=y # CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS is not set CONFIG_BOOTLOADER_RESERVE_RTC_SIZE=0x10 # CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC is not set +CONFIG_BOOTLOADER_RESERVE_RTC_MEM=y CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT=y # end of Bootloader config @@ -413,9 +417,9 @@ CONFIG_BOOT_ROM_LOG_ALWAYS_ON=y # CONFIG_ESPTOOLPY_NO_STUB is not set # CONFIG_ESPTOOLPY_OCT_FLASH is not set CONFIG_ESPTOOLPY_FLASH_MODE_AUTO_DETECT=y -# CONFIG_ESPTOOLPY_FLASHMODE_QIO is not set +CONFIG_ESPTOOLPY_FLASHMODE_QIO=y # CONFIG_ESPTOOLPY_FLASHMODE_QOUT is not set -CONFIG_ESPTOOLPY_FLASHMODE_DIO=y +# CONFIG_ESPTOOLPY_FLASHMODE_DIO is not set # CONFIG_ESPTOOLPY_FLASHMODE_DOUT is not set CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR=y CONFIG_ESPTOOLPY_FLASHMODE="dio" @@ -457,7 +461,7 @@ CONFIG_PARTITION_TABLE_OFFSET=0x8000 CONFIG_PARTITION_TABLE_MD5=y # end of Partition Table -CONFIG_LIB_BUILDER_FLASHMODE="dio" +CONFIG_LIB_BUILDER_FLASHMODE="qio" CONFIG_LIB_BUILDER_FLASHFREQ="80m" CONFIG_LIB_BUILDER_COMPILE=y @@ -1141,7 +1145,6 @@ CONFIG_BT_SMP_ENABLE=y # CONFIG_BT_BLE_ACT_SCAN_REP_ADV_SCAN is not set CONFIG_BT_BLE_ESTAB_LINK_CONN_TOUT=30 CONFIG_BT_MAX_DEVICE_NAME_LEN=32 -CONFIG_BT_BLE_RPA_SUPPORTED=y CONFIG_BT_BLE_RPA_TIMEOUT=900 CONFIG_BT_BLE_50_FEATURES_SUPPORTED=y CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y @@ -1151,8 +1154,8 @@ CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y # Controller Options # CONFIG_BT_CTRL_MODE_EFF=1 -CONFIG_BT_CTRL_BLE_MAX_ACT=10 -CONFIG_BT_CTRL_BLE_MAX_ACT_EFF=10 +CONFIG_BT_CTRL_BLE_MAX_ACT=6 +CONFIG_BT_CTRL_BLE_MAX_ACT_EFF=6 CONFIG_BT_CTRL_BLE_STATIC_ACL_TX_BUF_NB=0 CONFIG_BT_CTRL_PINNED_TO_CORE_0=y # CONFIG_BT_CTRL_PINNED_TO_CORE_1 is not set @@ -1327,6 +1330,7 @@ CONFIG_BLE_MESH_DISCARD_OLD_SEQ_AUTH=y # BLE Mesh specific test option # # CONFIG_BLE_MESH_SELF_TEST is not set +# CONFIG_BLE_MESH_BQB_TEST is not set # CONFIG_BLE_MESH_SHELL is not set # CONFIG_BLE_MESH_DEBUG is not set # end of BLE Mesh specific test option @@ -1699,15 +1703,13 @@ CONFIG_SPIRAM_CS_IO=26 # CONFIG_SPIRAM_FETCH_INSTRUCTIONS is not set # CONFIG_SPIRAM_RODATA is not set # CONFIG_SPIRAM_SPEED_120M is not set -# CONFIG_SPIRAM_SPEED_80M is not set -CONFIG_SPIRAM_SPEED_40M=y -CONFIG_SPIRAM_SPEED=40 -CONFIG_SPIRAM_BOOT_INIT=y -# CONFIG_SPIRAM_IGNORE_NOTFOUND is not set +CONFIG_SPIRAM_SPEED_80M=y +# CONFIG_SPIRAM_SPEED_40M is not set +CONFIG_SPIRAM_SPEED=80 +# CONFIG_SPIRAM_BOOT_INIT is not set # CONFIG_SPIRAM_USE_MEMMAP is not set # CONFIG_SPIRAM_USE_CAPS_ALLOC is not set CONFIG_SPIRAM_USE_MALLOC=y -CONFIG_SPIRAM_MEMTEST=y CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=4096 CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP=y CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL=0 @@ -1719,7 +1721,6 @@ CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL=0 # ESP Ringbuf # # CONFIG_RINGBUF_PLACE_FUNCTIONS_INTO_FLASH is not set -# CONFIG_RINGBUF_PLACE_ISR_FUNCTIONS_INTO_FLASH is not set # end of ESP Ringbuf # @@ -1902,12 +1903,19 @@ CONFIG_ESP_WIFI_MBEDTLS_CRYPTO=y CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT=y # CONFIG_ESP_WIFI_WAPI_PSK is not set # CONFIG_ESP_WIFI_SUITE_B_192 is not set -# CONFIG_ESP_WIFI_WPS_STRICT is not set # CONFIG_ESP_WIFI_11KV_SUPPORT is not set # CONFIG_ESP_WIFI_MBO_SUPPORT is not set # CONFIG_ESP_WIFI_DPP_SUPPORT is not set # CONFIG_ESP_WIFI_11R_SUPPORT is not set # CONFIG_ESP_WIFI_WPS_SOFTAP_REGISTRAR is not set + +# +# WPS Configuration Options +# +# CONFIG_ESP_WIFI_WPS_STRICT is not set +# CONFIG_ESP_WIFI_WPS_PASSPHRASE is not set +# end of WPS Configuration Options + # CONFIG_ESP_WIFI_DEBUG_PRINT is not set # CONFIG_ESP_WIFI_TESTING_OPTIONS is not set # end of Wi-Fi @@ -2044,6 +2052,7 @@ CONFIG_HEAP_POISONING_LIGHT=y CONFIG_HEAP_TRACING_OFF=y # CONFIG_HEAP_TRACING_STANDALONE is not set # CONFIG_HEAP_TRACING_TOHOST is not set +# CONFIG_HEAP_USE_HOOKS is not set # CONFIG_HEAP_TASK_TRACKING is not set # CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS is not set # end of Heap memory debugging @@ -2783,6 +2792,8 @@ CONFIG_MDNS_PREDEF_NETIF_ETH=y # end of mDNS # end of Component config +# CONFIG_IDF_EXPERIMENTAL_FEATURES is not set + # Deprecated options for backward compatibility # CONFIG_APP_BUILD_TYPE_ELF_RAM is not set # CONFIG_NO_BLOBS is not set @@ -2796,9 +2807,9 @@ CONFIG_LOG_BOOTLOADER_LEVEL=0 CONFIG_APP_ROLLBACK_ENABLE=y # CONFIG_APP_ANTI_ROLLBACK is not set # CONFIG_FLASH_ENCRYPTION_ENABLED is not set -# CONFIG_FLASHMODE_QIO is not set +CONFIG_FLASHMODE_QIO=y # CONFIG_FLASHMODE_QOUT is not set -CONFIG_FLASHMODE_DIO=y +# CONFIG_FLASHMODE_DIO is not set # CONFIG_FLASHMODE_DOUT is not set CONFIG_MONITOR_BAUD=115200 # CONFIG_OPTIMIZATION_LEVEL_DEBUG is not set @@ -3100,12 +3111,12 @@ CONFIG_WPA_MBEDTLS_CRYPTO=y CONFIG_WPA_MBEDTLS_TLS_CLIENT=y # CONFIG_WPA_WAPI_PSK is not set # CONFIG_WPA_SUITE_B_192 is not set -# CONFIG_WPA_WPS_STRICT is not set # CONFIG_WPA_11KV_SUPPORT is not set # CONFIG_WPA_MBO_SUPPORT is not set # CONFIG_WPA_DPP_SUPPORT is not set # CONFIG_WPA_11R_SUPPORT is not set # CONFIG_WPA_WPS_SOFTAP_REGISTRAR is not set +# CONFIG_WPA_WPS_STRICT is not set # CONFIG_WPA_DEBUG_PRINT is not set # CONFIG_WPA_TESTING_OPTIONS is not set CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH=y diff --git a/tools/sdk/tools.json b/tools/sdk/tools.json index 370997044d1..8de812616ca 100644 --- a/tools/sdk/tools.json +++ b/tools/sdk/tools.json @@ -37,7 +37,7 @@ { "packager": "esp32", "name": "openocd-esp32", - "version": "v0.11.0-esp32-20221026" + "version": "v0.12.0-esp32-20230313" } ] } @@ -417,56 +417,56 @@ }, { "name": "openocd-esp32", - "version": "v0.11.0-esp32-20221026", + "version": "v0.12.0-esp32-20230313", "systems": [ { "host": "x86_64-pc-linux-gnu", - "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.11.0-esp32-20221026/openocd-esp32-linux-amd64-0.11.0-esp32-20221026.tar.gz", - "archiveFileName": "openocd-esp32-linux-amd64-0.11.0-esp32-20221026.tar.gz", - "checksum": "SHA-256:ce63e9b1dfab60cc62da5dc2abcc22ba7036c42afe74671c787eb026744e7d0b", - "size": "2051435" + "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20230313/openocd-esp32-linux-amd64-0.12.0-esp32-20230313.tar.gz", + "archiveFileName": "openocd-esp32-linux-amd64-0.12.0-esp32-20230313.tar.gz", + "checksum": "SHA-256:a62e560eba02eeca82d52b8eea8ef1e432e083242ce6b01033815e9afad4343e", + "size": "2087489" }, { "host": "aarch64-linux-gnu", - "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.11.0-esp32-20221026/openocd-esp32-linux-arm64-0.11.0-esp32-20221026.tar.gz", - "archiveFileName": "openocd-esp32-linux-arm64-0.11.0-esp32-20221026.tar.gz", - "checksum": "SHA-256:fe60a3a603e8c6bee47367e40fcb8c0da3a38e01163e9674ebc919b067700506", - "size": "1993843" + "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20230313/openocd-esp32-linux-arm64-0.12.0-esp32-20230313.tar.gz", + "archiveFileName": "openocd-esp32-linux-arm64-0.12.0-esp32-20230313.tar.gz", + "checksum": "SHA-256:12570d3513ace5a8f6f4afb53605abc2ed572243fa36f1c797ae7f7a8558deed", + "size": "1984119" }, { "host": "arm-linux-gnueabihf", - "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.11.0-esp32-20221026/openocd-esp32-linux-armel-0.11.0-esp32-20221026.tar.gz", - "archiveFileName": "openocd-esp32-linux-armel-0.11.0-esp32-20221026.tar.gz", - "checksum": "SHA-256:6ef76101cca196a4be30fc74f191eff34abb423e32930a383012b866c9b76135", - "size": "2092111" + "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20230313/openocd-esp32-linux-armel-0.12.0-esp32-20230313.tar.gz", + "archiveFileName": "openocd-esp32-linux-armel-0.12.0-esp32-20230313.tar.gz", + "checksum": "SHA-256:e1b300a87f83a665d33ae9d8f7a47b883f1d0a20a90c30cdaa9ed0750ddc7a61", + "size": "2126878" }, { "host": "x86_64-apple-darwin", - "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.11.0-esp32-20221026/openocd-esp32-macos-0.11.0-esp32-20221026.tar.gz", - "archiveFileName": "openocd-esp32-macos-0.11.0-esp32-20221026.tar.gz", - "checksum": "SHA-256:8edc666a0a230432554b73df7c62e0b5ec21fb018e7fda13b11a7ca8b6c1763b", - "size": "2199855" + "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20230313/openocd-esp32-macos-0.12.0-esp32-20230313.tar.gz", + "archiveFileName": "openocd-esp32-macos-0.12.0-esp32-20230313.tar.gz", + "checksum": "SHA-256:3c462379fdca456eb9fcd696f68b489602cd51d80ebc7b45fc9f0c41404f382a", + "size": "2191546" }, { "host": "arm64-apple-darwin", - "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.11.0-esp32-20221026/openocd-esp32-macos-arm64-0.11.0-esp32-20221026.tar.gz", - "archiveFileName": "openocd-esp32-macos-arm64-0.11.0-esp32-20221026.tar.gz", - "checksum": "SHA-256:c426c0158ba6488e2f432f7c5b22e79155b5b0fae6d1ad5bbd7894723b43aa12", - "size": "2247179" + "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20230313/openocd-esp32-macos-arm64-0.12.0-esp32-20230313.tar.gz", + "archiveFileName": "openocd-esp32-macos-arm64-0.12.0-esp32-20230313.tar.gz", + "checksum": "SHA-256:d19628bd64008298180a93c36fb8a3f0586c13800f5bb66c0a0f25c7eb9a8d6e", + "size": "2239378" }, { "host": "i686-mingw32", - "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.11.0-esp32-20221026/openocd-esp32-win32-0.11.0-esp32-20221026.zip", - "archiveFileName": "openocd-esp32-win32-0.11.0-esp32-20221026.zip", - "checksum": "SHA-256:e0e789d35308c029c6b53457cf4a42a5620cb1a3014740026c089c2ed4fd77b2", - "size": "2493214" + "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20230313/openocd-esp32-win32-0.12.0-esp32-20230313.zip", + "archiveFileName": "openocd-esp32-win32-0.12.0-esp32-20230313.zip", + "checksum": "SHA-256:46580ccb9cc00d76c419636b884c5cc57422124a0a0f755595218f30b92884fa", + "size": "2492151" }, { "host": "x86_64-mingw32", - "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.11.0-esp32-20221026/openocd-esp32-win32-0.11.0-esp32-20221026.zip", - "archiveFileName": "openocd-esp32-win32-0.11.0-esp32-20221026.zip", - "checksum": "SHA-256:e0e789d35308c029c6b53457cf4a42a5620cb1a3014740026c089c2ed4fd77b2", - "size": "2493214" + "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20230313/openocd-esp32-win32-0.12.0-esp32-20230313.zip", + "archiveFileName": "openocd-esp32-win32-0.12.0-esp32-20230313.zip", + "checksum": "SHA-256:46580ccb9cc00d76c419636b884c5cc57422124a0a0f755595218f30b92884fa", + "size": "2492151" } ] } diff --git a/tools/sdk/versions.txt b/tools/sdk/versions.txt index 938d9d24d95..a95b594b7e3 100644 --- a/tools/sdk/versions.txt +++ b/tools/sdk/versions.txt @@ -1,10 +1,10 @@ -esp-idf: release/v5.1 bb9200acec -arduino: esp-idf-v5.1-libs 1f0343d2 +esp-idf: release/v5.1 420ebd208a +arduino: idf-release/v5.1 cc29d126 esp-dl: master 0632d24 esp-insights: main d8b2dfc esp-rainmaker: master cc861bf esp-sr: master a3b0d67 -esp32-camera: master 6edafc7 +esp32-camera: master 2e6a36d esp_littlefs: master fb1470a espressif__esp-dsp: master b376d9f tinyusb: master 28817a715