From 82d444ec96527ec9db8ecc8ae85cf369a3fa4c5a Mon Sep 17 00:00:00 2001 From: hreintke Date: Fri, 24 Jan 2020 16:55:36 +0100 Subject: [PATCH 1/2] Minimize HardwareSerial Receive and Transmit delays --- cores/esp32/esp32-hal-uart.c | 26 +++++++++++++++++++++++++- cores/esp32/esp32-hal-uart.h | 2 ++ 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/cores/esp32/esp32-hal-uart.c b/cores/esp32/esp32-hal-uart.c index 90acf54f2b1..8ec1fe6f7d1 100644 --- a/cores/esp32/esp32-hal-uart.c +++ b/cores/esp32/esp32-hal-uart.c @@ -208,6 +208,11 @@ uart_t* uartBegin(uint8_t uart_nr, uint32_t baudrate, uint32_t config, int8_t rx uart->dev->conf0.stop_bit_num = ONE_STOP_BITS_CONF; uart->dev->rs485_conf.dl1_en = 1; } + + // tx_idle_num : idle interval after tx FIFO is empty(unit: the time it takes to send one bit under current baudrate) + // Setting it to 0 prevents line idle time/delays when sending messages with small intervals + uart->dev->idle_conf.tx_idle_num = 0; // + UART_MUTEX_UNLOCK(); if(rxPin != -1) { @@ -265,7 +270,7 @@ uint32_t uartAvailable(uart_t* uart) if(uart == NULL || uart->queue == NULL) { return 0; } - return uxQueueMessagesWaiting(uart->queue); + return (uxQueueMessagesWaiting(uart->queue) + uart->dev->status.rxfifo_cnt) ; } uint32_t uartAvailableForWrite(uart_t* uart) @@ -276,12 +281,27 @@ uint32_t uartAvailableForWrite(uart_t* uart) return 0x7f - uart->dev->status.txfifo_cnt; } +void uartRxFifoToQueue(uart_t* uart) +{ + uint8_t c; + UART_MUTEX_LOCK(); + while(uart->dev->status.rxfifo_cnt || (uart->dev->mem_rx_status.wr_addr != uart->dev->mem_rx_status.rd_addr)) { + c = uart->dev->fifo.rw_byte; + xQueueSend(uart->queue, &c, 0); + } + UART_MUTEX_UNLOCK(); +} + uint8_t uartRead(uart_t* uart) { if(uart == NULL || uart->queue == NULL) { return 0; } uint8_t c; + if ((uxQueueMessagesWaiting(uart->queue) == 0) && (uart->dev->status.rxfifo_cnt > 0)) + { + uartRxFifoToQueue(uart); + } if(xQueueReceive(uart->queue, &c, 0)) { return c; } @@ -294,6 +314,10 @@ uint8_t uartPeek(uart_t* uart) return 0; } uint8_t c; + if ((uxQueueMessagesWaiting(uart->queue) == 0) && (uart->dev->status.rxfifo_cnt > 0)) + { + uartRxFifoToQueue(uart); + } if(xQueuePeek(uart->queue, &c, 0)) { return c; } diff --git a/cores/esp32/esp32-hal-uart.h b/cores/esp32/esp32-hal-uart.h index e44d25bbc5e..8c4bb8f0e07 100644 --- a/cores/esp32/esp32-hal-uart.h +++ b/cores/esp32/esp32-hal-uart.h @@ -59,6 +59,8 @@ uint32_t uartAvailableForWrite(uart_t* uart); uint8_t uartRead(uart_t* uart); uint8_t uartPeek(uart_t* uart); +void uartRxFifoToQueue(uart_t* uart); + void uartWrite(uart_t* uart, uint8_t c); void uartWriteBuf(uart_t* uart, const uint8_t * data, size_t len); From 3ab827334b57c2fd603b3cad6b9f29f02dffcb5e Mon Sep 17 00:00:00 2001 From: hreintke Date: Sat, 25 Jan 2020 16:44:51 +0100 Subject: [PATCH 2/2] Remove uartRxFifoToQueue from esp-hal-uart.h --- cores/esp32/esp32-hal-uart.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/cores/esp32/esp32-hal-uart.h b/cores/esp32/esp32-hal-uart.h index 8c4bb8f0e07..e44d25bbc5e 100644 --- a/cores/esp32/esp32-hal-uart.h +++ b/cores/esp32/esp32-hal-uart.h @@ -59,8 +59,6 @@ uint32_t uartAvailableForWrite(uart_t* uart); uint8_t uartRead(uart_t* uart); uint8_t uartPeek(uart_t* uart); -void uartRxFifoToQueue(uart_t* uart); - void uartWrite(uart_t* uart, uint8_t c); void uartWriteBuf(uart_t* uart, const uint8_t * data, size_t len);