diff --git a/cores/esp32/esp32-hal-misc.c b/cores/esp32/esp32-hal-misc.c index 09383fbd4f7..f3175c9d0ae 100644 --- a/cores/esp32/esp32-hal-misc.c +++ b/cores/esp32/esp32-hal-misc.c @@ -21,6 +21,9 @@ #include "esp_partition.h" #include "esp_log.h" #include "esp_timer.h" +#ifdef CONFIG_APP_ROLLBACK_ENABLE +#include "esp_ota_ops.h" +#endif //CONFIG_APP_ROLLBACK_ENABLE #ifdef CONFIG_BT_ENABLED #include "esp_bt.h" #endif //CONFIG_BT_ENABLED @@ -145,6 +148,9 @@ void initVariant() {} void init() __attribute__((weak)); void init() {} +bool verifyOta() __attribute__((weak)); +bool verifyOta() { return true; } + #ifdef CONFIG_BT_ENABLED //overwritten in esp32-hal-bt.c bool btInUse() __attribute__((weak)); @@ -153,6 +159,20 @@ bool btInUse(){ return false; } void initArduino() { +#ifdef CONFIG_APP_ROLLBACK_ENABLE + const esp_partition_t *running = esp_ota_get_running_partition(); + esp_ota_img_states_t ota_state; + if (esp_ota_get_state_partition(running, &ota_state) == ESP_OK) { + if (ota_state == ESP_OTA_IMG_PENDING_VERIFY) { + if (verifyOta()) { + esp_ota_mark_app_valid_cancel_rollback(); + } else { + log_e("OTA verification failed! Start rollback to the previous version ..."); + esp_ota_mark_app_invalid_rollback_and_reboot(); + } + } + } +#endif //init proper ref tick value for PLL (uncomment if REF_TICK is different than 1MHz) //ESP_REG(APB_CTRL_PLL_TICK_CONF_REG) = APB_CLK_FREQ / REF_CLK_FREQ - 1; #ifdef F_CPU diff --git a/cores/esp32/esp32-hal-psram.c b/cores/esp32/esp32-hal-psram.c index 9a1fd8cd37d..905cb96a313 100644 --- a/cores/esp32/esp32-hal-psram.c +++ b/cores/esp32/esp32-hal-psram.c @@ -19,7 +19,7 @@ bool psramInit(){ } uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG); uint32_t pkg_ver = chip_ver & 0x7; - if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 || pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 || pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) { + if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 || pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) { spiramFailed = true; log_w("PSRAM not supported!"); return false; diff --git a/package/package_esp32_index.template.json b/package/package_esp32_index.template.json index ec5bdfbbf66..b8692bdf66e 100644 --- a/package/package_esp32_index.template.json +++ b/package/package_esp32_index.template.json @@ -38,7 +38,7 @@ { "packager": "esp32", "name": "esptool_py", - "version": "2.6.0" + "version": "2.6.1" }, { "packager": "esp32", @@ -85,42 +85,42 @@ }, { "name": "esptool_py", - "version": "2.6.0", + "version": "2.6.1", "systems": [ { "host": "i686-mingw32", - "url": "https://dl.espressif.com/dl/esptool-2.6.0-windows.zip", - "archiveFileName": "esptool-2.6.0-windows.zip", - "checksum": "SHA-256:a73f4cf68db240d7f1d250c5c7f2dfcb53c17a37483729f1bf71f8f43d79a799", - "size": "3421208" + "url": "https://dl.espressif.com/dl/esptool-2.6.1-windows.zip", + "archiveFileName": "esptool-2.6.1-windows.zip", + "checksum": "SHA-256:84cf0b369a7707fe566434faba148852fc464992111d5baa95b658b374802f96", + "size": "3422445" }, { "host": "x86_64-apple-darwin", - "url": "https://dl.espressif.com/dl/esptool-2.6.0-macos.tar.gz", - "archiveFileName": "esptool-2.6.0-macos.tar.gz", - "checksum": "SHA-256:0a881b91547c840fab8c72ae3d031069384278b8c2e5241647e8c8292c5e4a4b", - "size": "3835660" + "url": "https://dl.espressif.com/dl/esptool-2.6.1-macos.tar.gz", + "archiveFileName": "esptool-2.6.1-macos.tar.gz", + "checksum": "SHA-256:f4eb758a301d6902cc9dfcd49d36345d2f075ad123da7cf8132d15cfb7533457", + "size": "3837085" }, { "host": "x86_64-pc-linux-gnu", - "url": "https://dl.espressif.com/dl/esptool-2.6.0-linux.tar.gz", - "archiveFileName": "esptool-2.6.0-linux.tar.gz", - "checksum": "SHA-256:6d162f70f395ca31f5008829dd7e833e729f044a9c7355d5be8ce333a054e110", - "size": "43535" + "url": "https://dl.espressif.com/dl/esptool-2.6.1-linux.tar.gz", + "archiveFileName": "esptool-2.6.1-linux.tar.gz", + "checksum": "SHA-256:eaf82ff4070d9792f6a42ae1e485375de5a87bec59ef01dfb95de901519ec7fb", + "size": "44762" }, { "host": "i686-pc-linux-gnu", - "url": "https://dl.espressif.com/dl/esptool-2.6.0-linux.tar.gz", - "archiveFileName": "esptool-2.6.0-linux.tar.gz", - "checksum": "SHA-256:6d162f70f395ca31f5008829dd7e833e729f044a9c7355d5be8ce333a054e110", - "size": "43535" + "url": "https://dl.espressif.com/dl/esptool-2.6.1-linux.tar.gz", + "archiveFileName": "esptool-2.6.1-linux.tar.gz", + "checksum": "SHA-256:eaf82ff4070d9792f6a42ae1e485375de5a87bec59ef01dfb95de901519ec7fb", + "size": "44762" }, { "host": "arm-linux-gnueabihf", - "url": "https://dl.espressif.com/dl/esptool-2.6.0-linux.tar.gz", - "archiveFileName": "esptool-2.6.0-linux.tar.gz", - "checksum": "SHA-256:6d162f70f395ca31f5008829dd7e833e729f044a9c7355d5be8ce333a054e110", - "size": "43535" + "url": "https://dl.espressif.com/dl/esptool-2.6.1-linux.tar.gz", + "archiveFileName": "esptool-2.6.1-linux.tar.gz", + "checksum": "SHA-256:eaf82ff4070d9792f6a42ae1e485375de5a87bec59ef01dfb95de901519ec7fb", + "size": "44762" } ] }, diff --git a/tools/esptool.py b/tools/esptool.py index a091a8f2f99..6bfa1f7b667 100755 --- a/tools/esptool.py +++ b/tools/esptool.py @@ -32,9 +32,12 @@ import time import zlib import string -import serial.tools.list_ports as list_ports -import serial +try: + import serial +except ImportError: + print("Pyserial is not installed for %s. Check the README for installation instructions." % (sys.executable)) + raise # check 'serial' is 'pyserial' and not 'serial' https://github.com/espressif/esptool/issues/269 try: @@ -50,8 +53,14 @@ except TypeError: pass # __doc__ returns None for pyserial +try: + import serial.tools.list_ports as list_ports +except ImportError: + print("The installed version (%s) of pyserial appears to be too old for esptool.py (Python interpreter %s). " + "Check the README for installation instructions." % (sys.VERSION, sys.executable)) + raise -__version__ = "2.6-beta1" +__version__ = "2.6" MAX_UINT32 = 0xffffffff MAX_UINT24 = 0xffffff @@ -221,7 +230,12 @@ def __init__(self, port=DEFAULT_PORT, baud=ESP_ROM_BAUD, trace_enabled=False): self._set_port_baudrate(baud) self._trace_enabled = trace_enabled # set write timeout, to prevent esptool blocked at write forever. - self._port.write_timeout = DEFAULT_SERIAL_WRITE_TIMEOUT + try: + self._port.write_timeout = DEFAULT_SERIAL_WRITE_TIMEOUT + except NotImplementedError: + # no write timeout for RFC2217 ports + # need to set the property back to None or it will continue to fail + self._port.write_timeout = None def _set_port_baudrate(self, baud): try: @@ -1274,19 +1288,26 @@ def __repr__(self): class BaseFirmwareImage(object): SEG_HEADER_LEN = 8 + SHA256_DIGEST_LEN = 32 """ Base class with common firmware image functions """ def __init__(self): self.segments = [] self.entrypoint = 0 + self.elf_sha256 = None + self.elf_sha256_offset = 0 def load_common_header(self, load_file, expected_magic): (magic, segments, self.flash_mode, self.flash_size_freq, self.entrypoint) = struct.unpack(' 16: - raise FatalError('Invalid firmware image magic=%d segments=%d' % (magic, segments)) + if magic != expected_magic: + raise FatalError('Invalid firmware image magic=0x%x' % (magic)) return segments + def verify(self): + if len(self.segments) > 16: + raise FatalError('Invalid segment count %d (max 16). Usually this indicates a linker script problem.' % len(self.segments)) + def load_segment(self, f, is_irom_segment=False): """ Load the next segment from the image file """ file_offs = f.tell() @@ -1304,12 +1325,33 @@ def warn_if_unusual_segment(self, offset, size, is_irom_segment): if offset > 0x40200000 or offset < 0x3ffe0000 or size > 65536: print('WARNING: Suspicious segment 0x%x, length %d' % (offset, size)) + def maybe_patch_segment_data(self, f, segment_data): + """If SHA256 digest of the ELF file needs to be inserted into this segment, do so. Returns segment data.""" + segment_len = len(segment_data) + file_pos = f.tell() + if self.elf_sha256_offset >= file_pos and self.elf_sha256_offset < file_pos + segment_len: + # SHA256 digest needs to be patched into this segment, + # calculate offset of the digest inside the segment. + patch_offset = self.elf_sha256_offset - file_pos + # Sanity checks + if patch_offset < self.SEG_HEADER_LEN or patch_offset + self.SHA256_DIGEST_LEN > segment_len: + raise FatalError('Can not place SHA256 digest on segment boundary' + + '(elf_sha256_offset=%d, file_pos=%d, segment_size=%d)' % + (self.elf_sha256_offset, file_pos, segment_len)) + assert(len(self.elf_sha256) == self.SHA256_DIGEST_LEN) + # offset relative to the data part + patch_offset -= self.SEG_HEADER_LEN + segment_data = segment_data[0:patch_offset] + self.elf_sha256 + \ + segment_data[patch_offset + self.SHA256_DIGEST_LEN:] + return segment_data + def save_segment(self, f, segment, checksum=None): """ Save the next segment to the image file, return next checksum value if provided """ - f.write(struct.pack(' 0: last_addr = flash_segments[0].addr for segment in flash_segments[1:]: - if segment.addr // IROM_ALIGN == last_addr // IROM_ALIGN: + if segment.addr // self.IROM_ALIGN == last_addr // self.IROM_ALIGN: raise FatalError(("Segment loaded at 0x%08x lands in same 64KB flash mapping as segment loaded at 0x%08x. " + "Can't generate binary. Suggest changing linker script or ELF to merge sections.") % (segment.addr, last_addr)) @@ -1596,15 +1644,15 @@ def get_alignment_data_needed(segment): # # (this is because the segment's vaddr may not be IROM_ALIGNed, more likely is aligned # IROM_ALIGN+0x18 to account for the binary file header - align_past = (segment.addr % IROM_ALIGN) - self.SEG_HEADER_LEN - pad_len = (IROM_ALIGN - (f.tell() % IROM_ALIGN)) + align_past - if pad_len == 0 or pad_len == IROM_ALIGN: + align_past = (segment.addr % self.IROM_ALIGN) - self.SEG_HEADER_LEN + pad_len = (self.IROM_ALIGN - (f.tell() % self.IROM_ALIGN)) + align_past + if pad_len == 0 or pad_len == self.IROM_ALIGN: return 0 # already aligned # subtract SEG_HEADER_LEN a second time, as the padding block has a header as well pad_len -= self.SEG_HEADER_LEN if pad_len < 0: - pad_len += IROM_ALIGN + pad_len += self.IROM_ALIGN return pad_len # try to fit each flash segment on a 64kB aligned boundary @@ -1623,8 +1671,8 @@ def get_alignment_data_needed(segment): total_segments += 1 else: # write the flash segment - assert (f.tell() + 8) % IROM_ALIGN == segment.addr % IROM_ALIGN - checksum = self.save_segment(f, segment, checksum) + assert (f.tell() + 8) % self.IROM_ALIGN == segment.addr % self.IROM_ALIGN + checksum = self.save_flash_segment(f, segment, checksum) flash_segments.pop(0) total_segments += 1 @@ -1638,12 +1686,12 @@ def get_alignment_data_needed(segment): # This ensures all mapped flash content will be verified. if not self.append_digest: raise FatalError("secure_pad only applies if a SHA-256 digest is also appended to the image") - align_past = (f.tell() + self.SEG_HEADER_LEN) % IROM_ALIGN + align_past = (f.tell() + self.SEG_HEADER_LEN) % self.IROM_ALIGN # 16 byte aligned checksum (force the alignment to simplify calculations) checksum_space = 16 # after checksum: SHA-256 digest + (to be added by signing process) version, signature + 12 trailing bytes due to alignment space_after_checksum = 32 + 4 + 64 + 12 - pad_len = (IROM_ALIGN - align_past - checksum_space - space_after_checksum) % IROM_ALIGN + pad_len = (self.IROM_ALIGN - align_past - checksum_space - space_after_checksum) % self.IROM_ALIGN pad_segment = ImageSegment(0, b'\x00' * pad_len, f.tell()) checksum = self.save_segment(f, pad_segment, checksum) @@ -1654,7 +1702,7 @@ def get_alignment_data_needed(segment): image_length = f.tell() if self.secure_pad: - assert ((image_length + space_after_checksum) % IROM_ALIGN) == 0 + assert ((image_length + space_after_checksum) % self.IROM_ALIGN) == 0 # kinda hacky: go back to the initial header and write the new segment count # that includes padding segments. This header is not checksummed @@ -1674,6 +1722,16 @@ def get_alignment_data_needed(segment): with open(filename, 'wb') as real_file: real_file.write(f.getvalue()) + def save_flash_segment(self, f, segment, checksum=None): + """ Save the next segment to the image file, return next checksum value if provided """ + segment_end_pos = f.tell() + len(segment.data) + self.SEG_HEADER_LEN + segment_len_remainder = segment_end_pos % self.IROM_ALIGN + if segment_len_remainder < 0x24: + # Work around a bug in ESP-IDF 2nd stage bootloader, that it didn't map the + # last MMU page, if an IROM/DROM segment was < 0x24 bytes over the page boundary. + segment.data += b'\x00' * (0x24 - segment_len_remainder) + return self.save_segment(f, segment, checksum) + def load_extended_header(self, load_file): def split_byte(n): return (n & 0x0F, (n >> 4) & 0x0F) @@ -1790,9 +1848,16 @@ def read_data(offs,size): return f.read(size) prog_sections = [ELFSection(lookup_string(n_offs), lma, read_data(offs, size)) for (n_offs, _type, lma, size, offs) in prog_sections - if lma != 0] + if lma != 0 and size > 0] self.sections = prog_sections + def sha256(self): + # return SHA256 hash of the input ELF file + sha256 = hashlib.sha256() + with open(self.name, 'rb') as f: + sha256.update(f.read()) + return sha256.digest() + def slip_reader(port, trace_function): """Generator to read SLIP packets from a serial port. @@ -1991,15 +2056,15 @@ def write_mem(esp, args): def dump_mem(esp, args): - f = open(args.filename, 'wb') - for i in range(args.size // 4): - d = esp.read_reg(args.address + (i * 4)) - f.write(struct.pack(b' -#include -#include "esp_err.h" - #ifdef __cplusplus extern "C" { #endif +#include "esp_types.h" +#include "esp_err.h" + +/** + * @brief Ethernet interface mode + * + */ typedef enum { - ETH_MODE_RMII = 0, - ETH_MODE_MII, + ETH_MODE_RMII = 0, /*!< RMII mode */ + ETH_MODE_MII, /*!< MII mode */ } eth_mode_t; +/** + * @brief Ethernet clock mode + * + */ typedef enum { - ETH_CLOCK_GPIO0_IN = 0, - ETH_CLOCK_GPIO16_OUT = 2, - ETH_CLOCK_GPIO17_OUT = 3 + ETH_CLOCK_GPIO0_IN = 0, /*!< RMII clock input to GPIO0 */ + ETH_CLOCK_GPIO0_OUT = 1, /*!< RMII clock output from GPIO0 */ + ETH_CLOCK_GPIO16_OUT = 2, /*!< RMII clock output from GPIO16 */ + ETH_CLOCK_GPIO17_OUT = 3 /*!< RMII clock output from GPIO17 */ } eth_clock_mode_t; +/** + * @brief Ethernet Speed + * + */ typedef enum { - ETH_SPEED_MODE_10M = 0, - ETH_SPEED_MODE_100M, + ETH_SPEED_MODE_10M = 0, /*!< Ethernet speed: 10Mbps */ + ETH_SPEED_MODE_100M, /*!< Ethernet speed: 100Mbps */ } eth_speed_mode_t; +/** + * @brief Ethernet Duplex + * + */ typedef enum { - ETH_MODE_HALFDUPLEX = 0, - ETH_MODE_FULLDUPLEX, + ETH_MODE_HALFDUPLEX = 0, /*!< Ethernet half duplex */ + ETH_MODE_FULLDUPLEX, /*!< Ethernet full duplex */ } eth_duplex_mode_t; +/** + * @brief Ethernet PHY address + * + */ typedef enum { - PHY0 = 0, - PHY1, - PHY2, - PHY3, - PHY4, - PHY5, - PHY6, - PHY7, - PHY8, - PHY9, - PHY10, - PHY11, - PHY12, - PHY13, - PHY14, - PHY15, - PHY16, - PHY17, - PHY18, - PHY19, - PHY20, - PHY21, - PHY22, - PHY23, - PHY24, - PHY25, - PHY26, - PHY27, - PHY28, - PHY29, - PHY30, - PHY31, + PHY0 = 0, /*!< PHY address 0 */ + PHY1, /*!< PHY address 1 */ + PHY2, /*!< PHY address 2 */ + PHY3, /*!< PHY address 3 */ + PHY4, /*!< PHY address 4 */ + PHY5, /*!< PHY address 5 */ + PHY6, /*!< PHY address 6 */ + PHY7, /*!< PHY address 7 */ + PHY8, /*!< PHY address 8 */ + PHY9, /*!< PHY address 9 */ + PHY10, /*!< PHY address 10 */ + PHY11, /*!< PHY address 11 */ + PHY12, /*!< PHY address 12 */ + PHY13, /*!< PHY address 13 */ + PHY14, /*!< PHY address 14 */ + PHY15, /*!< PHY address 15 */ + PHY16, /*!< PHY address 16 */ + PHY17, /*!< PHY address 17 */ + PHY18, /*!< PHY address 18 */ + PHY19, /*!< PHY address 19 */ + PHY20, /*!< PHY address 20 */ + PHY21, /*!< PHY address 21 */ + PHY22, /*!< PHY address 22 */ + PHY23, /*!< PHY address 23 */ + PHY24, /*!< PHY address 24 */ + PHY25, /*!< PHY address 25 */ + PHY26, /*!< PHY address 26 */ + PHY27, /*!< PHY address 27 */ + PHY28, /*!< PHY address 28 */ + PHY29, /*!< PHY address 29 */ + PHY30, /*!< PHY address 30 */ + PHY31 /*!< PHY address 31 */ } eth_phy_base_t; typedef bool (*eth_phy_check_link_func)(void); @@ -94,15 +114,15 @@ typedef void (*eth_phy_power_enable_func)(bool enable); * */ typedef struct { - eth_phy_base_t phy_addr; /*!< phy base addr (0~31) */ - eth_mode_t mac_mode; /*!< mac mode only support RMII now */ - eth_clock_mode_t clock_mode; /*!< external/internal clock mode selecton */ - eth_tcpip_input_func tcpip_input; /*!< tcpip input func */ - eth_phy_func phy_init; /*!< phy init func */ - eth_phy_check_link_func phy_check_link; /*!< phy check link func */ - eth_phy_check_init_func phy_check_init; /*!< phy check init func */ - eth_phy_get_speed_mode_func phy_get_speed_mode; /*!< phy check init func */ - eth_phy_get_duplex_mode_func phy_get_duplex_mode; /*!< phy check init func */ + eth_phy_base_t phy_addr; /*!< PHY address (0~31) */ + eth_mode_t mac_mode; /*!< MAC mode: only support RMII now */ + eth_clock_mode_t clock_mode; /*!< external/internal clock mode selection */ + eth_tcpip_input_func tcpip_input; /*!< tcpip input func */ + eth_phy_func phy_init; /*!< phy init func */ + eth_phy_check_link_func phy_check_link; /*!< phy check link func */ + eth_phy_check_init_func phy_check_init; /*!< phy check init func */ + eth_phy_get_speed_mode_func phy_get_speed_mode; /*!< phy check init func */ + eth_phy_get_duplex_mode_func phy_get_duplex_mode; /*!< phy check init func */ eth_gpio_config_func gpio_config; /*!< gpio config func */ bool flow_ctrl_enable; /*!< flag of flow ctrl enable */ eth_phy_get_partner_pause_enable_func phy_get_partner_pause_enable; /*!< get partner pause enable */ diff --git a/tools/sdk/include/ethernet/eth_phy/phy.h b/tools/sdk/include/ethernet/eth_phy/phy.h index 18b8f3f6c97..d38e9819d6d 100644 --- a/tools/sdk/include/ethernet/eth_phy/phy.h +++ b/tools/sdk/include/ethernet/eth_phy/phy.h @@ -20,38 +20,55 @@ extern "C" { #include "esp_eth.h" -/** Common PHY-management functions. - - These are not enough to drive any particular Ethernet PHY, but they provide a common configuration structure and - management functions. -*/ - -/** Configure fixed pins for RMII data interface. - - This configures GPIOs 0, 19, 22, 25, 26, 27 for use with RMII - data interface. These pins cannot be changed, and must be wired to - ethernet functions. +/** + * @brief Common PHY-management functions. + * + * @note These are not enough to drive any particular Ethernet PHY. + * They provide a common configuration structure and management functions. + * + */ - This is not sufficient to fully configure the Ethernet PHY, - MDIO configuration interface pins (such as SMI MDC, MDO, MDI) - must also be configured correctly in the GPIO matrix. -*/ +/** + * @brief Configure fixed pins for RMII data interface. + * + * @note This configures GPIOs 0, 19, 22, 25, 26, 27 for use with RMII data interface. + * These pins cannot be changed, and must be wired to ethernet functions. + * This is not sufficient to fully configure the Ethernet PHY. + * MDIO configuration interface pins (such as SMI MDC, MDO, MDI) must also be configured correctly in the GPIO matrix. + * + */ void phy_rmii_configure_data_interface_pins(void); -/** Configure variable pins for SMI (MDIO) ethernet functions. - - Calling this function along with mii_configure_default_pins() will - fully configure the GPIOs for the ethernet PHY. +/** + * @brief Configure variable pins for SMI ethernet functions. + * + * @param mdc_gpio MDC GPIO Pin number + * @param mdio_gpio MDIO GPIO Pin number + * + * @note Calling this function along with mii_configure_default_pins() will fully configure the GPIOs for the ethernet PHY. */ void phy_rmii_smi_configure_pins(uint8_t mdc_gpio, uint8_t mdio_gpio); - -/** Enable flow control in standard PHY MII register. +/** + * @brief Enable flow control in standard PHY MII register. + * */ void phy_mii_enable_flow_ctrl(void); +/** + * @brief Check Ethernet link status via MII interface + * + * @return true Link is on + * @return false Link is off + */ bool phy_mii_check_link_status(void); +/** + * @brief Check pause frame ability of partner via MII interface + * + * @return true Partner is able to process pause frame + * @return false Partner can not process pause frame + */ bool phy_mii_get_partner_pause_enable(void); #ifdef __cplusplus diff --git a/tools/sdk/include/ethernet/eth_phy/phy_ip101.h b/tools/sdk/include/ethernet/eth_phy/phy_ip101.h new file mode 100644 index 00000000000..d18ef2d0964 --- /dev/null +++ b/tools/sdk/include/ethernet/eth_phy/phy_ip101.h @@ -0,0 +1,75 @@ +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "phy.h" + +/** + * @brief Dump IP101 PHY SMI configuration registers + * + */ +void phy_ip101_dump_registers(); + +/** + * @brief Default IP101 phy_check_init function + * + */ +void phy_ip101_check_phy_init(void); + +/** + * @brief Default IP101 phy_get_speed_mode function + * + * @return eth_speed_mode_t Ethernet speed mode + */ +eth_speed_mode_t phy_ip101_get_speed_mode(void); + +/** + * @brief Default IP101 phy_get_duplex_mode function + * + * @return eth_duplex_mode_t Ethernet duplex mode + */ +eth_duplex_mode_t phy_ip101_get_duplex_mode(void); + +/** + * @brief Default IP101 phy_power_enable function + * + */ +void phy_ip101_power_enable(bool); + +/** + * @brief Default IP101 phy_init function + * + * @return esp_err_t + * - ESP_OK on success + * - ESP_FAIL on error + */ +esp_err_t phy_ip101_init(void); + +/** + * @brief Default IP101 PHY configuration + * + * @note This configuration is not suitable for use as-is, + * it will need to be modified for your particular PHY hardware setup. + * + */ +extern const eth_config_t phy_ip101_default_ethernet_config; + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/include/ethernet/eth_phy/phy_lan8720.h b/tools/sdk/include/ethernet/eth_phy/phy_lan8720.h index 325820bd866..1448f36556c 100644 --- a/tools/sdk/include/ethernet/eth_phy/phy_lan8720.h +++ b/tools/sdk/include/ethernet/eth_phy/phy_lan8720.h @@ -20,45 +20,53 @@ extern "C" { #include "phy.h" - -/** @brief Dump all LAN8720 PHY SMI configuration registers +/** + * @brief Dump LAN8720 PHY SMI configuration registers * - * @note These registers are dumped at 'debug' level, so output - * may not be visible depending on default log levels. */ void phy_lan8720_dump_registers(); -/** @brief Default LAN8720 phy_check_init function. +/** + * @brief Default LAN8720 phy_check_init function + * */ void phy_lan8720_check_phy_init(void); -/** @brief Default LAN8720 phy_get_speed_mode function. +/** + * @brief Default LAN8720 phy_get_speed_mode function + * + * @return eth_speed_mode_t Ethernet speed mode */ eth_speed_mode_t phy_lan8720_get_speed_mode(void); -/** @brief Default LAN8720 phy_get_duplex_mode function. +/** + * @brief Default LAN8720 phy_get_duplex_mode function + * + * @return eth_duplex_mode_t Ethernet duplex mode */ eth_duplex_mode_t phy_lan8720_get_duplex_mode(void); -/** @brief Default LAN8720 phy_power_enable function. - * - * @note This function may need to be replaced with a custom function - * if the PHY has a GPIO to enable power or start a clock. +/** + * @brief Default LAN8720 phy_power_enable function * - * Consult the ethernet example to see how this is done. */ void phy_lan8720_power_enable(bool); -/** @brief Default LAN8720 phy_init function. +/** + * @brief Default LAN8720 phy_init function + * + * @return esp_err_t + * - ESP_OK on success + * - ESP_FAIL on error */ esp_err_t phy_lan8720_init(void); -/** @brief Default LAN8720 PHY configuration +/** + * @brief Default LAN8720 PHY configuration * - * This configuration is not suitable for use as-is, it will need - * to be modified for your particular PHY hardware setup. + * @note This configuration is not suitable for use as-is, + * it will need to be modified for your particular PHY hardware setup. * - * Consult the Ethernet example to see how this is done. */ extern const eth_config_t phy_lan8720_default_ethernet_config; diff --git a/tools/sdk/include/ethernet/eth_phy/phy_reg.h b/tools/sdk/include/ethernet/eth_phy/phy_reg.h index 7dbf02b2e4c..2a9a141676a 100644 --- a/tools/sdk/include/ethernet/eth_phy/phy_reg.h +++ b/tools/sdk/include/ethernet/eth_phy/phy_reg.h @@ -18,9 +18,10 @@ extern "C" { #endif -/* This header contains register/bit masks for the standard - PHY MII registers that should be supported by all PHY models. -*/ +/** + * @brief This header contains register/bit masks for the standard PHY MII registers that should be supported by all PHY models. + * + */ #define MII_BASIC_MODE_CONTROL_REG (0x0) #define MII_SOFTWARE_RESET BIT(15) diff --git a/tools/sdk/include/ethernet/eth_phy/phy_tlk110.h b/tools/sdk/include/ethernet/eth_phy/phy_tlk110.h index e6b2d974997..077f13cece0 100644 --- a/tools/sdk/include/ethernet/eth_phy/phy_tlk110.h +++ b/tools/sdk/include/ethernet/eth_phy/phy_tlk110.h @@ -20,44 +20,53 @@ extern "C" { #include "phy.h" -/** @brief Dump all TLK110 PHY SMI configuration registers +/** + * @brief Dump TLK110 PHY SMI configuration registers * - * @note These registers are dumped at 'debug' level, so output - * may not be visible depending on default log levels. */ void phy_tlk110_dump_registers(); -/** @brief Default TLK110 phy_check_init function. +/** + * @brief Default TLK110 phy_check_init function + * */ void phy_tlk110_check_phy_init(void); -/** @brief Default TLK110 phy_get_speed_mode function. +/** + * @brief Default TLK110 phy_get_speed_mode function + * + * @return eth_speed_mode_t Ethernet speed mode */ eth_speed_mode_t phy_tlk110_get_speed_mode(void); -/** @brief Default TLK110 phy_get_duplex_mode function. +/** + * @brief Default TLK110 phy_get_duplex_mode function + * + * @return eth_duplex_mode_t Ethernet duplex mode */ eth_duplex_mode_t phy_tlk110_get_duplex_mode(void); -/** @brief Default TLK110 phy_power_enable function. +/** + * @brief Default TLK110 phy_power_enable function * - * @note This function may need to be replaced with a custom function - * if the PHY has a GPIO to enable power or start a clock. - * - * Consult the ethernet example to see how this is done. */ void phy_tlk110_power_enable(bool); -/** @brief Default TLK110 phy_init function. +/** + * @brief Default TLK110 phy_init function + * + * @return esp_err_t + * - ESP_OK on success + * - ESP_FAIL on error */ esp_err_t phy_tlk110_init(void); -/** @brief Default TLK110 PHY configuration +/** + * @brief Default TLK110 PHY configuration * - * This configuration is not suitable for use as-is, it will need - * to be modified for your particular PHY hardware setup. + * @note This configuration is not suitable for use as-is, + * it will need to be modified for your particular PHY hardware setup. * - * Consult the Ethernet example to see how this is done. */ extern const eth_config_t phy_tlk110_default_ethernet_config; diff --git a/tools/sdk/include/freemodbus/mbcontroller.h b/tools/sdk/include/freemodbus/mbcontroller.h index b6b206e2a68..267fa34aed1 100644 --- a/tools/sdk/include/freemodbus/mbcontroller.h +++ b/tools/sdk/include/freemodbus/mbcontroller.h @@ -26,7 +26,7 @@ /* ----------------------- Defines ------------------------------------------*/ #define MB_INST_MIN_SIZE (2) // The minimal size of Modbus registers area in bytes -#define MB_INST_MAX_SIZE (2048) // The maximum size of Modbus area in bytes +#define MB_INST_MAX_SIZE (65535 * 2) // The maximum size of Modbus area in bytes #define MB_CONTROLLER_STACK_SIZE (CONFIG_MB_CONTROLLER_STACK_SIZE) // Stack size for Modbus controller #define MB_CONTROLLER_PRIORITY (CONFIG_MB_SERIAL_TASK_PRIO - 1) // priority of MB controller task diff --git a/tools/sdk/include/lwip/lwipopts.h b/tools/sdk/include/lwip/lwipopts.h index 53b598609c6..27f436d9dcd 100644 --- a/tools/sdk/include/lwip/lwipopts.h +++ b/tools/sdk/include/lwip/lwipopts.h @@ -1,8 +1,8 @@ /* * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, @@ -11,21 +11,21 @@ * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. + * derived from this software without specific prior written permission. * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY * OF SUCH DAMAGE. * * This file is part of the lwIP TCP/IP stack. - * + * * Author: Simon Goldschmidt * */ @@ -316,7 +316,7 @@ * scenario happens: 192.168.0.2 -> 0.0.0.0 -> 192.168.0.2 or 192.168.0.2 -> 0.0.0.0 */ -#define ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES CONFIG_ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES +#define ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES CONFIG_ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES /* * LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all * events (accept, sent, etc) that happen in the system. @@ -576,6 +576,11 @@ #if PPP_SUPPORT +/** + * PPP_NOTIFY_PHASE==1: Support PPP notify phase. + */ +#define PPP_NOTIFY_PHASE CONFIG_PPP_NOTIFY_PHASE_SUPPORT + /** * PAP_SUPPORT==1: Support PAP. */ @@ -759,7 +764,7 @@ #if CONFIG_LWIP_IRAM_OPTIMIZATION #define ESP_IRAM_ATTR IRAM_ATTR #else -#define ESP_IRAM_ATTR +#define ESP_IRAM_ATTR #endif #if ESP_PERF @@ -782,7 +787,7 @@ enum { }; #else -#define DBG_PERF_PATH_SET(dir, point) +#define DBG_PERF_PATH_SET(dir, point) #define DBG_PERF_FILTER_LEN 1000 #endif diff --git a/tools/sdk/include/mqtt/mqtt_client.h b/tools/sdk/include/mqtt/mqtt_client.h index 630ba1727ba..56d6aeabbd8 100755 --- a/tools/sdk/include/mqtt/mqtt_client.h +++ b/tools/sdk/include/mqtt/mqtt_client.h @@ -45,6 +45,7 @@ typedef enum { - current_data_offset offset of the current data for this event - total_data_len total length of the data received */ + MQTT_EVENT_BEFORE_CONNECT, /*!< The event occurs before connecting */ } esp_mqtt_event_id_t; typedef enum { @@ -103,6 +104,7 @@ typedef struct { const char *client_cert_pem; /*!< Pointer to certificate data in PEM format for SSL mutual authentication, default is NULL, not required if mutual authentication is not needed. If it is not NULL, also `client_key_pem` has to be provided. */ const char *client_key_pem; /*!< Pointer to private key data in PEM format for SSL mutual authentication, default is NULL, not required if mutual authentication is not needed. If it is not NULL, also `client_cert_pem` has to be provided. */ esp_mqtt_transport_t transport; /*!< overrides URI transport */ + int refresh_connection_after_ms; /*!< Refresh connection after this value (in milliseconds) */ } esp_mqtt_client_config_t; esp_mqtt_client_handle_t esp_mqtt_client_init(const esp_mqtt_client_config_t *config); @@ -113,6 +115,7 @@ esp_err_t esp_mqtt_client_subscribe(esp_mqtt_client_handle_t client, const char esp_err_t esp_mqtt_client_unsubscribe(esp_mqtt_client_handle_t client, const char *topic); int esp_mqtt_client_publish(esp_mqtt_client_handle_t client, const char *topic, const char *data, int len, int qos, int retain); esp_err_t esp_mqtt_client_destroy(esp_mqtt_client_handle_t client); +esp_err_t esp_mqtt_set_config(esp_mqtt_client_handle_t client, const esp_mqtt_client_config_t *config); #ifdef __cplusplus } diff --git a/tools/sdk/include/nvs_flash/nvs.h b/tools/sdk/include/nvs_flash/nvs.h index 0cc3ba09a6e..1d88217ee0b 100644 --- a/tools/sdk/include/nvs_flash/nvs.h +++ b/tools/sdk/include/nvs_flash/nvs.h @@ -65,6 +65,20 @@ typedef enum { NVS_READWRITE /*!< Read and write */ } nvs_open_mode; +typedef enum { + NVS_TYPE_U8 = 0x01, + NVS_TYPE_I8 = 0x11, + NVS_TYPE_U16 = 0x02, + NVS_TYPE_I16 = 0x12, + NVS_TYPE_U32 = 0x04, + NVS_TYPE_I32 = 0x14, + NVS_TYPE_U64 = 0x08, + NVS_TYPE_I64 = 0x18, + NVS_TYPE_STR = 0x21, + NVS_TYPE_BLOB = 0x42, + NVS_TYPE_ANY = 0xff // Must be last +} nvs_type_t; + /** * @brief Open non-volatile storage with a given namespace from the default NVS partition * diff --git a/tools/sdk/include/soc/soc/efuse_reg.h b/tools/sdk/include/soc/soc/efuse_reg.h index 6c3f45c542d..ee404d22e62 100644 --- a/tools/sdk/include/soc/soc/efuse_reg.h +++ b/tools/sdk/include/soc/soc/efuse_reg.h @@ -205,12 +205,28 @@ #define EFUSE_RD_FLASH_CRYPT_CONFIG_M ((EFUSE_RD_FLASH_CRYPT_CONFIG_V)<<(EFUSE_RD_FLASH_CRYPT_CONFIG_S)) #define EFUSE_RD_FLASH_CRYPT_CONFIG_V 0xF #define EFUSE_RD_FLASH_CRYPT_CONFIG_S 28 +/* EFUSE_RD_DIG_VOL_L6: RO; bitpos:[27:24]; */ +/*descritpion: This field stores the difference between the digital regulator voltage at level6 and 1.2 V. (RO) + BIT[27] is the sign bit, 0: + , 1: - + BIT[26:24] is the difference value, unit: 0.017V + volt_lv6 = BIT[27] ? 1.2 - BIT[26:24] * 0.017 : 1.2 + BIT[26:24] * 0.017 */ +#define EFUSE_RD_DIG_VOL_L6 0x0F +#define EFUSE_RD_DIG_VOL_L6_M ((EFUSE_RD_DIG_VOL_L6_V)<<(EFUSE_RD_DIG_VOL_L6_S)) +#define EFUSE_RD_DIG_VOL_L6_V 0x0F +#define EFUSE_RD_DIG_VOL_L6_S 24 +/* EFUSE_RD_VOL_LEVEL_HP_INV: RO; bitpos:[23:22] */ +/*description: This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz. +0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO)*/ +#define EFUSE_RD_VOL_LEVEL_HP_INV 0x03 +#define EFUSE_RD_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V)<<(EFUSE_RD_VOL_LEVEL_HP_INV_S)) +#define EFUSE_RD_VOL_LEVEL_HP_INV_V 0x03 +#define EFUSE_RD_VOL_LEVEL_HP_INV_S 22 /* EFUSE_RD_INST_CONFIG : RO ;bitpos:[27:20] ;default: 8'b0 ; */ -/*description: */ -#define EFUSE_RD_INST_CONFIG 0x000000FF -#define EFUSE_RD_INST_CONFIG_M ((EFUSE_RD_INST_CONFIG_V)<<(EFUSE_RD_INST_CONFIG_S)) -#define EFUSE_RD_INST_CONFIG_V 0xFF -#define EFUSE_RD_INST_CONFIG_S 20 +/* Deprecated */ +#define EFUSE_RD_INST_CONFIG 0x000000FF /** Deprecated **/ +#define EFUSE_RD_INST_CONFIG_M ((EFUSE_RD_INST_CONFIG_V)<<(EFUSE_RD_INST_CONFIG_S)) /** Deprecated **/ +#define EFUSE_RD_INST_CONFIG_V 0xFF /** Deprecated **/ +#define EFUSE_RD_INST_CONFIG_S 20 /** Deprecated **/ /* EFUSE_RD_SPI_PAD_CONFIG_CS0 : RO ;bitpos:[19:15] ;default: 5'b0 ; */ /*description: read for SPI_pad_config_cs0*/ #define EFUSE_RD_SPI_PAD_CONFIG_CS0 0x0000001F @@ -464,12 +480,28 @@ #define EFUSE_FLASH_CRYPT_CONFIG_M ((EFUSE_FLASH_CRYPT_CONFIG_V)<<(EFUSE_FLASH_CRYPT_CONFIG_S)) #define EFUSE_FLASH_CRYPT_CONFIG_V 0xF #define EFUSE_FLASH_CRYPT_CONFIG_S 28 +/* EFUSE_DIG_VOL_L6: R/W; bitpos:[27:24]; */ +/*descritpion: This field stores the difference between the digital regulator voltage at level6 and 1.2 V. (R/W) + BIT[27] is the sign bit, 0: + , 1: - + BIT[26:24] is the difference value, unit: 0.017V + volt_lv6 = BIT[27] ? 1.2 - BIT[26:24] * 0.017 : 1.2 + BIT[26:24] * 0.017 */ +#define EFUSE_DIG_VOL_L6 0x0F +#define EFUSE_DIG_VOL_L6_M ((EFUSE_RD_DIG_VOL_L6_V)<<(EFUSE_RD_DIG_VOL_L6_S)) +#define EFUSE_DIG_VOL_L6_V 0x0F +#define EFUSE_DIG_VOL_L6_S 24 +/* EFUSE_VOL_LEVEL_HP_INV: R/W; bitpos:[23:22] */ +/*description: This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz. +0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (R/W)*/ +#define EFUSE_VOL_LEVEL_HP_INV 0x03 +#define EFUSE_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V)<<(EFUSE_RD_VOL_LEVEL_HP_INV_S)) +#define EFUSE_VOL_LEVEL_HP_INV_V 0x03 +#define EFUSE_VOL_LEVEL_HP_INV_S 22 /* EFUSE_INST_CONFIG : R/W ;bitpos:[27:20] ;default: 8'b0 ; */ -/*description: */ -#define EFUSE_INST_CONFIG 0x000000FF -#define EFUSE_INST_CONFIG_M ((EFUSE_INST_CONFIG_V)<<(EFUSE_INST_CONFIG_S)) -#define EFUSE_INST_CONFIG_V 0xFF -#define EFUSE_INST_CONFIG_S 20 +/* Deprecated */ +#define EFUSE_INST_CONFIG 0x000000FF /** Deprecated **/ +#define EFUSE_INST_CONFIG_M ((EFUSE_INST_CONFIG_V)<<(EFUSE_INST_CONFIG_S)) /** Deprecated **/ +#define EFUSE_INST_CONFIG_V 0xFF /** Deprecated **/ +#define EFUSE_INST_CONFIG_S 20 /** Deprecated **/ /* EFUSE_SPI_PAD_CONFIG_CS0 : R/W ;bitpos:[19:15] ;default: 5'b0 ; */ /*description: program for SPI_pad_config_cs0*/ #define EFUSE_SPI_PAD_CONFIG_CS0 0x0000001F diff --git a/tools/sdk/lib/libapp_trace.a b/tools/sdk/lib/libapp_trace.a index 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CONFIG_ARDUHAL_PARTITION_SCHEME_MINIMAL= CONFIG_ARDUHAL_PARTITION_SCHEME_NO_OTA= +CONFIG_ARDUHAL_PARTITION_SCHEME_HUGE_APP= CONFIG_ARDUHAL_PARTITION_SCHEME_MIN_SPIFFS= CONFIG_ARDUHAL_PARTITION_SCHEME="default" CONFIG_AUTOCONNECT_WIFI= @@ -62,7 +63,7 @@ CONFIG_BOOTLOADER_APP_TEST= CONFIG_BOOTLOADER_WDT_ENABLE=y CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE= CONFIG_BOOTLOADER_WDT_TIME_MS=9000 -CONFIG_APP_ROLLBACK_ENABLE= +CONFIG_APP_ROLLBACK_ENABLE=y # # Security features @@ -225,6 +226,7 @@ CONFIG_BT_ALLOCATION_FROM_SPIRAM_FIRST=y CONFIG_BT_BLE_DYNAMIC_ENV_MEMORY=y CONFIG_BLE_HOST_QUEUE_CONGESTION_CHECK= CONFIG_SMP_ENABLE=y +CONFIG_BLE_ACTIVE_SCAN_REPORT_ADV_SCAN_RSP_INDIVIDUALLY= CONFIG_BT_RESERVE_DRAM=0xdb5c # @@ -272,6 +274,7 @@ CONFIG_SPIRAM_BANKSWITCH_ENABLE=y CONFIG_SPIRAM_BANKSWITCH_RESERVE=8 CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST=y CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY= +CONFIG_PICO_PSRAM_CS_IO=10 CONFIG_MEMMAP_TRACEMEM= CONFIG_MEMMAP_TRACEMEM_TWOBANKS= CONFIG_ESP32_TRAX= @@ -417,6 +420,11 @@ CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS=y CONFIG_HTTPD_MAX_REQ_HDR_LEN=512 CONFIG_HTTPD_MAX_URI_LEN=512 +# +# ESP HTTPS OTA +# +CONFIG_OTA_ALLOW_HTTP= + # # Ethernet # @@ -600,6 +608,7 @@ CONFIG_TCPIP_TASK_AFFINITY_CPU0=y CONFIG_TCPIP_TASK_AFFINITY_CPU1= CONFIG_TCPIP_TASK_AFFINITY=0x0 CONFIG_PPP_SUPPORT=y +CONFIG_PPP_NOTIFY_PHASE_SUPPORT= CONFIG_PPP_PAP_SUPPORT=y CONFIG_PPP_CHAP_SUPPORT=y CONFIG_PPP_MSCHAP_SUPPORT=y @@ -748,9 +757,6 @@ CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread" CONFIG_SPI_FLASH_VERIFY_WRITE= CONFIG_SPI_FLASH_ENABLE_COUNTERS= CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y -CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y -CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS= -CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED= # # SPIFFS Configuration