From c688f3090f5ecb722c6b0ad196bb13bd53ded169 Mon Sep 17 00:00:00 2001
From: Lucas Saavedra Vaz <32426024+lucasssvaz@users.noreply.github.com>
Date: Mon, 16 Dec 2024 10:48:50 -0300
Subject: [PATCH] fix(clk_src): Fix error as APLL is not yet supported for P4

---
 cores/esp32/esp32-hal-cpu.c | 13 ++-----------
 1 file changed, 2 insertions(+), 11 deletions(-)

diff --git a/cores/esp32/esp32-hal-cpu.c b/cores/esp32/esp32-hal-cpu.c
index e9baf3613c2..1ffde860792 100644
--- a/cores/esp32/esp32-hal-cpu.c
+++ b/cores/esp32/esp32-hal-cpu.c
@@ -259,18 +259,10 @@ bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz) {
   if (apb_change_callbacks) {
     triggerApbChangeCallback(APB_AFTER_CHANGE, capb, apb);
   }
-  // clang-format off
-#ifdef SOC_CLK_APLL_SUPPORTED
+#if defined(SOC_CLK_APLL_SUPPORTED) && !defined(CONFIG_IDF_TARGET_ESP32P4)  // APLL not yet supported in ESP32-P4
   log_d(
     "%s: %u / %u = %u Mhz, APB: %u Hz",
-    (conf.source == SOC_CPU_CLK_SRC_PLL) ? "PLL"
-                                          : ((conf.source == SOC_CPU_CLK_SRC_APLL) ? "APLL"
-                                          : ((conf.source == SOC_CPU_CLK_SRC_XTAL) ? "XTAL"
-#ifdef CONFIG_IDF_TARGET_ESP32P4
-                                          : "17.5M")),
-#else
-                                          : "8M")),
-#endif
+    (conf.source == SOC_CPU_CLK_SRC_PLL) ? "PLL" : ((conf.source == SOC_CPU_CLK_SRC_APLL) ? "APLL" : ((conf.source == SOC_CPU_CLK_SRC_XTAL) ? "XTAL" : "8M")),
     conf.source_freq_mhz, conf.div, conf.freq_mhz, apb
   );
 #else
@@ -279,7 +271,6 @@ bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz) {
     conf.source_freq_mhz, conf.div, conf.freq_mhz, apb
   );
 #endif
-  // clang-format on
   return true;
 }