From d129308df3eddf54a79441c0111dc4b38efe61e0 Mon Sep 17 00:00:00 2001 From: Rodrigo Garcia Date: Tue, 30 Jul 2024 17:45:45 -0300 Subject: [PATCH 1/7] fix(uart): Sets XTAL as clock source for uart C6 and H2 have problems after returning from light sleep. The baud rate seems to be off when APB is used as clock source. This fix solves the issue using a steady clock source. --- cores/esp32/esp32-hal-uart.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/cores/esp32/esp32-hal-uart.c b/cores/esp32/esp32-hal-uart.c index f87775a83ba..71c9469b679 100644 --- a/cores/esp32/esp32-hal-uart.c +++ b/cores/esp32/esp32-hal-uart.c @@ -503,9 +503,15 @@ uart_t *uartBegin( uart_config.flow_ctrl = UART_HW_FLOWCTRL_DISABLE; uart_config.rx_flow_ctrl_thresh = rxfifo_full_thrhd; uart_config.baud_rate = baudrate; - // CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F40M for C2 -- CLK_PLL_F48M for H2 -- CLK_PLL_F80M for C6 - uart_config.source_clk = UART_SCLK_DEFAULT; - + // there is an issue when returning from light sleep with the C6 and H2: the uart baud rate is not restored + // therefore, uart clock source will set to XTAL for all SoC that support it. This fix solves the C6|H2 issue. +#if SOC_UART_SUPPORT_XTAL_CLK + uart_config.source_clk = UART_SCLK_XTAL; // valid for S3, C3, C6, H2 and P4 +#else + // Default CLK Source: CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F40M for C2 -- CLK_PLL_F48M for H2 -- CLK_PLL_F80M for C6 + uart_config.source_clk = UART_SCLK_DEFAULT; // valid for ESP32 and S2 +#endif + UART_MUTEX_LOCK(); bool retCode = ESP_OK == uart_driver_install(uart_nr, rx_buffer_size, tx_buffer_size, 20, &(uart->uart_event_queue), 0); From 4f1a39db3f4817c261096a60a253c97f3b9e67e3 Mon Sep 17 00:00:00 2001 From: Rodrigo Garcia Date: Tue, 30 Jul 2024 17:51:29 -0300 Subject: [PATCH 2/7] fix(typo): Typo and commentaries Adds C2 in the XTAL list. --- cores/esp32/esp32-hal-uart.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cores/esp32/esp32-hal-uart.c b/cores/esp32/esp32-hal-uart.c index 71c9469b679..80370c887f4 100644 --- a/cores/esp32/esp32-hal-uart.c +++ b/cores/esp32/esp32-hal-uart.c @@ -506,7 +506,7 @@ uart_t *uartBegin( // there is an issue when returning from light sleep with the C6 and H2: the uart baud rate is not restored // therefore, uart clock source will set to XTAL for all SoC that support it. This fix solves the C6|H2 issue. #if SOC_UART_SUPPORT_XTAL_CLK - uart_config.source_clk = UART_SCLK_XTAL; // valid for S3, C3, C6, H2 and P4 + uart_config.source_clk = UART_SCLK_XTAL; // valid for C2, S3, C3, C6, H2 and P4 #else // Default CLK Source: CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F40M for C2 -- CLK_PLL_F48M for H2 -- CLK_PLL_F80M for C6 uart_config.source_clk = UART_SCLK_DEFAULT; // valid for ESP32 and S2 From 6cf3d687a576c0664c052512305fe4f45ae52a41 Mon Sep 17 00:00:00 2001 From: Rodrigo Garcia Date: Wed, 31 Jul 2024 11:31:59 -0300 Subject: [PATCH 3/7] fix(uart): adjust get/set baudrate Fixes the functions for reading/writing UART baudrate by using IDF functions instead of HAL/LL. --- cores/esp32/esp32-hal-uart.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/cores/esp32/esp32-hal-uart.c b/cores/esp32/esp32-hal-uart.c index 80370c887f4..faf6afe5c39 100644 --- a/cores/esp32/esp32-hal-uart.c +++ b/cores/esp32/esp32-hal-uart.c @@ -784,25 +784,25 @@ void uartSetBaudRate(uart_t *uart, uint32_t baud_rate) { return; } UART_MUTEX_LOCK(); - uint32_t sclk_freq; - if (uart_get_sclk_freq(UART_SCLK_DEFAULT, &sclk_freq) == ESP_OK) { - uart_ll_set_baudrate(UART_LL_GET_HW(uart->num), baud_rate, sclk_freq); + if (uart_set_baudrate(uart->num, baud_rate) == ESP_OK) { + uart->_baudrate = baud_rate; + } else { + log_e("Setting UART%d baud rate to %d has failed.", uart->num, baud_rate); } - uart->_baudrate = baud_rate; UART_MUTEX_UNLOCK(); } uint32_t uartGetBaudRate(uart_t *uart) { uint32_t baud_rate = 0; - uint32_t sclk_freq; if (uart == NULL) { return 0; } UART_MUTEX_LOCK(); - if (uart_get_sclk_freq(UART_SCLK_DEFAULT, &sclk_freq) == ESP_OK) { - baud_rate = uart_ll_get_baudrate(UART_LL_GET_HW(uart->num), sclk_freq); + if (uart_get_baudrate(uart->num, &baud_rate) != ESP_OK) { + log_e("Getting UART%d baud rate has failed.", uart->num); + baud_rate = (uint32_t) -1; // return value when failed } UART_MUTEX_UNLOCK(); return baud_rate; From a9082d49cd8195d2e540b96fd10c1905501581eb Mon Sep 17 00:00:00 2001 From: Rodrigo Garcia Date: Wed, 31 Jul 2024 14:29:11 -0300 Subject: [PATCH 4/7] fix(uart): uses REF_TICK for ESP32/S2 --- cores/esp32/esp32-hal-uart.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/cores/esp32/esp32-hal-uart.c b/cores/esp32/esp32-hal-uart.c index faf6afe5c39..07cbd77031c 100644 --- a/cores/esp32/esp32-hal-uart.c +++ b/cores/esp32/esp32-hal-uart.c @@ -507,9 +507,11 @@ uart_t *uartBegin( // therefore, uart clock source will set to XTAL for all SoC that support it. This fix solves the C6|H2 issue. #if SOC_UART_SUPPORT_XTAL_CLK uart_config.source_clk = UART_SCLK_XTAL; // valid for C2, S3, C3, C6, H2 and P4 +#elif SOC_UART_SUPPORT_REF_TICK + uart_config.source_clk = UART_SCLK_REF_TICK; // valid for ESP32, S2 #else // Default CLK Source: CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F40M for C2 -- CLK_PLL_F48M for H2 -- CLK_PLL_F80M for C6 - uart_config.source_clk = UART_SCLK_DEFAULT; // valid for ESP32 and S2 + uart_config.source_clk = UART_SCLK_DEFAULT; // baudrate may change with the CPU Frequency! #endif UART_MUTEX_LOCK(); From 3dd24fb2044b621f875e09d4cf8043139ce42772 Mon Sep 17 00:00:00 2001 From: Rodrigo Garcia Date: Wed, 31 Jul 2024 14:43:10 -0300 Subject: [PATCH 5/7] fix(uart): esp32/s2 baudrate > 1MHz Fixes the baudrate for ESP32 and ESP32-S2 when the baud rate is higher than 1MHz. REF_TICK is just 2MHZ and can handle up to 1MHZ baudrate. --- cores/esp32/esp32-hal-uart.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/cores/esp32/esp32-hal-uart.c b/cores/esp32/esp32-hal-uart.c index 07cbd77031c..17e75d0fc9c 100644 --- a/cores/esp32/esp32-hal-uart.c +++ b/cores/esp32/esp32-hal-uart.c @@ -508,10 +508,14 @@ uart_t *uartBegin( #if SOC_UART_SUPPORT_XTAL_CLK uart_config.source_clk = UART_SCLK_XTAL; // valid for C2, S3, C3, C6, H2 and P4 #elif SOC_UART_SUPPORT_REF_TICK - uart_config.source_clk = UART_SCLK_REF_TICK; // valid for ESP32, S2 + if (baudrate <= 1000000) { + uart_config.source_clk = UART_SCLK_REF_TICK; // valid for ESP32, S2 - MAX supported baud rate is 1MHz + } else { + uart_config.source_clk = UART_SCLK_APB; // baudrate may change with the APB Frequency! + } #else // Default CLK Source: CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F40M for C2 -- CLK_PLL_F48M for H2 -- CLK_PLL_F80M for C6 - uart_config.source_clk = UART_SCLK_DEFAULT; // baudrate may change with the CPU Frequency! + uart_config.source_clk = UART_SCLK_DEFAULT; // baudrate may change with the APB Frequency! #endif UART_MUTEX_LOCK(); From e082695a88eb408fb5a1ac1b6a82eea4507e1934 Mon Sep 17 00:00:00 2001 From: Rodrigo Garcia Date: Wed, 31 Jul 2024 20:17:43 -0300 Subject: [PATCH 6/7] fix(uart): rxTimeout minimum Default RxTimeout changed to the minimum = 1. When TICK_REF is used as clock source, this is mandatory, --- cores/esp32/HardwareSerial.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cores/esp32/HardwareSerial.cpp b/cores/esp32/HardwareSerial.cpp index 3d7c7068728..1f064faada6 100644 --- a/cores/esp32/HardwareSerial.cpp +++ b/cores/esp32/HardwareSerial.cpp @@ -96,7 +96,7 @@ void serialEventRun(void) { #endif HardwareSerial::HardwareSerial(uint8_t uart_nr) - : _uart_nr(uart_nr), _uart(NULL), _rxBufferSize(256), _txBufferSize(0), _onReceiveCB(NULL), _onReceiveErrorCB(NULL), _onReceiveTimeout(false), _rxTimeout(2), + : _uart_nr(uart_nr), _uart(NULL), _rxBufferSize(256), _txBufferSize(0), _onReceiveCB(NULL), _onReceiveErrorCB(NULL), _onReceiveTimeout(false), _rxTimeout(1), _rxFIFOFull(0), _eventTask(NULL) #if !CONFIG_DISABLE_HAL_LOCKS , From 854111f4ad083692298b52f73d7f33b506c8315a Mon Sep 17 00:00:00 2001 From: "pre-commit-ci-lite[bot]" <117423508+pre-commit-ci-lite[bot]@users.noreply.github.com> Date: Thu, 1 Aug 2024 07:50:06 +0000 Subject: [PATCH 7/7] ci(pre-commit): Apply automatic fixes --- cores/esp32/esp32-hal-uart.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/cores/esp32/esp32-hal-uart.c b/cores/esp32/esp32-hal-uart.c index 17e75d0fc9c..a33345daa26 100644 --- a/cores/esp32/esp32-hal-uart.c +++ b/cores/esp32/esp32-hal-uart.c @@ -506,18 +506,18 @@ uart_t *uartBegin( // there is an issue when returning from light sleep with the C6 and H2: the uart baud rate is not restored // therefore, uart clock source will set to XTAL for all SoC that support it. This fix solves the C6|H2 issue. #if SOC_UART_SUPPORT_XTAL_CLK - uart_config.source_clk = UART_SCLK_XTAL; // valid for C2, S3, C3, C6, H2 and P4 + uart_config.source_clk = UART_SCLK_XTAL; // valid for C2, S3, C3, C6, H2 and P4 #elif SOC_UART_SUPPORT_REF_TICK if (baudrate <= 1000000) { - uart_config.source_clk = UART_SCLK_REF_TICK; // valid for ESP32, S2 - MAX supported baud rate is 1MHz + uart_config.source_clk = UART_SCLK_REF_TICK; // valid for ESP32, S2 - MAX supported baud rate is 1MHz } else { - uart_config.source_clk = UART_SCLK_APB; // baudrate may change with the APB Frequency! + uart_config.source_clk = UART_SCLK_APB; // baudrate may change with the APB Frequency! } #else // Default CLK Source: CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F40M for C2 -- CLK_PLL_F48M for H2 -- CLK_PLL_F80M for C6 - uart_config.source_clk = UART_SCLK_DEFAULT; // baudrate may change with the APB Frequency! + uart_config.source_clk = UART_SCLK_DEFAULT; // baudrate may change with the APB Frequency! #endif - + UART_MUTEX_LOCK(); bool retCode = ESP_OK == uart_driver_install(uart_nr, rx_buffer_size, tx_buffer_size, 20, &(uart->uart_event_queue), 0); @@ -808,7 +808,7 @@ uint32_t uartGetBaudRate(uart_t *uart) { UART_MUTEX_LOCK(); if (uart_get_baudrate(uart->num, &baud_rate) != ESP_OK) { log_e("Getting UART%d baud rate has failed.", uart->num); - baud_rate = (uint32_t) -1; // return value when failed + baud_rate = (uint32_t)-1; // return value when failed } UART_MUTEX_UNLOCK(); return baud_rate;