Debug: 108295 741489 riscv.c:1401 resume_prep(): [0]
Debug: 108296 741489 riscv.c:1291 riscv_resume_prep_all_harts(): [esp32c3] prep hart
Debug: 108297 741489 program.c:35 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f)
Debug: 108298 741490 riscv-013.c:4382 riscv013_write_debug_buffer(): cache hit for 0x100f @0
Debug: 108299 741490 program.c:35 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f)
Debug: 108300 741490 riscv-013.c:4382 riscv013_write_debug_buffer(): cache hit for 0xf @1
Debug: 108301 741490 program.c:35 riscv_program_write(): debug_buffer[02] = DASM(0x00100073)
Debug: 108302 741490 riscv-013.c:4382 riscv013_write_debug_buffer(): cache hit for 0x100073 @2
Debug: 108303 741490 riscv-013.c:800 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000
Debug: 108304 741491 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 108305 741492 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x4000b043
Debug: 108306 741492 riscv.c:3482 riscv_set_register(): [esp32c3] dcsr <- 4000b043
Debug: 108307 741492 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x4000b043 to register dcsr
Debug: 108308 741492 riscv-013.c:1315 register_write_direct(): {0} dcsr <- 0x4000b043
Debug: 108309 741493 riscv-013.c:800 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 108310 741494 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x4000b043 to dcsr valid=0
Debug: 108311 741494 riscv.c:1302 riscv_resume_prep_all_harts(): [esp32c3] mark as prepped
Debug: 108312 741494 riscv.c:1426 resume_prep(): [0] mark as prepped
Debug: 108313 741494 riscv.c:3280 riscv_resume_go_all_harts(): [esp32c3] resuming hart
Debug: 108314 741495 riscv-013.c:4191 select_prepped_harts(): index=0, coreid=0, prepped=1
Debug: 108315 741495 riscv-013.c:4818 riscv013_step_or_resume_current_hart(): resuming hart 0 (for step?=0)
Debug: 108316 741495 riscv.c:3402 riscv_invalidate_register_cache(): [0]
Debug: 108317 741495 target.c:1847 target_call_event_callbacks(): target event 2 (resumed) for core esp32c3
Debug: 108318 741495 esp32c3.c:177 esp32c3_handle_target_event(): 2
Debug: 108319 741495 esp_riscv.c:356 esp_riscv_handle_target_event(): 2
Debug: 108320 741527 riscv.c:2081 riscv_poll_hart():   triggered a halt
Debug: 108321 741527 riscv.c:2261 riscv_openocd_poll():   hart 0 halted
Debug: 108322 741527 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 108323 741528 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x4000b043
Debug: 108324 741528 riscv-013.c:4346 riscv013_halt_reason(): dcsr.cause: 0x1
Debug: 108325 741528 riscv.c:2116 set_debug_reason(): [esp32c3] debug_reason=1
Debug: 108326 741528 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register pc
Debug: 108327 741528 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 108328 741530 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x40387716
Debug: 108329 741530 riscv-013.c:4096 riscv013_get_register(): [0] read PC from DPC: 0x40387716
Debug: 108330 741530 riscv.c:3539 riscv_get_register(): [esp32c3] pc: 40387716
Debug: 108331 741530 esp_riscv.c:609 esp_riscv_read_memory(): Use 32-bit access: size: 2        count:2 start address: 0x40387712
Debug: 108332 741533 riscv-013.c:2859 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 108333 741533 esp_riscv.c:609 esp_riscv_read_memory(): Use 32-bit access: size: 2        count:2 start address: 0x40387716
Debug: 108334 741536 riscv-013.c:2859 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 108335 741536 esp_riscv.c:609 esp_riscv_read_memory(): Use 32-bit access: size: 2        count:2 start address: 0x4038771a
Debug: 108336 741539 riscv-013.c:2859 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 108337 741539 riscv_semihosting.c:95 riscv_semihosting(): check 01f01013 00100073 40705013 from 0x40387716-4
Debug: 108338 741539 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register a0
Debug: 108339 741539 riscv-013.c:800 execute_abstract_command(): command=0x22100a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100a
Debug: 108340 741540 riscv-013.c:1504 register_read_direct(): {0} a0 = 0x103
Debug: 108341 741541 riscv.c:3539 riscv_get_register(): [esp32c3] a0: 103
Debug: 108342 741541 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register a1
Debug: 108343 741541 riscv-013.c:800 execute_abstract_command(): command=0x22100b; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100b
Debug: 108344 741542 riscv-013.c:1504 register_read_direct(): {0} a1 = 0x3fc9bfe4
Debug: 108345 741543 riscv.c:3539 riscv_get_register(): [esp32c3] a1: 3fc9bfe4
Debug: 108346 741543 semihosting_common.c:327 semihosting_common(): op=0x103, param=0x3fc9bfe4
Debug: 108347 741543 esp_semihosting.c:266 esp_semihosting_common(): [esp32c3] op=0x103, param=0x3fc9bfe4
Debug: 108348 741543 esp_riscv.c:146 esp_riscv_semihosting(): op:(103) param: (3fc9bfe4)
Debug: 108349 741543 target.c:2764 target_write_u32(): address: 0x6001f064, value: 0x50d83aa1
Debug: 108350 741544 riscv-013.c:3681 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 108351 741545 riscv-013.c:2859 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 108352 741545 target.c:2764 target_write_u32(): address: 0x6001f048, value: 0x00000000
Debug: 108353 741546 riscv-013.c:3681 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 108354 741547 riscv-013.c:2859 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 108355 741547 target.c:2764 target_write_u32(): address: 0x60020064, value: 0x50d83aa1
Debug: 108356 741547 riscv-013.c:3681 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 108357 741547 riscv-013.c:2859 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 108358 741547 target.c:2764 target_write_u32(): address: 0x60020048, value: 0x00000000
Debug: 108359 741547 riscv-013.c:3681 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 108360 741547 riscv-013.c:2859 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 108361 741552 target.c:2764 target_write_u32(): address: 0x600080a8, value: 0x50d83aa1
Debug: 108362 741552 riscv-013.c:3681 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 108363 741552 riscv-013.c:2859 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 108364 741552 target.c:2764 target_write_u32(): address: 0x60008090, value: 0x00000000
Debug: 108365 741554 riscv-013.c:3681 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 108366 741555 riscv-013.c:2859 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 108367 741557 riscv-013.c:2859 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 108368 741558 riscv.c:930 remove_trigger(): [0] Stop using resource 1 for bp 675
Debug: 108369 741558 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register tselect
Debug: 108370 741558 riscv-013.c:800 execute_abstract_command(): command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0
Debug: 108371 741559 riscv-013.c:1504 register_read_direct(): {0} tselect = 0x0
Debug: 108372 741559 riscv.c:3539 riscv_get_register(): [esp32c3] tselect: 0
Debug: 108373 741559 riscv.c:3482 riscv_set_register(): [esp32c3] tselect <- 1
Debug: 108374 741559 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x1 to register tselect
Debug: 108375 741560 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x1
Debug: 108376 741560 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 108377 741562 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x1 to tselect valid=0
Debug: 108378 741562 riscv.c:3482 riscv_set_register(): [esp32c3] tdata1 <- 0
Debug: 108379 741562 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x0 to register tdata1
Debug: 108380 741562 riscv-013.c:1315 register_write_direct(): {0} tdata1 <- 0x0
Debug: 108381 741562 riscv-013.c:800 execute_abstract_command(): command=0x2307a1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a1
Debug: 108382 741562 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to tdata1 valid=0
Debug: 108383 741562 riscv.c:3482 riscv_set_register(): [esp32c3] tselect <- 0
Debug: 108384 741562 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x0 to register tselect
Debug: 108385 741562 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x0
Debug: 108386 741562 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 108387 741562 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to tselect valid=0
Debug: 108388 741562 breakpoints.c:291 breakpoint_free(): free BPID: 675 --> 0
Debug: 108389 741562 riscv.c:866 riscv_add_breakpoint(): [0] @0x4200004e
Debug: 108390 741562 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register tselect
Debug: 108391 741562 riscv-013.c:800 execute_abstract_command(): command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0
Debug: 108392 741562 riscv-013.c:1504 register_read_direct(): {0} tselect = 0x0
Debug: 108393 741562 riscv.c:3539 riscv_get_register(): [esp32c3] tselect: 0
Debug: 108394 741562 riscv.c:3482 riscv_set_register(): [esp32c3] tselect <- 1
Debug: 108395 741562 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x1 to register tselect
Debug: 108396 741562 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x1
Debug: 108397 741562 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 108398 741562 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x1 to tselect valid=0
Debug: 108399 741562 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register tdata1
Debug: 108400 741562 riscv-013.c:800 execute_abstract_command(): command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1
Debug: 108401 741572 riscv-013.c:1504 register_read_direct(): {0} tdata1 = 0x23e00000
Debug: 108402 741572 riscv.c:3539 riscv_get_register(): [esp32c3] tdata1: 23e00000
Debug: 108403 741572 riscv.c:3482 riscv_set_register(): [esp32c3] tdata1 <- 2be0104c
Debug: 108404 741572 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x2be0104c to register tdata1
Debug: 108405 741572 riscv-013.c:1315 register_write_direct(): {0} tdata1 <- 0x2be0104c
Debug: 108406 741573 riscv-013.c:800 execute_abstract_command(): command=0x2307a1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a1
Debug: 108407 741574 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x2be0104c to tdata1 valid=0
Debug: 108408 741574 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register tdata1
Debug: 108409 741574 riscv-013.c:800 execute_abstract_command(): command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1
Debug: 108410 741575 riscv-013.c:1504 register_read_direct(): {0} tdata1 = 0x2be0104c
Debug: 108411 741575 riscv.c:3539 riscv_get_register(): [esp32c3] tdata1: 2be0104c
Debug: 108412 741575 riscv.c:621 maybe_add_trigger_t2(): tdata1=0x2be0104c
Debug: 108413 741575 riscv.c:3482 riscv_set_register(): [esp32c3] tdata2 <- 4200004e
Debug: 108414 741575 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x4200004e to register tdata2
Debug: 108415 741575 riscv-013.c:1315 register_write_direct(): {0} tdata2 <- 0x4200004e
Debug: 108416 741576 riscv-013.c:800 execute_abstract_command(): command=0x2307a2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a2
Debug: 108417 741577 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x4200004e to tdata2 valid=0
Debug: 108418 741577 riscv.c:731 add_trigger(): [0] Using trigger 1 (type 2) for bp 676
Debug: 108419 741577 riscv.c:3482 riscv_set_register(): [esp32c3] tselect <- 0
Debug: 108420 741577 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x0 to register tselect
Debug: 108421 741577 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x0
Debug: 108422 741579 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 108423 741579 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to tselect valid=0
Debug: 108424 741579 breakpoints.c:93 breakpoint_add_internal(): [0] added hardware breakpoint at 0x4200004e of length 0x00000002, (BPID: 676)
Debug: 108425 741579 riscv_semihosting.c:188 riscv_semihosting_post_result(): 0x0
Debug: 108426 741579 riscv.c:3482 riscv_set_register(): [esp32c3] a0 <- 0
Debug: 108427 741579 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x0 to register a0
Debug: 108428 741579 riscv-013.c:1315 register_write_direct(): {0} a0 <- 0x0
Debug: 108429 741579 riscv-013.c:800 execute_abstract_command(): command=0x23100a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100a
Debug: 108430 741583 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to a0 valid=1
Debug: 108431 741583 riscv.c:3482 riscv_set_register(): [esp32c3] pc <- 4038771a
Debug: 108432 741583 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x4038771a to register pc
Debug: 108433 741583 riscv-013.c:4121 riscv013_set_register(): [0] writing PC to DPC: 0x4038771a
Debug: 108434 741583 riscv-013.c:1315 register_write_direct(): {0} dpc <- 0x4038771a
Debug: 108435 741583 riscv-013.c:800 execute_abstract_command(): command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1
Debug: 108436 741583 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 108437 741583 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x4038771a
Debug: 108438 741583 riscv-013.c:4125 riscv013_set_register(): [0]   actual DPC written: 0x000000004038771a
Debug: 108439 741583 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x4038771a to pc valid=0
Debug: 108440 741583 riscv_semihosting.c:154 riscv_semihosting():    -> HANDLED
Debug: 108441 741583 riscv.c:1474 riscv_resume(): handle_breakpoints=0
Debug: 108442 741583 riscv.c:1401 resume_prep(): [0]
Debug: 108443 741583 riscv.c:1291 riscv_resume_prep_all_harts(): [esp32c3] prep hart
Debug: 108444 741583 program.c:35 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f)
Debug: 108445 741583 riscv-013.c:4382 riscv013_write_debug_buffer(): cache hit for 0x100f @0
Debug: 108446 741583 program.c:35 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f)
Debug: 108447 741583 riscv-013.c:4382 riscv013_write_debug_buffer(): cache hit for 0xf @1
Debug: 108448 741583 program.c:35 riscv_program_write(): debug_buffer[02] = DASM(0x00100073)
Debug: 108449 741583 riscv-013.c:4382 riscv013_write_debug_buffer(): cache hit for 0x100073 @2
Debug: 108450 741588 riscv-013.c:800 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000
Debug: 108451 741589 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 108452 741590 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x4000b043
Debug: 108453 741590 riscv.c:3482 riscv_set_register(): [esp32c3] dcsr <- 4000b043
Debug: 108454 741590 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x4000b043 to register dcsr
Debug: 108455 741590 riscv-013.c:1315 register_write_direct(): {0} dcsr <- 0x4000b043
Debug: 108456 741591 riscv-013.c:800 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 108457 741592 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x4000b043 to dcsr valid=0
Debug: 108458 741592 riscv.c:1302 riscv_resume_prep_all_harts(): [esp32c3] mark as prepped
Debug: 108459 741592 riscv.c:1426 resume_prep(): [0] mark as prepped
Debug: 108460 741592 riscv.c:3280 riscv_resume_go_all_harts(): [esp32c3] resuming hart
Debug: 108461 741592 riscv-013.c:4191 select_prepped_harts(): index=0, coreid=0, prepped=1
Debug: 108462 741593 riscv-013.c:4818 riscv013_step_or_resume_current_hart(): resuming hart 0 (for step?=0)
Debug: 108463 741594 riscv.c:3402 riscv_invalidate_register_cache(): [0]
Debug: 108464 741594 target.c:1847 target_call_event_callbacks(): target event 2 (resumed) for core esp32c3
Debug: 108465 741594 esp32c3.c:177 esp32c3_handle_target_event(): 2
Debug: 108466 741594 esp_riscv.c:356 esp_riscv_handle_target_event(): 2
Debug: 108467 741627 riscv.c:2081 riscv_poll_hart():   triggered a halt
Debug: 108468 741627 riscv.c:2261 riscv_openocd_poll():   hart 0 halted
Debug: 108469 741628 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 108470 741629 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x4000b043
Debug: 108471 741629 riscv-013.c:4346 riscv013_halt_reason(): dcsr.cause: 0x1
Debug: 108472 741629 riscv.c:2116 set_debug_reason(): [esp32c3] debug_reason=1
Debug: 108473 741629 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register pc
Debug: 108474 741629 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 108475 741631 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x40387716
Debug: 108476 741631 riscv-013.c:4096 riscv013_get_register(): [0] read PC from DPC: 0x40387716
Debug: 108477 741631 riscv.c:3539 riscv_get_register(): [esp32c3] pc: 40387716
Debug: 108478 741631 esp_riscv.c:609 esp_riscv_read_memory(): Use 32-bit access: size: 2        count:2 start address: 0x40387712
Debug: 108479 741634 riscv-013.c:2859 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 108480 741634 esp_riscv.c:609 esp_riscv_read_memory(): Use 32-bit access: size: 2        count:2 start address: 0x40387716
Debug: 108481 741637 riscv-013.c:2859 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 108482 741637 esp_riscv.c:609 esp_riscv_read_memory(): Use 32-bit access: size: 2        count:2 start address: 0x4038771a
Debug: 108483 741640 riscv-013.c:2859 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 108484 741640 riscv_semihosting.c:95 riscv_semihosting(): check 01f01013 00100073 40705013 from 0x40387716-4
Debug: 108485 741640 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register a0
Debug: 108486 741640 riscv-013.c:800 execute_abstract_command(): command=0x22100a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100a
Debug: 108487 741641 riscv-013.c:1504 register_read_direct(): {0} a0 = 0x103
Debug: 108488 741641 riscv.c:3539 riscv_get_register(): [esp32c3] a0: 103
Debug: 108489 741641 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register a1
Debug: 108490 741642 riscv-013.c:800 execute_abstract_command(): command=0x22100b; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100b
Debug: 108491 741643 riscv-013.c:1504 register_read_direct(): {0} a1 = 0x3fc9bfe4
Debug: 108492 741643 riscv.c:3539 riscv_get_register(): [esp32c3] a1: 3fc9bfe4
Debug: 108493 741643 semihosting_common.c:327 semihosting_common(): op=0x103, param=0x3fc9bfe4
Debug: 108494 741643 esp_semihosting.c:266 esp_semihosting_common(): [esp32c3] op=0x103, param=0x3fc9bfe4
Debug: 108495 741643 esp_riscv.c:146 esp_riscv_semihosting(): op:(103) param: (3fc9bfe4)
Debug: 108496 741643 target.c:2764 target_write_u32(): address: 0x6001f064, value: 0x50d83aa1
Debug: 108497 741644 riscv-013.c:3681 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 108498 741645 riscv-013.c:2859 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 108499 741645 target.c:2764 target_write_u32(): address: 0x6001f048, value: 0x00000000
Debug: 108500 741645 riscv-013.c:3681 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 108501 741645 riscv-013.c:2859 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 108502 741645 target.c:2764 target_write_u32(): address: 0x60020064, value: 0x50d83aa1
Debug: 108503 741645 riscv-013.c:3681 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 108504 741645 riscv-013.c:2859 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 108505 741645 target.c:2764 target_write_u32(): address: 0x60020048, value: 0x00000000
Debug: 108506 741645 riscv-013.c:3681 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 108507 741645 riscv-013.c:2859 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 108508 741645 target.c:2764 target_write_u32(): address: 0x600080a8, value: 0x50d83aa1
Debug: 108509 741645 riscv-013.c:3681 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 108510 741645 riscv-013.c:2859 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 108511 741654 target.c:2764 target_write_u32(): address: 0x60008090, value: 0x00000000
Debug: 108512 741655 riscv-013.c:3681 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 108513 741655 riscv-013.c:2859 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 108514 741658 riscv-013.c:2859 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 108515 741658 riscv.c:930 remove_trigger(): [0] Stop using resource 1 for bp 676
Debug: 108516 741659 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register tselect
Debug: 108517 741659 riscv-013.c:800 execute_abstract_command(): command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0
Debug: 108518 741660 riscv-013.c:1504 register_read_direct(): {0} tselect = 0x0
Debug: 108519 741660 riscv.c:3539 riscv_get_register(): [esp32c3] tselect: 0
Debug: 108520 741660 riscv.c:3482 riscv_set_register(): [esp32c3] tselect <- 1
Debug: 108521 741660 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x1 to register tselect
Debug: 108522 741660 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x1
Debug: 108523 741661 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 108524 741662 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x1 to tselect valid=0
Debug: 108525 741663 riscv.c:3482 riscv_set_register(): [esp32c3] tdata1 <- 0
Debug: 108526 741663 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x0 to register tdata1
Debug: 108527 741663 riscv-013.c:1315 register_write_direct(): {0} tdata1 <- 0x0
Debug: 108528 741663 riscv-013.c:800 execute_abstract_command(): command=0x2307a1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a1
Debug: 108529 741663 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to tdata1 valid=0
Debug: 108530 741663 riscv.c:3482 riscv_set_register(): [esp32c3] tselect <- 0
Debug: 108531 741665 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x0 to register tselect
Debug: 108532 741665 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x0
Debug: 108533 741665 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 108534 741665 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to tselect valid=0
Debug: 108535 741665 breakpoints.c:291 breakpoint_free(): free BPID: 676 --> 0
Debug: 108536 741665 riscv.c:866 riscv_add_breakpoint(): [0] @0x4200004e
Debug: 108537 741665 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register tselect
Debug: 108538 741665 riscv-013.c:800 execute_abstract_command(): command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0
Debug: 108539 741665 riscv-013.c:1504 register_read_direct(): {0} tselect = 0x0
Debug: 108540 741665 riscv.c:3539 riscv_get_register(): [esp32c3] tselect: 0
Debug: 108541 741665 riscv.c:3482 riscv_set_register(): [esp32c3] tselect <- 1
Debug: 108542 741665 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x1 to register tselect
Debug: 108543 741665 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x1
Debug: 108544 741665 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 108545 741665 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x1 to tselect valid=0
Debug: 108546 741665 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register tdata1
Debug: 108547 741665 riscv-013.c:800 execute_abstract_command(): command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1
Debug: 108548 741671 riscv-013.c:1504 register_read_direct(): {0} tdata1 = 0x23e00000
Debug: 108549 741671 riscv.c:3539 riscv_get_register(): [esp32c3] tdata1: 23e00000
Debug: 108550 741671 riscv.c:3482 riscv_set_register(): [esp32c3] tdata1 <- 2be0104c
Debug: 108551 741671 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x2be0104c to register tdata1
Debug: 108552 741671 riscv-013.c:1315 register_write_direct(): {0} tdata1 <- 0x2be0104c
Debug: 108553 741672 riscv-013.c:800 execute_abstract_command(): command=0x2307a1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a1
Debug: 108554 741673 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x2be0104c to tdata1 valid=0
Debug: 108555 741673 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register tdata1
Debug: 108556 741673 riscv-013.c:800 execute_abstract_command(): command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1
Debug: 108557 741674 riscv-013.c:1504 register_read_direct(): {0} tdata1 = 0x2be0104c
Debug: 108558 741674 riscv.c:3539 riscv_get_register(): [esp32c3] tdata1: 2be0104c
Debug: 108559 741674 riscv.c:621 maybe_add_trigger_t2(): tdata1=0x2be0104c
Debug: 108560 741674 riscv.c:3482 riscv_set_register(): [esp32c3] tdata2 <- 4200004e
Debug: 108561 741674 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x4200004e to register tdata2
Debug: 108562 741675 riscv-013.c:1315 register_write_direct(): {0} tdata2 <- 0x4200004e
Debug: 108563 741675 riscv-013.c:800 execute_abstract_command(): command=0x2307a2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a2
Debug: 108564 741676 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x4200004e to tdata2 valid=0
Debug: 108565 741676 riscv.c:731 add_trigger(): [0] Using trigger 1 (type 2) for bp 677
Debug: 108566 741676 riscv.c:3482 riscv_set_register(): [esp32c3] tselect <- 0
Debug: 108567 741676 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x0 to register tselect
Debug: 108568 741676 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x0
Debug: 108569 741677 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 108570 741678 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to tselect valid=0
Debug: 108571 741678 breakpoints.c:93 breakpoint_add_internal(): [0] added hardware breakpoint at 0x4200004e of length 0x00000002, (BPID: 677)
Debug: 108572 741678 riscv_semihosting.c:188 riscv_semihosting_post_result(): 0x0
Debug: 108573 741679 riscv.c:3482 riscv_set_register(): [esp32c3] a0 <- 0
Debug: 108574 741679 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x0 to register a0
Debug: 108575 741679 riscv-013.c:1315 register_write_direct(): {0} a0 <- 0x0
Debug: 108576 741679 riscv-013.c:800 execute_abstract_command(): command=0x23100a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100a
Debug: 108577 741679 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to a0 valid=1
Debug: 108578 741679 riscv.c:3482 riscv_set_register(): [esp32c3] pc <- 4038771a
Debug: 108579 741679 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x4038771a to register pc
Debug: 108580 741679 riscv-013.c:4121 riscv013_set_register(): [0] writing PC to DPC: 0x4038771a
Debug: 108581 741679 riscv-013.c:1315 register_write_direct(): {0} dpc <- 0x4038771a
Debug: 108582 741679 riscv-013.c:800 execute_abstract_command(): command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1
Debug: 108583 741679 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 108584 741679 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x4038771a
Debug: 108585 741679 riscv-013.c:4125 riscv013_set_register(): [0]   actual DPC written: 0x000000004038771a
Debug: 108586 741679 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x4038771a to pc valid=0
Debug: 108587 741679 riscv_semihosting.c:154 riscv_semihosting():    -> HANDLED
Debug: 108588 741679 riscv.c:1474 riscv_resume(): handle_breakpoints=0
Debug: 108589 741679 riscv.c:1401 resume_prep(): [0]
Debug: 108590 741679 riscv.c:1291 riscv_resume_prep_all_harts(): [esp32c3] prep hart
Debug: 108591 741679 program.c:35 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f)
Debug: 108592 741685 riscv-013.c:4382 riscv013_write_debug_buffer(): cache hit for 0x100f @0
Debug: 108593 741685 program.c:35 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f)
Debug: 108594 741685 riscv-013.c:4382 riscv013_write_debug_buffer(): cache hit for 0xf @1
Debug: 108595 741685 program.c:35 riscv_program_write(): debug_buffer[02] = DASM(0x00100073)
Debug: 108596 741685 riscv-013.c:4382 riscv013_write_debug_buffer(): cache hit for 0x100073 @2
Debug: 108597 741685 riscv-013.c:800 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000
Debug: 108598 741685 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 108599 741688 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x4000b043
Debug: 108600 741688 riscv.c:3482 riscv_set_register(): [esp32c3] dcsr <- 4000b043
Debug: 108601 741689 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x4000b043 to register dcsr
Debug: 108602 741689 riscv-013.c:1315 register_write_direct(): {0} dcsr <- 0x4000b043
Debug: 108603 741689 riscv-013.c:800 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 108604 741690 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x4000b043 to dcsr valid=0
Debug: 108605 741690 riscv.c:1302 riscv_resume_prep_all_harts(): [esp32c3] mark as prepped
Debug: 108606 741690 riscv.c:1426 resume_prep(): [0] mark as prepped
Debug: 108607 741690 riscv.c:3280 riscv_resume_go_all_harts(): [esp32c3] resuming hart
Debug: 108608 741691 riscv-013.c:4191 select_prepped_harts(): index=0, coreid=0, prepped=1
Debug: 108609 741691 riscv-013.c:4818 riscv013_step_or_resume_current_hart(): resuming hart 0 (for step?=0)
Debug: 108610 741693 riscv.c:3402 riscv_invalidate_register_cache(): [0]
Debug: 108611 741693 target.c:1847 target_call_event_callbacks(): target event 2 (resumed) for core esp32c3
Debug: 108612 741693 esp32c3.c:177 esp32c3_handle_target_event(): 2
Debug: 108613 741693 esp_riscv.c:356 esp_riscv_handle_target_event(): 2
Debug: 108614 741744 riscv.c:2081 riscv_poll_hart():   triggered a halt
Debug: 108615 741744 riscv.c:2261 riscv_openocd_poll():   hart 0 halted
Debug: 108616 741744 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 108617 741746 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x4000b043
Debug: 108618 741746 riscv-013.c:4346 riscv013_halt_reason(): dcsr.cause: 0x1
Debug: 108619 741747 riscv.c:2116 set_debug_reason(): [esp32c3] debug_reason=1
Debug: 108620 741747 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register pc
Debug: 108621 741747 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 108622 741749 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x40387716
Debug: 108623 741749 riscv-013.c:4096 riscv013_get_register(): [0] read PC from DPC: 0x40387716
Debug: 108624 741749 riscv.c:3539 riscv_get_register(): [esp32c3] pc: 40387716
Debug: 108625 741749 esp_riscv.c:609 esp_riscv_read_memory(): Use 32-bit access: size: 2        count:2 start address: 0x40387712
Debug: 108626 741749 riscv-013.c:2859 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 108627 741749 esp_riscv.c:609 esp_riscv_read_memory(): Use 32-bit access: size: 2        count:2 start address: 0x40387716
Debug: 108628 741759 riscv-013.c:2859 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 108629 741759 esp_riscv.c:609 esp_riscv_read_memory(): Use 32-bit access: size: 2        count:2 start address: 0x4038771a
Debug: 108630 741762 riscv-013.c:2859 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 108631 741762 riscv_semihosting.c:95 riscv_semihosting(): check 01f01013 00100073 40705013 from 0x40387716-4
Debug: 108632 741762 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register a0
Debug: 108633 741762 riscv-013.c:800 execute_abstract_command(): command=0x22100a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100a
Debug: 108634 741762 riscv-013.c:1504 register_read_direct(): {0} a0 = 0x103
Debug: 108635 741762 riscv.c:3539 riscv_get_register(): [esp32c3] a0: 103
Debug: 108636 741762 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register a1
Debug: 108637 741762 riscv-013.c:800 execute_abstract_command(): command=0x22100b; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100b
Debug: 108638 741762 riscv-013.c:1504 register_read_direct(): {0} a1 = 0x3fc9bfe4
Debug: 108639 741762 riscv.c:3539 riscv_get_register(): [esp32c3] a1: 3fc9bfe4
Debug: 108640 741762 semihosting_common.c:327 semihosting_common(): op=0x103, param=0x3fc9bfe4
Debug: 108641 741762 esp_semihosting.c:266 esp_semihosting_common(): [esp32c3] op=0x103, param=0x3fc9bfe4
Debug: 108642 741762 esp_riscv.c:146 esp_riscv_semihosting(): op:(103) param: (3fc9bfe4)
Debug: 108643 741762 target.c:2764 target_write_u32(): address: 0x6001f064, value: 0x50d83aa1
Debug: 108644 741768 riscv-013.c:3681 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 108645 741768 riscv-013.c:2859 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 108646 741768 target.c:2764 target_write_u32(): address: 0x6001f048, value: 0x00000000
Debug: 108647 741768 riscv-013.c:3681 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 108648 741771 riscv-013.c:2859 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 108649 741771 target.c:2764 target_write_u32(): address: 0x60020064, value: 0x50d83aa1
Debug: 108650 741772 riscv-013.c:3681 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 108651 741774 riscv-013.c:2859 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 108652 741775 target.c:2764 target_write_u32(): address: 0x60020048, value: 0x00000000
Debug: 108653 741776 riscv-013.c:3681 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 108654 741777 riscv-013.c:2859 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 108655 741777 target.c:2764 target_write_u32(): address: 0x600080a8, value: 0x50d83aa1
Debug: 108656 741777 riscv-013.c:3681 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 108657 741778 riscv-013.c:2859 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 108658 741778 target.c:2764 target_write_u32(): address: 0x60008090, value: 0x00000000
Debug: 108659 741779 riscv-013.c:3681 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 108660 741780 riscv-013.c:2859 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 108661 741781 riscv-013.c:2859 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 108662 741781 riscv.c:930 remove_trigger(): [0] Stop using resource 1 for bp 677
Debug: 108663 741781 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register tselect
Debug: 108664 741781 riscv-013.c:800 execute_abstract_command(): command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0
Debug: 108665 741781 riscv-013.c:1504 register_read_direct(): {0} tselect = 0x0
Debug: 108666 741781 riscv.c:3539 riscv_get_register(): [esp32c3] tselect: 0
Debug: 108667 741781 riscv.c:3482 riscv_set_register(): [esp32c3] tselect <- 1
Debug: 108668 741781 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x1 to register tselect
Debug: 108669 741781 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x1
Debug: 108670 741781 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 108671 741788 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x1 to tselect valid=0
Debug: 108672 741788 riscv.c:3482 riscv_set_register(): [esp32c3] tdata1 <- 0
Debug: 108673 741788 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x0 to register tdata1
Debug: 108674 741788 riscv-013.c:1315 register_write_direct(): {0} tdata1 <- 0x0
Debug: 108675 741789 riscv-013.c:800 execute_abstract_command(): command=0x2307a1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a1
Debug: 108676 741789 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to tdata1 valid=0
Debug: 108677 741789 riscv.c:3482 riscv_set_register(): [esp32c3] tselect <- 0
Debug: 108678 741790 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x0 to register tselect
Debug: 108679 741790 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x0
Debug: 108680 741790 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 108681 741791 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to tselect valid=0
Debug: 108682 741791 breakpoints.c:291 breakpoint_free(): free BPID: 677 --> 0
Debug: 108683 741791 riscv.c:866 riscv_add_breakpoint(): [0] @0x4200004e
Debug: 108684 741791 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register tselect
Debug: 108685 741792 riscv-013.c:800 execute_abstract_command(): command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0
Debug: 108686 741793 riscv-013.c:1504 register_read_direct(): {0} tselect = 0x0
Debug: 108687 741793 riscv.c:3539 riscv_get_register(): [esp32c3] tselect: 0
Debug: 108688 741793 riscv.c:3482 riscv_set_register(): [esp32c3] tselect <- 1
Debug: 108689 741793 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x1 to register tselect
Debug: 108690 741794 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x1
Debug: 108691 741794 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 108692 741796 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x1 to tselect valid=0
Debug: 108693 741796 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register tdata1
Debug: 108694 741796 riscv-013.c:800 execute_abstract_command(): command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1
Debug: 108695 741796 riscv-013.c:1504 register_read_direct(): {0} tdata1 = 0x23e00000
Debug: 108696 741796 riscv.c:3539 riscv_get_register(): [esp32c3] tdata1: 23e00000
Debug: 108697 741796 riscv.c:3482 riscv_set_register(): [esp32c3] tdata1 <- 2be0104c
Debug: 108698 741796 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x2be0104c to register tdata1
Debug: 108699 741796 riscv-013.c:1315 register_write_direct(): {0} tdata1 <- 0x2be0104c
Debug: 108700 741799 riscv-013.c:800 execute_abstract_command(): command=0x2307a1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a1
Debug: 108701 741799 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x2be0104c to tdata1 valid=0
Debug: 108702 741799 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register tdata1
Debug: 108703 741799 riscv-013.c:800 execute_abstract_command(): command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1
Debug: 108704 741799 riscv-013.c:1504 register_read_direct(): {0} tdata1 = 0x2be0104c
Debug: 108705 741799 riscv.c:3539 riscv_get_register(): [esp32c3] tdata1: 2be0104c
Debug: 108706 741799 riscv.c:621 maybe_add_trigger_t2(): tdata1=0x2be0104c
Debug: 108707 741799 riscv.c:3482 riscv_set_register(): [esp32c3] tdata2 <- 4200004e
Debug: 108708 741799 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x4200004e to register tdata2
Debug: 108709 741799 riscv-013.c:1315 register_write_direct(): {0} tdata2 <- 0x4200004e
Debug: 108710 741799 riscv-013.c:800 execute_abstract_command(): command=0x2307a2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a2
Debug: 108711 741799 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x4200004e to tdata2 valid=0
Debug: 108712 741805 riscv.c:731 add_trigger(): [0] Using trigger 1 (type 2) for bp 678
Debug: 108713 741805 riscv.c:3482 riscv_set_register(): [esp32c3] tselect <- 0
Debug: 108714 741805 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x0 to register tselect
Debug: 108715 741805 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x0
Debug: 108716 741806 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 108717 741806 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to tselect valid=0
Debug: 108718 741807 breakpoints.c:93 breakpoint_add_internal(): [0] added hardware breakpoint at 0x4200004e of length 0x00000002, (BPID: 678)
Debug: 108719 741807 riscv_semihosting.c:188 riscv_semihosting_post_result(): 0x0
Debug: 108720 741807 riscv.c:3482 riscv_set_register(): [esp32c3] a0 <- 0
Debug: 108721 741807 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x0 to register a0
Debug: 108722 741807 riscv-013.c:1315 register_write_direct(): {0} a0 <- 0x0
Debug: 108723 741808 riscv-013.c:800 execute_abstract_command(): command=0x23100a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100a
Debug: 108724 741808 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to a0 valid=1
Debug: 108725 741808 riscv.c:3482 riscv_set_register(): [esp32c3] pc <- 4038771a
Debug: 108726 741808 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x4038771a to register pc
Debug: 108727 741808 riscv-013.c:4121 riscv013_set_register(): [0] writing PC to DPC: 0x4038771a
Debug: 108728 741808 riscv-013.c:1315 register_write_direct(): {0} dpc <- 0x4038771a
Debug: 108729 741809 riscv-013.c:800 execute_abstract_command(): command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1
Debug: 108730 741810 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 108731 741811 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x4038771a
Debug: 108732 741811 riscv-013.c:4125 riscv013_set_register(): [0]   actual DPC written: 0x000000004038771a
Debug: 108733 741811 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x4038771a to pc valid=0
Debug: 108734 741812 riscv_semihosting.c:154 riscv_semihosting():    -> HANDLED
Debug: 108735 741812 riscv.c:1474 riscv_resume(): handle_breakpoints=0
Debug: 108736 741812 riscv.c:1401 resume_prep(): [0]
Debug: 108737 741812 riscv.c:1291 riscv_resume_prep_all_harts(): [esp32c3] prep hart
Debug: 108738 741812 program.c:35 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f)
Debug: 108739 741812 riscv-013.c:4382 riscv013_write_debug_buffer(): cache hit for 0x100f @0
Debug: 108740 741812 program.c:35 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f)
Debug: 108741 741812 riscv-013.c:4382 riscv013_write_debug_buffer(): cache hit for 0xf @1
Debug: 108742 741812 program.c:35 riscv_program_write(): debug_buffer[02] = DASM(0x00100073)
Debug: 108743 741812 riscv-013.c:4382 riscv013_write_debug_buffer(): cache hit for 0x100073 @2
Debug: 108744 741812 riscv-013.c:800 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000
Debug: 108745 741812 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 108746 741812 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x4000b043
Debug: 108747 741812 riscv.c:3482 riscv_set_register(): [esp32c3] dcsr <- 4000b043
Debug: 108748 741812 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x4000b043 to register dcsr
Debug: 108749 741812 riscv-013.c:1315 register_write_direct(): {0} dcsr <- 0x4000b043
Debug: 108750 741812 riscv-013.c:800 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 108751 741812 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x4000b043 to dcsr valid=0
Debug: 108752 741812 riscv.c:1302 riscv_resume_prep_all_harts(): [esp32c3] mark as prepped
Debug: 108753 741812 riscv.c:1426 resume_prep(): [0] mark as prepped
Debug: 108754 741812 riscv.c:3280 riscv_resume_go_all_harts(): [esp32c3] resuming hart
Debug: 108755 741812 riscv-013.c:4191 select_prepped_harts(): index=0, coreid=0, prepped=1
Debug: 108756 741812 riscv-013.c:4818 riscv013_step_or_resume_current_hart(): resuming hart 0 (for step?=0)
Debug: 108757 741819 riscv.c:3402 riscv_invalidate_register_cache(): [0]
Debug: 108758 741819 target.c:1847 target_call_event_callbacks(): target event 2 (resumed) for core esp32c3
Debug: 108759 741819 esp32c3.c:177 esp32c3_handle_target_event(): 2
Debug: 108760 741819 esp_riscv.c:356 esp_riscv_handle_target_event(): 2
Debug: 108761 741844 riscv.c:2081 riscv_poll_hart():   triggered a halt
Debug: 108762 741844 riscv.c:2261 riscv_openocd_poll():   hart 0 halted
Debug: 108763 741845 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 108764 741845 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x4000b043
Debug: 108765 741845 riscv-013.c:4346 riscv013_halt_reason(): dcsr.cause: 0x1
Debug: 108766 741845 riscv.c:2116 set_debug_reason(): [esp32c3] debug_reason=1
Debug: 108767 741845 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register pc
Debug: 108768 741845 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 108769 741845 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x40387716
Debug: 108770 741845 riscv-013.c:4096 riscv013_get_register(): [0] read PC from DPC: 0x40387716
Debug: 108771 741845 riscv.c:3539 riscv_get_register(): [esp32c3] pc: 40387716
Debug: 108772 741845 esp_riscv.c:609 esp_riscv_read_memory(): Use 32-bit access: size: 2        count:2 start address: 0x40387712
Debug: 108773 741850 riscv-013.c:2859 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 108774 741850 esp_riscv.c:609 esp_riscv_read_memory(): Use 32-bit access: size: 2        count:2 start address: 0x40387716
Debug: 108775 741850 riscv-013.c:2859 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 108776 741850 esp_riscv.c:609 esp_riscv_read_memory(): Use 32-bit access: size: 2        count:2 start address: 0x4038771a
Debug: 108777 741859 riscv-013.c:2859 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 108778 741859 riscv_semihosting.c:95 riscv_semihosting(): check 01f01013 00100073 40705013 from 0x40387716-4
Debug: 108779 741859 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register a0
Debug: 108780 741859 riscv-013.c:800 execute_abstract_command(): command=0x22100a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100a
Debug: 108781 741860 riscv-013.c:1504 register_read_direct(): {0} a0 = 0x103
Debug: 108782 741860 riscv.c:3539 riscv_get_register(): [esp32c3] a0: 103
Debug: 108783 741861 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register a1
Debug: 108784 741861 riscv-013.c:800 execute_abstract_command(): command=0x22100b; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100b
Debug: 108785 741861 riscv-013.c:1504 register_read_direct(): {0} a1 = 0x3fc9bfe4
Debug: 108786 741862 riscv.c:3539 riscv_get_register(): [esp32c3] a1: 3fc9bfe4
Debug: 108787 741862 semihosting_common.c:327 semihosting_common(): op=0x103, param=0x3fc9bfe4
Debug: 108788 741862 esp_semihosting.c:266 esp_semihosting_common(): [esp32c3] op=0x103, param=0x3fc9bfe4
Debug: 108789 741862 esp_riscv.c:146 esp_riscv_semihosting(): op:(103) param: (3fc9bfe4)
Debug: 108790 741863 target.c:2764 target_write_u32(): address: 0x6001f064, value: 0x50d83aa1
Debug: 108791 741863 riscv-013.c:3681 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 108792 741864 riscv-013.c:2859 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 108793 741864 target.c:2764 target_write_u32(): address: 0x6001f048, value: 0x00000000
Debug: 108794 741866 riscv-013.c:3681 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 108795 741867 riscv-013.c:2859 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 108796 741867 target.c:2764 target_write_u32(): address: 0x60020064, value: 0x50d83aa1
Debug: 108797 741868 riscv-013.c:3681 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 108798 741869 riscv-013.c:2859 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 108799 741869 target.c:2764 target_write_u32(): address: 0x60020048, value: 0x00000000
Debug: 108800 741869 riscv-013.c:3681 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 108801 741871 riscv-013.c:2859 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 108802 741872 target.c:2764 target_write_u32(): address: 0x600080a8, value: 0x50d83aa1
Debug: 108803 741872 riscv-013.c:3681 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 108804 741873 riscv-013.c:2859 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 108805 741874 target.c:2764 target_write_u32(): address: 0x60008090, value: 0x00000000
Debug: 108806 741874 riscv-013.c:3681 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 108807 741875 riscv-013.c:2859 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 108808 741879 riscv-013.c:2859 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 108809 741879 riscv.c:930 remove_trigger(): [0] Stop using resource 1 for bp 678
Debug: 108810 741879 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register tselect
Debug: 108811 741879 riscv-013.c:800 execute_abstract_command(): command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0
Debug: 108812 741880 riscv-013.c:1504 register_read_direct(): {0} tselect = 0x0
Debug: 108813 741880 riscv.c:3539 riscv_get_register(): [esp32c3] tselect: 0
Debug: 108814 741880 riscv.c:3482 riscv_set_register(): [esp32c3] tselect <- 1
Debug: 108815 741881 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x1 to register tselect
Debug: 108816 741881 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x1
Debug: 108817 741881 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 108818 741883 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x1 to tselect valid=0
Debug: 108819 741883 riscv.c:3482 riscv_set_register(): [esp32c3] tdata1 <- 0
Debug: 108820 741883 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x0 to register tdata1
Debug: 108821 741883 riscv-013.c:1315 register_write_direct(): {0} tdata1 <- 0x0
Debug: 108822 741883 riscv-013.c:800 execute_abstract_command(): command=0x2307a1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a1
Debug: 108823 741883 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to tdata1 valid=0
Debug: 108824 741883 riscv.c:3482 riscv_set_register(): [esp32c3] tselect <- 0
Debug: 108825 741883 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x0 to register tselect
Debug: 108826 741883 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x0
Debug: 108827 741883 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 108828 741883 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to tselect valid=0
Debug: 108829 741883 breakpoints.c:291 breakpoint_free(): free BPID: 678 --> 0
Debug: 108830 741883 riscv.c:866 riscv_add_breakpoint(): [0] @0x4200004e
Debug: 108831 741883 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register tselect
Debug: 108832 741883 riscv-013.c:800 execute_abstract_command(): command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0
Debug: 108833 741883 riscv-013.c:1504 register_read_direct(): {0} tselect = 0x0
Debug: 108834 741883 riscv.c:3539 riscv_get_register(): [esp32c3] tselect: 0
Debug: 108835 741888 riscv.c:3482 riscv_set_register(): [esp32c3] tselect <- 1
Debug: 108836 741888 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x1 to register tselect
Debug: 108837 741888 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x1
Debug: 108838 741888 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 108839 741890 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x1 to tselect valid=0
Debug: 108840 741890 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register tdata1
Debug: 108841 741890 riscv-013.c:800 execute_abstract_command(): command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1
Debug: 108842 741892 riscv-013.c:1504 register_read_direct(): {0} tdata1 = 0x23e00000
Debug: 108843 741892 riscv.c:3539 riscv_get_register(): [esp32c3] tdata1: 23e00000
Debug: 108844 741892 riscv.c:3482 riscv_set_register(): [esp32c3] tdata1 <- 2be0104c
Debug: 108845 741892 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x2be0104c to register tdata1
Debug: 108846 741893 riscv-013.c:1315 register_write_direct(): {0} tdata1 <- 0x2be0104c
Debug: 108847 741893 riscv-013.c:800 execute_abstract_command(): command=0x2307a1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a1
Debug: 108848 741894 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x2be0104c to tdata1 valid=0
Debug: 108849 741894 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register tdata1
Debug: 108850 741894 riscv-013.c:800 execute_abstract_command(): command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1
Debug: 108851 741896 riscv-013.c:1504 register_read_direct(): {0} tdata1 = 0x2be0104c
Debug: 108852 741896 riscv.c:3539 riscv_get_register(): [esp32c3] tdata1: 2be0104c
Debug: 108853 741896 riscv.c:621 maybe_add_trigger_t2(): tdata1=0x2be0104c
Debug: 108854 741896 riscv.c:3482 riscv_set_register(): [esp32c3] tdata2 <- 4200004e
Debug: 108855 741896 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x4200004e to register tdata2
Debug: 108856 741896 riscv-013.c:1315 register_write_direct(): {0} tdata2 <- 0x4200004e
Debug: 108857 741897 riscv-013.c:800 execute_abstract_command(): command=0x2307a2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a2
Debug: 108858 741898 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x4200004e to tdata2 valid=0
Debug: 108859 741898 riscv.c:731 add_trigger(): [0] Using trigger 1 (type 2) for bp 679
Debug: 108860 741898 riscv.c:3482 riscv_set_register(): [esp32c3] tselect <- 0
Debug: 108861 741898 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x0 to register tselect
Debug: 108862 741898 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x0
Debug: 108863 741899 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 108864 741900 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to tselect valid=0
Debug: 108865 741900 breakpoints.c:93 breakpoint_add_internal(): [0] added hardware breakpoint at 0x4200004e of length 0x00000002, (BPID: 679)
Debug: 108866 741900 riscv_semihosting.c:188 riscv_semihosting_post_result(): 0x0
Debug: 108867 741900 riscv.c:3482 riscv_set_register(): [esp32c3] a0 <- 0
Debug: 108868 741901 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x0 to register a0
Debug: 108869 741901 riscv-013.c:1315 register_write_direct(): {0} a0 <- 0x0
Debug: 108870 741901 riscv-013.c:800 execute_abstract_command(): command=0x23100a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100a
Debug: 108871 741902 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to a0 valid=1
Debug: 108872 741902 riscv.c:3482 riscv_set_register(): [esp32c3] pc <- 4038771a
Debug: 108873 741902 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x4038771a to register pc
Debug: 108874 741902 riscv-013.c:4121 riscv013_set_register(): [0] writing PC to DPC: 0x4038771a
Debug: 108875 741902 riscv-013.c:1315 register_write_direct(): {0} dpc <- 0x4038771a
Debug: 108876 741903 riscv-013.c:800 execute_abstract_command(): command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1
Debug: 108877 741903 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 108878 741905 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x4038771a
Debug: 108879 741906 riscv-013.c:4125 riscv013_set_register(): [0]   actual DPC written: 0x000000004038771a
Debug: 108880 741906 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x4038771a to pc valid=0
Debug: 108881 741906 riscv_semihosting.c:154 riscv_semihosting():    -> HANDLED
Debug: 108882 741906 riscv.c:1474 riscv_resume(): handle_breakpoints=0
Debug: 108883 741906 riscv.c:1401 resume_prep(): [0]
Debug: 108884 741906 riscv.c:1291 riscv_resume_prep_all_harts(): [esp32c3] prep hart
Debug: 108885 741907 program.c:35 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f)
Debug: 108886 741907 riscv-013.c:4382 riscv013_write_debug_buffer(): cache hit for 0x100f @0
Debug: 108887 741907 program.c:35 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f)
Debug: 108888 741907 riscv-013.c:4382 riscv013_write_debug_buffer(): cache hit for 0xf @1
Debug: 108889 741907 program.c:35 riscv_program_write(): debug_buffer[02] = DASM(0x00100073)
Debug: 108890 741907 riscv-013.c:4382 riscv013_write_debug_buffer(): cache hit for 0x100073 @2
Debug: 108891 741907 riscv-013.c:800 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000
Debug: 108892 741909 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 108893 741911 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x4000b043
Debug: 108894 741911 riscv.c:3482 riscv_set_register(): [esp32c3] dcsr <- 4000b043
Debug: 108895 741911 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x4000b043 to register dcsr
Debug: 108896 741912 riscv-013.c:1315 register_write_direct(): {0} dcsr <- 0x4000b043
Debug: 108897 741912 riscv-013.c:800 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 108898 741912 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x4000b043 to dcsr valid=0
Debug: 108899 741912 riscv.c:1302 riscv_resume_prep_all_harts(): [esp32c3] mark as prepped
Debug: 108900 741912 riscv.c:1426 resume_prep(): [0] mark as prepped
Debug: 108901 741912 riscv.c:3280 riscv_resume_go_all_harts(): [esp32c3] resuming hart
Debug: 108902 741912 riscv-013.c:4191 select_prepped_harts(): index=0, coreid=0, prepped=1
Debug: 108903 741912 riscv-013.c:4818 riscv013_step_or_resume_current_hart(): resuming hart 0 (for step?=0)
Debug: 108904 741912 riscv.c:3402 riscv_invalidate_register_cache(): [0]
Debug: 108905 741912 target.c:1847 target_call_event_callbacks(): target event 2 (resumed) for core esp32c3
Debug: 108906 741912 esp32c3.c:177 esp32c3_handle_target_event(): 2
Debug: 108907 741912 esp_riscv.c:356 esp_riscv_handle_target_event(): 2
Debug: 108908 741912 gdb_server.c:390 gdb_log_incoming_packet(): [esp32c3] received packet: <Ctrl-C>
Debug: 108909 741912 FreeRTOS.c:550 freertos_find_target_from_threadid(): Find target for thr 0x3fcdfaac
Debug: 108910 741912 FreeRTOS.c:578 freertos_target_for_threadid(): target found : esp32c3
Debug: 108911 741912 riscv.c:1234 riscv_halt(): [0] halting all harts
Debug: 108912 741912 riscv.c:1170 halt_prep(): [esp32c3] prep hart, debug_reason=5
Debug: 108913 741912 riscv.c:1175 halt_prep(): [esp32c3] Hart is already halted (reason=5).
Debug: 108914 741912 riscv.c:1192 riscv_halt_go_all_harts(): [esp32c3] Hart is already halted.
Debug: 108915 741912 riscv.c:3402 riscv_invalidate_register_cache(): [0]
Debug: 108916 741912 target.c:1847 target_call_event_callbacks(): target event 0 (gdb-halt) for core esp32c3
Debug: 108917 741912 esp32c3.c:177 esp32c3_handle_target_event(): 0
Debug: 108918 741912 esp_riscv.c:356 esp_riscv_handle_target_event(): 0
Debug: 108919 741912 FreeRTOS.c:865 freertos_update_threads(): freertos_update_threads
Debug: 108920 741912 riscv-013.c:2859 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 108921 741912 target.c:2676 target_read_u32(): address: 0x3fc8c080, value: 0x00000018
Debug: 108922 741922 riscv-013.c:2859 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 108923 741922 target.c:2676 target_read_u32(): address: 0x3fc95774, value: 0x00000004
Debug: 108924 741922 FreeRTOS.c:935 freertos_update_threads(): Read uxCurrentNumberOfTasks at 0x3fc95774, value 4
Debug: 108925 741924 riscv-013.c:2859 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 108926 741924 target.c:2676 target_read_u32(): address: 0x3fc95780, value: 0x00000005
Debug: 108927 741924 FreeRTOS.c:956 freertos_update_threads(): Read uxTaskNumber at 0x3fc95780, value 5
Debug: 108928 741924 target.c:2522 target_read_buffer(): reading buffer of 4 byte at 0x3fc95768
Debug: 108929 741926 riscv-013.c:2859 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 108930 741926 FreeRTOS.c:540 freertos_current_threadid_from_target(): Curr thread 0x3fcdfaac on target [esp32c3]
Debug: 108931 741926 FreeRTOS.c:978 freertos_update_threads(): FreeRTOS: Read pxCurrentTCB at 0x3fc95768, value 0x3fcdfaac
Debug: 108932 741927 FreeRTOS.c:550 freertos_find_target_from_threadid(): Find target for thr 0x3fcdfaac
Debug: 108933 741927 FreeRTOS.c:578 freertos_target_for_threadid(): target found : esp32c3
Debug: 108934 741927 gdb_server.c:407 gdb_log_outgoing_packet(): [esp32c3] sending packet: $T02thread:3fcdfaac;#8e
Debug: 108935 741927 target.c:1847 target_call_event_callbacks(): target event 1 (halted) for core esp32c3
Debug: 108936 741927 target.c:5139 target_handle_event(): target(0): esp32c3 (esp32c3) event: 1 (halted) action: 
    esp32c3_wdt_disable

Debug: 108937 741927 command.c:155 script_debug(): command - command mode
Debug: 108938 741929 command.c:155 script_debug(): command - mww 0x6001f064 0x50D83AA1
Debug: 108939 741929 riscv-013.c:3681 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 108940 741929 riscv-013.c:2859 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 108941 741929 command.c:155 script_debug(): command - mww 0x6001F048 0
Debug: 108942 741932 riscv-013.c:3681 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 108943 741932 riscv-013.c:2859 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 108944 741932 command.c:155 script_debug(): command - mww 0x60020064 0x50D83AA1
Debug: 108945 741932 riscv-013.c:3681 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 108946 741932 riscv-013.c:2859 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 108947 741932 command.c:155 script_debug(): command - mww 0x60020048 0
Debug: 108948 741932 riscv-013.c:3681 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 108949 741938 riscv-013.c:2859 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 108950 741938 command.c:155 script_debug(): command - mww 0x600080a8 0x50D83AA1
Debug: 108951 741940 riscv-013.c:3681 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 108952 741941 riscv-013.c:2859 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 108953 741941 command.c:155 script_debug(): command - mww 0x60008090 0
Debug: 108954 741943 riscv-013.c:3681 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 108955 741944 riscv-013.c:2859 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 108956 741944 command.c:155 script_debug(): command - mww 0x600080b0 0x8F1D312A
Debug: 108957 741945 riscv-013.c:3681 write_memory_bus_v1(): transferring burst starting at address 0x600080b0
Debug: 108958 741946 riscv-013.c:2859 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 108959 741946 command.c:155 script_debug(): command - mww 0x600080ac 0x84B00000
Debug: 108960 741946 riscv-013.c:3681 write_memory_bus_v1(): transferring burst starting at address 0x600080ac
Debug: 108961 741946 riscv-013.c:2859 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 108962 741946 esp32c3.c:177 esp32c3_handle_target_event(): 1
Debug: 108963 741946 esp_riscv.c:356 esp_riscv_handle_target_event(): 1
Debug: 108964 741946 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register mcause
Debug: 108965 741946 riscv-013.c:800 execute_abstract_command(): command=0x220342; access register, size=32, postexec=0, transfer=1, write=0, regno=0x342
Debug: 108966 741946 riscv-013.c:1504 register_read_direct(): {0} mcause = 0x80000018
Debug: 108967 741946 riscv.c:3539 riscv_get_register(): [esp32c3] mcause: 80000018
Debug: 108968 741946 esp_riscv.c:132 esp_riscv_print_exception_reason(): [esp32c3] mcause=80000018
Debug: 108969 741946 target.c:1847 target_call_event_callbacks(): target event 8 (gdb-end) for core esp32c3
Debug: 108970 741946 esp32c3.c:177 esp32c3_handle_target_event(): 8
Debug: 108971 741946 esp_riscv.c:356 esp_riscv_handle_target_event(): 8
Debug: 108972 741946 gdb_server.c:390 gdb_log_incoming_packet(): [esp32c3] received packet: g
Debug: 108973 741946 riscv.c:1765 riscv_get_gdb_reg_list_internal(): [esp32c3] {0} reg_class=1, read=0
Debug: 108974 741946 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register zero
Debug: 108975 741946 riscv.c:3539 riscv_get_register(): [esp32c3] zero: 0
Debug: 108976 741946 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from zero (valid=1)
Debug: 108977 741946 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register ra
Debug: 108978 741946 riscv-013.c:800 execute_abstract_command(): command=0x221001; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1001
Debug: 108979 741953 riscv-013.c:1504 register_read_direct(): {0} ra = 0x4038774a
Debug: 108980 741953 riscv.c:3539 riscv_get_register(): [esp32c3] ra: 4038774a
Debug: 108981 741953 riscv.c:3893 register_get(): [esp32c3] read 0x4038774a from ra (valid=1)
Debug: 108982 741953 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register sp
Debug: 108983 741953 riscv-013.c:800 execute_abstract_command(): command=0x221002; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1002
Debug: 108984 741956 riscv-013.c:1504 register_read_direct(): {0} sp = 0x3fc9bfe0
Debug: 108985 741956 riscv.c:3539 riscv_get_register(): [esp32c3] sp: 3fc9bfe0
Debug: 108986 741956 riscv.c:3893 register_get(): [esp32c3] read 0x3fc9bfe0 from sp (valid=1)
Debug: 108987 741956 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register gp
Debug: 108988 741956 riscv-013.c:800 execute_abstract_command(): command=0x221003; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1003
Debug: 108989 741958 riscv-013.c:1504 register_read_direct(): {0} gp = 0x3fc8c200
Debug: 108990 741958 riscv.c:3539 riscv_get_register(): [esp32c3] gp: 3fc8c200
Debug: 108991 741958 riscv.c:3893 register_get(): [esp32c3] read 0x3fc8c200 from gp (valid=1)
Debug: 108992 741958 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register tp
Debug: 108993 741958 riscv-013.c:800 execute_abstract_command(): command=0x221004; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1004
Debug: 108994 741960 riscv-013.c:1504 register_read_direct(): {0} tp = 0x3fc93230
Debug: 108995 741960 riscv.c:3539 riscv_get_register(): [esp32c3] tp: 3fc93230
Debug: 108996 741960 riscv.c:3893 register_get(): [esp32c3] read 0x3fc93230 from tp (valid=1)
Debug: 108997 741960 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register t0
Debug: 108998 741960 riscv-013.c:800 execute_abstract_command(): command=0x221005; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1005
Debug: 108999 741962 riscv-013.c:1504 register_read_direct(): {0} t0 = 0x4005890e
Debug: 109000 741962 riscv.c:3539 riscv_get_register(): [esp32c3] t0: 4005890e
Debug: 109001 741962 riscv.c:3893 register_get(): [esp32c3] read 0x4005890e from t0 (valid=1)
Debug: 109002 741962 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register t1
Debug: 109003 741962 riscv-013.c:800 execute_abstract_command(): command=0x221006; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1006
Debug: 109004 741963 riscv-013.c:1504 register_read_direct(): {0} t1 = 0xf
Debug: 109005 741963 riscv.c:3539 riscv_get_register(): [esp32c3] t1: f
Debug: 109006 741963 riscv.c:3893 register_get(): [esp32c3] read 0x0000000f from t1 (valid=1)
Debug: 109007 741963 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register t2
Debug: 109008 741963 riscv-013.c:800 execute_abstract_command(): command=0x221007; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1007
Debug: 109009 741963 riscv-013.c:1504 register_read_direct(): {0} t2 = 0x0
Debug: 109010 741963 riscv.c:3539 riscv_get_register(): [esp32c3] t2: 0
Debug: 109011 741963 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from t2 (valid=1)
Debug: 109012 741963 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register s0
Debug: 109013 741963 riscv-013.c:800 execute_abstract_command(): command=0x221008; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1008
Debug: 109014 741963 riscv-013.c:1504 register_read_direct(): {0} s0 = 0x4200004e
Debug: 109015 741963 riscv.c:3539 riscv_get_register(): [esp32c3] s0: 4200004e
Debug: 109016 741963 riscv.c:3893 register_get(): [esp32c3] read 0x4200004e from fp (valid=1)
Debug: 109017 741963 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register s1
Debug: 109018 741963 riscv-013.c:800 execute_abstract_command(): command=0x221009; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1009
Debug: 109019 741963 riscv-013.c:1504 register_read_direct(): {0} s1 = 0x0
Debug: 109020 741963 riscv.c:3539 riscv_get_register(): [esp32c3] s1: 0
Debug: 109021 741963 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from s1 (valid=1)
Debug: 109022 741963 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register a0
Debug: 109023 741963 riscv-013.c:800 execute_abstract_command(): command=0x22100a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100a
Debug: 109024 741963 riscv-013.c:1504 register_read_direct(): {0} a0 = 0x103
Debug: 109025 741963 riscv.c:3539 riscv_get_register(): [esp32c3] a0: 103
Debug: 109026 741963 riscv.c:3893 register_get(): [esp32c3] read 0x00000103 from a0 (valid=1)
Debug: 109027 741963 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register a1
Debug: 109028 741963 riscv-013.c:800 execute_abstract_command(): command=0x22100b; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100b
Debug: 109029 741972 riscv-013.c:1504 register_read_direct(): {0} a1 = 0x3fc9bfe4
Debug: 109030 741972 riscv.c:3539 riscv_get_register(): [esp32c3] a1: 3fc9bfe4
Debug: 109031 741972 riscv.c:3893 register_get(): [esp32c3] read 0x3fc9bfe4 from a1 (valid=1)
Debug: 109032 741972 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register a2
Debug: 109033 741972 riscv-013.c:800 execute_abstract_command(): command=0x22100c; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100c
Debug: 109034 741974 riscv-013.c:1504 register_read_direct(): {0} a2 = 0x1
Debug: 109035 741974 riscv.c:3539 riscv_get_register(): [esp32c3] a2: 1
Debug: 109036 741975 riscv.c:3893 register_get(): [esp32c3] read 0x00000001 from a2 (valid=1)
Debug: 109037 741975 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register a3
Debug: 109038 741975 riscv-013.c:800 execute_abstract_command(): command=0x22100d; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100d
Debug: 109039 741976 riscv-013.c:1504 register_read_direct(): {0} a3 = 0x0
Debug: 109040 741976 riscv.c:3539 riscv_get_register(): [esp32c3] a3: 0
Debug: 109041 741976 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from a3 (valid=1)
Debug: 109042 741976 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register a4
Debug: 109043 741977 riscv-013.c:800 execute_abstract_command(): command=0x22100e; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100e
Debug: 109044 741978 riscv-013.c:1504 register_read_direct(): {0} a4 = 0x2
Debug: 109045 741978 riscv.c:3539 riscv_get_register(): [esp32c3] a4: 2
Debug: 109046 741978 riscv.c:3893 register_get(): [esp32c3] read 0x00000002 from a4 (valid=1)
Debug: 109047 741978 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register a5
Debug: 109048 741978 riscv-013.c:800 execute_abstract_command(): command=0x22100f; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100f
Debug: 109049 741978 riscv-013.c:1504 register_read_direct(): {0} a5 = 0x1
Debug: 109050 741978 riscv.c:3539 riscv_get_register(): [esp32c3] a5: 1
Debug: 109051 741978 riscv.c:3893 register_get(): [esp32c3] read 0x00000001 from a5 (valid=1)
Debug: 109052 741978 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register a6
Debug: 109053 741978 riscv-013.c:800 execute_abstract_command(): command=0x221010; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1010
Debug: 109054 741978 riscv-013.c:1504 register_read_direct(): {0} a6 = 0x0
Debug: 109055 741978 riscv.c:3539 riscv_get_register(): [esp32c3] a6: 0
Debug: 109056 741978 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from a6 (valid=1)
Debug: 109057 741978 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register a7
Debug: 109058 741978 riscv-013.c:800 execute_abstract_command(): command=0x221011; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1011
Debug: 109059 741978 riscv-013.c:1504 register_read_direct(): {0} a7 = 0x0
Debug: 109060 741978 riscv.c:3539 riscv_get_register(): [esp32c3] a7: 0
Debug: 109061 741978 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from a7 (valid=1)
Debug: 109062 741984 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register s2
Debug: 109063 741984 riscv-013.c:800 execute_abstract_command(): command=0x221012; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1012
Debug: 109064 741984 riscv-013.c:1504 register_read_direct(): {0} s2 = 0x3c032000
Debug: 109065 741984 riscv.c:3539 riscv_get_register(): [esp32c3] s2: 3c032000
Debug: 109066 741984 riscv.c:3893 register_get(): [esp32c3] read 0x3c032000 from s2 (valid=1)
Debug: 109067 741984 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register s3
Debug: 109068 741984 riscv-013.c:800 execute_abstract_command(): command=0x221013; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1013
Debug: 109069 741984 riscv-013.c:1504 register_read_direct(): {0} s3 = 0x0
Debug: 109070 741984 riscv.c:3539 riscv_get_register(): [esp32c3] s3: 0
Debug: 109071 741984 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from s3 (valid=1)
Debug: 109072 741984 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register s4
Debug: 109073 741984 riscv-013.c:800 execute_abstract_command(): command=0x221014; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1014
Debug: 109074 741988 riscv-013.c:1504 register_read_direct(): {0} s4 = 0x0
Debug: 109075 741989 riscv.c:3539 riscv_get_register(): [esp32c3] s4: 0
Debug: 109076 741989 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from s4 (valid=1)
Debug: 109077 741989 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register s5
Debug: 109078 741989 riscv-013.c:800 execute_abstract_command(): command=0x221015; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1015
Debug: 109079 741990 riscv-013.c:1504 register_read_direct(): {0} s5 = 0x0
Debug: 109080 741990 riscv.c:3539 riscv_get_register(): [esp32c3] s5: 0
Debug: 109081 741991 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from s5 (valid=1)
Debug: 109082 741991 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register s6
Debug: 109083 741991 riscv-013.c:800 execute_abstract_command(): command=0x221016; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1016
Debug: 109084 741992 riscv-013.c:1504 register_read_direct(): {0} s6 = 0x0
Debug: 109085 741992 riscv.c:3539 riscv_get_register(): [esp32c3] s6: 0
Debug: 109086 741992 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from s6 (valid=1)
Debug: 109087 741992 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register s7
Debug: 109088 741992 riscv-013.c:800 execute_abstract_command(): command=0x221017; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1017
Debug: 109089 741993 riscv-013.c:1504 register_read_direct(): {0} s7 = 0x0
Debug: 109090 741993 riscv.c:3539 riscv_get_register(): [esp32c3] s7: 0
Debug: 109091 741993 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from s7 (valid=1)
Debug: 109092 741995 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register s8
Debug: 109093 741995 riscv-013.c:800 execute_abstract_command(): command=0x221018; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1018
Debug: 109094 741996 riscv-013.c:1504 register_read_direct(): {0} s8 = 0x0
Debug: 109095 741996 riscv.c:3539 riscv_get_register(): [esp32c3] s8: 0
Debug: 109096 741996 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from s8 (valid=1)
Debug: 109097 741996 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register s9
Debug: 109098 741996 riscv-013.c:800 execute_abstract_command(): command=0x221019; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1019
Debug: 109099 741996 riscv-013.c:1504 register_read_direct(): {0} s9 = 0x0
Debug: 109100 741996 riscv.c:3539 riscv_get_register(): [esp32c3] s9: 0
Debug: 109101 741996 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from s9 (valid=1)
Debug: 109102 741996 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register s10
Debug: 109103 741996 riscv-013.c:800 execute_abstract_command(): command=0x22101a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101a
Debug: 109104 741996 riscv-013.c:1504 register_read_direct(): {0} s10 = 0x0
Debug: 109105 741996 riscv.c:3539 riscv_get_register(): [esp32c3] s10: 0
Debug: 109106 741996 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from s10 (valid=1)
Debug: 109107 741996 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register s11
Debug: 109108 741996 riscv-013.c:800 execute_abstract_command(): command=0x22101b; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101b
Debug: 109109 741996 riscv-013.c:1504 register_read_direct(): {0} s11 = 0x0
Debug: 109110 741996 riscv.c:3539 riscv_get_register(): [esp32c3] s11: 0
Debug: 109111 741996 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from s11 (valid=1)
Debug: 109112 741996 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register t3
Debug: 109113 741996 riscv-013.c:800 execute_abstract_command(): command=0x22101c; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101c
Debug: 109114 741996 riscv-013.c:1504 register_read_direct(): {0} t3 = 0x0
Debug: 109115 741996 riscv.c:3539 riscv_get_register(): [esp32c3] t3: 0
Debug: 109116 741996 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from t3 (valid=1)
Debug: 109117 741996 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register t4
Debug: 109118 741996 riscv-013.c:800 execute_abstract_command(): command=0x22101d; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101d
Debug: 109119 742005 riscv-013.c:1504 register_read_direct(): {0} t4 = 0x0
Debug: 109120 742005 riscv.c:3539 riscv_get_register(): [esp32c3] t4: 0
Debug: 109121 742005 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from t4 (valid=1)
Debug: 109122 742005 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register t5
Debug: 109123 742005 riscv-013.c:800 execute_abstract_command(): command=0x22101e; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101e
Debug: 109124 742007 riscv-013.c:1504 register_read_direct(): {0} t5 = 0x0
Debug: 109125 742007 riscv.c:3539 riscv_get_register(): [esp32c3] t5: 0
Debug: 109126 742007 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from t5 (valid=1)
Debug: 109127 742007 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register t6
Debug: 109128 742007 riscv-013.c:800 execute_abstract_command(): command=0x22101f; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101f
Debug: 109129 742009 riscv-013.c:1504 register_read_direct(): {0} t6 = 0x0
Debug: 109130 742009 riscv.c:3539 riscv_get_register(): [esp32c3] t6: 0
Debug: 109131 742009 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from t6 (valid=1)
Debug: 109132 742009 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register pc
Debug: 109133 742009 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 109134 742010 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x40387716
Debug: 109135 742010 riscv-013.c:4096 riscv013_get_register(): [0] read PC from DPC: 0x40387716
Debug: 109136 742011 riscv.c:3539 riscv_get_register(): [esp32c3] pc: 40387716
Debug: 109137 742011 riscv.c:3893 register_get(): [esp32c3] read 0x40387716 from pc (valid=0)
Debug: 109138 742011 gdb_server.c:407 gdb_log_outgoing_packet(): [esp32c3] sending packet: $000000004a773840e0bfc93f00c2c83f3032c93f0e8905400f000000000000004e0000420000000003010000e4bfc93f0100000000000000020000000100000000000000000000000020033c0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000016773840#4b
Debug: 109139 742012 gdb_server.c:390 gdb_log_incoming_packet(): [esp32c3] received packet: qXfer:threads:read::0,1000
Debug: 109140 742012 gdb_server.c:404 gdb_log_outgoing_packet(): [esp32c3] sending packet: $<binary-data-278-bytes>#12
Debug: 109141 742012 gdb_server.c:390 gdb_log_incoming_packet(): [esp32c3] received packet: z1,4200006c,2
Debug: 109142 742012 gdb_server.c:1745 gdb_breakpoint_watchpoint_packet(): [esp32c3]
Debug: 109143 742012 riscv.c:930 remove_trigger(): [0] Stop using resource 0 for bp 2
Debug: 109144 742012 riscv-013.c:4087 riscv013_get_register(): [esp32c3] reading register tselect
Debug: 109145 742012 riscv-013.c:800 execute_abstract_command(): command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0
Debug: 109146 742015 riscv-013.c:1504 register_read_direct(): {0} tselect = 0x0
Debug: 109147 742015 riscv.c:3539 riscv_get_register(): [esp32c3] tselect: 0
Debug: 109148 742015 riscv.c:3482 riscv_set_register(): [esp32c3] tselect <- 0
Debug: 109149 742015 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x0 to register tselect
Debug: 109150 742015 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x0
Debug: 109151 742016 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 109152 742017 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to tselect valid=0
Debug: 109153 742017 riscv.c:3482 riscv_set_register(): [esp32c3] tdata1 <- 0
Debug: 109154 742017 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x0 to register tdata1
Debug: 109155 742017 riscv-013.c:1315 register_write_direct(): {0} tdata1 <- 0x0
Debug: 109156 742018 riscv-013.c:800 execute_abstract_command(): command=0x2307a1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a1
Debug: 109157 742019 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to tdata1 valid=0
Debug: 109158 742019 riscv.c:3482 riscv_set_register(): [esp32c3] tselect <- 0
Debug: 109159 742019 riscv-013.c:4116 riscv013_set_register(): [0] writing 0x0 to register tselect
Debug: 109160 742019 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x0
Debug: 109161 742019 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 109162 742020 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to tselect valid=0
Debug: 109163 742020 breakpoints.c:291 breakpoint_free(): free BPID: 2 --> 0
Debug: 109164 742020 gdb_server.c:407 gdb_log_outgoing_packet(): [esp32c3] sending packet: $OK#9a
Debug: 109165 742021 gdb_server.c:390 gdb_log_incoming_packet(): [esp32c3] received packet: m3fc9bfc0,40
Debug: 109166 742021 gdb_server.c:1533 gdb_read_memory_packet(): addr: 0x000000003fc9bfc0, len: 0x00000040
Debug: 109167 742021 target.c:2522 target_read_buffer(): reading buffer of 64 byte at 0x3fc9bfc0
Debug: 109168 742026 riscv-013.c:2859 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 109169 742027 gdb_server.c:407 gdb_log_outgoing_packet(): [esp32c3] sending packet: $a5a5a5a5a5a5a5a5a5a5a50a01000000000000000000000000000000000000000100000001000000000000004e0000420020033c0050c93f7cc0c93f00820042#6c
Debug: 109170 742029 gdb_server.c:390 gdb_log_incoming_packet(): [esp32c3] received packet: m3fc9c040,40
Debug: 109171 742029 gdb_server.c:1533 gdb_read_memory_packet(): addr: 0x000000003fc9c040, len: 0x00000040
Debug: 109172 742029 target.c:2522 target_read_buffer(): reading buffer of 64 byte at 0x3fc9c040
Debug: 109173 742035 riscv-013.c:2859 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 109174 742035 gdb_server.c:407 gdb_log_outgoing_packet(): [esp32c3] sending packet: $a5a5a5a5a5a5a5a5a5a5a5a5431db138a5a5a5a5a5a5a5a5a5a5a5a5000000000100000000000000b0c0c93fe2850042a5a5a5a5a5a5a5a5a5a5a5a500000000#37
Debug: 109175 742187 gdb_server.c:228 gdb_get_char_inner(): GDB connection closed by the remote client
Debug: 109176 742187 gdb_server.c:1115 gdb_connection_closed(): GDB Close, Target: esp32c3, state: halted, gdb_actual_connections=0
Debug: 109177 742187 target.c:1847 target_call_event_callbacks(): target event 8 (gdb-end) for core esp32c3
Debug: 109178 742187 esp32c3.c:177 esp32c3_handle_target_event(): 8
Debug: 109179 742187 esp_riscv.c:356 esp_riscv_handle_target_event(): 8
Debug: 109180 742187 target.c:1847 target_call_event_callbacks(): target event 23 (gdb-detach) for core esp32c3
Debug: 109181 742190 esp32c3.c:177 esp32c3_handle_target_event(): 23
Debug: 109182 742190 esp_riscv.c:356 esp_riscv_handle_target_event(): 23
Info : 109183 742191 server.c:569 server_loop(): dropped 'gdb' connection
[2023-06-27T13:22:11.228Z] SERVER CONSOLE DEBUG: onBackendConnect: gdb-server session closed
GDB server session ended. This terminal will be reused, waiting for next session to start...