Skip to content

Commit f46725e

Browse files
me-no-devme-no-dev
committed
feat(idf): Add initial support for IDF v5.5 and ESP32-C5
1 parent 115caf2 commit f46725e

14 files changed

+357
-53
lines changed

‎CMakeLists.txt

+1-1
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66
# idf.py build
77

88
set(min_supported_idf_version "5.3.0")
9-
set(max_supported_idf_version "5.4.99")
9+
set(max_supported_idf_version "5.5.99")
1010
set(idf_version "${IDF_VERSION_MAJOR}.${IDF_VERSION_MINOR}.${IDF_VERSION_PATCH}")
1111

1212
if ("${idf_version}" AND NOT "$ENV{ARDUINO_SKIP_IDF_VERSION_CHECK}")

‎boards.txt

+212
Original file line numberDiff line numberDiff line change
@@ -161,6 +161,218 @@ esp32c2.menu.EraseFlash.all.upload.erase_cmd=-e
161161

162162
##############################################################
163163

164+
esp32c5.name=ESP32C5 Dev Module
165+
166+
esp32c5.bootloader.tool=esptool_py
167+
esp32c5.bootloader.tool.default=esptool_py
168+
169+
esp32c5.upload.tool=esptool_py
170+
esp32c5.upload.tool.default=esptool_py
171+
esp32c5.upload.tool.network=esp_ota
172+
173+
esp32c5.upload.maximum_size=1310720
174+
esp32c5.upload.maximum_data_size=327680
175+
esp32c5.upload.flags=
176+
esp32c5.upload.extra_flags=
177+
esp32c5.upload.use_1200bps_touch=false
178+
esp32c5.upload.wait_for_upload_port=false
179+
180+
esp32c5.serial.disableDTR=false
181+
esp32c5.serial.disableRTS=false
182+
183+
esp32c5.build.tarch=riscv32
184+
esp32c5.build.target=esp
185+
esp32c5.build.mcu=esp32c5
186+
esp32c5.build.core=esp32
187+
esp32c5.build.variant=esp32c5
188+
esp32c5.build.board=ESP32C5_DEV
189+
esp32c5.build.bootloader_addr=0x0
190+
191+
esp32c5.build.cdc_on_boot=0
192+
esp32c5.build.f_cpu=240000000L
193+
esp32c5.build.flash_size=4MB
194+
esp32c5.build.flash_freq=80m
195+
esp32c5.build.flash_mode=qio
196+
esp32c5.build.boot=qio
197+
esp32c5.build.partitions=default
198+
esp32c5.build.defines=
199+
200+
## IDE 2.0 Seems to not update the value
201+
esp32c5.menu.JTAGAdapter.default=Disabled
202+
esp32c5.menu.JTAGAdapter.default.build.copy_jtag_files=0
203+
esp32c5.menu.JTAGAdapter.builtin=Integrated USB JTAG
204+
esp32c5.menu.JTAGAdapter.builtin.build.openocdscript=esp32c5-builtin.cfg
205+
esp32c5.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
206+
esp32c5.menu.JTAGAdapter.external=FTDI Adapter
207+
esp32c5.menu.JTAGAdapter.external.build.openocdscript=esp32c5-ftdi.cfg
208+
esp32c5.menu.JTAGAdapter.external.build.copy_jtag_files=1
209+
esp32c5.menu.JTAGAdapter.bridge=ESP USB Bridge
210+
esp32c5.menu.JTAGAdapter.bridge.build.openocdscript=esp32c5-bridge.cfg
211+
esp32c5.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
212+
213+
esp32c5.menu.CDCOnBoot.default=Disabled
214+
esp32c5.menu.CDCOnBoot.default.build.cdc_on_boot=0
215+
esp32c5.menu.CDCOnBoot.cdc=Enabled
216+
esp32c5.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
217+
218+
esp32c5.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
219+
esp32c5.menu.PartitionScheme.default.build.partitions=default
220+
esp32c5.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
221+
esp32c5.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
222+
esp32c5.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
223+
esp32c5.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
224+
esp32c5.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
225+
esp32c5.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
226+
esp32c5.menu.PartitionScheme.minimal.build.partitions=minimal
227+
esp32c5.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2)
228+
esp32c5.menu.PartitionScheme.no_fs.build.partitions=no_fs
229+
esp32c5.menu.PartitionScheme.no_fs.upload.maximum_size=2031616
230+
esp32c5.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
231+
esp32c5.menu.PartitionScheme.no_ota.build.partitions=no_ota
232+
esp32c5.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
233+
esp32c5.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
234+
esp32c5.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
235+
esp32c5.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
236+
esp32c5.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
237+
esp32c5.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
238+
esp32c5.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
239+
esp32c5.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
240+
esp32c5.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
241+
esp32c5.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
242+
esp32c5.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
243+
esp32c5.menu.PartitionScheme.huge_app.build.partitions=huge_app
244+
esp32c5.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
245+
esp32c5.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
246+
esp32c5.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
247+
esp32c5.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
248+
esp32c5.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
249+
esp32c5.menu.PartitionScheme.fatflash.build.partitions=ffat
250+
esp32c5.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
251+
esp32c5.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
252+
esp32c5.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
253+
esp32c5.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
254+
esp32c5.menu.PartitionScheme.rainmaker=RainMaker 4MB
255+
esp32c5.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
256+
esp32c5.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
257+
esp32c5.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
258+
esp32c5.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
259+
esp32c5.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
260+
esp32c5.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
261+
esp32c5.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
262+
esp32c5.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
263+
esp32c5.menu.PartitionScheme.zigbee_2MB=Zigbee 2MB with spiffs
264+
esp32c5.menu.PartitionScheme.zigbee_2MB.build.partitions=zigbee_2MB
265+
esp32c5.menu.PartitionScheme.zigbee_2MB.upload.maximum_size=1310720
266+
esp32c5.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs
267+
esp32c5.menu.PartitionScheme.zigbee.build.partitions=zigbee
268+
esp32c5.menu.PartitionScheme.zigbee.upload.maximum_size=1310720
269+
esp32c5.menu.PartitionScheme.zigbee_8MB=Zigbee 8MB with spiffs
270+
esp32c5.menu.PartitionScheme.zigbee_8MB.build.partitions=zigbee_8MB
271+
esp32c5.menu.PartitionScheme.zigbee_8MB.upload.maximum_size=3407872
272+
esp32c5.menu.PartitionScheme.zigbee_zczr_2MB=Zigbee ZCZR 2MB with spiffs
273+
esp32c5.menu.PartitionScheme.zigbee_zczr_2MB.build.partitions=zigbee_zczr_2MB
274+
esp32c5.menu.PartitionScheme.zigbee_zczr_2MB.upload.maximum_size=1310720
275+
esp32c5.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
276+
esp32c5.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
277+
esp32c5.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
278+
esp32c5.menu.PartitionScheme.zigbee_zczr_8MB=Zigbee ZCZR 8MB with spiffs
279+
esp32c5.menu.PartitionScheme.zigbee_zczr_8MB.build.partitions=zigbee_zczr_8MB
280+
esp32c5.menu.PartitionScheme.zigbee_zczr_8MB.upload.maximum_size=3407872
281+
esp32c5.menu.PartitionScheme.custom=Custom
282+
esp32c5.menu.PartitionScheme.custom.build.partitions=
283+
esp32c5.menu.PartitionScheme.custom.upload.maximum_size=16777216
284+
285+
esp32c5.menu.CPUFreq.240=240MHz (WiFi)
286+
esp32c5.menu.CPUFreq.240.build.f_cpu=240000000L
287+
esp32c5.menu.CPUFreq.120=120MHz (WiFi)
288+
esp32c5.menu.CPUFreq.120.build.f_cpu=120000000L
289+
esp32c5.menu.CPUFreq.80=80MHz (WiFi)
290+
esp32c5.menu.CPUFreq.80.build.f_cpu=80000000L
291+
esp32c5.menu.CPUFreq.40=40MHz
292+
esp32c5.menu.CPUFreq.40.build.f_cpu=40000000L
293+
esp32c5.menu.CPUFreq.20=20MHz
294+
esp32c5.menu.CPUFreq.20.build.f_cpu=20000000L
295+
esp32c5.menu.CPUFreq.10=10MHz
296+
esp32c5.menu.CPUFreq.10.build.f_cpu=10000000L
297+
298+
esp32c5.menu.FlashMode.qio=QIO
299+
esp32c5.menu.FlashMode.qio.build.flash_mode=dio
300+
esp32c5.menu.FlashMode.qio.build.boot=qio
301+
esp32c5.menu.FlashMode.dio=DIO
302+
esp32c5.menu.FlashMode.dio.build.flash_mode=dio
303+
esp32c5.menu.FlashMode.dio.build.boot=dio
304+
305+
esp32c5.menu.FlashFreq.80=80MHz
306+
esp32c5.menu.FlashFreq.80.build.flash_freq=80m
307+
esp32c5.menu.FlashFreq.40=40MHz
308+
esp32c5.menu.FlashFreq.40.build.flash_freq=40m
309+
310+
esp32c5.menu.FlashSize.4M=4MB (32Mb)
311+
esp32c5.menu.FlashSize.4M.build.flash_size=4MB
312+
esp32c5.menu.FlashSize.8M=8MB (64Mb)
313+
esp32c5.menu.FlashSize.8M.build.flash_size=8MB
314+
esp32c5.menu.FlashSize.2M=2MB (16Mb)
315+
esp32c5.menu.FlashSize.2M.build.flash_size=2MB
316+
esp32c5.menu.FlashSize.16M=16MB (128Mb)
317+
esp32c5.menu.FlashSize.16M.build.flash_size=16MB
318+
319+
esp32c5.menu.UploadSpeed.921600=921600
320+
esp32c5.menu.UploadSpeed.921600.upload.speed=921600
321+
esp32c5.menu.UploadSpeed.115200=115200
322+
esp32c5.menu.UploadSpeed.115200.upload.speed=115200
323+
esp32c5.menu.UploadSpeed.256000.windows=256000
324+
esp32c5.menu.UploadSpeed.256000.upload.speed=256000
325+
esp32c5.menu.UploadSpeed.230400.windows.upload.speed=256000
326+
esp32c5.menu.UploadSpeed.230400=230400
327+
esp32c5.menu.UploadSpeed.230400.upload.speed=230400
328+
esp32c5.menu.UploadSpeed.460800.linux=460800
329+
esp32c5.menu.UploadSpeed.460800.macosx=460800
330+
esp32c5.menu.UploadSpeed.460800.upload.speed=460800
331+
esp32c5.menu.UploadSpeed.512000.windows=512000
332+
esp32c5.menu.UploadSpeed.512000.upload.speed=512000
333+
334+
esp32c5.menu.DebugLevel.none=None
335+
esp32c5.menu.DebugLevel.none.build.code_debug=0
336+
esp32c5.menu.DebugLevel.error=Error
337+
esp32c5.menu.DebugLevel.error.build.code_debug=1
338+
esp32c5.menu.DebugLevel.warn=Warn
339+
esp32c5.menu.DebugLevel.warn.build.code_debug=2
340+
esp32c5.menu.DebugLevel.info=Info
341+
esp32c5.menu.DebugLevel.info.build.code_debug=3
342+
esp32c5.menu.DebugLevel.debug=Debug
343+
esp32c5.menu.DebugLevel.debug.build.code_debug=4
344+
esp32c5.menu.DebugLevel.verbose=Verbose
345+
esp32c5.menu.DebugLevel.verbose.build.code_debug=5
346+
347+
esp32c5.menu.EraseFlash.none=Disabled
348+
esp32c5.menu.EraseFlash.none.upload.erase_cmd=
349+
esp32c5.menu.EraseFlash.all=Enabled
350+
esp32c5.menu.EraseFlash.all.upload.erase_cmd=-e
351+
352+
esp32c5.menu.ZigbeeMode.default=Disabled
353+
esp32c5.menu.ZigbeeMode.default.build.zigbee_mode=
354+
esp32c5.menu.ZigbeeMode.default.build.zigbee_libs=
355+
esp32c5.menu.ZigbeeMode.ed=Zigbee ED (end device)
356+
esp32c5.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED
357+
esp32c5.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api_ed -lesp_zb_cli_command -lzboss_stack.ed -lzboss_port
358+
esp32c5.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
359+
esp32c5.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
360+
esp32c5.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api_zczr -lesp_zb_cli_command -lzboss_stack.zczr -lzboss_port
361+
esp32c5.menu.ZigbeeMode.rcp=Zigbee RCP (radio co-processor)
362+
esp32c5.menu.ZigbeeMode.rcp.build.zigbee_mode=-DZIGBEE_MODE_RCP
363+
esp32c5.menu.ZigbeeMode.rcp.build.zigbee_libs=-lesp_zb_api_rcp -lesp_zb_cli_command -lzboss_stack.rcp -lzboss_port
364+
esp32c5.menu.ZigbeeMode.ed_debug=Zigbee ED (end device) - Debug
365+
esp32c5.menu.ZigbeeMode.ed_debug.build.zigbee_mode=-DZIGBEE_MODE_ED
366+
esp32c5.menu.ZigbeeMode.ed_debug.build.zigbee_libs=-lesp_zb_api_ed.debug -lesp_zb_cli_command -lzboss_stack.ed.debug -lzboss_port.debug
367+
esp32c5.menu.ZigbeeMode.zczr_debug=Zigbee ZCZR (coordinator/router) - Debug
368+
esp32c5.menu.ZigbeeMode.zczr_debug.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
369+
esp32c5.menu.ZigbeeMode.zczr_debug.build.zigbee_libs=-lesp_zb_api_zczr.debug -lesp_zb_cli_command -lzboss_stack.zczr.debug -lzboss_port.debug
370+
esp32c5.menu.ZigbeeMode.rcp_debug=Zigbee RCP (radio co-processor) - Debug
371+
esp32c5.menu.ZigbeeMode.rcp_debug.build.zigbee_mode=-DZIGBEE_MODE_RCP
372+
esp32c5.menu.ZigbeeMode.rcp_debug.build.zigbee_libs=-lesp_zb_api_rcp.debug -lesp_zb_cli_command -lzboss_stack.rcp.debug -lzboss_port.debug
373+
374+
##############################################################
375+
164376
esp32p4.name=ESP32P4 Dev Module
165377

166378
esp32p4.bootloader.tool=esptool_py

‎cores/esp32/Esp.cpp

+3
Original file line numberDiff line numberDiff line change
@@ -63,6 +63,9 @@ extern "C" {
6363
#elif CONFIG_IDF_TARGET_ESP32P4
6464
#include "esp32p4/rom/spi_flash.h"
6565
#define ESP_FLASH_IMAGE_BASE 0x2000 // Esp32p4 is located at 0x2000
66+
#elif CONFIG_IDF_TARGET_ESP32C5
67+
#include "esp32c5/rom/spi_flash.h"
68+
#define ESP_FLASH_IMAGE_BASE 0x0000 // Esp32c5 is located at 0x0000
6669
#else
6770
#error Target CONFIG_IDF_TARGET is not supported
6871
#endif

‎cores/esp32/HardwareSerial.h

+8
Original file line numberDiff line numberDiff line change
@@ -127,6 +127,8 @@ typedef enum {
127127
#define SOC_RX0 (gpio_num_t)23
128128
#elif CONFIG_IDF_TARGET_ESP32P4
129129
#define SOC_RX0 (gpio_num_t)38
130+
#elif CONFIG_IDF_TARGET_ESP32C5
131+
#define SOC_RX0 (gpio_num_t)12
130132
#endif
131133
#endif
132134

@@ -145,6 +147,8 @@ typedef enum {
145147
#define SOC_TX0 (gpio_num_t)24
146148
#elif CONFIG_IDF_TARGET_ESP32P4
147149
#define SOC_TX0 (gpio_num_t)37
150+
#elif CONFIG_IDF_TARGET_ESP32C5
151+
#define SOC_TX0 (gpio_num_t)11
148152
#endif
149153
#endif
150154

@@ -168,6 +172,8 @@ typedef enum {
168172
#define RX1 (gpio_num_t)0
169173
#elif CONFIG_IDF_TARGET_ESP32P4
170174
#define RX1 (gpio_num_t)11
175+
#elif CONFIG_IDF_TARGET_ESP32C5
176+
#define RX1 (gpio_num_t)4
171177
#endif
172178
#endif
173179

@@ -188,6 +194,8 @@ typedef enum {
188194
#define TX1 (gpio_num_t)1
189195
#elif CONFIG_IDF_TARGET_ESP32P4
190196
#define TX1 (gpio_num_t)10
197+
#elif CONFIG_IDF_TARGET_ESP32C5
198+
#define TX1 (gpio_num_t)5
191199
#endif
192200
#endif
193201
#endif /* SOC_UART_HP_NUM > 1 */

‎cores/esp32/esp32-hal-cpu.c

+5-3
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@
1919
#include "esp_attr.h"
2020
#include "esp_log.h"
2121
#include "soc/rtc.h"
22-
#if !defined(CONFIG_IDF_TARGET_ESP32C2) && !defined(CONFIG_IDF_TARGET_ESP32C6) && !defined(CONFIG_IDF_TARGET_ESP32H2) && !defined(CONFIG_IDF_TARGET_ESP32P4)
22+
#if !defined(CONFIG_IDF_TARGET_ESP32C2) && !defined(CONFIG_IDF_TARGET_ESP32C6) && !defined(CONFIG_IDF_TARGET_ESP32H2) && !defined(CONFIG_IDF_TARGET_ESP32P4) && !defined(CONFIG_IDF_TARGET_ESP32C5)
2323
#include "soc/rtc_cntl_reg.h"
2424
#include "soc/syscon_reg.h"
2525
#endif
@@ -48,6 +48,8 @@
4848
#include "esp32h2/rom/rtc.h"
4949
#elif CONFIG_IDF_TARGET_ESP32P4
5050
#include "esp32p4/rom/rtc.h"
51+
#elif CONFIG_IDF_TARGET_ESP32C5
52+
#include "esp32c5/rom/rtc.h"
5153
#else
5254
#error Target CONFIG_IDF_TARGET is not supported
5355
#endif
@@ -179,7 +181,7 @@ bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz) {
179181
rtc_cpu_freq_config_t conf, cconf;
180182
uint32_t capb, apb;
181183
//Get XTAL Frequency and calculate min CPU MHz
182-
#if (!defined(CONFIG_IDF_TARGET_ESP32H2) && !defined(CONFIG_IDF_TARGET_ESP32P4))
184+
#if (!defined(CONFIG_IDF_TARGET_ESP32H2) && !defined(CONFIG_IDF_TARGET_ESP32P4) && !defined(CONFIG_IDF_TARGET_ESP32C5))
183185
rtc_xtal_freq_t xtal = rtc_clk_xtal_freq_get();
184186
#endif
185187
#if CONFIG_IDF_TARGET_ESP32
@@ -195,7 +197,7 @@ bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz) {
195197
}
196198
}
197199
#endif
198-
#if (!defined(CONFIG_IDF_TARGET_ESP32H2) && !defined(CONFIG_IDF_TARGET_ESP32P4))
200+
#if (!defined(CONFIG_IDF_TARGET_ESP32H2) && !defined(CONFIG_IDF_TARGET_ESP32P4) && !defined(CONFIG_IDF_TARGET_ESP32C5))
199201
if (cpu_freq_mhz > xtal && cpu_freq_mhz != 240 && cpu_freq_mhz != 160 && cpu_freq_mhz != 120 && cpu_freq_mhz != 80) {
200202
if (xtal >= RTC_XTAL_FREQ_40M) {
201203
log_e("Bad frequency: %u MHz! Options are: 240, 160, 120, 80, %u, %u and %u MHz", cpu_freq_mhz, xtal, xtal / 2, xtal / 4);

‎cores/esp32/esp32-hal-i2c-slave.c

+6-1
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,9 @@
4343
#include "soc/i2c_struct.h"
4444
#include "soc/periph_defs.h"
4545
#include "hal/i2c_ll.h"
46+
#ifndef CONFIG_IDF_TARGET_ESP32C5
4647
#include "hal/clk_gate_ll.h"
48+
#endif
4749
#include "esp32-hal-log.h"
4850
#include "esp32-hal-i2c-slave.h"
4951
#include "esp32-hal-periman.h"
@@ -325,7 +327,7 @@ esp_err_t i2cSlaveInit(uint8_t num, int sda, int scl, uint16_t slaveID, uint32_t
325327
frequency = 100000L;
326328
}
327329
frequency = (frequency * 5) / 4;
328-
#if !defined(CONFIG_IDF_TARGET_ESP32P4)
330+
#if !defined(CONFIG_IDF_TARGET_ESP32P4) && !defined(CONFIG_IDF_TARGET_ESP32C5)
329331
if (i2c->num == 0) {
330332
periph_ll_enable_clk_clear_rst(PERIPH_I2C0_MODULE);
331333
#if SOC_HP_I2C_NUM > 1
@@ -556,6 +558,9 @@ static bool i2c_slave_set_frequency(i2c_slave_struct_t *i2c, uint32_t clk_speed)
556558
i2c_ll_set_source_clk(i2c->dev, SOC_MOD_CLK_APB); /*!< I2C source clock from APB, 80M*/
557559
}
558560
#elif SOC_I2C_SUPPORT_XTAL
561+
#ifndef XTAL_CLK_FREQ
562+
#define XTAL_CLK_FREQ APB_CLK_FREQ
563+
#endif
559564
i2c_ll_master_cal_bus_clk(XTAL_CLK_FREQ, clk_speed, &clk_cal);
560565
I2C_CLOCK_SRC_ATOMIC() {
561566
i2c_ll_set_source_clk(i2c->dev, SOC_MOD_CLK_XTAL); /*!< I2C source clock from XTAL, 40M */

‎cores/esp32/esp32-hal-matrix.c

+2
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,8 @@
3434
#include "esp32h2/rom/gpio.h"
3535
#elif CONFIG_IDF_TARGET_ESP32P4
3636
#include "esp32p4/rom/gpio.h"
37+
#elif CONFIG_IDF_TARGET_ESP32C5
38+
#include "esp32c5/rom/gpio.h"
3739
#else
3840
#error Target CONFIG_IDF_TARGET is not supported
3941
#endif

‎cores/esp32/esp32-hal-misc.c

+3-1
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@
3030
#endif //CONFIG_BT_ENABLED
3131
#include <sys/time.h>
3232
#include "soc/rtc.h"
33-
#if !defined(CONFIG_IDF_TARGET_ESP32C2) && !defined(CONFIG_IDF_TARGET_ESP32C6) && !defined(CONFIG_IDF_TARGET_ESP32H2) && !defined(CONFIG_IDF_TARGET_ESP32P4)
33+
#if !defined(CONFIG_IDF_TARGET_ESP32C2) && !defined(CONFIG_IDF_TARGET_ESP32C6) && !defined(CONFIG_IDF_TARGET_ESP32H2) && !defined(CONFIG_IDF_TARGET_ESP32P4) && !defined(CONFIG_IDF_TARGET_ESP32C5)
3434
#include "soc/rtc_cntl_reg.h"
3535
#include "soc/syscon_reg.h"
3636
#endif
@@ -56,6 +56,8 @@
5656
#include "esp32h2/rom/rtc.h"
5757
#elif CONFIG_IDF_TARGET_ESP32P4
5858
#include "esp32p4/rom/rtc.h"
59+
#elif CONFIG_IDF_TARGET_ESP32C5
60+
#include "esp32c5/rom/rtc.h"
5961

6062
#else
6163
#error Target CONFIG_IDF_TARGET is not supported

0 commit comments

Comments
 (0)