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me-no-devpre-commit-ci-lite[bot]
me-no-dev
and
pre-commit-ci-lite[bot]
committedFeb 18, 2025·
feat(i2c): Add support for the new I2C driver in IDF v5.4 (#10858)
* feat(i2c): Add support for the new I2C driver in IDF v5.4 * fix(build): Add the new driver to CMakeLists.txt * fix(i2c): Guard sleep retention Not all chips can restore I2C bus after light sleep * ci(pre-commit): Apply automatic fixes --------- Co-authored-by: pre-commit-ci-lite[bot] <117423508+pre-commit-ci-lite[bot]@users.noreply.github.com>
·
3.3.0-alpha13.2.0-RC1
1 parent 18cbd76 commit f0cf3b1

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6 files changed

+476
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6 files changed

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‎CMakeLists.txt

+1
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,7 @@ set(CORE_SRCS
3333
cores/esp32/esp32-hal-dac.c
3434
cores/esp32/esp32-hal-gpio.c
3535
cores/esp32/esp32-hal-i2c.c
36+
cores/esp32/esp32-hal-i2c-ng.c
3637
cores/esp32/esp32-hal-i2c-slave.c
3738
cores/esp32/esp32-hal-ledc.c
3839
cores/esp32/esp32-hal-matrix.c

‎cores/esp32/esp32-hal-i2c-ng.c

+445
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,445 @@
1+
// Copyright 2015-2025 Espressif Systems (Shanghai) PTE LTD
2+
//
3+
// Licensed under the Apache License, Version 2.0 (the "License");
4+
// you may not use this file except in compliance with the License.
5+
// You may obtain a copy of the License at
6+
7+
// http://www.apache.org/licenses/LICENSE-2.0
8+
//
9+
// Unless required by applicable law or agreed to in writing, software
10+
// distributed under the License is distributed on an "AS IS" BASIS,
11+
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12+
// See the License for the specific language governing permissions and
13+
// limitations under the License.
14+
15+
#include "esp32-hal-i2c.h"
16+
17+
#if SOC_I2C_SUPPORTED
18+
#include "esp_idf_version.h"
19+
#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 0)
20+
#include "esp32-hal.h"
21+
#if !CONFIG_DISABLE_HAL_LOCKS
22+
#include "freertos/FreeRTOS.h"
23+
#include "freertos/task.h"
24+
#include "freertos/semphr.h"
25+
#endif
26+
#include "esp_attr.h"
27+
#include "esp_system.h"
28+
#include "soc/soc_caps.h"
29+
#include "driver/i2c_master.h"
30+
#include "esp32-hal-periman.h"
31+
32+
typedef volatile struct {
33+
bool initialized;
34+
uint32_t frequency;
35+
#if !CONFIG_DISABLE_HAL_LOCKS
36+
SemaphoreHandle_t lock;
37+
#endif
38+
int8_t scl;
39+
int8_t sda;
40+
i2c_master_bus_handle_t bus_handle;
41+
i2c_master_dev_handle_t dev_handles[128];
42+
} i2c_bus_t;
43+
44+
static i2c_bus_t bus[SOC_I2C_NUM];
45+
46+
static bool i2cDetachBus(void *bus_i2c_num) {
47+
uint8_t i2c_num = (int)bus_i2c_num - 1;
48+
if (!bus[i2c_num].initialized) {
49+
return true;
50+
}
51+
esp_err_t err = i2cDeinit(i2c_num);
52+
if (err != ESP_OK) {
53+
log_e("i2cDeinit failed with error: %d", err);
54+
return false;
55+
}
56+
return true;
57+
}
58+
59+
bool i2cIsInit(uint8_t i2c_num) {
60+
if (i2c_num >= SOC_I2C_NUM) {
61+
return false;
62+
}
63+
return bus[i2c_num].initialized;
64+
}
65+
66+
esp_err_t i2cInit(uint8_t i2c_num, int8_t sda, int8_t scl, uint32_t frequency) {
67+
esp_err_t ret = ESP_OK;
68+
if (i2c_num >= SOC_I2C_NUM) {
69+
return ESP_ERR_INVALID_ARG;
70+
}
71+
#if !CONFIG_DISABLE_HAL_LOCKS
72+
if (bus[i2c_num].lock == NULL) {
73+
bus[i2c_num].lock = xSemaphoreCreateMutex();
74+
if (bus[i2c_num].lock == NULL) {
75+
log_e("xSemaphoreCreateMutex failed");
76+
return ESP_ERR_NO_MEM;
77+
}
78+
}
79+
//acquire lock
80+
if (xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE) {
81+
log_e("could not acquire lock");
82+
return ESP_FAIL;
83+
}
84+
#endif
85+
if (bus[i2c_num].initialized) {
86+
log_e("bus is already initialized");
87+
ret = ESP_FAIL;
88+
goto init_fail;
89+
}
90+
91+
if (!frequency) {
92+
frequency = 100000UL;
93+
} else if (frequency > 1000000UL) {
94+
frequency = 1000000UL;
95+
}
96+
97+
perimanSetBusDeinit(ESP32_BUS_TYPE_I2C_MASTER_SDA, i2cDetachBus);
98+
perimanSetBusDeinit(ESP32_BUS_TYPE_I2C_MASTER_SCL, i2cDetachBus);
99+
100+
if (!perimanClearPinBus(sda) || !perimanClearPinBus(scl)) {
101+
ret = ESP_FAIL;
102+
goto init_fail;
103+
}
104+
105+
log_i("Initializing I2C Master: num=%u sda=%d scl=%d freq=%lu", i2c_num, sda, scl, frequency);
106+
107+
i2c_master_bus_handle_t bus_handle = NULL;
108+
i2c_master_bus_config_t bus_config;
109+
memset(&bus_config, 0, sizeof(i2c_master_bus_config_t));
110+
bus_config.i2c_port = (i2c_port_num_t)i2c_num;
111+
bus_config.sda_io_num = (gpio_num_t)sda;
112+
bus_config.scl_io_num = (gpio_num_t)scl;
113+
#if SOC_LP_I2C_SUPPORTED
114+
if (i2c_num >= SOC_HP_I2C_NUM) {
115+
bus_config.lp_source_clk = LP_I2C_SCLK_DEFAULT;
116+
} else
117+
#endif
118+
{
119+
bus_config.clk_source = I2C_CLK_SRC_DEFAULT;
120+
}
121+
bus_config.glitch_ignore_cnt = 7;
122+
bus_config.intr_priority = 0; // auto
123+
bus_config.trans_queue_depth = 0; // only valid in asynchronous transaction, which Arduino does not use
124+
bus_config.flags.enable_internal_pullup = 1;
125+
#if SOC_I2C_SUPPORT_SLEEP_RETENTION
126+
bus_config.flags.allow_pd = 1; // backup/restore the I2C registers before/after entering/exist sleep mode
127+
#endif
128+
129+
ret = i2c_new_master_bus(&bus_config, &bus_handle);
130+
if (ret != ESP_OK) {
131+
log_e("i2c_new_master_bus failed: [%d] %s", ret, esp_err_to_name(ret));
132+
} else {
133+
bus[i2c_num].initialized = true;
134+
bus[i2c_num].frequency = frequency;
135+
bus[i2c_num].scl = scl;
136+
bus[i2c_num].sda = sda;
137+
bus[i2c_num].bus_handle = bus_handle;
138+
for (uint8_t i = 0; i < 128; i++) {
139+
bus[i2c_num].dev_handles[i] = NULL;
140+
}
141+
if (!perimanSetPinBus(sda, ESP32_BUS_TYPE_I2C_MASTER_SDA, (void *)(i2c_num + 1), i2c_num, -1)
142+
|| !perimanSetPinBus(scl, ESP32_BUS_TYPE_I2C_MASTER_SCL, (void *)(i2c_num + 1), i2c_num, -1)) {
143+
#if !CONFIG_DISABLE_HAL_LOCKS
144+
//release lock so that i2cDetachBus can execute i2cDeinit
145+
xSemaphoreGive(bus[i2c_num].lock);
146+
#endif
147+
i2cDetachBus((void *)(i2c_num + 1));
148+
return ESP_FAIL;
149+
}
150+
}
151+
152+
init_fail:
153+
#if !CONFIG_DISABLE_HAL_LOCKS
154+
//release lock
155+
xSemaphoreGive(bus[i2c_num].lock);
156+
#endif
157+
return ret;
158+
}
159+
160+
esp_err_t i2cDeinit(uint8_t i2c_num) {
161+
esp_err_t err = ESP_FAIL;
162+
if (i2c_num >= SOC_I2C_NUM) {
163+
return ESP_ERR_INVALID_ARG;
164+
}
165+
#if !CONFIG_DISABLE_HAL_LOCKS
166+
//acquire lock
167+
if (bus[i2c_num].lock == NULL || xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE) {
168+
log_e("could not acquire lock");
169+
return err;
170+
}
171+
#endif
172+
if (!bus[i2c_num].initialized) {
173+
log_e("bus is not initialized");
174+
} else {
175+
// remove devices from the bus
176+
for (uint8_t i = 0; i < 128; i++) {
177+
if (bus[i2c_num].dev_handles[i] != NULL) {
178+
err = i2c_master_bus_rm_device(bus[i2c_num].dev_handles[i]);
179+
bus[i2c_num].dev_handles[i] = NULL;
180+
if (err != ESP_OK) {
181+
log_e("i2c_master_bus_rm_device failed: [%d] %s", err, esp_err_to_name(err));
182+
}
183+
}
184+
}
185+
err = i2c_del_master_bus(bus[i2c_num].bus_handle);
186+
if (err != ESP_OK) {
187+
log_e("i2c_del_master_bus failed: [%d] %s", err, esp_err_to_name(err));
188+
} else {
189+
bus[i2c_num].initialized = false;
190+
perimanClearPinBus(bus[i2c_num].scl);
191+
perimanClearPinBus(bus[i2c_num].sda);
192+
bus[i2c_num].scl = -1;
193+
bus[i2c_num].sda = -1;
194+
bus[i2c_num].bus_handle = NULL;
195+
}
196+
}
197+
#if !CONFIG_DISABLE_HAL_LOCKS
198+
//release lock
199+
xSemaphoreGive(bus[i2c_num].lock);
200+
#endif
201+
return err;
202+
}
203+
204+
static esp_err_t i2cAddDeviceIfNeeded(uint8_t i2c_num, uint16_t address) {
205+
esp_err_t ret = ESP_OK;
206+
if (bus[i2c_num].dev_handles[address] == NULL) {
207+
i2c_master_dev_handle_t dev_handle = NULL;
208+
i2c_device_config_t dev_config;
209+
memset(&dev_config, 0, sizeof(i2c_device_config_t));
210+
dev_config.dev_addr_length = I2C_ADDR_BIT_LEN_7; // Arduino supports only 7bit addresses
211+
dev_config.device_address = address;
212+
dev_config.scl_speed_hz = bus[i2c_num].frequency;
213+
dev_config.scl_wait_us = 0;
214+
dev_config.flags.disable_ack_check = 0;
215+
216+
ret = i2c_master_bus_add_device(bus[i2c_num].bus_handle, &dev_config, &dev_handle);
217+
if (ret != ESP_OK) {
218+
log_e("i2c_master_bus_add_device failed: [%d] %s", ret, esp_err_to_name(ret));
219+
} else {
220+
bus[i2c_num].dev_handles[address] = dev_handle;
221+
log_v("added device: bus=%u addr=0x%x handle=0x%08x", i2c_num, address, dev_handle);
222+
}
223+
}
224+
return ret;
225+
}
226+
227+
esp_err_t i2cWrite(uint8_t i2c_num, uint16_t address, const uint8_t *buff, size_t size, uint32_t timeOutMillis) {
228+
esp_err_t ret = ESP_FAIL;
229+
// i2c_cmd_handle_t cmd = NULL;
230+
if (i2c_num >= SOC_I2C_NUM) {
231+
return ESP_ERR_INVALID_ARG;
232+
}
233+
if (address >= 128) {
234+
log_e("Only 7bit I2C addresses are supported");
235+
return ESP_ERR_INVALID_ARG;
236+
}
237+
#if !CONFIG_DISABLE_HAL_LOCKS
238+
//acquire lock
239+
if (bus[i2c_num].lock == NULL || xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE) {
240+
log_e("could not acquire lock");
241+
return ret;
242+
}
243+
#endif
244+
if (!bus[i2c_num].initialized) {
245+
log_e("bus is not initialized");
246+
goto end;
247+
}
248+
249+
if (size == 0) {
250+
// Probe device
251+
ret = i2c_master_probe(bus[i2c_num].bus_handle, address, timeOutMillis);
252+
if (ret != ESP_OK) {
253+
log_v("i2c_master_probe failed: [%d] %s", ret, esp_err_to_name(ret));
254+
}
255+
} else {
256+
// writing data to device
257+
ret = i2cAddDeviceIfNeeded(i2c_num, address);
258+
if (ret != ESP_OK) {
259+
goto end;
260+
}
261+
262+
log_v("i2c_master_transmit: bus=%u addr=0x%x handle=0x%08x size=%u", i2c_num, address, bus[i2c_num].dev_handles[address], size);
263+
ret = i2c_master_transmit(bus[i2c_num].dev_handles[address], buff, size, timeOutMillis);
264+
if (ret != ESP_OK) {
265+
log_e("i2c_master_transmit failed: [%d] %s", ret, esp_err_to_name(ret));
266+
goto end;
267+
}
268+
269+
// wait for transactions to finish (is it needed with sync transactions?)
270+
// ret = i2c_master_bus_wait_all_done(bus[i2c_num].bus_handle, timeOutMillis);
271+
// if (ret != ESP_OK) {
272+
// log_e("i2c_master_bus_wait_all_done failed: [%d] %s", ret, esp_err_to_name(ret));
273+
// goto end;
274+
// }
275+
}
276+
277+
end:
278+
#if !CONFIG_DISABLE_HAL_LOCKS
279+
//release lock
280+
xSemaphoreGive(bus[i2c_num].lock);
281+
#endif
282+
return ret;
283+
}
284+
285+
esp_err_t i2cRead(uint8_t i2c_num, uint16_t address, uint8_t *buff, size_t size, uint32_t timeOutMillis, size_t *readCount) {
286+
esp_err_t ret = ESP_FAIL;
287+
*readCount = 0;
288+
if (i2c_num >= SOC_I2C_NUM) {
289+
return ESP_ERR_INVALID_ARG;
290+
}
291+
#if !CONFIG_DISABLE_HAL_LOCKS
292+
//acquire lock
293+
if (bus[i2c_num].lock == NULL || xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE) {
294+
log_e("could not acquire lock");
295+
return ret;
296+
}
297+
#endif
298+
if (!bus[i2c_num].initialized) {
299+
log_e("bus is not initialized");
300+
goto end;
301+
}
302+
303+
ret = i2cAddDeviceIfNeeded(i2c_num, address);
304+
if (ret != ESP_OK) {
305+
goto end;
306+
}
307+
308+
log_v("i2c_master_receive: bus=%u addr=0x%x handle=0x%08x size=%u", i2c_num, address, bus[i2c_num].dev_handles[address], size);
309+
ret = i2c_master_receive(bus[i2c_num].dev_handles[address], buff, size, timeOutMillis);
310+
if (ret != ESP_OK) {
311+
log_e("i2c_master_receive failed: [%d] %s", ret, esp_err_to_name(ret));
312+
goto end;
313+
}
314+
315+
// wait for transactions to finish (is it needed with sync transactions?)
316+
// ret = i2c_master_bus_wait_all_done(bus[i2c_num].bus_handle, timeOutMillis);
317+
// if (ret != ESP_OK) {
318+
// log_e("i2c_master_bus_wait_all_done failed: [%d] %s", ret, esp_err_to_name(ret));
319+
// goto end;
320+
// }
321+
*readCount = size;
322+
323+
end:
324+
#if !CONFIG_DISABLE_HAL_LOCKS
325+
//release lock
326+
xSemaphoreGive(bus[i2c_num].lock);
327+
#endif
328+
return ret;
329+
}
330+
331+
esp_err_t i2cWriteReadNonStop(
332+
uint8_t i2c_num, uint16_t address, const uint8_t *wbuff, size_t wsize, uint8_t *rbuff, size_t rsize, uint32_t timeOutMillis, size_t *readCount
333+
) {
334+
esp_err_t ret = ESP_FAIL;
335+
*readCount = 0;
336+
if (i2c_num >= SOC_I2C_NUM) {
337+
return ESP_ERR_INVALID_ARG;
338+
}
339+
#if !CONFIG_DISABLE_HAL_LOCKS
340+
//acquire lock
341+
if (bus[i2c_num].lock == NULL || xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE) {
342+
log_e("could not acquire lock");
343+
return ret;
344+
}
345+
#endif
346+
if (!bus[i2c_num].initialized) {
347+
log_e("bus is not initialized");
348+
goto end;
349+
}
350+
351+
ret = i2cAddDeviceIfNeeded(i2c_num, address);
352+
if (ret != ESP_OK) {
353+
goto end;
354+
}
355+
356+
log_v("i2c_master_transmit_receive: bus=%u addr=0x%x handle=0x%08x write=%u read=%u", i2c_num, address, bus[i2c_num].dev_handles[address], wsize, rsize);
357+
ret = i2c_master_transmit_receive(bus[i2c_num].dev_handles[address], wbuff, wsize, rbuff, rsize, timeOutMillis);
358+
if (ret != ESP_OK) {
359+
log_e("i2c_master_transmit_receive failed: [%d] %s", ret, esp_err_to_name(ret));
360+
goto end;
361+
}
362+
363+
// wait for transactions to finish (is it needed with sync transactions?)
364+
// ret = i2c_master_bus_wait_all_done(bus[i2c_num].bus_handle, timeOutMillis);
365+
// if (ret != ESP_OK) {
366+
// log_e("i2c_master_bus_wait_all_done failed: [%d] %s", ret, esp_err_to_name(ret));
367+
// goto end;
368+
// }
369+
*readCount = rsize;
370+
371+
end:
372+
#if !CONFIG_DISABLE_HAL_LOCKS
373+
//release lock
374+
xSemaphoreGive(bus[i2c_num].lock);
375+
#endif
376+
return ret;
377+
}
378+
379+
esp_err_t i2cSetClock(uint8_t i2c_num, uint32_t frequency) {
380+
esp_err_t ret = ESP_FAIL;
381+
if (i2c_num >= SOC_I2C_NUM) {
382+
return ESP_ERR_INVALID_ARG;
383+
}
384+
#if !CONFIG_DISABLE_HAL_LOCKS
385+
//acquire lock
386+
if (bus[i2c_num].lock == NULL || xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE) {
387+
log_e("could not acquire lock");
388+
return ret;
389+
}
390+
#endif
391+
if (!bus[i2c_num].initialized) {
392+
log_e("bus is not initialized");
393+
goto end;
394+
}
395+
if (bus[i2c_num].frequency == frequency) {
396+
ret = ESP_OK;
397+
goto end;
398+
}
399+
if (!frequency) {
400+
frequency = 100000UL;
401+
} else if (frequency > 1000000UL) {
402+
frequency = 1000000UL;
403+
}
404+
405+
bus[i2c_num].frequency = frequency;
406+
407+
// loop through devices, remove them and then re-add them with the new frequency
408+
for (uint8_t i = 0; i < 128; i++) {
409+
if (bus[i2c_num].dev_handles[i] != NULL) {
410+
ret = i2c_master_bus_rm_device(bus[i2c_num].dev_handles[i]);
411+
if (ret != ESP_OK) {
412+
log_e("i2c_master_bus_rm_device failed: [%d] %s", ret, esp_err_to_name(ret));
413+
goto end;
414+
} else {
415+
bus[i2c_num].dev_handles[i] = NULL;
416+
ret = i2cAddDeviceIfNeeded(i2c_num, i);
417+
if (ret != ESP_OK) {
418+
goto end;
419+
}
420+
}
421+
}
422+
}
423+
424+
end:
425+
#if !CONFIG_DISABLE_HAL_LOCKS
426+
//release lock
427+
xSemaphoreGive(bus[i2c_num].lock);
428+
#endif
429+
return ret;
430+
}
431+
432+
esp_err_t i2cGetClock(uint8_t i2c_num, uint32_t *frequency) {
433+
if (i2c_num >= SOC_I2C_NUM) {
434+
return ESP_ERR_INVALID_ARG;
435+
}
436+
if (!bus[i2c_num].initialized) {
437+
log_e("bus is not initialized");
438+
return ESP_FAIL;
439+
}
440+
*frequency = bus[i2c_num].frequency;
441+
return ESP_OK;
442+
}
443+
444+
#endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 0) */
445+
#endif /* SOC_I2C_SUPPORTED */

‎cores/esp32/esp32-hal-i2c.c

+3
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,8 @@
1515
#include "esp32-hal-i2c.h"
1616

1717
#if SOC_I2C_SUPPORTED
18+
#include "esp_idf_version.h"
19+
#if ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(5, 4, 0)
1820
#include "esp32-hal.h"
1921
#if !CONFIG_DISABLE_HAL_LOCKS
2022
#include "freertos/FreeRTOS.h"
@@ -429,4 +431,5 @@ esp_err_t i2cGetClock(uint8_t i2c_num, uint32_t *frequency) {
429431
return ESP_OK;
430432
}
431433

434+
#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(5, 4, 0) */
432435
#endif /* SOC_I2C_SUPPORTED */

‎libraries/Wire/src/Wire.cpp

+13-4
Original file line numberDiff line numberDiff line change
@@ -462,10 +462,11 @@ uint8_t TwoWire::endTransmission(bool sendStop) {
462462
nonStop = true;
463463
}
464464
switch (err) {
465-
case ESP_OK: return 0;
466-
case ESP_FAIL: return 2;
467-
case ESP_ERR_TIMEOUT: return 5;
468-
default: break;
465+
case ESP_OK: return 0;
466+
case ESP_FAIL: return 2;
467+
case ESP_ERR_NOT_FOUND: return 2;
468+
case ESP_ERR_TIMEOUT: return 5;
469+
default: break;
469470
}
470471
return 4;
471472
}
@@ -646,8 +647,16 @@ void TwoWire::onRequestService(uint8_t num, void *arg) {
646647
#endif /* SOC_I2C_SUPPORT_SLAVE */
647648

648649
TwoWire Wire = TwoWire(0);
650+
#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 0)
651+
#if SOC_I2C_NUM > 1
652+
TwoWire Wire1 = TwoWire(1);
653+
#elif SOC_I2C_NUM > 2
654+
TwoWire Wire2 = TwoWire(2);
655+
#endif /* SOC_I2C_NUM */
656+
#else
649657
#if SOC_HP_I2C_NUM > 1
650658
TwoWire Wire1 = TwoWire(1);
651659
#endif /* SOC_HP_I2C_NUM */
660+
#endif
652661

653662
#endif /* SOC_I2C_SUPPORTED */

‎libraries/Wire/src/Wire.h

+9
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,7 @@
2828

2929
#include "soc/soc_caps.h"
3030
#if SOC_I2C_SUPPORTED
31+
#include "esp_idf_version.h"
3132

3233
#include <esp32-hal.h>
3334
#include <esp32-hal-log.h>
@@ -144,9 +145,17 @@ class TwoWire : public HardwareI2C {
144145
};
145146

146147
extern TwoWire Wire;
148+
#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 0)
149+
#if SOC_I2C_NUM > 1
150+
extern TwoWire Wire1;
151+
#elif SOC_I2C_NUM > 2
152+
extern TwoWire Wire2;
153+
#endif /* SOC_I2C_NUM */
154+
#else
147155
#if SOC_HP_I2C_NUM > 1
148156
extern TwoWire Wire1;
149157
#endif /* SOC_HP_I2C_NUM */
158+
#endif
150159

151160
#endif /* SOC_I2C_SUPPORTED */
152161
#endif /* TwoWire_h */

‎variants/esp32c6/pins_arduino.h

+5
Original file line numberDiff line numberDiff line change
@@ -32,4 +32,9 @@ static const uint8_t A4 = 4;
3232
static const uint8_t A5 = 5;
3333
static const uint8_t A6 = 6;
3434

35+
// LP I2C Pins are fixed on ESP32-C6
36+
#define WIRE1_PIN_DEFINED
37+
static const uint8_t SDA1 = 6;
38+
static const uint8_t SCL1 = 7;
39+
3540
#endif /* Pins_Arduino_h */

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