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Make SPI speed configurable
1 parent da42146 commit b54750c

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2 files changed

+22
-20
lines changed

2 files changed

+22
-20
lines changed

Diff for: libraries/Ethernet/src/ETH.cpp

+13-8
Original file line numberDiff line numberDiff line change
@@ -52,6 +52,7 @@ ETHClass::ETHClass(uint8_t eth_index)
5252
#if ETH_SPI_SUPPORTS_CUSTOM
5353
,_spi(NULL)
5454
#endif
55+
,_spi_freq_mhz(20)
5556
,_pin_cs(-1)
5657
,_pin_irq(-1)
5758
,_pin_rst(-1)
@@ -252,7 +253,7 @@ esp_err_t ETHClass::eth_spi_read(uint32_t cmd, uint32_t addr, void *data, uint32
252253
return ESP_FAIL;
253254
}
254255
// log_i(" 0x%04lx 0x%04lx %lu", cmd, addr, data_len);
255-
_spi->beginTransaction(SPISettings(ETH_SPI_CLOCK_MHZ * 1000 * 1000, MSBFIRST, SPI_MODE0));
256+
_spi->beginTransaction(SPISettings(_spi_freq_mhz * 1000 * 1000, MSBFIRST, SPI_MODE0));
256257
digitalWrite(_pin_cs, LOW);
257258

258259
#if CONFIG_ETH_SPI_ETHERNET_DM9051
@@ -294,7 +295,7 @@ esp_err_t ETHClass::eth_spi_write(uint32_t cmd, uint32_t addr, const void *data,
294295
return ESP_FAIL;
295296
}
296297
// log_i("0x%04lx 0x%04lx %lu", cmd, addr, data_len);
297-
_spi->beginTransaction(SPISettings(ETH_SPI_CLOCK_MHZ * 1000 * 1000, MSBFIRST, SPI_MODE0));
298+
_spi->beginTransaction(SPISettings(_spi_freq_mhz * 1000 * 1000, MSBFIRST, SPI_MODE0));
298299
digitalWrite(_pin_cs, LOW);
299300

300301
#if CONFIG_ETH_SPI_ETHERNET_DM9051
@@ -336,7 +337,7 @@ bool ETHClass::beginSPI(eth_phy_type_t type, uint8_t phy_addr, int cs, int irq,
336337
#if ETH_SPI_SUPPORTS_CUSTOM
337338
SPIClass *spi,
338339
#endif
339-
int sck, int miso, int mosi, spi_host_device_t spi_host){
340+
int sck, int miso, int mosi, spi_host_device_t spi_host, uint8_t spi_freq_mhz){
340341
esp_err_t ret = ESP_OK;
341342

342343
if(_eth_started || _esp_netif != NULL || _eth_handle != NULL){
@@ -372,6 +373,9 @@ bool ETHClass::beginSPI(eth_phy_type_t type, uint8_t phy_addr, int cs, int irq,
372373
#if ETH_SPI_SUPPORTS_CUSTOM
373374
_spi = spi;
374375
#endif
376+
if(spi_freq_mhz){
377+
_spi_freq_mhz = spi_freq_mhz;
378+
}
375379
_phy_type = type;
376380
_pin_cs = cs;
377381
_pin_irq = irq;
@@ -423,7 +427,8 @@ bool ETHClass::beginSPI(eth_phy_type_t type, uint8_t phy_addr, int cs, int irq,
423427
// Configure SPI interface for specific SPI module
424428
spi_device_interface_config_t spi_devcfg = {
425429
.mode = 0,
426-
.clock_speed_hz = ETH_SPI_CLOCK_MHZ * 1000 * 1000,
430+
.clock_speed_hz = _spi_freq_mhz * 1000 * 1000,
431+
.input_delay_ns = 20,
427432
.spics_io_num = _pin_cs,
428433
.queue_size = 20,
429434
};
@@ -597,19 +602,19 @@ bool ETHClass::beginSPI(eth_phy_type_t type, uint8_t phy_addr, int cs, int irq,
597602
}
598603

599604
#if ETH_SPI_SUPPORTS_CUSTOM
600-
bool ETHClass::begin(eth_phy_type_t type, uint8_t phy_addr, int cs, int irq, int rst, SPIClass &spi){
605+
bool ETHClass::begin(eth_phy_type_t type, uint8_t phy_addr, int cs, int irq, int rst, SPIClass &spi, uint8_t spi_freq_mhz){
601606

602-
return beginSPI(type, phy_addr, cs, irq, rst, &spi, -1, -1, -1, SPI2_HOST);
607+
return beginSPI(type, phy_addr, cs, irq, rst, &spi, -1, -1, -1, SPI2_HOST, spi_freq_mhz);
603608
}
604609
#endif
605610

606-
bool ETHClass::begin(eth_phy_type_t type, uint8_t phy_addr, int cs, int irq, int rst, spi_host_device_t spi_host, int sck, int miso, int mosi){
611+
bool ETHClass::begin(eth_phy_type_t type, uint8_t phy_addr, int cs, int irq, int rst, spi_host_device_t spi_host, int sck, int miso, int mosi, uint8_t spi_freq_mhz){
607612

608613
return beginSPI(type, phy_addr, cs, irq, rst,
609614
#if ETH_SPI_SUPPORTS_CUSTOM
610615
NULL,
611616
#endif
612-
sck, miso, mosi, spi_host);
617+
sck, miso, mosi, spi_host, spi_freq_mhz);
613618
}
614619

615620
void ETHClass::end(void)

Diff for: libraries/Ethernet/src/ETH.h

+9-12
Original file line numberDiff line numberDiff line change
@@ -83,13 +83,9 @@ typedef enum { ETH_CLOCK_GPIO0_IN, ETH_CLOCK_GPIO0_OUT, ETH_CLOCK_GPIO16_OUT, ET
8383
#define ETH_RMII_CRS_DV 27
8484
#endif /* CONFIG_ETH_USE_ESP32_EMAC */
8585

86-
#ifndef ETH_SPI_CLOCK_MHZ
87-
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
88-
#define ETH_SPI_CLOCK_MHZ 36
89-
#else
90-
#define ETH_SPI_CLOCK_MHZ 12
91-
#endif
92-
#endif /* ETH_SPI_CLOCK_MHZ */
86+
#ifndef ETH_PHY_SPI_FREQ_MHZ
87+
#define ETH_PHY_SPI_FREQ_MHZ 20
88+
#endif /* ETH_PHY_SPI_FREQ_MHZ */
9389

9490
typedef enum {
9591
#if CONFIG_ETH_USE_ESP32_EMAC
@@ -116,19 +112,19 @@ class ETHClass {
116112
bool begin(eth_phy_type_t type, uint8_t phy_addr, int mdc, int mdio, int power, eth_clock_mode_t clk_mode);
117113
#endif /* CONFIG_ETH_USE_ESP32_EMAC */
118114
#if ETH_SPI_SUPPORTS_CUSTOM
119-
bool begin(eth_phy_type_t type, uint8_t phy_addr, int cs, int irq, int rst, SPIClass &spi);
115+
bool begin(eth_phy_type_t type, uint8_t phy_addr, int cs, int irq, int rst, SPIClass &spi, uint8_t spi_freq_mhz=ETH_PHY_SPI_FREQ_MHZ);
120116
#endif
121-
bool begin(eth_phy_type_t type, uint8_t phy_addr, int cs, int irq, int rst, spi_host_device_t spi_host, int sck=-1, int miso=-1, int mosi=-1);
117+
bool begin(eth_phy_type_t type, uint8_t phy_addr, int cs, int irq, int rst, spi_host_device_t spi_host, int sck=-1, int miso=-1, int mosi=-1, uint8_t spi_freq_mhz=ETH_PHY_SPI_FREQ_MHZ);
122118

123119
bool begin(){
124120
#if defined(ETH_PHY_TYPE) && defined(ETH_PHY_ADDR)
125121
#if defined(CONFIG_ETH_USE_ESP32_EMAC) && defined(ETH_PHY_POWER) && defined(ETH_PHY_MDC) && defined(ETH_PHY_MDIO) && defined(ETH_CLK_MODE)
126122
return begin(ETH_PHY_TYPE, ETH_PHY_ADDR, ETH_PHY_MDC, ETH_PHY_MDIO, ETH_PHY_POWER, ETH_CLK_MODE);
127123
#elif defined(ETH_PHY_CS) && defined(ETH_PHY_IRQ) && defined(ETH_PHY_RST)
128124
#if ETH_SPI_SUPPORTS_CUSTOM && defined(ETH_PHY_SPI)
129-
return begin(ETH_PHY_TYPE, ETH_PHY_ADDR, ETH_PHY_CS, ETH_PHY_IRQ, ETH_PHY_RST, ETH_PHY_SPI);
125+
return begin(ETH_PHY_TYPE, ETH_PHY_ADDR, ETH_PHY_CS, ETH_PHY_IRQ, ETH_PHY_RST, ETH_PHY_SPI, ETH_PHY_SPI_FREQ_MHZ);
130126
#elif defined(ETH_PHY_SPI_HOST) && defined(ETH_PHY_SPI_SCK) && defined(ETH_PHY_SPI_MISO) && defined(ETH_PHY_SPI_MOSI)
131-
return begin(ETH_PHY_TYPE, ETH_PHY_ADDR, ETH_PHY_CS, ETH_PHY_IRQ, ETH_PHY_RST, ETH_PHY_SPI_HOST, ETH_PHY_SPI_SCK, ETH_PHY_SPI_MISO, ETH_PHY_SPI_MOSI);
127+
return begin(ETH_PHY_TYPE, ETH_PHY_ADDR, ETH_PHY_CS, ETH_PHY_IRQ, ETH_PHY_RST, ETH_PHY_SPI_HOST, ETH_PHY_SPI_SCK, ETH_PHY_SPI_MISO, ETH_PHY_SPI_MOSI, ETH_PHY_SPI_FREQ_MHZ);
132128
#endif
133129
#endif
134130
#endif
@@ -196,6 +192,7 @@ class ETHClass {
196192
#if ETH_SPI_SUPPORTS_CUSTOM
197193
SPIClass * _spi;
198194
#endif
195+
uint8_t _spi_freq_mhz;
199196
int8_t _pin_cs;
200197
int8_t _pin_irq;
201198
int8_t _pin_rst;
@@ -214,7 +211,7 @@ class ETHClass {
214211
#if ETH_SPI_SUPPORTS_CUSTOM
215212
SPIClass * spi,
216213
#endif
217-
int sck, int miso, int mosi, spi_host_device_t spi_host);
214+
int sck, int miso, int mosi, spi_host_device_t spi_host, uint8_t spi_freq_mhz);
218215
};
219216

220217
extern ETHClass ETH;

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