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david-cermakdavid-cermak
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rmt driver initial version
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‎cores/esp32/esp32-hal-rmt.c

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#include "esp32-hal.h"
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#include "esp8266-compat.h"
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#include "soc/gpio_reg.h"
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#include "soc/gpio_reg.h"
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#include "esp32-hal-rmt.h"
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#include "driver/periph_ctrl.h"
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#include "soc/rmt_struct.h"
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#include "esp_intr_alloc.h"
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#define MAX_CHANNELS 8
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#define ABS(a) (a>0?a:-a)
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struct rmt_obj_s
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{
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bool allocated;
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intr_handle_t intr_handle;
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int pin;
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int channel;
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bool tx_not_rx;
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int buffers;
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};
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static rmt_obj_t g_rmt_objects[MAX_CHANNELS] = {
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{ false, NULL, 0, 0, 0, 0},
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{ false, NULL, 0, 0, 0, 0},
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};
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static intr_handle_t intr_handle;
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static bool periph_enabled = false;
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static void _initPin(int pin, int channel);
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bool rmtDeinit(rmt_obj_t *rmt)
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{
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if (!rmt) {
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return false;
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}
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// sanity check
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if (rmt != &(g_rmt_objects[rmt->channel])) {
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return false;
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}
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size_t from = rmt->channel;
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size_t to = rmt->buffers + rmt->channel;
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size_t i;
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for (i = from; i < to; i++) {
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g_rmt_objects[i].allocated = false;
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}
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return true;
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g_rmt_objects[from].channel = 0;
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g_rmt_objects[from].buffers = 0;
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}
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bool rmtSend(uint32_t* data, size_t size, rmt_obj_t* rmt)
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{
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if (!rmt) {
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return false;
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}
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int channel = rmt->channel;
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RMT.apb_conf.fifo_mask = 1;
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size_t i;
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for (i = 0; i < size; i++) {
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RMTMEM.chan[channel].data32[i].val = data[i];
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}
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RMT.conf_ch[channel].conf1.mem_rd_rst = 1;
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RMT.conf_ch[channel].conf1.tx_start = 1;
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return true;
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}
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rmt_obj_t* _rmtAllocate(int pin, int from, int size)
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{
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size_t i;
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// setup how many buffers shall we use
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g_rmt_objects[from].buffers = size;
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for (i=0; i<size; i++) {
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// mark the block of channels as used
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g_rmt_objects[i+from].allocated = true;
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}
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return &(g_rmt_objects[from]);
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}
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float rmtSetTick(rmt_obj_t* rmt, float tick)
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{
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if (!rmt) {
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return false;
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}
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int apb_div = 0xFF & (int)(tick/12.5);
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int ref_div = 0xFF & (int)(tick/1000);
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float apb_tick = 12.5 * apb_div;
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float ref_tick = 1000.0 * ref_div;
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size_t channel = rmt->channel;
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if (ABS(apb_tick - tick) < ABS(ref_tick - tick)) {
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RMT.conf_ch[channel].conf0.div_cnt = apb_div;
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RMT.conf_ch[channel].conf1.ref_always_on = 1;
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return apb_tick;
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} else {
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RMT.conf_ch[channel].conf0.div_cnt = ref_div;
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RMT.conf_ch[channel].conf1.ref_always_on = 0;
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return ref_tick;
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}
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}
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rmt_obj_t* rmtInit(int pin, bool tx_not_rx, int entries, int period)
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{
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int buffers = 1 + entries/64;
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rmt_obj_t* rmt;
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size_t i;
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size_t j;
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for (i=0; i<MAX_CHANNELS; i++) {
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for (j=0; j<buffers && i+j < MAX_CHANNELS; j++) {
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// if the space is ocupied break and continue on other channel
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if (g_rmt_objects[i+j].allocated) {
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i += j; // continue searching from latter channel
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break;
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}
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}
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if (j == buffers) {
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// found a space in channel descriptors
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break;
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}
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}
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if (i == MAX_CHANNELS) {
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return NULL;
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}
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rmt = _rmtAllocate(pin, i, buffers);
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size_t channel = i;
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rmt->pin = pin;
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rmt->tx_not_rx = tx_not_rx;
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rmt->buffers =buffers;
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rmt->channel = channel;
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_initPin(pin, channel);
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// rmt tick from 1/80M -> 12.5ns (1x)
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// 3.2 us (FFx 00 is more)
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// rmt tick for 1 MHz -> 1us (1x)
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// 256us (00x)
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// default config (period of 1us)
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RMT.conf_ch[channel].conf0.div_cnt = 1;
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RMT.conf_ch[channel].conf0.mem_size = buffers;
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RMT.conf_ch[channel].conf0.carrier_en = 0;
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RMT.conf_ch[channel].conf0.carrier_out_lv = 0;
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RMT.conf_ch[channel].conf0.mem_pd = 0;
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RMT.conf_ch[channel].conf1.rx_en = 1;
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RMT.conf_ch[channel].conf1.tx_conti_mode = 0;
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RMT.conf_ch[channel].conf1.ref_cnt_rst = 0;
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RMT.conf_ch[channel].conf1.rx_filter_en = 0;
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RMT.conf_ch[channel].conf1.rx_filter_thres = 0;
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RMT.conf_ch[channel].conf1.idle_out_lv = 0; // signal level for idle
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RMT.conf_ch[channel].conf1.idle_out_en = 1; // enable idle
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RMT.conf_ch[channel].conf1.ref_always_on = 0; // base clock
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if (tx_not_rx) {
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RMT.conf_ch[channel].conf1.rx_en = 0;
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RMT.conf_ch[channel].conf1.mem_owner = 0;
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} else {
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RMT.conf_ch[channel].conf1.rx_en = 1;
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RMT.conf_ch[channel].conf1.mem_owner = 1;
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}
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// RMT.conf_ch[channel].conf0.val = ((uint32_t*)config)[0];
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// RMT.conf_ch[channel].conf1.val = ((uint32_t*)config)[1];
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return rmt;
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}
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static void _initPin(int pin, int channel)
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// rmt_driver_config_t* config)
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{
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if (!periph_enabled) {
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periph_enabled = true;
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periph_module_enable( PERIPH_RMT_MODULE );
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}
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pinMode(pin, OUTPUT);
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pinMatrixOutAttach(pin, RMT_SIG_OUT0_IDX + channel, 0, 0);
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// memcpy( (uint8_t*)&RMT.conf_ch[channel].conf0.val, (uint8_t*)config, 8);
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// memcpy( (uint8_t*)&RMT.conf_ch[channel].conf1.val, ((uint8_t*)config) + 4, sizeof(uint32_t));
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}
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void initMemory(int offset, uint32_t* data, size_t size)
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{
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RMT.apb_conf.fifo_mask = 1;
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size_t i;
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// uint16_t * ptr = (uint16_t*)&(RMTMEM.chan[offset].data16[0]);
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// uint16_t * ptr = (uint16_t*)(0x3ff56800);
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// // uint16_t ptr[32];
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// memset(ptr, 0, 32);
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// for (i = 0; i < size; i++) {
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// printf(">> %x\n", ptr[i]);
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// }
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for (i = 0; i < size; i++) {
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RMTMEM.chan[offset].data32[i].val = data[i];
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// printf(">> %x\n", data[i]);
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// RMTMEM.chan[offset].data16[i]
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// RMTMEM.chan[offset].data32[i].val = data[i];
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// printf(" %x\n", RMTMEM.chan[offset].data16[i].val);
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// RMTMEM.chan[offset].data16[i] = data[i];
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// *ptr++ = i;
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// ptr[i] = i;
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// RMTMEM.chan[i].data1 = 0x11+ i;
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// RMTMEM.chan[i].data2 = 0x22+ i;
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// printf(" %x\n", RMTMEM.chan[offset].data16[i].val);
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// printf(" %x\n", RMTMEM.chan[offset].data32[i/2].val);
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// printf("--------\n");
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// printf(" %x\n", RMTMEM.chan[offset].xx.data16[i]);
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// RMTMEM.chan[offset].xx.data16[i] = data[i];
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// printf(" %x\n", RMTMEM.chan[offset].xx.data16[i]);
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// printf(" %x\n", RMTMEM.chan[offset].xx.data32[i/2]);
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// printf("--------\n");
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}
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}
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// 00000000
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// 00010000
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void startTx(int channel)
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{
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// reset rd value
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RMT.conf_ch[channel].conf1.mem_rd_rst = 1;
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RMT.conf_ch[channel].conf1.tx_start = 1;
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}
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// struct rmt_struct_t {
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// uart_dev_t * dev;
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// #if !CONFIG_DISABLE_HAL_LOCKS
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// xSemaphoreHandle lock;
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// #endif
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// uint8_t num;
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// xQueueHandle queue;
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// intr_handle_t intr_handle;
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// };
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static int state = 0;
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static void IRAM_ATTR _rmt_isr(void* arg)
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{
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RMT.int_clr.val = 1;
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// printf("test");
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state ^= 1;
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digitalWrite(4, state);
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}
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int config();
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int setpin(int pin)
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{
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int channel = 0;
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pinMode(pin, OUTPUT);
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// *((uint32_t*)0x3FF49070) = 0x002A0000;
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pinMatrixOutAttach(pin, RMT_SIG_OUT0_IDX + channel, 0, 0);
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periph_module_enable( PERIPH_RMT_MODULE );
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// 0x3ff49000 : 0x3FF49000 <Hex>
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// Address 0 - 3 4 - 7 8 - B C - F
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// 3FF49000 FF030000 00080000 00080000 00080000
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// 3FF49010 00080000 00080000 00080000 00080000
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// 3FF49020 00080000 00080000 00080000 000A0000
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// 3FF49030 000A0000 800A0000 000A0000 000B0000
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// 3FF49040 800A0000 000B0000 800A0000 000A0000
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// 3FF49050 000A0000 002B0000 002B0000 002B0000
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// 3FF49060 001B0000 002B0000 002B0000 000B0000
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// 3FF49070 002A0000 000A0000 000A0000 000A0000
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// 3FF49080 000A0000 000B0000 000A0000 000A0000
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// 3FF49090 00080000 00080000 00080000 00080000
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// 3FF490A0 00080000 00080000 00080000 00080000
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*((unsigned int*)(0x3FF560F0)) = 1;
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// SET(RMT_DATA_REG, 0x8010020);
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*((uint32_t*)0x3ff56800) = 0x8FFF0FFF;
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*((uint32_t*)0x3ff56804) = 0x9FFF0FFF;
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*((uint32_t*)0x3ff56808) = 0;
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*((uint32_t*)0x3ff5680C) = 0;
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*((uint32_t*)0x3ff56810) = 0;
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*((uint32_t*)0x3FF560D0) = 0;
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// uint32_t test = 0x8010;
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// uint32_t zero = 0;
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// memcpy((uint8_t*)0x3ff56800, &test, 4);
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// memcpy((uint8_t*)0x3ff56804, &zero, 4);
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RMT.conf_ch[0].conf0.val = 0x01000001;
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RMT.conf_ch[0].conf1.val = 0x20000;
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esp_intr_alloc(ETS_RMT_INTR_SOURCE, (int)ESP_INTR_FLAG_IRAM, _rmt_isr, NULL, &intr_handle);
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RMT.int_ena.val = 1;
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// RMT[0].conf0 = 0x01000001;
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// // SET(RMT_CHnCONF0_REG(0), 0x31000001);
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// // SET(RMT_CHnCONF1_REG(0), 0x20000);
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// RMT[1].conf1 = 0x20000;
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// 0x311000ff
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//-- 0x01000ff
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// 0xa0f00
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return 1;
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}
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int run()
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{
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// SET(RMT_CHnCONF0_REG(0), 0x1000001);
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// *((unsigned int*)(0x3FF560F0)) = 1;
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// // SET(RMT_DATA_REG, 0x8010020);
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// *((uint32_t*)0x3ff56800) = 0x8010;
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// *((uint32_t*)0x3ff56804) = 0;
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// SET(RMT_CHnCONF1_REG(0), 0x20009);
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return 0;
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}

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