IDF release/v4.4 c9140caf8c

Author: me-no-dev

platform.txt

@@ -42,21 +42,20 @@
     ],
 
     CFLAGS=[
-        "-mlongcalls",
         "-Wno-frame-address",
         "-std=gnu99",
         "-Wno-old-style-declaration"
     ],
 
     CXXFLAGS=[
-        "-mlongcalls",
         "-Wno-frame-address",
         "-std=gnu++11",
         "-fexceptions",
         "-fno-rtti"
     ],
 
     CCFLAGS=[
+        "-mlongcalls",
         "-ffunction-sections",
         "-fdata-sections",
         "-Wno-error=unused-function",
@@ -324,7 +323,7 @@
         "UNITY_INCLUDE_CONFIG_H",
         "WITH_POSIX",
         "_GNU_SOURCE",
-        ("IDF_VER", '\\"v4.4.1-405-g6c5fb29c2c\\"'),
+        ("IDF_VER", '\\"v4.4.1-472-gc9140caf8c\\"'),
         "ESP_PLATFORM",
         "_POSIX_READER_WRITER_LOCKS",
         "ARDUINO_ARCH_ESP32",

tools/platformio-build-esp32.py

@@ -318,7 +318,7 @@
         "UNITY_INCLUDE_CONFIG_H",
         "WITH_POSIX",
         "_GNU_SOURCE",
-        ("IDF_VER", '\\"v4.4.1-405-g6c5fb29c2c\\"'),
+        ("IDF_VER", '\\"v4.4.1-472-gc9140caf8c\\"'),
         "ESP_PLATFORM",
         "_POSIX_READER_WRITER_LOCKS",
         "ARDUINO_ARCH_ESP32",

tools/platformio-build-esp32c3.py

@@ -43,19 +43,18 @@
     ],
 
     CFLAGS=[
-        "-mlongcalls",
         "-std=gnu99",
         "-Wno-old-style-declaration"
     ],
 
     CXXFLAGS=[
-        "-mlongcalls",
         "-std=gnu++11",
         "-fexceptions",
         "-fno-rtti"
     ],
 
     CCFLAGS=[
+        "-mlongcalls",
         "-ffunction-sections",
         "-fdata-sections",
         "-Wno-error=unused-function",
@@ -307,7 +306,7 @@
         "UNITY_INCLUDE_CONFIG_H",
         "WITH_POSIX",
         "_GNU_SOURCE",
-        ("IDF_VER", '\\"v4.4.1-405-g6c5fb29c2c\\"'),
+        ("IDF_VER", '\\"v4.4.1-472-gc9140caf8c\\"'),
         "ESP_PLATFORM",
         "_POSIX_READER_WRITER_LOCKS",
         "ARDUINO_ARCH_ESP32",

tools/platformio-build-esp32s2.py

@@ -42,19 +42,18 @@
     ],
 
     CFLAGS=[
-        "-mlongcalls",
         "-std=gnu99",
         "-Wno-old-style-declaration"
     ],
 
     CXXFLAGS=[
-        "-mlongcalls",
         "-std=gnu++11",
         "-fexceptions",
         "-fno-rtti"
     ],
 
     CCFLAGS=[
+        "-mlongcalls",
         "-ffunction-sections",
         "-fdata-sections",
         "-Wno-error=unused-function",
@@ -323,7 +322,7 @@
         "UNITY_INCLUDE_CONFIG_H",
         "WITH_POSIX",
         "_GNU_SOURCE",
-        ("IDF_VER", '\\"v4.4.1-405-g6c5fb29c2c\\"'),
+        ("IDF_VER", '\\"v4.4.1-472-gc9140caf8c\\"'),
         "ESP_PLATFORM",
         "_POSIX_READER_WRITER_LOCKS",
         "ARDUINO_ARCH_ESP32",

tools/platformio-build-esp32s3.py

@@ -23,6 +23,7 @@
 #define CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE 1
 #define CONFIG_BOOTLOADER_WDT_ENABLE 1
 #define CONFIG_BOOTLOADER_WDT_TIME_MS 9000
+#define CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE 1
 #define CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP 1
 #define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x10
 #define CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT 1
@@ -186,6 +187,7 @@
 #define CONFIG_BLE_MESH_SENSOR_SERVER 1
 #define CONFIG_BLE_MESH_TIME_SCENE_SERVER 1
 #define CONFIG_BLE_MESH_LIGHTING_SERVER 1
+#define CONFIG_BLE_MESH_DISCARD_OLD_SEQ_AUTH 1
 #define CONFIG_COAP_MBEDTLS_PSK 1
 #define CONFIG_COAP_LOG_DEFAULT_LEVEL 0
 #define CONFIG_ADC_DISABLE_DAC 1
@@ -580,6 +582,7 @@
 #define CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES 16
 #define CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT 30
 #define CONFIG_WIFI_PROV_BLE_BONDING 1
+#define CONFIG_WIFI_PROV_BLE_FORCE_ENCRYPTION 1
 #define CONFIG_WPA_MBEDTLS_CRYPTO 1
 #define CONFIG_IO_GLITCH_FILTER_TIME_MS 50
 #define CONFIG_ESP_RMAKER_LIB_ESP_MQTT 1
@@ -633,6 +636,7 @@
 /* List of deprecated options */
 #define CONFIG_A2DP_ENABLE CONFIG_BT_A2DP_ENABLE
 #define CONFIG_ADC2_DISABLE_DAC CONFIG_ADC_DISABLE_DAC
+#define CONFIG_APP_ROLLBACK_ENABLE CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE
 #define CONFIG_BLE_ADV_REPORT_DISCARD_THRSHOLD CONFIG_BTDM_BLE_ADV_REPORT_DISCARD_THRSHOLD
 #define CONFIG_BLE_ADV_REPORT_FLOW_CONTROL_NUM CONFIG_BTDM_BLE_ADV_REPORT_FLOW_CTRL_NUM
 #define CONFIG_BLE_ADV_REPORT_FLOW_CONTROL_SUPPORTED CONFIG_BTDM_BLE_ADV_REPORT_FLOW_CTRL_SUPP
@@ -743,5 +747,5 @@
 #define CONFIG_ULP_COPROC_ENABLED CONFIG_ESP32_ULP_COPROC_ENABLED
 #define CONFIG_ULP_COPROC_RESERVE_MEM CONFIG_ESP32_ULP_COPROC_RESERVE_MEM
 #define CONFIG_WARN_WRITE_STRINGS CONFIG_COMPILER_WARN_WRITE_STRINGS
-#define CONFIG_ARDUINO_IDF_COMMIT "6c5fb29c2c"
+#define CONFIG_ARDUINO_IDF_COMMIT "c9140caf8c"
 #define CONFIG_ARDUINO_IDF_BRANCH "release/v4.4"

tools/sdk/esp32/bin/bootloader_dio_40m.bin

@@ -23,6 +23,7 @@
 #define CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE 1
 #define CONFIG_BOOTLOADER_WDT_ENABLE 1
 #define CONFIG_BOOTLOADER_WDT_TIME_MS 9000
+#define CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE 1
 #define CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP 1
 #define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x10
 #define CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT 1
@@ -186,6 +187,7 @@
 #define CONFIG_BLE_MESH_SENSOR_SERVER 1
 #define CONFIG_BLE_MESH_TIME_SCENE_SERVER 1
 #define CONFIG_BLE_MESH_LIGHTING_SERVER 1
+#define CONFIG_BLE_MESH_DISCARD_OLD_SEQ_AUTH 1
 #define CONFIG_COAP_MBEDTLS_PSK 1
 #define CONFIG_COAP_LOG_DEFAULT_LEVEL 0
 #define CONFIG_ADC_DISABLE_DAC 1
@@ -580,6 +582,7 @@
 #define CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES 16
 #define CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT 30
 #define CONFIG_WIFI_PROV_BLE_BONDING 1
+#define CONFIG_WIFI_PROV_BLE_FORCE_ENCRYPTION 1
 #define CONFIG_WPA_MBEDTLS_CRYPTO 1
 #define CONFIG_IO_GLITCH_FILTER_TIME_MS 50
 #define CONFIG_ESP_RMAKER_LIB_ESP_MQTT 1
@@ -633,6 +636,7 @@
 /* List of deprecated options */
 #define CONFIG_A2DP_ENABLE CONFIG_BT_A2DP_ENABLE
 #define CONFIG_ADC2_DISABLE_DAC CONFIG_ADC_DISABLE_DAC
+#define CONFIG_APP_ROLLBACK_ENABLE CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE
 #define CONFIG_BLE_ADV_REPORT_DISCARD_THRSHOLD CONFIG_BTDM_BLE_ADV_REPORT_DISCARD_THRSHOLD
 #define CONFIG_BLE_ADV_REPORT_FLOW_CONTROL_NUM CONFIG_BTDM_BLE_ADV_REPORT_FLOW_CTRL_NUM
 #define CONFIG_BLE_ADV_REPORT_FLOW_CONTROL_SUPPORTED CONFIG_BTDM_BLE_ADV_REPORT_FLOW_CTRL_SUPP
@@ -743,5 +747,5 @@
 #define CONFIG_ULP_COPROC_ENABLED CONFIG_ESP32_ULP_COPROC_ENABLED
 #define CONFIG_ULP_COPROC_RESERVE_MEM CONFIG_ESP32_ULP_COPROC_RESERVE_MEM
 #define CONFIG_WARN_WRITE_STRINGS CONFIG_COMPILER_WARN_WRITE_STRINGS
-#define CONFIG_ARDUINO_IDF_COMMIT "6c5fb29c2c"
+#define CONFIG_ARDUINO_IDF_COMMIT "c9140caf8c"
 #define CONFIG_ARDUINO_IDF_BRANCH "release/v4.4"

tools/sdk/esp32/bin/bootloader_dio_80m.bin

@@ -34,6 +34,10 @@ extern "C" {
 #define ESP_HF_PEER_FEAT_ECC        0x80        /* Enhanced Call Control */
 #define ESP_HF_PEER_FEAT_EXTERR    0x100        /* Extended error codes */
 #define ESP_HF_PEER_FEAT_CODEC     0x200        /* Codec Negotiation */
+/* HFP 1.7+ */
+#define ESP_HF_PEER_FEAT_HF_IND    0x400        /* HF Indicators */
+#define ESP_HF_PEER_FEAT_ESCO_S4   0x800        /* eSCO S4 Setting Supported */
+
 
 /* CHLD feature masks of HF AG */
 #define ESP_HF_CHLD_FEAT_REL           0x01       /* 0  Release waiting call or held calls */

tools/sdk/esp32/bin/bootloader_dout_40m.bin

@@ -17,10 +17,43 @@
 extern "C" {
 #endif
 
-#define LEDC_APB_CLK_HZ  (APB_CLK_FREQ)
-#define LEDC_REF_CLK_HZ  (REF_CLK_FREQ)
-#define LEDC_ERR_DUTY    (0xFFFFFFFF)
-#define LEDC_ERR_VAL     (-1)
+#define LEDC_APB_CLK_HZ         (APB_CLK_FREQ)
+#define LEDC_REF_CLK_HZ         (REF_CLK_FREQ)
+#define LEDC_ERR_DUTY           (0xFFFFFFFF)
+#define LEDC_ERR_VAL            (-1)
+
+/**
+ * @brief Configuration parameters of LEDC channel for ledc_channel_config function
+ */
+typedef struct {
+    int gpio_num;                   /*!< the LEDC output gpio_num, if you want to use gpio16, gpio_num = 16 */
+    ledc_mode_t speed_mode;         /*!< LEDC speed speed_mode, high-speed mode or low-speed mode */
+    ledc_channel_t channel;         /*!< LEDC channel (0 - 7) */
+    ledc_intr_type_t intr_type;     /*!< configure interrupt, Fade interrupt enable  or Fade interrupt disable */
+    ledc_timer_t timer_sel;         /*!< Select the timer source of channel (0 - 3) */
+    uint32_t duty;                  /*!< LEDC channel duty, the range of duty setting is [0, (2**duty_resolution)] */
+    int hpoint;                     /*!< LEDC channel hpoint value, the max value is 0xfffff */
+    struct {
+        unsigned int output_invert: 1;/*!< Enable (1) or disable (0) gpio output invert */
+    } flags;                        /*!< LEDC flags */
+
+} ledc_channel_config_t;
+
+/**
+ * @brief Configuration parameters of LEDC Timer timer for ledc_timer_config function
+ */
+typedef struct {
+    ledc_mode_t speed_mode;                /*!< LEDC speed speed_mode, high-speed mode or low-speed mode */
+    union {
+        ledc_timer_bit_t duty_resolution;  /*!< LEDC channel duty resolution */
+        ledc_timer_bit_t bit_num __attribute__((deprecated)); /*!< Deprecated in ESP-IDF 3.0. This is an alias to 'duty_resolution' for backward compatibility with ESP-IDF 2.1 */
+    };
+    ledc_timer_t  timer_num;               /*!< The timer source of channel (0 - 3) */
+    uint32_t freq_hz;                      /*!< LEDC timer frequency (Hz) */
+    ledc_clk_cfg_t clk_cfg;                /*!< Configure LEDC source clock.
+                                                For low speed channels and high speed channels, you can specify the source clock using LEDC_USE_REF_TICK, LEDC_USE_APB_CLK or LEDC_AUTO_CLK.
+                                                For low speed channels, you can also specify the source clock using LEDC_USE_RTC8M_CLK, in this case, all low speed channel's source clock must be RTC8M_CLK*/
+} ledc_timer_config_t;
 
 typedef intr_handle_t ledc_isr_handle_t;
 

tools/sdk/esp32/bin/bootloader_dout_80m.bin

@@ -761,6 +761,20 @@ esp_err_t esp_efuse_write_keys(const esp_efuse_purpose_t purposes[], uint8_t key
 esp_err_t esp_secure_boot_read_key_digests(ets_secure_boot_key_digests_t *trusted_keys);
 #endif
 
+/**
+ * @brief   Checks eFuse errors in BLOCK0.
+ *
+ * @note Refers to ESP32-C3 only.
+ *
+ * It does a BLOCK0 check if eFuse EFUSE_ERR_RST_ENABLE is set.
+ * If BLOCK0 has an error, it prints the error and returns ESP_FAIL, which should be treated as esp_restart.
+ *
+ * @return
+ *         - ESP_OK: No errors in BLOCK0.
+ *         - ESP_FAIL: Error in BLOCK0 requiring reboot.
+ */
+esp_err_t esp_efuse_check_errors(void);
+
 #ifdef __cplusplus
 }
 #endif

tools/sdk/esp32/bin/bootloader_qio_40m.bin

@@ -28,6 +28,7 @@ typedef enum {
     GC0308_PID = 0x9b,
     BF3005_PID = 0x30,
     BF20A6_PID = 0x20a6,
+    SC101IOT_PID = 0xda4a,
     SC030IOT_PID = 0x9a46,
 } camera_pid_t;
 
@@ -43,6 +44,7 @@ typedef enum {
     CAMERA_GC0308,
     CAMERA_BF3005,
     CAMERA_BF20A6,
+    CAMERA_SC101IOT,
     CAMERA_SC030IOT,
     CAMERA_MODEL_MAX,
     CAMERA_NONE,
@@ -60,6 +62,7 @@ typedef enum {
     GC0308_SCCB_ADDR   = 0x21,// 0x42 >> 1
     BF3005_SCCB_ADDR   = 0x6E,
     BF20A6_SCCB_ADDR   = 0x6E,
+    SC101IOT_SCCB_ADDR = 0x68,// 0xd0 >> 1
     SC030IOT_SCCB_ADDR = 0x68,// 0xd0 >> 1
 } camera_sccb_addr_t;
 

tools/sdk/esp32/bin/bootloader_qio_80m.bin

@@ -97,6 +97,7 @@ typedef enum {
     TG1WDT_CPU_RESET       = 17,    /**<17, Time Group1 reset CPU*/
     SUPER_WDT_RESET        = 18,    /**<18, super watchdog reset digital core and rtc module*/
     GLITCH_RTC_RESET       = 19,    /**<19, glitch reset digital core and rtc module*/
+    EFUSE_RESET            = 20,    /**<20, efuse reset digital core*/
 } RESET_REASON;
 
 // Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
@@ -113,6 +114,7 @@ _Static_assert((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BR
 _Static_assert((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
 _Static_assert((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
 _Static_assert((soc_reset_reason_t)GLITCH_RTC_RESET == RESET_REASON_SYS_CLK_GLITCH, "GLITCH_RTC_RESET != RESET_REASON_SYS_CLK_GLITCH");
+_Static_assert((soc_reset_reason_t)EFUSE_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_RESET != RESET_REASON_CORE_EFUSE_CRC");
 
 typedef enum {
     NO_SLEEP        = 0,

tools/sdk/esp32/bin/bootloader_qout_40m.bin

@@ -1,16 +1,8 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 // The LL layer for LEDC register operations.
 // Note that most of the register operations in this layer are non-atomic operations.
@@ -22,6 +14,27 @@
 #include "soc/ledc_struct.h"
 
 #define LEDC_LL_GET_HW() &LEDC
+#define LEDC_LL_FRACTIONAL_BITS    (8)
+#define LEDC_LL_FRACTIONAL_MAX     ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
+
+#define LEDC_LL_GLOBAL_CLOCKS { \
+                                LEDC_SLOW_CLK_APB, \
+                                LEDC_SLOW_CLK_RTC8M, \
+                            }
+#define LEDC_LL_TIMER_SPECIFIC_CLOCKS \
+                            {\
+                                { \
+                                    .clk = LEDC_REF_TICK, \
+                                    .freq = LEDC_REF_CLK_HZ, \
+                                } \
+                            }
+
+/* On ESP32, APB clock is a timer-specific clock only in fast clock mode */
+#define LEDC_LL_IS_TIMER_SPECIFIC_CLOCK(SPEED, CLK) (\
+                                                     ((CLK) == LEDC_USE_REF_TICK) || \
+                                                     ((SPEED) == LEDC_HIGH_SPEED_MODE && (CLK) == LEDC_USE_APB_CLK) \
+                                                    )
+
 
 #ifdef __cplusplus
 extern "C" {